sh_eth.c revision 264be2f5a973cc85be3e31d6bf6234b55a256627
1/* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 4 * Copyright (C) 2008-2014 Renesas Solutions Corp. 5 * Copyright (C) 2013-2014 Cogent Embedded, Inc. 6 * Copyright (C) 2014 Codethink Limited 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * The full GNU General Public License is included in this distribution in 18 * the file called "COPYING". 19 */ 20 21#include <linux/module.h> 22#include <linux/kernel.h> 23#include <linux/spinlock.h> 24#include <linux/interrupt.h> 25#include <linux/dma-mapping.h> 26#include <linux/etherdevice.h> 27#include <linux/delay.h> 28#include <linux/platform_device.h> 29#include <linux/mdio-bitbang.h> 30#include <linux/netdevice.h> 31#include <linux/of.h> 32#include <linux/of_device.h> 33#include <linux/of_irq.h> 34#include <linux/of_net.h> 35#include <linux/phy.h> 36#include <linux/cache.h> 37#include <linux/io.h> 38#include <linux/pm_runtime.h> 39#include <linux/slab.h> 40#include <linux/ethtool.h> 41#include <linux/if_vlan.h> 42#include <linux/clk.h> 43#include <linux/sh_eth.h> 44#include <linux/of_mdio.h> 45 46#include "sh_eth.h" 47 48#define SH_ETH_DEF_MSG_ENABLE \ 49 (NETIF_MSG_LINK | \ 50 NETIF_MSG_TIMER | \ 51 NETIF_MSG_RX_ERR| \ 52 NETIF_MSG_TX_ERR) 53 54static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 55 [EDSR] = 0x0000, 56 [EDMR] = 0x0400, 57 [EDTRR] = 0x0408, 58 [EDRRR] = 0x0410, 59 [EESR] = 0x0428, 60 [EESIPR] = 0x0430, 61 [TDLAR] = 0x0010, 62 [TDFAR] = 0x0014, 63 [TDFXR] = 0x0018, 64 [TDFFR] = 0x001c, 65 [RDLAR] = 0x0030, 66 [RDFAR] = 0x0034, 67 [RDFXR] = 0x0038, 68 [RDFFR] = 0x003c, 69 [TRSCER] = 0x0438, 70 [RMFCR] = 0x0440, 71 [TFTR] = 0x0448, 72 [FDR] = 0x0450, 73 [RMCR] = 0x0458, 74 [RPADIR] = 0x0460, 75 [FCFTR] = 0x0468, 76 [CSMR] = 0x04E4, 77 78 [ECMR] = 0x0500, 79 [ECSR] = 0x0510, 80 [ECSIPR] = 0x0518, 81 [PIR] = 0x0520, 82 [PSR] = 0x0528, 83 [PIPR] = 0x052c, 84 [RFLR] = 0x0508, 85 [APR] = 0x0554, 86 [MPR] = 0x0558, 87 [PFTCR] = 0x055c, 88 [PFRCR] = 0x0560, 89 [TPAUSER] = 0x0564, 90 [GECMR] = 0x05b0, 91 [BCULR] = 0x05b4, 92 [MAHR] = 0x05c0, 93 [MALR] = 0x05c8, 94 [TROCR] = 0x0700, 95 [CDCR] = 0x0708, 96 [LCCR] = 0x0710, 97 [CEFCR] = 0x0740, 98 [FRECR] = 0x0748, 99 [TSFRCR] = 0x0750, 100 [TLFRCR] = 0x0758, 101 [RFCR] = 0x0760, 102 [CERCR] = 0x0768, 103 [CEECR] = 0x0770, 104 [MAFCR] = 0x0778, 105 [RMII_MII] = 0x0790, 106 107 [ARSTR] = 0x0000, 108 [TSU_CTRST] = 0x0004, 109 [TSU_FWEN0] = 0x0010, 110 [TSU_FWEN1] = 0x0014, 111 [TSU_FCM] = 0x0018, 112 [TSU_BSYSL0] = 0x0020, 113 [TSU_BSYSL1] = 0x0024, 114 [TSU_PRISL0] = 0x0028, 115 [TSU_PRISL1] = 0x002c, 116 [TSU_FWSL0] = 0x0030, 117 [TSU_FWSL1] = 0x0034, 118 [TSU_FWSLC] = 0x0038, 119 [TSU_QTAG0] = 0x0040, 120 [TSU_QTAG1] = 0x0044, 121 [TSU_FWSR] = 0x0050, 122 [TSU_FWINMK] = 0x0054, 123 [TSU_ADQT0] = 0x0048, 124 [TSU_ADQT1] = 0x004c, 125 [TSU_VTAG0] = 0x0058, 126 [TSU_VTAG1] = 0x005c, 127 [TSU_ADSBSY] = 0x0060, 128 [TSU_TEN] = 0x0064, 129 [TSU_POST1] = 0x0070, 130 [TSU_POST2] = 0x0074, 131 [TSU_POST3] = 0x0078, 132 [TSU_POST4] = 0x007c, 133 [TSU_ADRH0] = 0x0100, 134 [TSU_ADRL0] = 0x0104, 135 [TSU_ADRH31] = 0x01f8, 136 [TSU_ADRL31] = 0x01fc, 137 138 [TXNLCR0] = 0x0080, 139 [TXALCR0] = 0x0084, 140 [RXNLCR0] = 0x0088, 141 [RXALCR0] = 0x008c, 142 [FWNLCR0] = 0x0090, 143 [FWALCR0] = 0x0094, 144 [TXNLCR1] = 0x00a0, 145 [TXALCR1] = 0x00a0, 146 [RXNLCR1] = 0x00a8, 147 [RXALCR1] = 0x00ac, 148 [FWNLCR1] = 0x00b0, 149 [FWALCR1] = 0x00b4, 150}; 151 152static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 153 [EDSR] = 0x0000, 154 [EDMR] = 0x0400, 155 [EDTRR] = 0x0408, 156 [EDRRR] = 0x0410, 157 [EESR] = 0x0428, 158 [EESIPR] = 0x0430, 159 [TDLAR] = 0x0010, 160 [TDFAR] = 0x0014, 161 [TDFXR] = 0x0018, 162 [TDFFR] = 0x001c, 163 [RDLAR] = 0x0030, 164 [RDFAR] = 0x0034, 165 [RDFXR] = 0x0038, 166 [RDFFR] = 0x003c, 167 [TRSCER] = 0x0438, 168 [RMFCR] = 0x0440, 169 [TFTR] = 0x0448, 170 [FDR] = 0x0450, 171 [RMCR] = 0x0458, 172 [RPADIR] = 0x0460, 173 [FCFTR] = 0x0468, 174 [CSMR] = 0x04E4, 175 176 [ECMR] = 0x0500, 177 [RFLR] = 0x0508, 178 [ECSR] = 0x0510, 179 [ECSIPR] = 0x0518, 180 [PIR] = 0x0520, 181 [APR] = 0x0554, 182 [MPR] = 0x0558, 183 [PFTCR] = 0x055c, 184 [PFRCR] = 0x0560, 185 [TPAUSER] = 0x0564, 186 [MAHR] = 0x05c0, 187 [MALR] = 0x05c8, 188 [CEFCR] = 0x0740, 189 [FRECR] = 0x0748, 190 [TSFRCR] = 0x0750, 191 [TLFRCR] = 0x0758, 192 [RFCR] = 0x0760, 193 [MAFCR] = 0x0778, 194 195 [ARSTR] = 0x0000, 196 [TSU_CTRST] = 0x0004, 197 [TSU_VTAG0] = 0x0058, 198 [TSU_ADSBSY] = 0x0060, 199 [TSU_TEN] = 0x0064, 200 [TSU_ADRH0] = 0x0100, 201 [TSU_ADRL0] = 0x0104, 202 [TSU_ADRH31] = 0x01f8, 203 [TSU_ADRL31] = 0x01fc, 204 205 [TXNLCR0] = 0x0080, 206 [TXALCR0] = 0x0084, 207 [RXNLCR0] = 0x0088, 208 [RXALCR0] = 0x008C, 209}; 210 211static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 212 [ECMR] = 0x0300, 213 [RFLR] = 0x0308, 214 [ECSR] = 0x0310, 215 [ECSIPR] = 0x0318, 216 [PIR] = 0x0320, 217 [PSR] = 0x0328, 218 [RDMLR] = 0x0340, 219 [IPGR] = 0x0350, 220 [APR] = 0x0354, 221 [MPR] = 0x0358, 222 [RFCF] = 0x0360, 223 [TPAUSER] = 0x0364, 224 [TPAUSECR] = 0x0368, 225 [MAHR] = 0x03c0, 226 [MALR] = 0x03c8, 227 [TROCR] = 0x03d0, 228 [CDCR] = 0x03d4, 229 [LCCR] = 0x03d8, 230 [CNDCR] = 0x03dc, 231 [CEFCR] = 0x03e4, 232 [FRECR] = 0x03e8, 233 [TSFRCR] = 0x03ec, 234 [TLFRCR] = 0x03f0, 235 [RFCR] = 0x03f4, 236 [MAFCR] = 0x03f8, 237 238 [EDMR] = 0x0200, 239 [EDTRR] = 0x0208, 240 [EDRRR] = 0x0210, 241 [TDLAR] = 0x0218, 242 [RDLAR] = 0x0220, 243 [EESR] = 0x0228, 244 [EESIPR] = 0x0230, 245 [TRSCER] = 0x0238, 246 [RMFCR] = 0x0240, 247 [TFTR] = 0x0248, 248 [FDR] = 0x0250, 249 [RMCR] = 0x0258, 250 [TFUCR] = 0x0264, 251 [RFOCR] = 0x0268, 252 [RMIIMODE] = 0x026c, 253 [FCFTR] = 0x0270, 254 [TRIMD] = 0x027c, 255}; 256 257static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 258 [ECMR] = 0x0100, 259 [RFLR] = 0x0108, 260 [ECSR] = 0x0110, 261 [ECSIPR] = 0x0118, 262 [PIR] = 0x0120, 263 [PSR] = 0x0128, 264 [RDMLR] = 0x0140, 265 [IPGR] = 0x0150, 266 [APR] = 0x0154, 267 [MPR] = 0x0158, 268 [TPAUSER] = 0x0164, 269 [RFCF] = 0x0160, 270 [TPAUSECR] = 0x0168, 271 [BCFRR] = 0x016c, 272 [MAHR] = 0x01c0, 273 [MALR] = 0x01c8, 274 [TROCR] = 0x01d0, 275 [CDCR] = 0x01d4, 276 [LCCR] = 0x01d8, 277 [CNDCR] = 0x01dc, 278 [CEFCR] = 0x01e4, 279 [FRECR] = 0x01e8, 280 [TSFRCR] = 0x01ec, 281 [TLFRCR] = 0x01f0, 282 [RFCR] = 0x01f4, 283 [MAFCR] = 0x01f8, 284 [RTRATE] = 0x01fc, 285 286 [EDMR] = 0x0000, 287 [EDTRR] = 0x0008, 288 [EDRRR] = 0x0010, 289 [TDLAR] = 0x0018, 290 [RDLAR] = 0x0020, 291 [EESR] = 0x0028, 292 [EESIPR] = 0x0030, 293 [TRSCER] = 0x0038, 294 [RMFCR] = 0x0040, 295 [TFTR] = 0x0048, 296 [FDR] = 0x0050, 297 [RMCR] = 0x0058, 298 [TFUCR] = 0x0064, 299 [RFOCR] = 0x0068, 300 [FCFTR] = 0x0070, 301 [RPADIR] = 0x0078, 302 [TRIMD] = 0x007c, 303 [RBWAR] = 0x00c8, 304 [RDFAR] = 0x00cc, 305 [TBRAR] = 0x00d4, 306 [TDFAR] = 0x00d8, 307}; 308 309static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 310 [ECMR] = 0x0160, 311 [ECSR] = 0x0164, 312 [ECSIPR] = 0x0168, 313 [PIR] = 0x016c, 314 [MAHR] = 0x0170, 315 [MALR] = 0x0174, 316 [RFLR] = 0x0178, 317 [PSR] = 0x017c, 318 [TROCR] = 0x0180, 319 [CDCR] = 0x0184, 320 [LCCR] = 0x0188, 321 [CNDCR] = 0x018c, 322 [CEFCR] = 0x0194, 323 [FRECR] = 0x0198, 324 [TSFRCR] = 0x019c, 325 [TLFRCR] = 0x01a0, 326 [RFCR] = 0x01a4, 327 [MAFCR] = 0x01a8, 328 [IPGR] = 0x01b4, 329 [APR] = 0x01b8, 330 [MPR] = 0x01bc, 331 [TPAUSER] = 0x01c4, 332 [BCFR] = 0x01cc, 333 334 [ARSTR] = 0x0000, 335 [TSU_CTRST] = 0x0004, 336 [TSU_FWEN0] = 0x0010, 337 [TSU_FWEN1] = 0x0014, 338 [TSU_FCM] = 0x0018, 339 [TSU_BSYSL0] = 0x0020, 340 [TSU_BSYSL1] = 0x0024, 341 [TSU_PRISL0] = 0x0028, 342 [TSU_PRISL1] = 0x002c, 343 [TSU_FWSL0] = 0x0030, 344 [TSU_FWSL1] = 0x0034, 345 [TSU_FWSLC] = 0x0038, 346 [TSU_QTAGM0] = 0x0040, 347 [TSU_QTAGM1] = 0x0044, 348 [TSU_ADQT0] = 0x0048, 349 [TSU_ADQT1] = 0x004c, 350 [TSU_FWSR] = 0x0050, 351 [TSU_FWINMK] = 0x0054, 352 [TSU_ADSBSY] = 0x0060, 353 [TSU_TEN] = 0x0064, 354 [TSU_POST1] = 0x0070, 355 [TSU_POST2] = 0x0074, 356 [TSU_POST3] = 0x0078, 357 [TSU_POST4] = 0x007c, 358 359 [TXNLCR0] = 0x0080, 360 [TXALCR0] = 0x0084, 361 [RXNLCR0] = 0x0088, 362 [RXALCR0] = 0x008c, 363 [FWNLCR0] = 0x0090, 364 [FWALCR0] = 0x0094, 365 [TXNLCR1] = 0x00a0, 366 [TXALCR1] = 0x00a0, 367 [RXNLCR1] = 0x00a8, 368 [RXALCR1] = 0x00ac, 369 [FWNLCR1] = 0x00b0, 370 [FWALCR1] = 0x00b4, 371 372 [TSU_ADRH0] = 0x0100, 373 [TSU_ADRL0] = 0x0104, 374 [TSU_ADRL31] = 0x01fc, 375}; 376 377static bool sh_eth_is_gether(struct sh_eth_private *mdp) 378{ 379 return mdp->reg_offset == sh_eth_offset_gigabit; 380} 381 382static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp) 383{ 384 return mdp->reg_offset == sh_eth_offset_fast_rz; 385} 386 387static void sh_eth_select_mii(struct net_device *ndev) 388{ 389 u32 value = 0x0; 390 struct sh_eth_private *mdp = netdev_priv(ndev); 391 392 switch (mdp->phy_interface) { 393 case PHY_INTERFACE_MODE_GMII: 394 value = 0x2; 395 break; 396 case PHY_INTERFACE_MODE_MII: 397 value = 0x1; 398 break; 399 case PHY_INTERFACE_MODE_RMII: 400 value = 0x0; 401 break; 402 default: 403 pr_warn("PHY interface mode was not setup. Set to MII.\n"); 404 value = 0x1; 405 break; 406 } 407 408 sh_eth_write(ndev, value, RMII_MII); 409} 410 411static void sh_eth_set_duplex(struct net_device *ndev) 412{ 413 struct sh_eth_private *mdp = netdev_priv(ndev); 414 415 if (mdp->duplex) /* Full */ 416 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 417 else /* Half */ 418 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 419} 420 421/* There is CPU dependent code */ 422static void sh_eth_set_rate_r8a777x(struct net_device *ndev) 423{ 424 struct sh_eth_private *mdp = netdev_priv(ndev); 425 426 switch (mdp->speed) { 427 case 10: /* 10BASE */ 428 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR); 429 break; 430 case 100:/* 100BASE */ 431 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR); 432 break; 433 default: 434 break; 435 } 436} 437 438/* R8A7778/9 */ 439static struct sh_eth_cpu_data r8a777x_data = { 440 .set_duplex = sh_eth_set_duplex, 441 .set_rate = sh_eth_set_rate_r8a777x, 442 443 .register_type = SH_ETH_REG_FAST_RCAR, 444 445 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 446 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 447 .eesipr_value = 0x01ff009f, 448 449 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 450 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 451 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 452 EESR_ECI, 453 454 .apr = 1, 455 .mpr = 1, 456 .tpauser = 1, 457 .hw_swap = 1, 458}; 459 460/* R8A7790/1 */ 461static struct sh_eth_cpu_data r8a779x_data = { 462 .set_duplex = sh_eth_set_duplex, 463 .set_rate = sh_eth_set_rate_r8a777x, 464 465 .register_type = SH_ETH_REG_FAST_RCAR, 466 467 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 468 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 469 .eesipr_value = 0x01ff009f, 470 471 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 472 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 473 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 474 EESR_ECI, 475 476 .apr = 1, 477 .mpr = 1, 478 .tpauser = 1, 479 .hw_swap = 1, 480 .rmiimode = 1, 481 .shift_rd0 = 1, 482}; 483 484static void sh_eth_set_rate_sh7724(struct net_device *ndev) 485{ 486 struct sh_eth_private *mdp = netdev_priv(ndev); 487 488 switch (mdp->speed) { 489 case 10: /* 10BASE */ 490 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 491 break; 492 case 100:/* 100BASE */ 493 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 494 break; 495 default: 496 break; 497 } 498} 499 500/* SH7724 */ 501static struct sh_eth_cpu_data sh7724_data = { 502 .set_duplex = sh_eth_set_duplex, 503 .set_rate = sh_eth_set_rate_sh7724, 504 505 .register_type = SH_ETH_REG_FAST_SH4, 506 507 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 508 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 509 .eesipr_value = 0x01ff009f, 510 511 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 512 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 513 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 514 EESR_ECI, 515 516 .apr = 1, 517 .mpr = 1, 518 .tpauser = 1, 519 .hw_swap = 1, 520 .rpadir = 1, 521 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 522}; 523 524static void sh_eth_set_rate_sh7757(struct net_device *ndev) 525{ 526 struct sh_eth_private *mdp = netdev_priv(ndev); 527 528 switch (mdp->speed) { 529 case 10: /* 10BASE */ 530 sh_eth_write(ndev, 0, RTRATE); 531 break; 532 case 100:/* 100BASE */ 533 sh_eth_write(ndev, 1, RTRATE); 534 break; 535 default: 536 break; 537 } 538} 539 540/* SH7757 */ 541static struct sh_eth_cpu_data sh7757_data = { 542 .set_duplex = sh_eth_set_duplex, 543 .set_rate = sh_eth_set_rate_sh7757, 544 545 .register_type = SH_ETH_REG_FAST_SH4, 546 547 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 548 .rmcr_value = RMCR_RNC, 549 550 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 551 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 552 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 553 EESR_ECI, 554 555 .irq_flags = IRQF_SHARED, 556 .apr = 1, 557 .mpr = 1, 558 .tpauser = 1, 559 .hw_swap = 1, 560 .no_ade = 1, 561 .rpadir = 1, 562 .rpadir_value = 2 << 16, 563}; 564 565#define SH_GIGA_ETH_BASE 0xfee00000UL 566#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 567#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 568static void sh_eth_chip_reset_giga(struct net_device *ndev) 569{ 570 int i; 571 unsigned long mahr[2], malr[2]; 572 573 /* save MAHR and MALR */ 574 for (i = 0; i < 2; i++) { 575 malr[i] = ioread32((void *)GIGA_MALR(i)); 576 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 577 } 578 579 /* reset device */ 580 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 581 mdelay(1); 582 583 /* restore MAHR and MALR */ 584 for (i = 0; i < 2; i++) { 585 iowrite32(malr[i], (void *)GIGA_MALR(i)); 586 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 587 } 588} 589 590static void sh_eth_set_rate_giga(struct net_device *ndev) 591{ 592 struct sh_eth_private *mdp = netdev_priv(ndev); 593 594 switch (mdp->speed) { 595 case 10: /* 10BASE */ 596 sh_eth_write(ndev, 0x00000000, GECMR); 597 break; 598 case 100:/* 100BASE */ 599 sh_eth_write(ndev, 0x00000010, GECMR); 600 break; 601 case 1000: /* 1000BASE */ 602 sh_eth_write(ndev, 0x00000020, GECMR); 603 break; 604 default: 605 break; 606 } 607} 608 609/* SH7757(GETHERC) */ 610static struct sh_eth_cpu_data sh7757_data_giga = { 611 .chip_reset = sh_eth_chip_reset_giga, 612 .set_duplex = sh_eth_set_duplex, 613 .set_rate = sh_eth_set_rate_giga, 614 615 .register_type = SH_ETH_REG_GIGABIT, 616 617 .ecsr_value = ECSR_ICD | ECSR_MPD, 618 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 619 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 620 621 .tx_check = EESR_TC1 | EESR_FTC, 622 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 623 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 624 EESR_TDE | EESR_ECI, 625 .fdr_value = 0x0000072f, 626 .rmcr_value = RMCR_RNC, 627 628 .irq_flags = IRQF_SHARED, 629 .apr = 1, 630 .mpr = 1, 631 .tpauser = 1, 632 .bculr = 1, 633 .hw_swap = 1, 634 .rpadir = 1, 635 .rpadir_value = 2 << 16, 636 .no_trimd = 1, 637 .no_ade = 1, 638 .tsu = 1, 639}; 640 641static void sh_eth_chip_reset(struct net_device *ndev) 642{ 643 struct sh_eth_private *mdp = netdev_priv(ndev); 644 645 /* reset device */ 646 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 647 mdelay(1); 648} 649 650static void sh_eth_set_rate_gether(struct net_device *ndev) 651{ 652 struct sh_eth_private *mdp = netdev_priv(ndev); 653 654 switch (mdp->speed) { 655 case 10: /* 10BASE */ 656 sh_eth_write(ndev, GECMR_10, GECMR); 657 break; 658 case 100:/* 100BASE */ 659 sh_eth_write(ndev, GECMR_100, GECMR); 660 break; 661 case 1000: /* 1000BASE */ 662 sh_eth_write(ndev, GECMR_1000, GECMR); 663 break; 664 default: 665 break; 666 } 667} 668 669/* SH7734 */ 670static struct sh_eth_cpu_data sh7734_data = { 671 .chip_reset = sh_eth_chip_reset, 672 .set_duplex = sh_eth_set_duplex, 673 .set_rate = sh_eth_set_rate_gether, 674 675 .register_type = SH_ETH_REG_GIGABIT, 676 677 .ecsr_value = ECSR_ICD | ECSR_MPD, 678 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 679 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 680 681 .tx_check = EESR_TC1 | EESR_FTC, 682 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 683 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 684 EESR_TDE | EESR_ECI, 685 686 .apr = 1, 687 .mpr = 1, 688 .tpauser = 1, 689 .bculr = 1, 690 .hw_swap = 1, 691 .no_trimd = 1, 692 .no_ade = 1, 693 .tsu = 1, 694 .hw_crc = 1, 695 .select_mii = 1, 696}; 697 698/* SH7763 */ 699static struct sh_eth_cpu_data sh7763_data = { 700 .chip_reset = sh_eth_chip_reset, 701 .set_duplex = sh_eth_set_duplex, 702 .set_rate = sh_eth_set_rate_gether, 703 704 .register_type = SH_ETH_REG_GIGABIT, 705 706 .ecsr_value = ECSR_ICD | ECSR_MPD, 707 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 708 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 709 710 .tx_check = EESR_TC1 | EESR_FTC, 711 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 712 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 713 EESR_ECI, 714 715 .apr = 1, 716 .mpr = 1, 717 .tpauser = 1, 718 .bculr = 1, 719 .hw_swap = 1, 720 .no_trimd = 1, 721 .no_ade = 1, 722 .tsu = 1, 723 .irq_flags = IRQF_SHARED, 724}; 725 726static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 727{ 728 struct sh_eth_private *mdp = netdev_priv(ndev); 729 730 /* reset device */ 731 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 732 mdelay(1); 733 734 sh_eth_select_mii(ndev); 735} 736 737/* R8A7740 */ 738static struct sh_eth_cpu_data r8a7740_data = { 739 .chip_reset = sh_eth_chip_reset_r8a7740, 740 .set_duplex = sh_eth_set_duplex, 741 .set_rate = sh_eth_set_rate_gether, 742 743 .register_type = SH_ETH_REG_GIGABIT, 744 745 .ecsr_value = ECSR_ICD | ECSR_MPD, 746 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 747 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 748 749 .tx_check = EESR_TC1 | EESR_FTC, 750 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 751 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 752 EESR_TDE | EESR_ECI, 753 .fdr_value = 0x0000070f, 754 .rmcr_value = RMCR_RNC, 755 756 .apr = 1, 757 .mpr = 1, 758 .tpauser = 1, 759 .bculr = 1, 760 .hw_swap = 1, 761 .rpadir = 1, 762 .rpadir_value = 2 << 16, 763 .no_trimd = 1, 764 .no_ade = 1, 765 .tsu = 1, 766 .select_mii = 1, 767 .shift_rd0 = 1, 768}; 769 770/* R7S72100 */ 771static struct sh_eth_cpu_data r7s72100_data = { 772 .chip_reset = sh_eth_chip_reset, 773 .set_duplex = sh_eth_set_duplex, 774 775 .register_type = SH_ETH_REG_FAST_RZ, 776 777 .ecsr_value = ECSR_ICD, 778 .ecsipr_value = ECSIPR_ICDIP, 779 .eesipr_value = 0xff7f009f, 780 781 .tx_check = EESR_TC1 | EESR_FTC, 782 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 783 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 784 EESR_TDE | EESR_ECI, 785 .fdr_value = 0x0000070f, 786 .rmcr_value = RMCR_RNC, 787 788 .no_psr = 1, 789 .apr = 1, 790 .mpr = 1, 791 .tpauser = 1, 792 .hw_swap = 1, 793 .rpadir = 1, 794 .rpadir_value = 2 << 16, 795 .no_trimd = 1, 796 .no_ade = 1, 797 .hw_crc = 1, 798 .tsu = 1, 799 .shift_rd0 = 1, 800}; 801 802static struct sh_eth_cpu_data sh7619_data = { 803 .register_type = SH_ETH_REG_FAST_SH3_SH2, 804 805 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 806 807 .apr = 1, 808 .mpr = 1, 809 .tpauser = 1, 810 .hw_swap = 1, 811}; 812 813static struct sh_eth_cpu_data sh771x_data = { 814 .register_type = SH_ETH_REG_FAST_SH3_SH2, 815 816 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 817 .tsu = 1, 818}; 819 820static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 821{ 822 if (!cd->ecsr_value) 823 cd->ecsr_value = DEFAULT_ECSR_INIT; 824 825 if (!cd->ecsipr_value) 826 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 827 828 if (!cd->fcftr_value) 829 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 830 DEFAULT_FIFO_F_D_RFD; 831 832 if (!cd->fdr_value) 833 cd->fdr_value = DEFAULT_FDR_INIT; 834 835 if (!cd->rmcr_value) 836 cd->rmcr_value = DEFAULT_RMCR_VALUE; 837 838 if (!cd->tx_check) 839 cd->tx_check = DEFAULT_TX_CHECK; 840 841 if (!cd->eesr_err_check) 842 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 843} 844 845static int sh_eth_check_reset(struct net_device *ndev) 846{ 847 int ret = 0; 848 int cnt = 100; 849 850 while (cnt > 0) { 851 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 852 break; 853 mdelay(1); 854 cnt--; 855 } 856 if (cnt <= 0) { 857 pr_err("Device reset failed\n"); 858 ret = -ETIMEDOUT; 859 } 860 return ret; 861} 862 863static int sh_eth_reset(struct net_device *ndev) 864{ 865 struct sh_eth_private *mdp = netdev_priv(ndev); 866 int ret = 0; 867 868 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) { 869 sh_eth_write(ndev, EDSR_ENALL, EDSR); 870 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 871 EDMR); 872 873 ret = sh_eth_check_reset(ndev); 874 if (ret) 875 goto out; 876 877 /* Table Init */ 878 sh_eth_write(ndev, 0x0, TDLAR); 879 sh_eth_write(ndev, 0x0, TDFAR); 880 sh_eth_write(ndev, 0x0, TDFXR); 881 sh_eth_write(ndev, 0x0, TDFFR); 882 sh_eth_write(ndev, 0x0, RDLAR); 883 sh_eth_write(ndev, 0x0, RDFAR); 884 sh_eth_write(ndev, 0x0, RDFXR); 885 sh_eth_write(ndev, 0x0, RDFFR); 886 887 /* Reset HW CRC register */ 888 if (mdp->cd->hw_crc) 889 sh_eth_write(ndev, 0x0, CSMR); 890 891 /* Select MII mode */ 892 if (mdp->cd->select_mii) 893 sh_eth_select_mii(ndev); 894 } else { 895 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 896 EDMR); 897 mdelay(3); 898 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 899 EDMR); 900 } 901 902out: 903 return ret; 904} 905 906#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 907static void sh_eth_set_receive_align(struct sk_buff *skb) 908{ 909 int reserve; 910 911 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); 912 if (reserve) 913 skb_reserve(skb, reserve); 914} 915#else 916static void sh_eth_set_receive_align(struct sk_buff *skb) 917{ 918 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); 919} 920#endif 921 922 923/* CPU <-> EDMAC endian convert */ 924static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 925{ 926 switch (mdp->edmac_endian) { 927 case EDMAC_LITTLE_ENDIAN: 928 return cpu_to_le32(x); 929 case EDMAC_BIG_ENDIAN: 930 return cpu_to_be32(x); 931 } 932 return x; 933} 934 935static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) 936{ 937 switch (mdp->edmac_endian) { 938 case EDMAC_LITTLE_ENDIAN: 939 return le32_to_cpu(x); 940 case EDMAC_BIG_ENDIAN: 941 return be32_to_cpu(x); 942 } 943 return x; 944} 945 946/* Program the hardware MAC address from dev->dev_addr. */ 947static void update_mac_address(struct net_device *ndev) 948{ 949 sh_eth_write(ndev, 950 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 951 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 952 sh_eth_write(ndev, 953 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 954} 955 956/* Get MAC address from SuperH MAC address register 957 * 958 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 959 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 960 * When you want use this device, you must set MAC address in bootloader. 961 * 962 */ 963static void read_mac_address(struct net_device *ndev, unsigned char *mac) 964{ 965 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 966 memcpy(ndev->dev_addr, mac, ETH_ALEN); 967 } else { 968 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24); 969 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF; 970 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF; 971 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF); 972 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF; 973 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF); 974 } 975} 976 977static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 978{ 979 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) 980 return EDTRR_TRNS_GETHER; 981 else 982 return EDTRR_TRNS_ETHER; 983} 984 985struct bb_info { 986 void (*set_gate)(void *addr); 987 struct mdiobb_ctrl ctrl; 988 void *addr; 989 u32 mmd_msk;/* MMD */ 990 u32 mdo_msk; 991 u32 mdi_msk; 992 u32 mdc_msk; 993}; 994 995/* PHY bit set */ 996static void bb_set(void *addr, u32 msk) 997{ 998 iowrite32(ioread32(addr) | msk, addr); 999} 1000 1001/* PHY bit clear */ 1002static void bb_clr(void *addr, u32 msk) 1003{ 1004 iowrite32((ioread32(addr) & ~msk), addr); 1005} 1006 1007/* PHY bit read */ 1008static int bb_read(void *addr, u32 msk) 1009{ 1010 return (ioread32(addr) & msk) != 0; 1011} 1012 1013/* Data I/O pin control */ 1014static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1015{ 1016 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1017 1018 if (bitbang->set_gate) 1019 bitbang->set_gate(bitbang->addr); 1020 1021 if (bit) 1022 bb_set(bitbang->addr, bitbang->mmd_msk); 1023 else 1024 bb_clr(bitbang->addr, bitbang->mmd_msk); 1025} 1026 1027/* Set bit data*/ 1028static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1029{ 1030 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1031 1032 if (bitbang->set_gate) 1033 bitbang->set_gate(bitbang->addr); 1034 1035 if (bit) 1036 bb_set(bitbang->addr, bitbang->mdo_msk); 1037 else 1038 bb_clr(bitbang->addr, bitbang->mdo_msk); 1039} 1040 1041/* Get bit data*/ 1042static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1043{ 1044 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1045 1046 if (bitbang->set_gate) 1047 bitbang->set_gate(bitbang->addr); 1048 1049 return bb_read(bitbang->addr, bitbang->mdi_msk); 1050} 1051 1052/* MDC pin control */ 1053static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1054{ 1055 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1056 1057 if (bitbang->set_gate) 1058 bitbang->set_gate(bitbang->addr); 1059 1060 if (bit) 1061 bb_set(bitbang->addr, bitbang->mdc_msk); 1062 else 1063 bb_clr(bitbang->addr, bitbang->mdc_msk); 1064} 1065 1066/* mdio bus control struct */ 1067static struct mdiobb_ops bb_ops = { 1068 .owner = THIS_MODULE, 1069 .set_mdc = sh_mdc_ctrl, 1070 .set_mdio_dir = sh_mmd_ctrl, 1071 .set_mdio_data = sh_set_mdio, 1072 .get_mdio_data = sh_get_mdio, 1073}; 1074 1075/* free skb and descriptor buffer */ 1076static void sh_eth_ring_free(struct net_device *ndev) 1077{ 1078 struct sh_eth_private *mdp = netdev_priv(ndev); 1079 int i; 1080 1081 /* Free Rx skb ringbuffer */ 1082 if (mdp->rx_skbuff) { 1083 for (i = 0; i < mdp->num_rx_ring; i++) { 1084 if (mdp->rx_skbuff[i]) 1085 dev_kfree_skb(mdp->rx_skbuff[i]); 1086 } 1087 } 1088 kfree(mdp->rx_skbuff); 1089 mdp->rx_skbuff = NULL; 1090 1091 /* Free Tx skb ringbuffer */ 1092 if (mdp->tx_skbuff) { 1093 for (i = 0; i < mdp->num_tx_ring; i++) { 1094 if (mdp->tx_skbuff[i]) 1095 dev_kfree_skb(mdp->tx_skbuff[i]); 1096 } 1097 } 1098 kfree(mdp->tx_skbuff); 1099 mdp->tx_skbuff = NULL; 1100} 1101 1102/* format skb and descriptor buffer */ 1103static void sh_eth_ring_format(struct net_device *ndev) 1104{ 1105 struct sh_eth_private *mdp = netdev_priv(ndev); 1106 int i; 1107 struct sk_buff *skb; 1108 struct sh_eth_rxdesc *rxdesc = NULL; 1109 struct sh_eth_txdesc *txdesc = NULL; 1110 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1111 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1112 1113 mdp->cur_rx = 0; 1114 mdp->cur_tx = 0; 1115 mdp->dirty_rx = 0; 1116 mdp->dirty_tx = 0; 1117 1118 memset(mdp->rx_ring, 0, rx_ringsize); 1119 1120 /* build Rx ring buffer */ 1121 for (i = 0; i < mdp->num_rx_ring; i++) { 1122 /* skb */ 1123 mdp->rx_skbuff[i] = NULL; 1124 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1125 mdp->rx_skbuff[i] = skb; 1126 if (skb == NULL) 1127 break; 1128 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1129 DMA_FROM_DEVICE); 1130 sh_eth_set_receive_align(skb); 1131 1132 /* RX descriptor */ 1133 rxdesc = &mdp->rx_ring[i]; 1134 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1135 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1136 1137 /* The size of the buffer is 16 byte boundary. */ 1138 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1139 /* Rx descriptor address set */ 1140 if (i == 0) { 1141 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1142 if (sh_eth_is_gether(mdp) || 1143 sh_eth_is_rz_fast_ether(mdp)) 1144 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1145 } 1146 } 1147 1148 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1149 1150 /* Mark the last entry as wrapping the ring. */ 1151 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); 1152 1153 memset(mdp->tx_ring, 0, tx_ringsize); 1154 1155 /* build Tx ring buffer */ 1156 for (i = 0; i < mdp->num_tx_ring; i++) { 1157 mdp->tx_skbuff[i] = NULL; 1158 txdesc = &mdp->tx_ring[i]; 1159 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1160 txdesc->buffer_length = 0; 1161 if (i == 0) { 1162 /* Tx descriptor address set */ 1163 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1164 if (sh_eth_is_gether(mdp) || 1165 sh_eth_is_rz_fast_ether(mdp)) 1166 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1167 } 1168 } 1169 1170 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1171} 1172 1173/* Get skb and descriptor buffer */ 1174static int sh_eth_ring_init(struct net_device *ndev) 1175{ 1176 struct sh_eth_private *mdp = netdev_priv(ndev); 1177 int rx_ringsize, tx_ringsize, ret = 0; 1178 1179 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1180 * card needs room to do 8 byte alignment, +2 so we can reserve 1181 * the first 2 bytes, and +16 gets room for the status word from the 1182 * card. 1183 */ 1184 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1185 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1186 if (mdp->cd->rpadir) 1187 mdp->rx_buf_sz += NET_IP_ALIGN; 1188 1189 /* Allocate RX and TX skb rings */ 1190 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring, 1191 sizeof(*mdp->rx_skbuff), GFP_KERNEL); 1192 if (!mdp->rx_skbuff) { 1193 ret = -ENOMEM; 1194 return ret; 1195 } 1196 1197 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring, 1198 sizeof(*mdp->tx_skbuff), GFP_KERNEL); 1199 if (!mdp->tx_skbuff) { 1200 ret = -ENOMEM; 1201 goto skb_ring_free; 1202 } 1203 1204 /* Allocate all Rx descriptors. */ 1205 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1206 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 1207 GFP_KERNEL); 1208 if (!mdp->rx_ring) { 1209 ret = -ENOMEM; 1210 goto desc_ring_free; 1211 } 1212 1213 mdp->dirty_rx = 0; 1214 1215 /* Allocate all Tx descriptors. */ 1216 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1217 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 1218 GFP_KERNEL); 1219 if (!mdp->tx_ring) { 1220 ret = -ENOMEM; 1221 goto desc_ring_free; 1222 } 1223 return ret; 1224 1225desc_ring_free: 1226 /* free DMA buffer */ 1227 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); 1228 1229skb_ring_free: 1230 /* Free Rx and Tx skb ring buffer */ 1231 sh_eth_ring_free(ndev); 1232 mdp->tx_ring = NULL; 1233 mdp->rx_ring = NULL; 1234 1235 return ret; 1236} 1237 1238static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp) 1239{ 1240 int ringsize; 1241 1242 if (mdp->rx_ring) { 1243 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1244 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 1245 mdp->rx_desc_dma); 1246 mdp->rx_ring = NULL; 1247 } 1248 1249 if (mdp->tx_ring) { 1250 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1251 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 1252 mdp->tx_desc_dma); 1253 mdp->tx_ring = NULL; 1254 } 1255} 1256 1257static int sh_eth_dev_init(struct net_device *ndev, bool start) 1258{ 1259 int ret = 0; 1260 struct sh_eth_private *mdp = netdev_priv(ndev); 1261 u32 val; 1262 1263 /* Soft Reset */ 1264 ret = sh_eth_reset(ndev); 1265 if (ret) 1266 goto out; 1267 1268 if (mdp->cd->rmiimode) 1269 sh_eth_write(ndev, 0x1, RMIIMODE); 1270 1271 /* Descriptor format */ 1272 sh_eth_ring_format(ndev); 1273 if (mdp->cd->rpadir) 1274 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1275 1276 /* all sh_eth int mask */ 1277 sh_eth_write(ndev, 0, EESIPR); 1278 1279#if defined(__LITTLE_ENDIAN) 1280 if (mdp->cd->hw_swap) 1281 sh_eth_write(ndev, EDMR_EL, EDMR); 1282 else 1283#endif 1284 sh_eth_write(ndev, 0, EDMR); 1285 1286 /* FIFO size set */ 1287 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1288 sh_eth_write(ndev, 0, TFTR); 1289 1290 /* Frame recv control */ 1291 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR); 1292 1293 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER); 1294 1295 if (mdp->cd->bculr) 1296 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1297 1298 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1299 1300 if (!mdp->cd->no_trimd) 1301 sh_eth_write(ndev, 0, TRIMD); 1302 1303 /* Recv frame limit set register */ 1304 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1305 RFLR); 1306 1307 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 1308 if (start) 1309 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1310 1311 /* PAUSE Prohibition */ 1312 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | 1313 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 1314 1315 sh_eth_write(ndev, val, ECMR); 1316 1317 if (mdp->cd->set_rate) 1318 mdp->cd->set_rate(ndev); 1319 1320 /* E-MAC Status Register clear */ 1321 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1322 1323 /* E-MAC Interrupt Enable register */ 1324 if (start) 1325 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1326 1327 /* Set MAC address */ 1328 update_mac_address(ndev); 1329 1330 /* mask reset */ 1331 if (mdp->cd->apr) 1332 sh_eth_write(ndev, APR_AP, APR); 1333 if (mdp->cd->mpr) 1334 sh_eth_write(ndev, MPR_MP, MPR); 1335 if (mdp->cd->tpauser) 1336 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1337 1338 if (start) { 1339 /* Setting the Rx mode will start the Rx process. */ 1340 sh_eth_write(ndev, EDRRR_R, EDRRR); 1341 1342 netif_start_queue(ndev); 1343 } 1344 1345out: 1346 return ret; 1347} 1348 1349/* free Tx skb function */ 1350static int sh_eth_txfree(struct net_device *ndev) 1351{ 1352 struct sh_eth_private *mdp = netdev_priv(ndev); 1353 struct sh_eth_txdesc *txdesc; 1354 int free_num = 0; 1355 int entry = 0; 1356 1357 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1358 entry = mdp->dirty_tx % mdp->num_tx_ring; 1359 txdesc = &mdp->tx_ring[entry]; 1360 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 1361 break; 1362 /* Free the original skb. */ 1363 if (mdp->tx_skbuff[entry]) { 1364 dma_unmap_single(&ndev->dev, txdesc->addr, 1365 txdesc->buffer_length, DMA_TO_DEVICE); 1366 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1367 mdp->tx_skbuff[entry] = NULL; 1368 free_num++; 1369 } 1370 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1371 if (entry >= mdp->num_tx_ring - 1) 1372 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1373 1374 ndev->stats.tx_packets++; 1375 ndev->stats.tx_bytes += txdesc->buffer_length; 1376 } 1377 return free_num; 1378} 1379 1380/* Packet receive function */ 1381static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1382{ 1383 struct sh_eth_private *mdp = netdev_priv(ndev); 1384 struct sh_eth_rxdesc *rxdesc; 1385 1386 int entry = mdp->cur_rx % mdp->num_rx_ring; 1387 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1388 struct sk_buff *skb; 1389 int exceeded = 0; 1390 u16 pkt_len = 0; 1391 u32 desc_status; 1392 1393 rxdesc = &mdp->rx_ring[entry]; 1394 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1395 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1396 pkt_len = rxdesc->frame_length; 1397 1398 if (--boguscnt < 0) 1399 break; 1400 1401 if (*quota <= 0) { 1402 exceeded = 1; 1403 break; 1404 } 1405 (*quota)--; 1406 1407 if (!(desc_status & RDFEND)) 1408 ndev->stats.rx_length_errors++; 1409 1410 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1411 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1412 * bit 0. However, in case of the R8A7740, R8A779x, and 1413 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the 1414 * driver needs right shifting by 16. 1415 */ 1416 if (mdp->cd->shift_rd0) 1417 desc_status >>= 16; 1418 1419 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1420 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1421 ndev->stats.rx_errors++; 1422 if (desc_status & RD_RFS1) 1423 ndev->stats.rx_crc_errors++; 1424 if (desc_status & RD_RFS2) 1425 ndev->stats.rx_frame_errors++; 1426 if (desc_status & RD_RFS3) 1427 ndev->stats.rx_length_errors++; 1428 if (desc_status & RD_RFS4) 1429 ndev->stats.rx_length_errors++; 1430 if (desc_status & RD_RFS6) 1431 ndev->stats.rx_missed_errors++; 1432 if (desc_status & RD_RFS10) 1433 ndev->stats.rx_over_errors++; 1434 } else { 1435 if (!mdp->cd->hw_swap) 1436 sh_eth_soft_swap( 1437 phys_to_virt(ALIGN(rxdesc->addr, 4)), 1438 pkt_len + 2); 1439 skb = mdp->rx_skbuff[entry]; 1440 mdp->rx_skbuff[entry] = NULL; 1441 if (mdp->cd->rpadir) 1442 skb_reserve(skb, NET_IP_ALIGN); 1443 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr, 1444 mdp->rx_buf_sz, 1445 DMA_FROM_DEVICE); 1446 skb_put(skb, pkt_len); 1447 skb->protocol = eth_type_trans(skb, ndev); 1448 netif_receive_skb(skb); 1449 ndev->stats.rx_packets++; 1450 ndev->stats.rx_bytes += pkt_len; 1451 } 1452 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); 1453 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1454 rxdesc = &mdp->rx_ring[entry]; 1455 } 1456 1457 /* Refill the Rx ring buffers. */ 1458 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1459 entry = mdp->dirty_rx % mdp->num_rx_ring; 1460 rxdesc = &mdp->rx_ring[entry]; 1461 /* The size of the buffer is 16 byte boundary. */ 1462 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1463 1464 if (mdp->rx_skbuff[entry] == NULL) { 1465 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1466 mdp->rx_skbuff[entry] = skb; 1467 if (skb == NULL) 1468 break; /* Better luck next round. */ 1469 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1470 DMA_FROM_DEVICE); 1471 sh_eth_set_receive_align(skb); 1472 1473 skb_checksum_none_assert(skb); 1474 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1475 } 1476 if (entry >= mdp->num_rx_ring - 1) 1477 rxdesc->status |= 1478 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1479 else 1480 rxdesc->status |= 1481 cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1482 } 1483 1484 /* Restart Rx engine if stopped. */ 1485 /* If we don't need to check status, don't. -KDU */ 1486 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1487 /* fix the values for the next receiving if RDE is set */ 1488 if (intr_status & EESR_RDE) { 1489 u32 count = (sh_eth_read(ndev, RDFAR) - 1490 sh_eth_read(ndev, RDLAR)) >> 4; 1491 1492 mdp->cur_rx = count; 1493 mdp->dirty_rx = count; 1494 } 1495 sh_eth_write(ndev, EDRRR_R, EDRRR); 1496 } 1497 1498 return exceeded; 1499} 1500 1501static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1502{ 1503 /* disable tx and rx */ 1504 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1505 ~(ECMR_RE | ECMR_TE), ECMR); 1506} 1507 1508static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1509{ 1510 /* enable tx and rx */ 1511 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1512 (ECMR_RE | ECMR_TE), ECMR); 1513} 1514 1515/* error control function */ 1516static void sh_eth_error(struct net_device *ndev, int intr_status) 1517{ 1518 struct sh_eth_private *mdp = netdev_priv(ndev); 1519 u32 felic_stat; 1520 u32 link_stat; 1521 u32 mask; 1522 1523 if (intr_status & EESR_ECI) { 1524 felic_stat = sh_eth_read(ndev, ECSR); 1525 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1526 if (felic_stat & ECSR_ICD) 1527 ndev->stats.tx_carrier_errors++; 1528 if (felic_stat & ECSR_LCHNG) { 1529 /* Link Changed */ 1530 if (mdp->cd->no_psr || mdp->no_ether_link) { 1531 goto ignore_link; 1532 } else { 1533 link_stat = (sh_eth_read(ndev, PSR)); 1534 if (mdp->ether_link_active_low) 1535 link_stat = ~link_stat; 1536 } 1537 if (!(link_stat & PHY_ST_LINK)) { 1538 sh_eth_rcv_snd_disable(ndev); 1539 } else { 1540 /* Link Up */ 1541 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1542 ~DMAC_M_ECI, EESIPR); 1543 /* clear int */ 1544 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1545 ECSR); 1546 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1547 DMAC_M_ECI, EESIPR); 1548 /* enable tx and rx */ 1549 sh_eth_rcv_snd_enable(ndev); 1550 } 1551 } 1552 } 1553 1554ignore_link: 1555 if (intr_status & EESR_TWB) { 1556 /* Unused write back interrupt */ 1557 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1558 ndev->stats.tx_aborted_errors++; 1559 if (netif_msg_tx_err(mdp)) 1560 dev_err(&ndev->dev, "Transmit Abort\n"); 1561 } 1562 } 1563 1564 if (intr_status & EESR_RABT) { 1565 /* Receive Abort int */ 1566 if (intr_status & EESR_RFRMER) { 1567 /* Receive Frame Overflow int */ 1568 ndev->stats.rx_frame_errors++; 1569 if (netif_msg_rx_err(mdp)) 1570 dev_err(&ndev->dev, "Receive Abort\n"); 1571 } 1572 } 1573 1574 if (intr_status & EESR_TDE) { 1575 /* Transmit Descriptor Empty int */ 1576 ndev->stats.tx_fifo_errors++; 1577 if (netif_msg_tx_err(mdp)) 1578 dev_err(&ndev->dev, "Transmit Descriptor Empty\n"); 1579 } 1580 1581 if (intr_status & EESR_TFE) { 1582 /* FIFO under flow */ 1583 ndev->stats.tx_fifo_errors++; 1584 if (netif_msg_tx_err(mdp)) 1585 dev_err(&ndev->dev, "Transmit FIFO Under flow\n"); 1586 } 1587 1588 if (intr_status & EESR_RDE) { 1589 /* Receive Descriptor Empty int */ 1590 ndev->stats.rx_over_errors++; 1591 1592 if (netif_msg_rx_err(mdp)) 1593 dev_err(&ndev->dev, "Receive Descriptor Empty\n"); 1594 } 1595 1596 if (intr_status & EESR_RFE) { 1597 /* Receive FIFO Overflow int */ 1598 ndev->stats.rx_fifo_errors++; 1599 if (netif_msg_rx_err(mdp)) 1600 dev_err(&ndev->dev, "Receive FIFO Overflow\n"); 1601 } 1602 1603 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1604 /* Address Error */ 1605 ndev->stats.tx_fifo_errors++; 1606 if (netif_msg_tx_err(mdp)) 1607 dev_err(&ndev->dev, "Address Error\n"); 1608 } 1609 1610 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1611 if (mdp->cd->no_ade) 1612 mask &= ~EESR_ADE; 1613 if (intr_status & mask) { 1614 /* Tx error */ 1615 u32 edtrr = sh_eth_read(ndev, EDTRR); 1616 1617 /* dmesg */ 1618 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1619 intr_status, mdp->cur_tx, mdp->dirty_tx, 1620 (u32)ndev->state, edtrr); 1621 /* dirty buffer free */ 1622 sh_eth_txfree(ndev); 1623 1624 /* SH7712 BUG */ 1625 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1626 /* tx dma start */ 1627 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1628 } 1629 /* wakeup */ 1630 netif_wake_queue(ndev); 1631 } 1632} 1633 1634static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1635{ 1636 struct net_device *ndev = netdev; 1637 struct sh_eth_private *mdp = netdev_priv(ndev); 1638 struct sh_eth_cpu_data *cd = mdp->cd; 1639 irqreturn_t ret = IRQ_NONE; 1640 unsigned long intr_status, intr_enable; 1641 1642 spin_lock(&mdp->lock); 1643 1644 /* Get interrupt status */ 1645 intr_status = sh_eth_read(ndev, EESR); 1646 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1647 * enabled since it's the one that comes thru regardless of the mask, 1648 * and we need to fully handle it in sh_eth_error() in order to quench 1649 * it as it doesn't get cleared by just writing 1 to the ECI bit... 1650 */ 1651 intr_enable = sh_eth_read(ndev, EESIPR); 1652 intr_status &= intr_enable | DMAC_M_ECI; 1653 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) 1654 ret = IRQ_HANDLED; 1655 else 1656 goto other_irq; 1657 1658 if (intr_status & EESR_RX_CHECK) { 1659 if (napi_schedule_prep(&mdp->napi)) { 1660 /* Mask Rx interrupts */ 1661 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1662 EESIPR); 1663 __napi_schedule(&mdp->napi); 1664 } else { 1665 dev_warn(&ndev->dev, 1666 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n", 1667 intr_status, intr_enable); 1668 } 1669 } 1670 1671 /* Tx Check */ 1672 if (intr_status & cd->tx_check) { 1673 /* Clear Tx interrupts */ 1674 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1675 1676 sh_eth_txfree(ndev); 1677 netif_wake_queue(ndev); 1678 } 1679 1680 if (intr_status & cd->eesr_err_check) { 1681 /* Clear error interrupts */ 1682 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1683 1684 sh_eth_error(ndev, intr_status); 1685 } 1686 1687other_irq: 1688 spin_unlock(&mdp->lock); 1689 1690 return ret; 1691} 1692 1693static int sh_eth_poll(struct napi_struct *napi, int budget) 1694{ 1695 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1696 napi); 1697 struct net_device *ndev = napi->dev; 1698 int quota = budget; 1699 unsigned long intr_status; 1700 1701 for (;;) { 1702 intr_status = sh_eth_read(ndev, EESR); 1703 if (!(intr_status & EESR_RX_CHECK)) 1704 break; 1705 /* Clear Rx interrupts */ 1706 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1707 1708 if (sh_eth_rx(ndev, intr_status, "a)) 1709 goto out; 1710 } 1711 1712 napi_complete(napi); 1713 1714 /* Reenable Rx interrupts */ 1715 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1716out: 1717 return budget - quota; 1718} 1719 1720/* PHY state control function */ 1721static void sh_eth_adjust_link(struct net_device *ndev) 1722{ 1723 struct sh_eth_private *mdp = netdev_priv(ndev); 1724 struct phy_device *phydev = mdp->phydev; 1725 int new_state = 0; 1726 1727 if (phydev->link) { 1728 if (phydev->duplex != mdp->duplex) { 1729 new_state = 1; 1730 mdp->duplex = phydev->duplex; 1731 if (mdp->cd->set_duplex) 1732 mdp->cd->set_duplex(ndev); 1733 } 1734 1735 if (phydev->speed != mdp->speed) { 1736 new_state = 1; 1737 mdp->speed = phydev->speed; 1738 if (mdp->cd->set_rate) 1739 mdp->cd->set_rate(ndev); 1740 } 1741 if (!mdp->link) { 1742 sh_eth_write(ndev, 1743 sh_eth_read(ndev, ECMR) & ~ECMR_TXF, 1744 ECMR); 1745 new_state = 1; 1746 mdp->link = phydev->link; 1747 if (mdp->cd->no_psr || mdp->no_ether_link) 1748 sh_eth_rcv_snd_enable(ndev); 1749 } 1750 } else if (mdp->link) { 1751 new_state = 1; 1752 mdp->link = 0; 1753 mdp->speed = 0; 1754 mdp->duplex = -1; 1755 if (mdp->cd->no_psr || mdp->no_ether_link) 1756 sh_eth_rcv_snd_disable(ndev); 1757 } 1758 1759 if (new_state && netif_msg_link(mdp)) 1760 phy_print_status(phydev); 1761} 1762 1763/* PHY init function */ 1764static int sh_eth_phy_init(struct net_device *ndev) 1765{ 1766 struct device_node *np = ndev->dev.parent->of_node; 1767 struct sh_eth_private *mdp = netdev_priv(ndev); 1768 struct phy_device *phydev = NULL; 1769 1770 mdp->link = 0; 1771 mdp->speed = 0; 1772 mdp->duplex = -1; 1773 1774 /* Try connect to PHY */ 1775 if (np) { 1776 struct device_node *pn; 1777 1778 pn = of_parse_phandle(np, "phy-handle", 0); 1779 phydev = of_phy_connect(ndev, pn, 1780 sh_eth_adjust_link, 0, 1781 mdp->phy_interface); 1782 1783 if (!phydev) 1784 phydev = ERR_PTR(-ENOENT); 1785 } else { 1786 char phy_id[MII_BUS_ID_SIZE + 3]; 1787 1788 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1789 mdp->mii_bus->id, mdp->phy_id); 1790 1791 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1792 mdp->phy_interface); 1793 } 1794 1795 if (IS_ERR(phydev)) { 1796 dev_err(&ndev->dev, "failed to connect PHY\n"); 1797 return PTR_ERR(phydev); 1798 } 1799 1800 dev_info(&ndev->dev, "attached PHY %d (IRQ %d) to driver %s\n", 1801 phydev->addr, phydev->irq, phydev->drv->name); 1802 1803 mdp->phydev = phydev; 1804 1805 return 0; 1806} 1807 1808/* PHY control start function */ 1809static int sh_eth_phy_start(struct net_device *ndev) 1810{ 1811 struct sh_eth_private *mdp = netdev_priv(ndev); 1812 int ret; 1813 1814 ret = sh_eth_phy_init(ndev); 1815 if (ret) 1816 return ret; 1817 1818 phy_start(mdp->phydev); 1819 1820 return 0; 1821} 1822 1823static int sh_eth_get_settings(struct net_device *ndev, 1824 struct ethtool_cmd *ecmd) 1825{ 1826 struct sh_eth_private *mdp = netdev_priv(ndev); 1827 unsigned long flags; 1828 int ret; 1829 1830 spin_lock_irqsave(&mdp->lock, flags); 1831 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1832 spin_unlock_irqrestore(&mdp->lock, flags); 1833 1834 return ret; 1835} 1836 1837static int sh_eth_set_settings(struct net_device *ndev, 1838 struct ethtool_cmd *ecmd) 1839{ 1840 struct sh_eth_private *mdp = netdev_priv(ndev); 1841 unsigned long flags; 1842 int ret; 1843 1844 spin_lock_irqsave(&mdp->lock, flags); 1845 1846 /* disable tx and rx */ 1847 sh_eth_rcv_snd_disable(ndev); 1848 1849 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1850 if (ret) 1851 goto error_exit; 1852 1853 if (ecmd->duplex == DUPLEX_FULL) 1854 mdp->duplex = 1; 1855 else 1856 mdp->duplex = 0; 1857 1858 if (mdp->cd->set_duplex) 1859 mdp->cd->set_duplex(ndev); 1860 1861error_exit: 1862 mdelay(1); 1863 1864 /* enable tx and rx */ 1865 sh_eth_rcv_snd_enable(ndev); 1866 1867 spin_unlock_irqrestore(&mdp->lock, flags); 1868 1869 return ret; 1870} 1871 1872static int sh_eth_nway_reset(struct net_device *ndev) 1873{ 1874 struct sh_eth_private *mdp = netdev_priv(ndev); 1875 unsigned long flags; 1876 int ret; 1877 1878 spin_lock_irqsave(&mdp->lock, flags); 1879 ret = phy_start_aneg(mdp->phydev); 1880 spin_unlock_irqrestore(&mdp->lock, flags); 1881 1882 return ret; 1883} 1884 1885static u32 sh_eth_get_msglevel(struct net_device *ndev) 1886{ 1887 struct sh_eth_private *mdp = netdev_priv(ndev); 1888 return mdp->msg_enable; 1889} 1890 1891static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 1892{ 1893 struct sh_eth_private *mdp = netdev_priv(ndev); 1894 mdp->msg_enable = value; 1895} 1896 1897static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 1898 "rx_current", "tx_current", 1899 "rx_dirty", "tx_dirty", 1900}; 1901#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 1902 1903static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 1904{ 1905 switch (sset) { 1906 case ETH_SS_STATS: 1907 return SH_ETH_STATS_LEN; 1908 default: 1909 return -EOPNOTSUPP; 1910 } 1911} 1912 1913static void sh_eth_get_ethtool_stats(struct net_device *ndev, 1914 struct ethtool_stats *stats, u64 *data) 1915{ 1916 struct sh_eth_private *mdp = netdev_priv(ndev); 1917 int i = 0; 1918 1919 /* device-specific stats */ 1920 data[i++] = mdp->cur_rx; 1921 data[i++] = mdp->cur_tx; 1922 data[i++] = mdp->dirty_rx; 1923 data[i++] = mdp->dirty_tx; 1924} 1925 1926static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1927{ 1928 switch (stringset) { 1929 case ETH_SS_STATS: 1930 memcpy(data, *sh_eth_gstrings_stats, 1931 sizeof(sh_eth_gstrings_stats)); 1932 break; 1933 } 1934} 1935 1936static void sh_eth_get_ringparam(struct net_device *ndev, 1937 struct ethtool_ringparam *ring) 1938{ 1939 struct sh_eth_private *mdp = netdev_priv(ndev); 1940 1941 ring->rx_max_pending = RX_RING_MAX; 1942 ring->tx_max_pending = TX_RING_MAX; 1943 ring->rx_pending = mdp->num_rx_ring; 1944 ring->tx_pending = mdp->num_tx_ring; 1945} 1946 1947static int sh_eth_set_ringparam(struct net_device *ndev, 1948 struct ethtool_ringparam *ring) 1949{ 1950 struct sh_eth_private *mdp = netdev_priv(ndev); 1951 int ret; 1952 1953 if (ring->tx_pending > TX_RING_MAX || 1954 ring->rx_pending > RX_RING_MAX || 1955 ring->tx_pending < TX_RING_MIN || 1956 ring->rx_pending < RX_RING_MIN) 1957 return -EINVAL; 1958 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1959 return -EINVAL; 1960 1961 if (netif_running(ndev)) { 1962 netif_tx_disable(ndev); 1963 /* Disable interrupts by clearing the interrupt mask. */ 1964 sh_eth_write(ndev, 0x0000, EESIPR); 1965 /* Stop the chip's Tx and Rx processes. */ 1966 sh_eth_write(ndev, 0, EDTRR); 1967 sh_eth_write(ndev, 0, EDRRR); 1968 synchronize_irq(ndev->irq); 1969 } 1970 1971 /* Free all the skbuffs in the Rx queue. */ 1972 sh_eth_ring_free(ndev); 1973 /* Free DMA buffer */ 1974 sh_eth_free_dma_buffer(mdp); 1975 1976 /* Set new parameters */ 1977 mdp->num_rx_ring = ring->rx_pending; 1978 mdp->num_tx_ring = ring->tx_pending; 1979 1980 ret = sh_eth_ring_init(ndev); 1981 if (ret < 0) { 1982 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__); 1983 return ret; 1984 } 1985 ret = sh_eth_dev_init(ndev, false); 1986 if (ret < 0) { 1987 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__); 1988 return ret; 1989 } 1990 1991 if (netif_running(ndev)) { 1992 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1993 /* Setting the Rx mode will start the Rx process. */ 1994 sh_eth_write(ndev, EDRRR_R, EDRRR); 1995 netif_wake_queue(ndev); 1996 } 1997 1998 return 0; 1999} 2000 2001static const struct ethtool_ops sh_eth_ethtool_ops = { 2002 .get_settings = sh_eth_get_settings, 2003 .set_settings = sh_eth_set_settings, 2004 .nway_reset = sh_eth_nway_reset, 2005 .get_msglevel = sh_eth_get_msglevel, 2006 .set_msglevel = sh_eth_set_msglevel, 2007 .get_link = ethtool_op_get_link, 2008 .get_strings = sh_eth_get_strings, 2009 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2010 .get_sset_count = sh_eth_get_sset_count, 2011 .get_ringparam = sh_eth_get_ringparam, 2012 .set_ringparam = sh_eth_set_ringparam, 2013}; 2014 2015/* network device open function */ 2016static int sh_eth_open(struct net_device *ndev) 2017{ 2018 int ret = 0; 2019 struct sh_eth_private *mdp = netdev_priv(ndev); 2020 2021 pm_runtime_get_sync(&mdp->pdev->dev); 2022 2023 napi_enable(&mdp->napi); 2024 2025 ret = request_irq(ndev->irq, sh_eth_interrupt, 2026 mdp->cd->irq_flags, ndev->name, ndev); 2027 if (ret) { 2028 dev_err(&ndev->dev, "Can not assign IRQ number\n"); 2029 goto out_napi_off; 2030 } 2031 2032 /* Descriptor set */ 2033 ret = sh_eth_ring_init(ndev); 2034 if (ret) 2035 goto out_free_irq; 2036 2037 /* device init */ 2038 ret = sh_eth_dev_init(ndev, true); 2039 if (ret) 2040 goto out_free_irq; 2041 2042 /* PHY control start*/ 2043 ret = sh_eth_phy_start(ndev); 2044 if (ret) 2045 goto out_free_irq; 2046 2047 return ret; 2048 2049out_free_irq: 2050 free_irq(ndev->irq, ndev); 2051out_napi_off: 2052 napi_disable(&mdp->napi); 2053 pm_runtime_put_sync(&mdp->pdev->dev); 2054 return ret; 2055} 2056 2057/* Timeout function */ 2058static void sh_eth_tx_timeout(struct net_device *ndev) 2059{ 2060 struct sh_eth_private *mdp = netdev_priv(ndev); 2061 struct sh_eth_rxdesc *rxdesc; 2062 int i; 2063 2064 netif_stop_queue(ndev); 2065 2066 if (netif_msg_timer(mdp)) { 2067 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x, resetting...\n", 2068 ndev->name, (int)sh_eth_read(ndev, EESR)); 2069 } 2070 2071 /* tx_errors count up */ 2072 ndev->stats.tx_errors++; 2073 2074 /* Free all the skbuffs in the Rx queue. */ 2075 for (i = 0; i < mdp->num_rx_ring; i++) { 2076 rxdesc = &mdp->rx_ring[i]; 2077 rxdesc->status = 0; 2078 rxdesc->addr = 0xBADF00D0; 2079 if (mdp->rx_skbuff[i]) 2080 dev_kfree_skb(mdp->rx_skbuff[i]); 2081 mdp->rx_skbuff[i] = NULL; 2082 } 2083 for (i = 0; i < mdp->num_tx_ring; i++) { 2084 if (mdp->tx_skbuff[i]) 2085 dev_kfree_skb(mdp->tx_skbuff[i]); 2086 mdp->tx_skbuff[i] = NULL; 2087 } 2088 2089 /* device init */ 2090 sh_eth_dev_init(ndev, true); 2091} 2092 2093/* Packet transmit function */ 2094static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2095{ 2096 struct sh_eth_private *mdp = netdev_priv(ndev); 2097 struct sh_eth_txdesc *txdesc; 2098 u32 entry; 2099 unsigned long flags; 2100 2101 spin_lock_irqsave(&mdp->lock, flags); 2102 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2103 if (!sh_eth_txfree(ndev)) { 2104 if (netif_msg_tx_queued(mdp)) 2105 dev_warn(&ndev->dev, "TxFD exhausted.\n"); 2106 netif_stop_queue(ndev); 2107 spin_unlock_irqrestore(&mdp->lock, flags); 2108 return NETDEV_TX_BUSY; 2109 } 2110 } 2111 spin_unlock_irqrestore(&mdp->lock, flags); 2112 2113 entry = mdp->cur_tx % mdp->num_tx_ring; 2114 mdp->tx_skbuff[entry] = skb; 2115 txdesc = &mdp->tx_ring[entry]; 2116 /* soft swap. */ 2117 if (!mdp->cd->hw_swap) 2118 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), 2119 skb->len + 2); 2120 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, 2121 DMA_TO_DEVICE); 2122 if (skb->len < ETH_ZLEN) 2123 txdesc->buffer_length = ETH_ZLEN; 2124 else 2125 txdesc->buffer_length = skb->len; 2126 2127 if (entry >= mdp->num_tx_ring - 1) 2128 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 2129 else 2130 txdesc->status |= cpu_to_edmac(mdp, TD_TACT); 2131 2132 mdp->cur_tx++; 2133 2134 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 2135 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 2136 2137 return NETDEV_TX_OK; 2138} 2139 2140/* device close function */ 2141static int sh_eth_close(struct net_device *ndev) 2142{ 2143 struct sh_eth_private *mdp = netdev_priv(ndev); 2144 2145 netif_stop_queue(ndev); 2146 2147 /* Disable interrupts by clearing the interrupt mask. */ 2148 sh_eth_write(ndev, 0x0000, EESIPR); 2149 2150 /* Stop the chip's Tx and Rx processes. */ 2151 sh_eth_write(ndev, 0, EDTRR); 2152 sh_eth_write(ndev, 0, EDRRR); 2153 2154 /* PHY Disconnect */ 2155 if (mdp->phydev) { 2156 phy_stop(mdp->phydev); 2157 phy_disconnect(mdp->phydev); 2158 } 2159 2160 free_irq(ndev->irq, ndev); 2161 2162 napi_disable(&mdp->napi); 2163 2164 /* Free all the skbuffs in the Rx queue. */ 2165 sh_eth_ring_free(ndev); 2166 2167 /* free DMA buffer */ 2168 sh_eth_free_dma_buffer(mdp); 2169 2170 pm_runtime_put_sync(&mdp->pdev->dev); 2171 2172 return 0; 2173} 2174 2175static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2176{ 2177 struct sh_eth_private *mdp = netdev_priv(ndev); 2178 2179 if (sh_eth_is_rz_fast_ether(mdp)) 2180 return &ndev->stats; 2181 2182 pm_runtime_get_sync(&mdp->pdev->dev); 2183 2184 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR); 2185 sh_eth_write(ndev, 0, TROCR); /* (write clear) */ 2186 ndev->stats.collisions += sh_eth_read(ndev, CDCR); 2187 sh_eth_write(ndev, 0, CDCR); /* (write clear) */ 2188 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); 2189 sh_eth_write(ndev, 0, LCCR); /* (write clear) */ 2190 if (sh_eth_is_gether(mdp)) { 2191 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR); 2192 sh_eth_write(ndev, 0, CERCR); /* (write clear) */ 2193 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR); 2194 sh_eth_write(ndev, 0, CEECR); /* (write clear) */ 2195 } else { 2196 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); 2197 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ 2198 } 2199 pm_runtime_put_sync(&mdp->pdev->dev); 2200 2201 return &ndev->stats; 2202} 2203 2204/* ioctl to device function */ 2205static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2206{ 2207 struct sh_eth_private *mdp = netdev_priv(ndev); 2208 struct phy_device *phydev = mdp->phydev; 2209 2210 if (!netif_running(ndev)) 2211 return -EINVAL; 2212 2213 if (!phydev) 2214 return -ENODEV; 2215 2216 return phy_mii_ioctl(phydev, rq, cmd); 2217} 2218 2219/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2220static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2221 int entry) 2222{ 2223 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2224} 2225 2226static u32 sh_eth_tsu_get_post_mask(int entry) 2227{ 2228 return 0x0f << (28 - ((entry % 8) * 4)); 2229} 2230 2231static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2232{ 2233 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2234} 2235 2236static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2237 int entry) 2238{ 2239 struct sh_eth_private *mdp = netdev_priv(ndev); 2240 u32 tmp; 2241 void *reg_offset; 2242 2243 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2244 tmp = ioread32(reg_offset); 2245 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2246} 2247 2248static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2249 int entry) 2250{ 2251 struct sh_eth_private *mdp = netdev_priv(ndev); 2252 u32 post_mask, ref_mask, tmp; 2253 void *reg_offset; 2254 2255 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2256 post_mask = sh_eth_tsu_get_post_mask(entry); 2257 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2258 2259 tmp = ioread32(reg_offset); 2260 iowrite32(tmp & ~post_mask, reg_offset); 2261 2262 /* If other port enables, the function returns "true" */ 2263 return tmp & ref_mask; 2264} 2265 2266static int sh_eth_tsu_busy(struct net_device *ndev) 2267{ 2268 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2269 struct sh_eth_private *mdp = netdev_priv(ndev); 2270 2271 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2272 udelay(10); 2273 timeout--; 2274 if (timeout <= 0) { 2275 dev_err(&ndev->dev, "%s: timeout\n", __func__); 2276 return -ETIMEDOUT; 2277 } 2278 } 2279 2280 return 0; 2281} 2282 2283static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2284 const u8 *addr) 2285{ 2286 u32 val; 2287 2288 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2289 iowrite32(val, reg); 2290 if (sh_eth_tsu_busy(ndev) < 0) 2291 return -EBUSY; 2292 2293 val = addr[4] << 8 | addr[5]; 2294 iowrite32(val, reg + 4); 2295 if (sh_eth_tsu_busy(ndev) < 0) 2296 return -EBUSY; 2297 2298 return 0; 2299} 2300 2301static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2302{ 2303 u32 val; 2304 2305 val = ioread32(reg); 2306 addr[0] = (val >> 24) & 0xff; 2307 addr[1] = (val >> 16) & 0xff; 2308 addr[2] = (val >> 8) & 0xff; 2309 addr[3] = val & 0xff; 2310 val = ioread32(reg + 4); 2311 addr[4] = (val >> 8) & 0xff; 2312 addr[5] = val & 0xff; 2313} 2314 2315 2316static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2317{ 2318 struct sh_eth_private *mdp = netdev_priv(ndev); 2319 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2320 int i; 2321 u8 c_addr[ETH_ALEN]; 2322 2323 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2324 sh_eth_tsu_read_entry(reg_offset, c_addr); 2325 if (ether_addr_equal(addr, c_addr)) 2326 return i; 2327 } 2328 2329 return -ENOENT; 2330} 2331 2332static int sh_eth_tsu_find_empty(struct net_device *ndev) 2333{ 2334 u8 blank[ETH_ALEN]; 2335 int entry; 2336 2337 memset(blank, 0, sizeof(blank)); 2338 entry = sh_eth_tsu_find_entry(ndev, blank); 2339 return (entry < 0) ? -ENOMEM : entry; 2340} 2341 2342static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2343 int entry) 2344{ 2345 struct sh_eth_private *mdp = netdev_priv(ndev); 2346 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2347 int ret; 2348 u8 blank[ETH_ALEN]; 2349 2350 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2351 ~(1 << (31 - entry)), TSU_TEN); 2352 2353 memset(blank, 0, sizeof(blank)); 2354 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2355 if (ret < 0) 2356 return ret; 2357 return 0; 2358} 2359 2360static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2361{ 2362 struct sh_eth_private *mdp = netdev_priv(ndev); 2363 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2364 int i, ret; 2365 2366 if (!mdp->cd->tsu) 2367 return 0; 2368 2369 i = sh_eth_tsu_find_entry(ndev, addr); 2370 if (i < 0) { 2371 /* No entry found, create one */ 2372 i = sh_eth_tsu_find_empty(ndev); 2373 if (i < 0) 2374 return -ENOMEM; 2375 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2376 if (ret < 0) 2377 return ret; 2378 2379 /* Enable the entry */ 2380 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2381 (1 << (31 - i)), TSU_TEN); 2382 } 2383 2384 /* Entry found or created, enable POST */ 2385 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2386 2387 return 0; 2388} 2389 2390static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2391{ 2392 struct sh_eth_private *mdp = netdev_priv(ndev); 2393 int i, ret; 2394 2395 if (!mdp->cd->tsu) 2396 return 0; 2397 2398 i = sh_eth_tsu_find_entry(ndev, addr); 2399 if (i) { 2400 /* Entry found */ 2401 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2402 goto done; 2403 2404 /* Disable the entry if both ports was disabled */ 2405 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2406 if (ret < 0) 2407 return ret; 2408 } 2409done: 2410 return 0; 2411} 2412 2413static int sh_eth_tsu_purge_all(struct net_device *ndev) 2414{ 2415 struct sh_eth_private *mdp = netdev_priv(ndev); 2416 int i, ret; 2417 2418 if (unlikely(!mdp->cd->tsu)) 2419 return 0; 2420 2421 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2422 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2423 continue; 2424 2425 /* Disable the entry if both ports was disabled */ 2426 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2427 if (ret < 0) 2428 return ret; 2429 } 2430 2431 return 0; 2432} 2433 2434static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2435{ 2436 struct sh_eth_private *mdp = netdev_priv(ndev); 2437 u8 addr[ETH_ALEN]; 2438 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2439 int i; 2440 2441 if (unlikely(!mdp->cd->tsu)) 2442 return; 2443 2444 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2445 sh_eth_tsu_read_entry(reg_offset, addr); 2446 if (is_multicast_ether_addr(addr)) 2447 sh_eth_tsu_del_entry(ndev, addr); 2448 } 2449} 2450 2451/* Multicast reception directions set */ 2452static void sh_eth_set_multicast_list(struct net_device *ndev) 2453{ 2454 struct sh_eth_private *mdp = netdev_priv(ndev); 2455 u32 ecmr_bits; 2456 int mcast_all = 0; 2457 unsigned long flags; 2458 2459 spin_lock_irqsave(&mdp->lock, flags); 2460 /* Initial condition is MCT = 1, PRM = 0. 2461 * Depending on ndev->flags, set PRM or clear MCT 2462 */ 2463 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT; 2464 2465 if (!(ndev->flags & IFF_MULTICAST)) { 2466 sh_eth_tsu_purge_mcast(ndev); 2467 mcast_all = 1; 2468 } 2469 if (ndev->flags & IFF_ALLMULTI) { 2470 sh_eth_tsu_purge_mcast(ndev); 2471 ecmr_bits &= ~ECMR_MCT; 2472 mcast_all = 1; 2473 } 2474 2475 if (ndev->flags & IFF_PROMISC) { 2476 sh_eth_tsu_purge_all(ndev); 2477 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2478 } else if (mdp->cd->tsu) { 2479 struct netdev_hw_addr *ha; 2480 netdev_for_each_mc_addr(ha, ndev) { 2481 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2482 continue; 2483 2484 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2485 if (!mcast_all) { 2486 sh_eth_tsu_purge_mcast(ndev); 2487 ecmr_bits &= ~ECMR_MCT; 2488 mcast_all = 1; 2489 } 2490 } 2491 } 2492 } else { 2493 /* Normal, unicast/broadcast-only mode. */ 2494 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT; 2495 } 2496 2497 /* update the ethernet mode */ 2498 sh_eth_write(ndev, ecmr_bits, ECMR); 2499 2500 spin_unlock_irqrestore(&mdp->lock, flags); 2501} 2502 2503static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2504{ 2505 if (!mdp->port) 2506 return TSU_VTAG0; 2507 else 2508 return TSU_VTAG1; 2509} 2510 2511static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2512 __be16 proto, u16 vid) 2513{ 2514 struct sh_eth_private *mdp = netdev_priv(ndev); 2515 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2516 2517 if (unlikely(!mdp->cd->tsu)) 2518 return -EPERM; 2519 2520 /* No filtering if vid = 0 */ 2521 if (!vid) 2522 return 0; 2523 2524 mdp->vlan_num_ids++; 2525 2526 /* The controller has one VLAN tag HW filter. So, if the filter is 2527 * already enabled, the driver disables it and the filte 2528 */ 2529 if (mdp->vlan_num_ids > 1) { 2530 /* disable VLAN filter */ 2531 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2532 return 0; 2533 } 2534 2535 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2536 vtag_reg_index); 2537 2538 return 0; 2539} 2540 2541static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2542 __be16 proto, u16 vid) 2543{ 2544 struct sh_eth_private *mdp = netdev_priv(ndev); 2545 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2546 2547 if (unlikely(!mdp->cd->tsu)) 2548 return -EPERM; 2549 2550 /* No filtering if vid = 0 */ 2551 if (!vid) 2552 return 0; 2553 2554 mdp->vlan_num_ids--; 2555 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2556 2557 return 0; 2558} 2559 2560/* SuperH's TSU register init function */ 2561static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2562{ 2563 if (sh_eth_is_rz_fast_ether(mdp)) { 2564 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2565 return; 2566 } 2567 2568 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2569 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2570 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2571 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2572 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2573 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2574 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2575 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2576 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2577 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2578 if (sh_eth_is_gether(mdp)) { 2579 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2580 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2581 } else { 2582 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2583 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2584 } 2585 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2586 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2587 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2588 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2589 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2590 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2591 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2592} 2593 2594/* MDIO bus release function */ 2595static int sh_mdio_release(struct net_device *ndev) 2596{ 2597 struct mii_bus *bus = dev_get_drvdata(&ndev->dev); 2598 2599 /* unregister mdio bus */ 2600 mdiobus_unregister(bus); 2601 2602 /* remove mdio bus info from net_device */ 2603 dev_set_drvdata(&ndev->dev, NULL); 2604 2605 /* free bitbang info */ 2606 free_mdio_bitbang(bus); 2607 2608 return 0; 2609} 2610 2611/* MDIO bus init function */ 2612static int sh_mdio_init(struct net_device *ndev, int id, 2613 struct sh_eth_plat_data *pd) 2614{ 2615 int ret, i; 2616 struct bb_info *bitbang; 2617 struct sh_eth_private *mdp = netdev_priv(ndev); 2618 2619 /* create bit control struct for PHY */ 2620 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info), 2621 GFP_KERNEL); 2622 if (!bitbang) { 2623 ret = -ENOMEM; 2624 goto out; 2625 } 2626 2627 /* bitbang init */ 2628 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2629 bitbang->set_gate = pd->set_mdio_gate; 2630 bitbang->mdi_msk = PIR_MDI; 2631 bitbang->mdo_msk = PIR_MDO; 2632 bitbang->mmd_msk = PIR_MMD; 2633 bitbang->mdc_msk = PIR_MDC; 2634 bitbang->ctrl.ops = &bb_ops; 2635 2636 /* MII controller setting */ 2637 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2638 if (!mdp->mii_bus) { 2639 ret = -ENOMEM; 2640 goto out; 2641 } 2642 2643 /* Hook up MII support for ethtool */ 2644 mdp->mii_bus->name = "sh_mii"; 2645 mdp->mii_bus->parent = &ndev->dev; 2646 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2647 mdp->pdev->name, id); 2648 2649 /* PHY IRQ */ 2650 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev, 2651 sizeof(int) * PHY_MAX_ADDR, 2652 GFP_KERNEL); 2653 if (!mdp->mii_bus->irq) { 2654 ret = -ENOMEM; 2655 goto out_free_bus; 2656 } 2657 2658 /* register mdio bus */ 2659 if (ndev->dev.parent->of_node) { 2660 ret = of_mdiobus_register(mdp->mii_bus, 2661 ndev->dev.parent->of_node); 2662 } else { 2663 for (i = 0; i < PHY_MAX_ADDR; i++) 2664 mdp->mii_bus->irq[i] = PHY_POLL; 2665 if (pd->phy_irq > 0) 2666 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 2667 2668 ret = mdiobus_register(mdp->mii_bus); 2669 } 2670 2671 if (ret) 2672 goto out_free_bus; 2673 2674 dev_set_drvdata(&ndev->dev, mdp->mii_bus); 2675 2676 return 0; 2677 2678out_free_bus: 2679 free_mdio_bitbang(mdp->mii_bus); 2680 2681out: 2682 return ret; 2683} 2684 2685static const u16 *sh_eth_get_register_offset(int register_type) 2686{ 2687 const u16 *reg_offset = NULL; 2688 2689 switch (register_type) { 2690 case SH_ETH_REG_GIGABIT: 2691 reg_offset = sh_eth_offset_gigabit; 2692 break; 2693 case SH_ETH_REG_FAST_RZ: 2694 reg_offset = sh_eth_offset_fast_rz; 2695 break; 2696 case SH_ETH_REG_FAST_RCAR: 2697 reg_offset = sh_eth_offset_fast_rcar; 2698 break; 2699 case SH_ETH_REG_FAST_SH4: 2700 reg_offset = sh_eth_offset_fast_sh4; 2701 break; 2702 case SH_ETH_REG_FAST_SH3_SH2: 2703 reg_offset = sh_eth_offset_fast_sh3_sh2; 2704 break; 2705 default: 2706 break; 2707 } 2708 2709 return reg_offset; 2710} 2711 2712static const struct net_device_ops sh_eth_netdev_ops = { 2713 .ndo_open = sh_eth_open, 2714 .ndo_stop = sh_eth_close, 2715 .ndo_start_xmit = sh_eth_start_xmit, 2716 .ndo_get_stats = sh_eth_get_stats, 2717 .ndo_tx_timeout = sh_eth_tx_timeout, 2718 .ndo_do_ioctl = sh_eth_do_ioctl, 2719 .ndo_validate_addr = eth_validate_addr, 2720 .ndo_set_mac_address = eth_mac_addr, 2721 .ndo_change_mtu = eth_change_mtu, 2722}; 2723 2724static const struct net_device_ops sh_eth_netdev_ops_tsu = { 2725 .ndo_open = sh_eth_open, 2726 .ndo_stop = sh_eth_close, 2727 .ndo_start_xmit = sh_eth_start_xmit, 2728 .ndo_get_stats = sh_eth_get_stats, 2729 .ndo_set_rx_mode = sh_eth_set_multicast_list, 2730 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 2731 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 2732 .ndo_tx_timeout = sh_eth_tx_timeout, 2733 .ndo_do_ioctl = sh_eth_do_ioctl, 2734 .ndo_validate_addr = eth_validate_addr, 2735 .ndo_set_mac_address = eth_mac_addr, 2736 .ndo_change_mtu = eth_change_mtu, 2737}; 2738 2739#ifdef CONFIG_OF 2740static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 2741{ 2742 struct device_node *np = dev->of_node; 2743 struct sh_eth_plat_data *pdata; 2744 const char *mac_addr; 2745 2746 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2747 if (!pdata) 2748 return NULL; 2749 2750 pdata->phy_interface = of_get_phy_mode(np); 2751 2752 mac_addr = of_get_mac_address(np); 2753 if (mac_addr) 2754 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 2755 2756 pdata->no_ether_link = 2757 of_property_read_bool(np, "renesas,no-ether-link"); 2758 pdata->ether_link_active_low = 2759 of_property_read_bool(np, "renesas,ether-link-active-low"); 2760 2761 return pdata; 2762} 2763 2764static const struct of_device_id sh_eth_match_table[] = { 2765 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 2766 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data }, 2767 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data }, 2768 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data }, 2769 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data }, 2770 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 2771 { } 2772}; 2773MODULE_DEVICE_TABLE(of, sh_eth_match_table); 2774#else 2775static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 2776{ 2777 return NULL; 2778} 2779#endif 2780 2781static int sh_eth_drv_probe(struct platform_device *pdev) 2782{ 2783 int ret, devno = 0; 2784 struct resource *res; 2785 struct net_device *ndev = NULL; 2786 struct sh_eth_private *mdp = NULL; 2787 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 2788 const struct platform_device_id *id = platform_get_device_id(pdev); 2789 2790 /* get base addr */ 2791 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2792 if (unlikely(res == NULL)) { 2793 dev_err(&pdev->dev, "invalid resource\n"); 2794 ret = -EINVAL; 2795 goto out; 2796 } 2797 2798 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 2799 if (!ndev) { 2800 ret = -ENOMEM; 2801 goto out; 2802 } 2803 2804 /* The sh Ether-specific entries in the device structure. */ 2805 ndev->base_addr = res->start; 2806 devno = pdev->id; 2807 if (devno < 0) 2808 devno = 0; 2809 2810 ndev->dma = -1; 2811 ret = platform_get_irq(pdev, 0); 2812 if (ret < 0) { 2813 ret = -ENODEV; 2814 goto out_release; 2815 } 2816 ndev->irq = ret; 2817 2818 SET_NETDEV_DEV(ndev, &pdev->dev); 2819 2820 mdp = netdev_priv(ndev); 2821 mdp->num_tx_ring = TX_RING_SIZE; 2822 mdp->num_rx_ring = RX_RING_SIZE; 2823 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 2824 if (IS_ERR(mdp->addr)) { 2825 ret = PTR_ERR(mdp->addr); 2826 goto out_release; 2827 } 2828 2829 spin_lock_init(&mdp->lock); 2830 mdp->pdev = pdev; 2831 pm_runtime_enable(&pdev->dev); 2832 pm_runtime_resume(&pdev->dev); 2833 2834 if (pdev->dev.of_node) 2835 pd = sh_eth_parse_dt(&pdev->dev); 2836 if (!pd) { 2837 dev_err(&pdev->dev, "no platform data\n"); 2838 ret = -EINVAL; 2839 goto out_release; 2840 } 2841 2842 /* get PHY ID */ 2843 mdp->phy_id = pd->phy; 2844 mdp->phy_interface = pd->phy_interface; 2845 /* EDMAC endian */ 2846 mdp->edmac_endian = pd->edmac_endian; 2847 mdp->no_ether_link = pd->no_ether_link; 2848 mdp->ether_link_active_low = pd->ether_link_active_low; 2849 2850 /* set cpu data */ 2851 if (id) { 2852 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 2853 } else { 2854 const struct of_device_id *match; 2855 2856 match = of_match_device(of_match_ptr(sh_eth_match_table), 2857 &pdev->dev); 2858 mdp->cd = (struct sh_eth_cpu_data *)match->data; 2859 } 2860 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 2861 if (!mdp->reg_offset) { 2862 dev_err(&pdev->dev, "Unknown register type (%d)\n", 2863 mdp->cd->register_type); 2864 ret = -EINVAL; 2865 goto out_release; 2866 } 2867 sh_eth_set_default_cpu_data(mdp->cd); 2868 2869 /* set function */ 2870 if (mdp->cd->tsu) 2871 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 2872 else 2873 ndev->netdev_ops = &sh_eth_netdev_ops; 2874 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); 2875 ndev->watchdog_timeo = TX_TIMEOUT; 2876 2877 /* debug message level */ 2878 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 2879 2880 /* read and set MAC address */ 2881 read_mac_address(ndev, pd->mac_addr); 2882 if (!is_valid_ether_addr(ndev->dev_addr)) { 2883 dev_warn(&pdev->dev, 2884 "no valid MAC address supplied, using a random one.\n"); 2885 eth_hw_addr_random(ndev); 2886 } 2887 2888 /* ioremap the TSU registers */ 2889 if (mdp->cd->tsu) { 2890 struct resource *rtsu; 2891 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2892 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); 2893 if (IS_ERR(mdp->tsu_addr)) { 2894 ret = PTR_ERR(mdp->tsu_addr); 2895 goto out_release; 2896 } 2897 mdp->port = devno % 2; 2898 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 2899 } 2900 2901 /* initialize first or needed device */ 2902 if (!devno || pd->needs_init) { 2903 if (mdp->cd->chip_reset) 2904 mdp->cd->chip_reset(ndev); 2905 2906 if (mdp->cd->tsu) { 2907 /* TSU init (Init only)*/ 2908 sh_eth_tsu_init(mdp); 2909 } 2910 } 2911 2912 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 2913 2914 /* network device register */ 2915 ret = register_netdev(ndev); 2916 if (ret) 2917 goto out_napi_del; 2918 2919 /* mdio bus init */ 2920 ret = sh_mdio_init(ndev, pdev->id, pd); 2921 if (ret) { 2922 dev_err(&ndev->dev, "failed to initialise MDIO\n"); 2923 goto out_unregister; 2924 } 2925 2926 /* print device information */ 2927 pr_info("Base address at 0x%x, %pM, IRQ %d.\n", 2928 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2929 2930 platform_set_drvdata(pdev, ndev); 2931 2932 return ret; 2933 2934out_unregister: 2935 unregister_netdev(ndev); 2936 2937out_napi_del: 2938 netif_napi_del(&mdp->napi); 2939 2940out_release: 2941 /* net_dev free */ 2942 if (ndev) 2943 free_netdev(ndev); 2944 2945out: 2946 return ret; 2947} 2948 2949static int sh_eth_drv_remove(struct platform_device *pdev) 2950{ 2951 struct net_device *ndev = platform_get_drvdata(pdev); 2952 struct sh_eth_private *mdp = netdev_priv(ndev); 2953 2954 sh_mdio_release(ndev); 2955 unregister_netdev(ndev); 2956 netif_napi_del(&mdp->napi); 2957 pm_runtime_disable(&pdev->dev); 2958 free_netdev(ndev); 2959 2960 return 0; 2961} 2962 2963#ifdef CONFIG_PM 2964static int sh_eth_runtime_nop(struct device *dev) 2965{ 2966 /* Runtime PM callback shared between ->runtime_suspend() 2967 * and ->runtime_resume(). Simply returns success. 2968 * 2969 * This driver re-initializes all registers after 2970 * pm_runtime_get_sync() anyway so there is no need 2971 * to save and restore registers here. 2972 */ 2973 return 0; 2974} 2975 2976static const struct dev_pm_ops sh_eth_dev_pm_ops = { 2977 .runtime_suspend = sh_eth_runtime_nop, 2978 .runtime_resume = sh_eth_runtime_nop, 2979}; 2980#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 2981#else 2982#define SH_ETH_PM_OPS NULL 2983#endif 2984 2985static struct platform_device_id sh_eth_id_table[] = { 2986 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 2987 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 2988 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 2989 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 2990 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 2991 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 2992 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 2993 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data }, 2994 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, 2995 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data }, 2996 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data }, 2997 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data }, 2998 { } 2999}; 3000MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3001 3002static struct platform_driver sh_eth_driver = { 3003 .probe = sh_eth_drv_probe, 3004 .remove = sh_eth_drv_remove, 3005 .id_table = sh_eth_id_table, 3006 .driver = { 3007 .name = CARDNAME, 3008 .pm = SH_ETH_PM_OPS, 3009 .of_match_table = of_match_ptr(sh_eth_match_table), 3010 }, 3011}; 3012 3013module_platform_driver(sh_eth_driver); 3014 3015MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3016MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3017MODULE_LICENSE("GPL v2"); 3018