sh_eth.c revision 564044b0928d46a87774c246ae80cb3cead9264d
1/* 2 * SuperH Ethernet device driver 3 * 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2012 Renesas Solutions Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 */ 22 23#include <linux/init.h> 24#include <linux/module.h> 25#include <linux/kernel.h> 26#include <linux/spinlock.h> 27#include <linux/interrupt.h> 28#include <linux/dma-mapping.h> 29#include <linux/etherdevice.h> 30#include <linux/delay.h> 31#include <linux/platform_device.h> 32#include <linux/mdio-bitbang.h> 33#include <linux/netdevice.h> 34#include <linux/phy.h> 35#include <linux/cache.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38#include <linux/slab.h> 39#include <linux/ethtool.h> 40#include <linux/if_vlan.h> 41#include <linux/clk.h> 42#include <linux/sh_eth.h> 43 44#include "sh_eth.h" 45 46#define SH_ETH_DEF_MSG_ENABLE \ 47 (NETIF_MSG_LINK | \ 48 NETIF_MSG_TIMER | \ 49 NETIF_MSG_RX_ERR| \ 50 NETIF_MSG_TX_ERR) 51 52#if defined(CONFIG_CPU_SUBTYPE_SH7734) || \ 53 defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 54 defined(CONFIG_ARCH_R8A7740) 55static void sh_eth_select_mii(struct net_device *ndev) 56{ 57 u32 value = 0x0; 58 struct sh_eth_private *mdp = netdev_priv(ndev); 59 60 switch (mdp->phy_interface) { 61 case PHY_INTERFACE_MODE_GMII: 62 value = 0x2; 63 break; 64 case PHY_INTERFACE_MODE_MII: 65 value = 0x1; 66 break; 67 case PHY_INTERFACE_MODE_RMII: 68 value = 0x0; 69 break; 70 default: 71 pr_warn("PHY interface mode was not setup. Set to MII.\n"); 72 value = 0x1; 73 break; 74 } 75 76 sh_eth_write(ndev, value, RMII_MII); 77} 78#endif 79 80/* There is CPU dependent code */ 81#if defined(CONFIG_CPU_SUBTYPE_SH7724) || defined(CONFIG_ARCH_R8A7779) 82#define SH_ETH_RESET_DEFAULT 1 83static void sh_eth_set_duplex(struct net_device *ndev) 84{ 85 struct sh_eth_private *mdp = netdev_priv(ndev); 86 87 if (mdp->duplex) /* Full */ 88 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 89 else /* Half */ 90 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 91} 92 93static void sh_eth_set_rate(struct net_device *ndev) 94{ 95 struct sh_eth_private *mdp = netdev_priv(ndev); 96 unsigned int bits = ECMR_RTM; 97 98#if defined(CONFIG_ARCH_R8A7779) 99 bits |= ECMR_ELB; 100#endif 101 102 switch (mdp->speed) { 103 case 10: /* 10BASE */ 104 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~bits, ECMR); 105 break; 106 case 100:/* 100BASE */ 107 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | bits, ECMR); 108 break; 109 default: 110 break; 111 } 112} 113 114/* SH7724 */ 115static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 116 .set_duplex = sh_eth_set_duplex, 117 .set_rate = sh_eth_set_rate, 118 119 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 120 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 121 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f, 122 123 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 124 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 125 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 126 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 127 128 .apr = 1, 129 .mpr = 1, 130 .tpauser = 1, 131 .hw_swap = 1, 132 .rpadir = 1, 133 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 134}; 135#elif defined(CONFIG_CPU_SUBTYPE_SH7757) 136#define SH_ETH_HAS_BOTH_MODULES 1 137#define SH_ETH_HAS_TSU 1 138static int sh_eth_check_reset(struct net_device *ndev); 139 140static void sh_eth_set_duplex(struct net_device *ndev) 141{ 142 struct sh_eth_private *mdp = netdev_priv(ndev); 143 144 if (mdp->duplex) /* Full */ 145 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 146 else /* Half */ 147 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 148} 149 150static void sh_eth_set_rate(struct net_device *ndev) 151{ 152 struct sh_eth_private *mdp = netdev_priv(ndev); 153 154 switch (mdp->speed) { 155 case 10: /* 10BASE */ 156 sh_eth_write(ndev, 0, RTRATE); 157 break; 158 case 100:/* 100BASE */ 159 sh_eth_write(ndev, 1, RTRATE); 160 break; 161 default: 162 break; 163 } 164} 165 166/* SH7757 */ 167static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 168 .set_duplex = sh_eth_set_duplex, 169 .set_rate = sh_eth_set_rate, 170 171 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 172 .rmcr_value = 0x00000001, 173 174 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 175 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 176 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 177 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 178 179 .apr = 1, 180 .mpr = 1, 181 .tpauser = 1, 182 .hw_swap = 1, 183 .no_ade = 1, 184 .rpadir = 1, 185 .rpadir_value = 2 << 16, 186}; 187 188#define SH_GIGA_ETH_BASE 0xfee00000 189#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 190#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 191static void sh_eth_chip_reset_giga(struct net_device *ndev) 192{ 193 int i; 194 unsigned long mahr[2], malr[2]; 195 196 /* save MAHR and MALR */ 197 for (i = 0; i < 2; i++) { 198 malr[i] = ioread32((void *)GIGA_MALR(i)); 199 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 200 } 201 202 /* reset device */ 203 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 204 mdelay(1); 205 206 /* restore MAHR and MALR */ 207 for (i = 0; i < 2; i++) { 208 iowrite32(malr[i], (void *)GIGA_MALR(i)); 209 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 210 } 211} 212 213static int sh_eth_is_gether(struct sh_eth_private *mdp); 214static int sh_eth_reset(struct net_device *ndev) 215{ 216 struct sh_eth_private *mdp = netdev_priv(ndev); 217 int ret = 0; 218 219 if (sh_eth_is_gether(mdp)) { 220 sh_eth_write(ndev, 0x03, EDSR); 221 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 222 EDMR); 223 224 ret = sh_eth_check_reset(ndev); 225 if (ret) 226 goto out; 227 228 /* Table Init */ 229 sh_eth_write(ndev, 0x0, TDLAR); 230 sh_eth_write(ndev, 0x0, TDFAR); 231 sh_eth_write(ndev, 0x0, TDFXR); 232 sh_eth_write(ndev, 0x0, TDFFR); 233 sh_eth_write(ndev, 0x0, RDLAR); 234 sh_eth_write(ndev, 0x0, RDFAR); 235 sh_eth_write(ndev, 0x0, RDFXR); 236 sh_eth_write(ndev, 0x0, RDFFR); 237 } else { 238 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 239 EDMR); 240 mdelay(3); 241 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 242 EDMR); 243 } 244 245out: 246 return ret; 247} 248 249static void sh_eth_set_duplex_giga(struct net_device *ndev) 250{ 251 struct sh_eth_private *mdp = netdev_priv(ndev); 252 253 if (mdp->duplex) /* Full */ 254 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 255 else /* Half */ 256 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 257} 258 259static void sh_eth_set_rate_giga(struct net_device *ndev) 260{ 261 struct sh_eth_private *mdp = netdev_priv(ndev); 262 263 switch (mdp->speed) { 264 case 10: /* 10BASE */ 265 sh_eth_write(ndev, 0x00000000, GECMR); 266 break; 267 case 100:/* 100BASE */ 268 sh_eth_write(ndev, 0x00000010, GECMR); 269 break; 270 case 1000: /* 1000BASE */ 271 sh_eth_write(ndev, 0x00000020, GECMR); 272 break; 273 default: 274 break; 275 } 276} 277 278/* SH7757(GETHERC) */ 279static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = { 280 .chip_reset = sh_eth_chip_reset_giga, 281 .set_duplex = sh_eth_set_duplex_giga, 282 .set_rate = sh_eth_set_rate_giga, 283 284 .ecsr_value = ECSR_ICD | ECSR_MPD, 285 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 286 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 287 288 .tx_check = EESR_TC1 | EESR_FTC, 289 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 290 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 291 EESR_ECI, 292 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 293 EESR_TFE, 294 .fdr_value = 0x0000072f, 295 .rmcr_value = 0x00000001, 296 297 .apr = 1, 298 .mpr = 1, 299 .tpauser = 1, 300 .bculr = 1, 301 .hw_swap = 1, 302 .rpadir = 1, 303 .rpadir_value = 2 << 16, 304 .no_trimd = 1, 305 .no_ade = 1, 306 .tsu = 1, 307}; 308 309static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp) 310{ 311 if (sh_eth_is_gether(mdp)) 312 return &sh_eth_my_cpu_data_giga; 313 else 314 return &sh_eth_my_cpu_data; 315} 316 317#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) 318#define SH_ETH_HAS_TSU 1 319static int sh_eth_check_reset(struct net_device *ndev); 320static void sh_eth_reset_hw_crc(struct net_device *ndev); 321 322static void sh_eth_chip_reset(struct net_device *ndev) 323{ 324 struct sh_eth_private *mdp = netdev_priv(ndev); 325 326 /* reset device */ 327 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 328 mdelay(1); 329} 330 331static void sh_eth_set_duplex(struct net_device *ndev) 332{ 333 struct sh_eth_private *mdp = netdev_priv(ndev); 334 335 if (mdp->duplex) /* Full */ 336 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 337 else /* Half */ 338 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 339} 340 341static void sh_eth_set_rate(struct net_device *ndev) 342{ 343 struct sh_eth_private *mdp = netdev_priv(ndev); 344 345 switch (mdp->speed) { 346 case 10: /* 10BASE */ 347 sh_eth_write(ndev, GECMR_10, GECMR); 348 break; 349 case 100:/* 100BASE */ 350 sh_eth_write(ndev, GECMR_100, GECMR); 351 break; 352 case 1000: /* 1000BASE */ 353 sh_eth_write(ndev, GECMR_1000, GECMR); 354 break; 355 default: 356 break; 357 } 358} 359 360/* sh7763 */ 361static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 362 .chip_reset = sh_eth_chip_reset, 363 .set_duplex = sh_eth_set_duplex, 364 .set_rate = sh_eth_set_rate, 365 366 .ecsr_value = ECSR_ICD | ECSR_MPD, 367 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 368 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 369 370 .tx_check = EESR_TC1 | EESR_FTC, 371 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 372 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 373 EESR_ECI, 374 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 375 EESR_TFE, 376 377 .apr = 1, 378 .mpr = 1, 379 .tpauser = 1, 380 .bculr = 1, 381 .hw_swap = 1, 382 .no_trimd = 1, 383 .no_ade = 1, 384 .tsu = 1, 385#if defined(CONFIG_CPU_SUBTYPE_SH7734) 386 .hw_crc = 1, 387 .select_mii = 1, 388#endif 389}; 390 391static int sh_eth_reset(struct net_device *ndev) 392{ 393 int ret = 0; 394 395 sh_eth_write(ndev, EDSR_ENALL, EDSR); 396 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); 397 398 ret = sh_eth_check_reset(ndev); 399 if (ret) 400 goto out; 401 402 /* Table Init */ 403 sh_eth_write(ndev, 0x0, TDLAR); 404 sh_eth_write(ndev, 0x0, TDFAR); 405 sh_eth_write(ndev, 0x0, TDFXR); 406 sh_eth_write(ndev, 0x0, TDFFR); 407 sh_eth_write(ndev, 0x0, RDLAR); 408 sh_eth_write(ndev, 0x0, RDFAR); 409 sh_eth_write(ndev, 0x0, RDFXR); 410 sh_eth_write(ndev, 0x0, RDFFR); 411 412 /* Reset HW CRC register */ 413 sh_eth_reset_hw_crc(ndev); 414 415 /* Select MII mode */ 416 if (sh_eth_my_cpu_data.select_mii) 417 sh_eth_select_mii(ndev); 418out: 419 return ret; 420} 421 422static void sh_eth_reset_hw_crc(struct net_device *ndev) 423{ 424 if (sh_eth_my_cpu_data.hw_crc) 425 sh_eth_write(ndev, 0x0, CSMR); 426} 427 428#elif defined(CONFIG_ARCH_R8A7740) 429#define SH_ETH_HAS_TSU 1 430static int sh_eth_check_reset(struct net_device *ndev); 431 432static void sh_eth_chip_reset(struct net_device *ndev) 433{ 434 struct sh_eth_private *mdp = netdev_priv(ndev); 435 436 /* reset device */ 437 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 438 mdelay(1); 439 440 sh_eth_select_mii(ndev); 441} 442 443static int sh_eth_reset(struct net_device *ndev) 444{ 445 int ret = 0; 446 447 sh_eth_write(ndev, EDSR_ENALL, EDSR); 448 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); 449 450 ret = sh_eth_check_reset(ndev); 451 if (ret) 452 goto out; 453 454 /* Table Init */ 455 sh_eth_write(ndev, 0x0, TDLAR); 456 sh_eth_write(ndev, 0x0, TDFAR); 457 sh_eth_write(ndev, 0x0, TDFXR); 458 sh_eth_write(ndev, 0x0, TDFFR); 459 sh_eth_write(ndev, 0x0, RDLAR); 460 sh_eth_write(ndev, 0x0, RDFAR); 461 sh_eth_write(ndev, 0x0, RDFXR); 462 sh_eth_write(ndev, 0x0, RDFFR); 463 464out: 465 return ret; 466} 467 468static void sh_eth_set_duplex(struct net_device *ndev) 469{ 470 struct sh_eth_private *mdp = netdev_priv(ndev); 471 472 if (mdp->duplex) /* Full */ 473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 474 else /* Half */ 475 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 476} 477 478static void sh_eth_set_rate(struct net_device *ndev) 479{ 480 struct sh_eth_private *mdp = netdev_priv(ndev); 481 482 switch (mdp->speed) { 483 case 10: /* 10BASE */ 484 sh_eth_write(ndev, GECMR_10, GECMR); 485 break; 486 case 100:/* 100BASE */ 487 sh_eth_write(ndev, GECMR_100, GECMR); 488 break; 489 case 1000: /* 1000BASE */ 490 sh_eth_write(ndev, GECMR_1000, GECMR); 491 break; 492 default: 493 break; 494 } 495} 496 497/* R8A7740 */ 498static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 499 .chip_reset = sh_eth_chip_reset, 500 .set_duplex = sh_eth_set_duplex, 501 .set_rate = sh_eth_set_rate, 502 503 .ecsr_value = ECSR_ICD | ECSR_MPD, 504 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 505 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 506 507 .tx_check = EESR_TC1 | EESR_FTC, 508 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 509 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 510 EESR_ECI, 511 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 512 EESR_TFE, 513 514 .apr = 1, 515 .mpr = 1, 516 .tpauser = 1, 517 .bculr = 1, 518 .hw_swap = 1, 519 .no_trimd = 1, 520 .no_ade = 1, 521 .tsu = 1, 522 .select_mii = 1, 523}; 524 525#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 526#define SH_ETH_RESET_DEFAULT 1 527static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 528 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 529 530 .apr = 1, 531 .mpr = 1, 532 .tpauser = 1, 533 .hw_swap = 1, 534}; 535#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 536#define SH_ETH_RESET_DEFAULT 1 537#define SH_ETH_HAS_TSU 1 538static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 539 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 540 .tsu = 1, 541}; 542#endif 543 544static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 545{ 546 if (!cd->ecsr_value) 547 cd->ecsr_value = DEFAULT_ECSR_INIT; 548 549 if (!cd->ecsipr_value) 550 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 551 552 if (!cd->fcftr_value) 553 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \ 554 DEFAULT_FIFO_F_D_RFD; 555 556 if (!cd->fdr_value) 557 cd->fdr_value = DEFAULT_FDR_INIT; 558 559 if (!cd->rmcr_value) 560 cd->rmcr_value = DEFAULT_RMCR_VALUE; 561 562 if (!cd->tx_check) 563 cd->tx_check = DEFAULT_TX_CHECK; 564 565 if (!cd->eesr_err_check) 566 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 567 568 if (!cd->tx_error_check) 569 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; 570} 571 572#if defined(SH_ETH_RESET_DEFAULT) 573/* Chip Reset */ 574static int sh_eth_reset(struct net_device *ndev) 575{ 576 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR); 577 mdelay(3); 578 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR); 579 580 return 0; 581} 582#else 583static int sh_eth_check_reset(struct net_device *ndev) 584{ 585 int ret = 0; 586 int cnt = 100; 587 588 while (cnt > 0) { 589 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 590 break; 591 mdelay(1); 592 cnt--; 593 } 594 if (cnt < 0) { 595 pr_err("Device reset fail\n"); 596 ret = -ETIMEDOUT; 597 } 598 return ret; 599} 600#endif 601 602#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 603static void sh_eth_set_receive_align(struct sk_buff *skb) 604{ 605 int reserve; 606 607 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); 608 if (reserve) 609 skb_reserve(skb, reserve); 610} 611#else 612static void sh_eth_set_receive_align(struct sk_buff *skb) 613{ 614 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); 615} 616#endif 617 618 619/* CPU <-> EDMAC endian convert */ 620static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 621{ 622 switch (mdp->edmac_endian) { 623 case EDMAC_LITTLE_ENDIAN: 624 return cpu_to_le32(x); 625 case EDMAC_BIG_ENDIAN: 626 return cpu_to_be32(x); 627 } 628 return x; 629} 630 631static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) 632{ 633 switch (mdp->edmac_endian) { 634 case EDMAC_LITTLE_ENDIAN: 635 return le32_to_cpu(x); 636 case EDMAC_BIG_ENDIAN: 637 return be32_to_cpu(x); 638 } 639 return x; 640} 641 642/* 643 * Program the hardware MAC address from dev->dev_addr. 644 */ 645static void update_mac_address(struct net_device *ndev) 646{ 647 sh_eth_write(ndev, 648 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 649 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 650 sh_eth_write(ndev, 651 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 652} 653 654/* 655 * Get MAC address from SuperH MAC address register 656 * 657 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 658 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 659 * When you want use this device, you must set MAC address in bootloader. 660 * 661 */ 662static void read_mac_address(struct net_device *ndev, unsigned char *mac) 663{ 664 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 665 memcpy(ndev->dev_addr, mac, 6); 666 } else { 667 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24); 668 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF; 669 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF; 670 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF); 671 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF; 672 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF); 673 } 674} 675 676static int sh_eth_is_gether(struct sh_eth_private *mdp) 677{ 678 if (mdp->reg_offset == sh_eth_offset_gigabit) 679 return 1; 680 else 681 return 0; 682} 683 684static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 685{ 686 if (sh_eth_is_gether(mdp)) 687 return EDTRR_TRNS_GETHER; 688 else 689 return EDTRR_TRNS_ETHER; 690} 691 692struct bb_info { 693 void (*set_gate)(void *addr); 694 struct mdiobb_ctrl ctrl; 695 void *addr; 696 u32 mmd_msk;/* MMD */ 697 u32 mdo_msk; 698 u32 mdi_msk; 699 u32 mdc_msk; 700}; 701 702/* PHY bit set */ 703static void bb_set(void *addr, u32 msk) 704{ 705 iowrite32(ioread32(addr) | msk, addr); 706} 707 708/* PHY bit clear */ 709static void bb_clr(void *addr, u32 msk) 710{ 711 iowrite32((ioread32(addr) & ~msk), addr); 712} 713 714/* PHY bit read */ 715static int bb_read(void *addr, u32 msk) 716{ 717 return (ioread32(addr) & msk) != 0; 718} 719 720/* Data I/O pin control */ 721static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 722{ 723 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 724 725 if (bitbang->set_gate) 726 bitbang->set_gate(bitbang->addr); 727 728 if (bit) 729 bb_set(bitbang->addr, bitbang->mmd_msk); 730 else 731 bb_clr(bitbang->addr, bitbang->mmd_msk); 732} 733 734/* Set bit data*/ 735static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 736{ 737 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 738 739 if (bitbang->set_gate) 740 bitbang->set_gate(bitbang->addr); 741 742 if (bit) 743 bb_set(bitbang->addr, bitbang->mdo_msk); 744 else 745 bb_clr(bitbang->addr, bitbang->mdo_msk); 746} 747 748/* Get bit data*/ 749static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 750{ 751 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 752 753 if (bitbang->set_gate) 754 bitbang->set_gate(bitbang->addr); 755 756 return bb_read(bitbang->addr, bitbang->mdi_msk); 757} 758 759/* MDC pin control */ 760static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 761{ 762 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 763 764 if (bitbang->set_gate) 765 bitbang->set_gate(bitbang->addr); 766 767 if (bit) 768 bb_set(bitbang->addr, bitbang->mdc_msk); 769 else 770 bb_clr(bitbang->addr, bitbang->mdc_msk); 771} 772 773/* mdio bus control struct */ 774static struct mdiobb_ops bb_ops = { 775 .owner = THIS_MODULE, 776 .set_mdc = sh_mdc_ctrl, 777 .set_mdio_dir = sh_mmd_ctrl, 778 .set_mdio_data = sh_set_mdio, 779 .get_mdio_data = sh_get_mdio, 780}; 781 782/* free skb and descriptor buffer */ 783static void sh_eth_ring_free(struct net_device *ndev) 784{ 785 struct sh_eth_private *mdp = netdev_priv(ndev); 786 int i; 787 788 /* Free Rx skb ringbuffer */ 789 if (mdp->rx_skbuff) { 790 for (i = 0; i < mdp->num_rx_ring; i++) { 791 if (mdp->rx_skbuff[i]) 792 dev_kfree_skb(mdp->rx_skbuff[i]); 793 } 794 } 795 kfree(mdp->rx_skbuff); 796 mdp->rx_skbuff = NULL; 797 798 /* Free Tx skb ringbuffer */ 799 if (mdp->tx_skbuff) { 800 for (i = 0; i < mdp->num_tx_ring; i++) { 801 if (mdp->tx_skbuff[i]) 802 dev_kfree_skb(mdp->tx_skbuff[i]); 803 } 804 } 805 kfree(mdp->tx_skbuff); 806 mdp->tx_skbuff = NULL; 807} 808 809/* format skb and descriptor buffer */ 810static void sh_eth_ring_format(struct net_device *ndev) 811{ 812 struct sh_eth_private *mdp = netdev_priv(ndev); 813 int i; 814 struct sk_buff *skb; 815 struct sh_eth_rxdesc *rxdesc = NULL; 816 struct sh_eth_txdesc *txdesc = NULL; 817 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 818 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 819 820 mdp->cur_rx = mdp->cur_tx = 0; 821 mdp->dirty_rx = mdp->dirty_tx = 0; 822 823 memset(mdp->rx_ring, 0, rx_ringsize); 824 825 /* build Rx ring buffer */ 826 for (i = 0; i < mdp->num_rx_ring; i++) { 827 /* skb */ 828 mdp->rx_skbuff[i] = NULL; 829 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 830 mdp->rx_skbuff[i] = skb; 831 if (skb == NULL) 832 break; 833 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 834 DMA_FROM_DEVICE); 835 sh_eth_set_receive_align(skb); 836 837 /* RX descriptor */ 838 rxdesc = &mdp->rx_ring[i]; 839 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 840 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); 841 842 /* The size of the buffer is 16 byte boundary. */ 843 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 844 /* Rx descriptor address set */ 845 if (i == 0) { 846 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 847 if (sh_eth_is_gether(mdp)) 848 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 849 } 850 } 851 852 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 853 854 /* Mark the last entry as wrapping the ring. */ 855 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); 856 857 memset(mdp->tx_ring, 0, tx_ringsize); 858 859 /* build Tx ring buffer */ 860 for (i = 0; i < mdp->num_tx_ring; i++) { 861 mdp->tx_skbuff[i] = NULL; 862 txdesc = &mdp->tx_ring[i]; 863 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 864 txdesc->buffer_length = 0; 865 if (i == 0) { 866 /* Tx descriptor address set */ 867 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 868 if (sh_eth_is_gether(mdp)) 869 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 870 } 871 } 872 873 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 874} 875 876/* Get skb and descriptor buffer */ 877static int sh_eth_ring_init(struct net_device *ndev) 878{ 879 struct sh_eth_private *mdp = netdev_priv(ndev); 880 int rx_ringsize, tx_ringsize, ret = 0; 881 882 /* 883 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 884 * card needs room to do 8 byte alignment, +2 so we can reserve 885 * the first 2 bytes, and +16 gets room for the status word from the 886 * card. 887 */ 888 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 889 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 890 if (mdp->cd->rpadir) 891 mdp->rx_buf_sz += NET_IP_ALIGN; 892 893 /* Allocate RX and TX skb rings */ 894 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring, 895 sizeof(*mdp->rx_skbuff), GFP_KERNEL); 896 if (!mdp->rx_skbuff) { 897 ret = -ENOMEM; 898 return ret; 899 } 900 901 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring, 902 sizeof(*mdp->tx_skbuff), GFP_KERNEL); 903 if (!mdp->tx_skbuff) { 904 ret = -ENOMEM; 905 goto skb_ring_free; 906 } 907 908 /* Allocate all Rx descriptors. */ 909 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 910 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 911 GFP_KERNEL); 912 if (!mdp->rx_ring) { 913 ret = -ENOMEM; 914 goto desc_ring_free; 915 } 916 917 mdp->dirty_rx = 0; 918 919 /* Allocate all Tx descriptors. */ 920 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 921 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 922 GFP_KERNEL); 923 if (!mdp->tx_ring) { 924 ret = -ENOMEM; 925 goto desc_ring_free; 926 } 927 return ret; 928 929desc_ring_free: 930 /* free DMA buffer */ 931 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); 932 933skb_ring_free: 934 /* Free Rx and Tx skb ring buffer */ 935 sh_eth_ring_free(ndev); 936 mdp->tx_ring = NULL; 937 mdp->rx_ring = NULL; 938 939 return ret; 940} 941 942static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp) 943{ 944 int ringsize; 945 946 if (mdp->rx_ring) { 947 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 948 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 949 mdp->rx_desc_dma); 950 mdp->rx_ring = NULL; 951 } 952 953 if (mdp->tx_ring) { 954 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 955 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 956 mdp->tx_desc_dma); 957 mdp->tx_ring = NULL; 958 } 959} 960 961static int sh_eth_dev_init(struct net_device *ndev, bool start) 962{ 963 int ret = 0; 964 struct sh_eth_private *mdp = netdev_priv(ndev); 965 u32 val; 966 967 /* Soft Reset */ 968 ret = sh_eth_reset(ndev); 969 if (ret) 970 goto out; 971 972 /* Descriptor format */ 973 sh_eth_ring_format(ndev); 974 if (mdp->cd->rpadir) 975 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 976 977 /* all sh_eth int mask */ 978 sh_eth_write(ndev, 0, EESIPR); 979 980#if defined(__LITTLE_ENDIAN) 981 if (mdp->cd->hw_swap) 982 sh_eth_write(ndev, EDMR_EL, EDMR); 983 else 984#endif 985 sh_eth_write(ndev, 0, EDMR); 986 987 /* FIFO size set */ 988 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 989 sh_eth_write(ndev, 0, TFTR); 990 991 /* Frame recv control */ 992 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR); 993 994 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER); 995 996 if (mdp->cd->bculr) 997 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 998 999 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1000 1001 if (!mdp->cd->no_trimd) 1002 sh_eth_write(ndev, 0, TRIMD); 1003 1004 /* Recv frame limit set register */ 1005 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1006 RFLR); 1007 1008 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 1009 if (start) 1010 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1011 1012 /* PAUSE Prohibition */ 1013 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | 1014 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 1015 1016 sh_eth_write(ndev, val, ECMR); 1017 1018 if (mdp->cd->set_rate) 1019 mdp->cd->set_rate(ndev); 1020 1021 /* E-MAC Status Register clear */ 1022 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1023 1024 /* E-MAC Interrupt Enable register */ 1025 if (start) 1026 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1027 1028 /* Set MAC address */ 1029 update_mac_address(ndev); 1030 1031 /* mask reset */ 1032 if (mdp->cd->apr) 1033 sh_eth_write(ndev, APR_AP, APR); 1034 if (mdp->cd->mpr) 1035 sh_eth_write(ndev, MPR_MP, MPR); 1036 if (mdp->cd->tpauser) 1037 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1038 1039 if (start) { 1040 /* Setting the Rx mode will start the Rx process. */ 1041 sh_eth_write(ndev, EDRRR_R, EDRRR); 1042 1043 netif_start_queue(ndev); 1044 } 1045 1046out: 1047 return ret; 1048} 1049 1050/* free Tx skb function */ 1051static int sh_eth_txfree(struct net_device *ndev) 1052{ 1053 struct sh_eth_private *mdp = netdev_priv(ndev); 1054 struct sh_eth_txdesc *txdesc; 1055 int freeNum = 0; 1056 int entry = 0; 1057 1058 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1059 entry = mdp->dirty_tx % mdp->num_tx_ring; 1060 txdesc = &mdp->tx_ring[entry]; 1061 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 1062 break; 1063 /* Free the original skb. */ 1064 if (mdp->tx_skbuff[entry]) { 1065 dma_unmap_single(&ndev->dev, txdesc->addr, 1066 txdesc->buffer_length, DMA_TO_DEVICE); 1067 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1068 mdp->tx_skbuff[entry] = NULL; 1069 freeNum++; 1070 } 1071 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1072 if (entry >= mdp->num_tx_ring - 1) 1073 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1074 1075 ndev->stats.tx_packets++; 1076 ndev->stats.tx_bytes += txdesc->buffer_length; 1077 } 1078 return freeNum; 1079} 1080 1081/* Packet receive function */ 1082static int sh_eth_rx(struct net_device *ndev, u32 intr_status) 1083{ 1084 struct sh_eth_private *mdp = netdev_priv(ndev); 1085 struct sh_eth_rxdesc *rxdesc; 1086 1087 int entry = mdp->cur_rx % mdp->num_rx_ring; 1088 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1089 struct sk_buff *skb; 1090 u16 pkt_len = 0; 1091 u32 desc_status; 1092 1093 rxdesc = &mdp->rx_ring[entry]; 1094 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1095 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1096 pkt_len = rxdesc->frame_length; 1097 1098#if defined(CONFIG_ARCH_R8A7740) 1099 desc_status >>= 16; 1100#endif 1101 1102 if (--boguscnt < 0) 1103 break; 1104 1105 if (!(desc_status & RDFEND)) 1106 ndev->stats.rx_length_errors++; 1107 1108 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1109 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1110 ndev->stats.rx_errors++; 1111 if (desc_status & RD_RFS1) 1112 ndev->stats.rx_crc_errors++; 1113 if (desc_status & RD_RFS2) 1114 ndev->stats.rx_frame_errors++; 1115 if (desc_status & RD_RFS3) 1116 ndev->stats.rx_length_errors++; 1117 if (desc_status & RD_RFS4) 1118 ndev->stats.rx_length_errors++; 1119 if (desc_status & RD_RFS6) 1120 ndev->stats.rx_missed_errors++; 1121 if (desc_status & RD_RFS10) 1122 ndev->stats.rx_over_errors++; 1123 } else { 1124 if (!mdp->cd->hw_swap) 1125 sh_eth_soft_swap( 1126 phys_to_virt(ALIGN(rxdesc->addr, 4)), 1127 pkt_len + 2); 1128 skb = mdp->rx_skbuff[entry]; 1129 mdp->rx_skbuff[entry] = NULL; 1130 if (mdp->cd->rpadir) 1131 skb_reserve(skb, NET_IP_ALIGN); 1132 skb_put(skb, pkt_len); 1133 skb->protocol = eth_type_trans(skb, ndev); 1134 netif_rx(skb); 1135 ndev->stats.rx_packets++; 1136 ndev->stats.rx_bytes += pkt_len; 1137 } 1138 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); 1139 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1140 rxdesc = &mdp->rx_ring[entry]; 1141 } 1142 1143 /* Refill the Rx ring buffers. */ 1144 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1145 entry = mdp->dirty_rx % mdp->num_rx_ring; 1146 rxdesc = &mdp->rx_ring[entry]; 1147 /* The size of the buffer is 16 byte boundary. */ 1148 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1149 1150 if (mdp->rx_skbuff[entry] == NULL) { 1151 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1152 mdp->rx_skbuff[entry] = skb; 1153 if (skb == NULL) 1154 break; /* Better luck next round. */ 1155 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1156 DMA_FROM_DEVICE); 1157 sh_eth_set_receive_align(skb); 1158 1159 skb_checksum_none_assert(skb); 1160 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1161 } 1162 if (entry >= mdp->num_rx_ring - 1) 1163 rxdesc->status |= 1164 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1165 else 1166 rxdesc->status |= 1167 cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1168 } 1169 1170 /* Restart Rx engine if stopped. */ 1171 /* If we don't need to check status, don't. -KDU */ 1172 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1173 /* fix the values for the next receiving if RDE is set */ 1174 if (intr_status & EESR_RDE) 1175 mdp->cur_rx = mdp->dirty_rx = 1176 (sh_eth_read(ndev, RDFAR) - 1177 sh_eth_read(ndev, RDLAR)) >> 4; 1178 sh_eth_write(ndev, EDRRR_R, EDRRR); 1179 } 1180 1181 return 0; 1182} 1183 1184static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1185{ 1186 /* disable tx and rx */ 1187 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1188 ~(ECMR_RE | ECMR_TE), ECMR); 1189} 1190 1191static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1192{ 1193 /* enable tx and rx */ 1194 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1195 (ECMR_RE | ECMR_TE), ECMR); 1196} 1197 1198/* error control function */ 1199static void sh_eth_error(struct net_device *ndev, int intr_status) 1200{ 1201 struct sh_eth_private *mdp = netdev_priv(ndev); 1202 u32 felic_stat; 1203 u32 link_stat; 1204 u32 mask; 1205 1206 if (intr_status & EESR_ECI) { 1207 felic_stat = sh_eth_read(ndev, ECSR); 1208 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1209 if (felic_stat & ECSR_ICD) 1210 ndev->stats.tx_carrier_errors++; 1211 if (felic_stat & ECSR_LCHNG) { 1212 /* Link Changed */ 1213 if (mdp->cd->no_psr || mdp->no_ether_link) { 1214 if (mdp->link == PHY_DOWN) 1215 link_stat = 0; 1216 else 1217 link_stat = PHY_ST_LINK; 1218 } else { 1219 link_stat = (sh_eth_read(ndev, PSR)); 1220 if (mdp->ether_link_active_low) 1221 link_stat = ~link_stat; 1222 } 1223 if (!(link_stat & PHY_ST_LINK)) 1224 sh_eth_rcv_snd_disable(ndev); 1225 else { 1226 /* Link Up */ 1227 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1228 ~DMAC_M_ECI, EESIPR); 1229 /*clear int */ 1230 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1231 ECSR); 1232 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1233 DMAC_M_ECI, EESIPR); 1234 /* enable tx and rx */ 1235 sh_eth_rcv_snd_enable(ndev); 1236 } 1237 } 1238 } 1239 1240 if (intr_status & EESR_TWB) { 1241 /* Write buck end. unused write back interrupt */ 1242 if (intr_status & EESR_TABT) /* Transmit Abort int */ 1243 ndev->stats.tx_aborted_errors++; 1244 if (netif_msg_tx_err(mdp)) 1245 dev_err(&ndev->dev, "Transmit Abort\n"); 1246 } 1247 1248 if (intr_status & EESR_RABT) { 1249 /* Receive Abort int */ 1250 if (intr_status & EESR_RFRMER) { 1251 /* Receive Frame Overflow int */ 1252 ndev->stats.rx_frame_errors++; 1253 if (netif_msg_rx_err(mdp)) 1254 dev_err(&ndev->dev, "Receive Abort\n"); 1255 } 1256 } 1257 1258 if (intr_status & EESR_TDE) { 1259 /* Transmit Descriptor Empty int */ 1260 ndev->stats.tx_fifo_errors++; 1261 if (netif_msg_tx_err(mdp)) 1262 dev_err(&ndev->dev, "Transmit Descriptor Empty\n"); 1263 } 1264 1265 if (intr_status & EESR_TFE) { 1266 /* FIFO under flow */ 1267 ndev->stats.tx_fifo_errors++; 1268 if (netif_msg_tx_err(mdp)) 1269 dev_err(&ndev->dev, "Transmit FIFO Under flow\n"); 1270 } 1271 1272 if (intr_status & EESR_RDE) { 1273 /* Receive Descriptor Empty int */ 1274 ndev->stats.rx_over_errors++; 1275 1276 if (netif_msg_rx_err(mdp)) 1277 dev_err(&ndev->dev, "Receive Descriptor Empty\n"); 1278 } 1279 1280 if (intr_status & EESR_RFE) { 1281 /* Receive FIFO Overflow int */ 1282 ndev->stats.rx_fifo_errors++; 1283 if (netif_msg_rx_err(mdp)) 1284 dev_err(&ndev->dev, "Receive FIFO Overflow\n"); 1285 } 1286 1287 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1288 /* Address Error */ 1289 ndev->stats.tx_fifo_errors++; 1290 if (netif_msg_tx_err(mdp)) 1291 dev_err(&ndev->dev, "Address Error\n"); 1292 } 1293 1294 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1295 if (mdp->cd->no_ade) 1296 mask &= ~EESR_ADE; 1297 if (intr_status & mask) { 1298 /* Tx error */ 1299 u32 edtrr = sh_eth_read(ndev, EDTRR); 1300 /* dmesg */ 1301 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ", 1302 intr_status, mdp->cur_tx); 1303 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1304 mdp->dirty_tx, (u32) ndev->state, edtrr); 1305 /* dirty buffer free */ 1306 sh_eth_txfree(ndev); 1307 1308 /* SH7712 BUG */ 1309 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1310 /* tx dma start */ 1311 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1312 } 1313 /* wakeup */ 1314 netif_wake_queue(ndev); 1315 } 1316} 1317 1318static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1319{ 1320 struct net_device *ndev = netdev; 1321 struct sh_eth_private *mdp = netdev_priv(ndev); 1322 struct sh_eth_cpu_data *cd = mdp->cd; 1323 irqreturn_t ret = IRQ_NONE; 1324 u32 intr_status = 0; 1325 1326 spin_lock(&mdp->lock); 1327 1328 /* Get interrpt stat */ 1329 intr_status = sh_eth_read(ndev, EESR); 1330 /* Clear interrupt */ 1331 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | 1332 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | 1333 cd->tx_check | cd->eesr_err_check)) { 1334 sh_eth_write(ndev, intr_status, EESR); 1335 ret = IRQ_HANDLED; 1336 } else 1337 goto other_irq; 1338 1339 if (intr_status & (EESR_FRC | /* Frame recv*/ 1340 EESR_RMAF | /* Multi cast address recv*/ 1341 EESR_RRF | /* Bit frame recv */ 1342 EESR_RTLF | /* Long frame recv*/ 1343 EESR_RTSF | /* short frame recv */ 1344 EESR_PRE | /* PHY-LSI recv error */ 1345 EESR_CERF)){ /* recv frame CRC error */ 1346 sh_eth_rx(ndev, intr_status); 1347 } 1348 1349 /* Tx Check */ 1350 if (intr_status & cd->tx_check) { 1351 sh_eth_txfree(ndev); 1352 netif_wake_queue(ndev); 1353 } 1354 1355 if (intr_status & cd->eesr_err_check) 1356 sh_eth_error(ndev, intr_status); 1357 1358other_irq: 1359 spin_unlock(&mdp->lock); 1360 1361 return ret; 1362} 1363 1364/* PHY state control function */ 1365static void sh_eth_adjust_link(struct net_device *ndev) 1366{ 1367 struct sh_eth_private *mdp = netdev_priv(ndev); 1368 struct phy_device *phydev = mdp->phydev; 1369 int new_state = 0; 1370 1371 if (phydev->link != PHY_DOWN) { 1372 if (phydev->duplex != mdp->duplex) { 1373 new_state = 1; 1374 mdp->duplex = phydev->duplex; 1375 if (mdp->cd->set_duplex) 1376 mdp->cd->set_duplex(ndev); 1377 } 1378 1379 if (phydev->speed != mdp->speed) { 1380 new_state = 1; 1381 mdp->speed = phydev->speed; 1382 if (mdp->cd->set_rate) 1383 mdp->cd->set_rate(ndev); 1384 } 1385 if (mdp->link == PHY_DOWN) { 1386 sh_eth_write(ndev, 1387 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR); 1388 new_state = 1; 1389 mdp->link = phydev->link; 1390 } 1391 } else if (mdp->link) { 1392 new_state = 1; 1393 mdp->link = PHY_DOWN; 1394 mdp->speed = 0; 1395 mdp->duplex = -1; 1396 } 1397 1398 if (new_state && netif_msg_link(mdp)) 1399 phy_print_status(phydev); 1400} 1401 1402/* PHY init function */ 1403static int sh_eth_phy_init(struct net_device *ndev) 1404{ 1405 struct sh_eth_private *mdp = netdev_priv(ndev); 1406 char phy_id[MII_BUS_ID_SIZE + 3]; 1407 struct phy_device *phydev = NULL; 1408 1409 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1410 mdp->mii_bus->id , mdp->phy_id); 1411 1412 mdp->link = PHY_DOWN; 1413 mdp->speed = 0; 1414 mdp->duplex = -1; 1415 1416 /* Try connect to PHY */ 1417 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1418 mdp->phy_interface); 1419 if (IS_ERR(phydev)) { 1420 dev_err(&ndev->dev, "phy_connect failed\n"); 1421 return PTR_ERR(phydev); 1422 } 1423 1424 dev_info(&ndev->dev, "attached phy %i to driver %s\n", 1425 phydev->addr, phydev->drv->name); 1426 1427 mdp->phydev = phydev; 1428 1429 return 0; 1430} 1431 1432/* PHY control start function */ 1433static int sh_eth_phy_start(struct net_device *ndev) 1434{ 1435 struct sh_eth_private *mdp = netdev_priv(ndev); 1436 int ret; 1437 1438 ret = sh_eth_phy_init(ndev); 1439 if (ret) 1440 return ret; 1441 1442 /* reset phy - this also wakes it from PDOWN */ 1443 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET); 1444 phy_start(mdp->phydev); 1445 1446 return 0; 1447} 1448 1449static int sh_eth_get_settings(struct net_device *ndev, 1450 struct ethtool_cmd *ecmd) 1451{ 1452 struct sh_eth_private *mdp = netdev_priv(ndev); 1453 unsigned long flags; 1454 int ret; 1455 1456 spin_lock_irqsave(&mdp->lock, flags); 1457 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1458 spin_unlock_irqrestore(&mdp->lock, flags); 1459 1460 return ret; 1461} 1462 1463static int sh_eth_set_settings(struct net_device *ndev, 1464 struct ethtool_cmd *ecmd) 1465{ 1466 struct sh_eth_private *mdp = netdev_priv(ndev); 1467 unsigned long flags; 1468 int ret; 1469 1470 spin_lock_irqsave(&mdp->lock, flags); 1471 1472 /* disable tx and rx */ 1473 sh_eth_rcv_snd_disable(ndev); 1474 1475 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1476 if (ret) 1477 goto error_exit; 1478 1479 if (ecmd->duplex == DUPLEX_FULL) 1480 mdp->duplex = 1; 1481 else 1482 mdp->duplex = 0; 1483 1484 if (mdp->cd->set_duplex) 1485 mdp->cd->set_duplex(ndev); 1486 1487error_exit: 1488 mdelay(1); 1489 1490 /* enable tx and rx */ 1491 sh_eth_rcv_snd_enable(ndev); 1492 1493 spin_unlock_irqrestore(&mdp->lock, flags); 1494 1495 return ret; 1496} 1497 1498static int sh_eth_nway_reset(struct net_device *ndev) 1499{ 1500 struct sh_eth_private *mdp = netdev_priv(ndev); 1501 unsigned long flags; 1502 int ret; 1503 1504 spin_lock_irqsave(&mdp->lock, flags); 1505 ret = phy_start_aneg(mdp->phydev); 1506 spin_unlock_irqrestore(&mdp->lock, flags); 1507 1508 return ret; 1509} 1510 1511static u32 sh_eth_get_msglevel(struct net_device *ndev) 1512{ 1513 struct sh_eth_private *mdp = netdev_priv(ndev); 1514 return mdp->msg_enable; 1515} 1516 1517static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 1518{ 1519 struct sh_eth_private *mdp = netdev_priv(ndev); 1520 mdp->msg_enable = value; 1521} 1522 1523static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 1524 "rx_current", "tx_current", 1525 "rx_dirty", "tx_dirty", 1526}; 1527#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 1528 1529static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 1530{ 1531 switch (sset) { 1532 case ETH_SS_STATS: 1533 return SH_ETH_STATS_LEN; 1534 default: 1535 return -EOPNOTSUPP; 1536 } 1537} 1538 1539static void sh_eth_get_ethtool_stats(struct net_device *ndev, 1540 struct ethtool_stats *stats, u64 *data) 1541{ 1542 struct sh_eth_private *mdp = netdev_priv(ndev); 1543 int i = 0; 1544 1545 /* device-specific stats */ 1546 data[i++] = mdp->cur_rx; 1547 data[i++] = mdp->cur_tx; 1548 data[i++] = mdp->dirty_rx; 1549 data[i++] = mdp->dirty_tx; 1550} 1551 1552static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1553{ 1554 switch (stringset) { 1555 case ETH_SS_STATS: 1556 memcpy(data, *sh_eth_gstrings_stats, 1557 sizeof(sh_eth_gstrings_stats)); 1558 break; 1559 } 1560} 1561 1562static void sh_eth_get_ringparam(struct net_device *ndev, 1563 struct ethtool_ringparam *ring) 1564{ 1565 struct sh_eth_private *mdp = netdev_priv(ndev); 1566 1567 ring->rx_max_pending = RX_RING_MAX; 1568 ring->tx_max_pending = TX_RING_MAX; 1569 ring->rx_pending = mdp->num_rx_ring; 1570 ring->tx_pending = mdp->num_tx_ring; 1571} 1572 1573static int sh_eth_set_ringparam(struct net_device *ndev, 1574 struct ethtool_ringparam *ring) 1575{ 1576 struct sh_eth_private *mdp = netdev_priv(ndev); 1577 int ret; 1578 1579 if (ring->tx_pending > TX_RING_MAX || 1580 ring->rx_pending > RX_RING_MAX || 1581 ring->tx_pending < TX_RING_MIN || 1582 ring->rx_pending < RX_RING_MIN) 1583 return -EINVAL; 1584 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1585 return -EINVAL; 1586 1587 if (netif_running(ndev)) { 1588 netif_tx_disable(ndev); 1589 /* Disable interrupts by clearing the interrupt mask. */ 1590 sh_eth_write(ndev, 0x0000, EESIPR); 1591 /* Stop the chip's Tx and Rx processes. */ 1592 sh_eth_write(ndev, 0, EDTRR); 1593 sh_eth_write(ndev, 0, EDRRR); 1594 synchronize_irq(ndev->irq); 1595 } 1596 1597 /* Free all the skbuffs in the Rx queue. */ 1598 sh_eth_ring_free(ndev); 1599 /* Free DMA buffer */ 1600 sh_eth_free_dma_buffer(mdp); 1601 1602 /* Set new parameters */ 1603 mdp->num_rx_ring = ring->rx_pending; 1604 mdp->num_tx_ring = ring->tx_pending; 1605 1606 ret = sh_eth_ring_init(ndev); 1607 if (ret < 0) { 1608 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__); 1609 return ret; 1610 } 1611 ret = sh_eth_dev_init(ndev, false); 1612 if (ret < 0) { 1613 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__); 1614 return ret; 1615 } 1616 1617 if (netif_running(ndev)) { 1618 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1619 /* Setting the Rx mode will start the Rx process. */ 1620 sh_eth_write(ndev, EDRRR_R, EDRRR); 1621 netif_wake_queue(ndev); 1622 } 1623 1624 return 0; 1625} 1626 1627static const struct ethtool_ops sh_eth_ethtool_ops = { 1628 .get_settings = sh_eth_get_settings, 1629 .set_settings = sh_eth_set_settings, 1630 .nway_reset = sh_eth_nway_reset, 1631 .get_msglevel = sh_eth_get_msglevel, 1632 .set_msglevel = sh_eth_set_msglevel, 1633 .get_link = ethtool_op_get_link, 1634 .get_strings = sh_eth_get_strings, 1635 .get_ethtool_stats = sh_eth_get_ethtool_stats, 1636 .get_sset_count = sh_eth_get_sset_count, 1637 .get_ringparam = sh_eth_get_ringparam, 1638 .set_ringparam = sh_eth_set_ringparam, 1639}; 1640 1641/* network device open function */ 1642static int sh_eth_open(struct net_device *ndev) 1643{ 1644 int ret = 0; 1645 struct sh_eth_private *mdp = netdev_priv(ndev); 1646 1647 pm_runtime_get_sync(&mdp->pdev->dev); 1648 1649 ret = request_irq(ndev->irq, sh_eth_interrupt, 1650#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 1651 defined(CONFIG_CPU_SUBTYPE_SH7764) || \ 1652 defined(CONFIG_CPU_SUBTYPE_SH7757) 1653 IRQF_SHARED, 1654#else 1655 0, 1656#endif 1657 ndev->name, ndev); 1658 if (ret) { 1659 dev_err(&ndev->dev, "Can not assign IRQ number\n"); 1660 return ret; 1661 } 1662 1663 /* Descriptor set */ 1664 ret = sh_eth_ring_init(ndev); 1665 if (ret) 1666 goto out_free_irq; 1667 1668 /* device init */ 1669 ret = sh_eth_dev_init(ndev, true); 1670 if (ret) 1671 goto out_free_irq; 1672 1673 /* PHY control start*/ 1674 ret = sh_eth_phy_start(ndev); 1675 if (ret) 1676 goto out_free_irq; 1677 1678 return ret; 1679 1680out_free_irq: 1681 free_irq(ndev->irq, ndev); 1682 pm_runtime_put_sync(&mdp->pdev->dev); 1683 return ret; 1684} 1685 1686/* Timeout function */ 1687static void sh_eth_tx_timeout(struct net_device *ndev) 1688{ 1689 struct sh_eth_private *mdp = netdev_priv(ndev); 1690 struct sh_eth_rxdesc *rxdesc; 1691 int i; 1692 1693 netif_stop_queue(ndev); 1694 1695 if (netif_msg_timer(mdp)) 1696 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x," 1697 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR)); 1698 1699 /* tx_errors count up */ 1700 ndev->stats.tx_errors++; 1701 1702 /* Free all the skbuffs in the Rx queue. */ 1703 for (i = 0; i < mdp->num_rx_ring; i++) { 1704 rxdesc = &mdp->rx_ring[i]; 1705 rxdesc->status = 0; 1706 rxdesc->addr = 0xBADF00D0; 1707 if (mdp->rx_skbuff[i]) 1708 dev_kfree_skb(mdp->rx_skbuff[i]); 1709 mdp->rx_skbuff[i] = NULL; 1710 } 1711 for (i = 0; i < mdp->num_tx_ring; i++) { 1712 if (mdp->tx_skbuff[i]) 1713 dev_kfree_skb(mdp->tx_skbuff[i]); 1714 mdp->tx_skbuff[i] = NULL; 1715 } 1716 1717 /* device init */ 1718 sh_eth_dev_init(ndev, true); 1719} 1720 1721/* Packet transmit function */ 1722static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1723{ 1724 struct sh_eth_private *mdp = netdev_priv(ndev); 1725 struct sh_eth_txdesc *txdesc; 1726 u32 entry; 1727 unsigned long flags; 1728 1729 spin_lock_irqsave(&mdp->lock, flags); 1730 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 1731 if (!sh_eth_txfree(ndev)) { 1732 if (netif_msg_tx_queued(mdp)) 1733 dev_warn(&ndev->dev, "TxFD exhausted.\n"); 1734 netif_stop_queue(ndev); 1735 spin_unlock_irqrestore(&mdp->lock, flags); 1736 return NETDEV_TX_BUSY; 1737 } 1738 } 1739 spin_unlock_irqrestore(&mdp->lock, flags); 1740 1741 entry = mdp->cur_tx % mdp->num_tx_ring; 1742 mdp->tx_skbuff[entry] = skb; 1743 txdesc = &mdp->tx_ring[entry]; 1744 /* soft swap. */ 1745 if (!mdp->cd->hw_swap) 1746 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), 1747 skb->len + 2); 1748 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, 1749 DMA_TO_DEVICE); 1750 if (skb->len < ETHERSMALL) 1751 txdesc->buffer_length = ETHERSMALL; 1752 else 1753 txdesc->buffer_length = skb->len; 1754 1755 if (entry >= mdp->num_tx_ring - 1) 1756 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 1757 else 1758 txdesc->status |= cpu_to_edmac(mdp, TD_TACT); 1759 1760 mdp->cur_tx++; 1761 1762 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 1763 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1764 1765 return NETDEV_TX_OK; 1766} 1767 1768/* device close function */ 1769static int sh_eth_close(struct net_device *ndev) 1770{ 1771 struct sh_eth_private *mdp = netdev_priv(ndev); 1772 1773 netif_stop_queue(ndev); 1774 1775 /* Disable interrupts by clearing the interrupt mask. */ 1776 sh_eth_write(ndev, 0x0000, EESIPR); 1777 1778 /* Stop the chip's Tx and Rx processes. */ 1779 sh_eth_write(ndev, 0, EDTRR); 1780 sh_eth_write(ndev, 0, EDRRR); 1781 1782 /* PHY Disconnect */ 1783 if (mdp->phydev) { 1784 phy_stop(mdp->phydev); 1785 phy_disconnect(mdp->phydev); 1786 } 1787 1788 free_irq(ndev->irq, ndev); 1789 1790 /* Free all the skbuffs in the Rx queue. */ 1791 sh_eth_ring_free(ndev); 1792 1793 /* free DMA buffer */ 1794 sh_eth_free_dma_buffer(mdp); 1795 1796 pm_runtime_put_sync(&mdp->pdev->dev); 1797 1798 return 0; 1799} 1800 1801static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 1802{ 1803 struct sh_eth_private *mdp = netdev_priv(ndev); 1804 1805 pm_runtime_get_sync(&mdp->pdev->dev); 1806 1807 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR); 1808 sh_eth_write(ndev, 0, TROCR); /* (write clear) */ 1809 ndev->stats.collisions += sh_eth_read(ndev, CDCR); 1810 sh_eth_write(ndev, 0, CDCR); /* (write clear) */ 1811 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); 1812 sh_eth_write(ndev, 0, LCCR); /* (write clear) */ 1813 if (sh_eth_is_gether(mdp)) { 1814 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR); 1815 sh_eth_write(ndev, 0, CERCR); /* (write clear) */ 1816 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR); 1817 sh_eth_write(ndev, 0, CEECR); /* (write clear) */ 1818 } else { 1819 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); 1820 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ 1821 } 1822 pm_runtime_put_sync(&mdp->pdev->dev); 1823 1824 return &ndev->stats; 1825} 1826 1827/* ioctl to device function */ 1828static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, 1829 int cmd) 1830{ 1831 struct sh_eth_private *mdp = netdev_priv(ndev); 1832 struct phy_device *phydev = mdp->phydev; 1833 1834 if (!netif_running(ndev)) 1835 return -EINVAL; 1836 1837 if (!phydev) 1838 return -ENODEV; 1839 1840 return phy_mii_ioctl(phydev, rq, cmd); 1841} 1842 1843#if defined(SH_ETH_HAS_TSU) 1844/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 1845static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 1846 int entry) 1847{ 1848 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 1849} 1850 1851static u32 sh_eth_tsu_get_post_mask(int entry) 1852{ 1853 return 0x0f << (28 - ((entry % 8) * 4)); 1854} 1855 1856static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 1857{ 1858 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 1859} 1860 1861static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 1862 int entry) 1863{ 1864 struct sh_eth_private *mdp = netdev_priv(ndev); 1865 u32 tmp; 1866 void *reg_offset; 1867 1868 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 1869 tmp = ioread32(reg_offset); 1870 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 1871} 1872 1873static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 1874 int entry) 1875{ 1876 struct sh_eth_private *mdp = netdev_priv(ndev); 1877 u32 post_mask, ref_mask, tmp; 1878 void *reg_offset; 1879 1880 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 1881 post_mask = sh_eth_tsu_get_post_mask(entry); 1882 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 1883 1884 tmp = ioread32(reg_offset); 1885 iowrite32(tmp & ~post_mask, reg_offset); 1886 1887 /* If other port enables, the function returns "true" */ 1888 return tmp & ref_mask; 1889} 1890 1891static int sh_eth_tsu_busy(struct net_device *ndev) 1892{ 1893 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 1894 struct sh_eth_private *mdp = netdev_priv(ndev); 1895 1896 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 1897 udelay(10); 1898 timeout--; 1899 if (timeout <= 0) { 1900 dev_err(&ndev->dev, "%s: timeout\n", __func__); 1901 return -ETIMEDOUT; 1902 } 1903 } 1904 1905 return 0; 1906} 1907 1908static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 1909 const u8 *addr) 1910{ 1911 u32 val; 1912 1913 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 1914 iowrite32(val, reg); 1915 if (sh_eth_tsu_busy(ndev) < 0) 1916 return -EBUSY; 1917 1918 val = addr[4] << 8 | addr[5]; 1919 iowrite32(val, reg + 4); 1920 if (sh_eth_tsu_busy(ndev) < 0) 1921 return -EBUSY; 1922 1923 return 0; 1924} 1925 1926static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 1927{ 1928 u32 val; 1929 1930 val = ioread32(reg); 1931 addr[0] = (val >> 24) & 0xff; 1932 addr[1] = (val >> 16) & 0xff; 1933 addr[2] = (val >> 8) & 0xff; 1934 addr[3] = val & 0xff; 1935 val = ioread32(reg + 4); 1936 addr[4] = (val >> 8) & 0xff; 1937 addr[5] = val & 0xff; 1938} 1939 1940 1941static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 1942{ 1943 struct sh_eth_private *mdp = netdev_priv(ndev); 1944 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 1945 int i; 1946 u8 c_addr[ETH_ALEN]; 1947 1948 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 1949 sh_eth_tsu_read_entry(reg_offset, c_addr); 1950 if (memcmp(addr, c_addr, ETH_ALEN) == 0) 1951 return i; 1952 } 1953 1954 return -ENOENT; 1955} 1956 1957static int sh_eth_tsu_find_empty(struct net_device *ndev) 1958{ 1959 u8 blank[ETH_ALEN]; 1960 int entry; 1961 1962 memset(blank, 0, sizeof(blank)); 1963 entry = sh_eth_tsu_find_entry(ndev, blank); 1964 return (entry < 0) ? -ENOMEM : entry; 1965} 1966 1967static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 1968 int entry) 1969{ 1970 struct sh_eth_private *mdp = netdev_priv(ndev); 1971 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 1972 int ret; 1973 u8 blank[ETH_ALEN]; 1974 1975 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 1976 ~(1 << (31 - entry)), TSU_TEN); 1977 1978 memset(blank, 0, sizeof(blank)); 1979 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 1980 if (ret < 0) 1981 return ret; 1982 return 0; 1983} 1984 1985static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 1986{ 1987 struct sh_eth_private *mdp = netdev_priv(ndev); 1988 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 1989 int i, ret; 1990 1991 if (!mdp->cd->tsu) 1992 return 0; 1993 1994 i = sh_eth_tsu_find_entry(ndev, addr); 1995 if (i < 0) { 1996 /* No entry found, create one */ 1997 i = sh_eth_tsu_find_empty(ndev); 1998 if (i < 0) 1999 return -ENOMEM; 2000 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2001 if (ret < 0) 2002 return ret; 2003 2004 /* Enable the entry */ 2005 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2006 (1 << (31 - i)), TSU_TEN); 2007 } 2008 2009 /* Entry found or created, enable POST */ 2010 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2011 2012 return 0; 2013} 2014 2015static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2016{ 2017 struct sh_eth_private *mdp = netdev_priv(ndev); 2018 int i, ret; 2019 2020 if (!mdp->cd->tsu) 2021 return 0; 2022 2023 i = sh_eth_tsu_find_entry(ndev, addr); 2024 if (i) { 2025 /* Entry found */ 2026 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2027 goto done; 2028 2029 /* Disable the entry if both ports was disabled */ 2030 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2031 if (ret < 0) 2032 return ret; 2033 } 2034done: 2035 return 0; 2036} 2037 2038static int sh_eth_tsu_purge_all(struct net_device *ndev) 2039{ 2040 struct sh_eth_private *mdp = netdev_priv(ndev); 2041 int i, ret; 2042 2043 if (unlikely(!mdp->cd->tsu)) 2044 return 0; 2045 2046 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2047 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2048 continue; 2049 2050 /* Disable the entry if both ports was disabled */ 2051 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2052 if (ret < 0) 2053 return ret; 2054 } 2055 2056 return 0; 2057} 2058 2059static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2060{ 2061 struct sh_eth_private *mdp = netdev_priv(ndev); 2062 u8 addr[ETH_ALEN]; 2063 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2064 int i; 2065 2066 if (unlikely(!mdp->cd->tsu)) 2067 return; 2068 2069 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2070 sh_eth_tsu_read_entry(reg_offset, addr); 2071 if (is_multicast_ether_addr(addr)) 2072 sh_eth_tsu_del_entry(ndev, addr); 2073 } 2074} 2075 2076/* Multicast reception directions set */ 2077static void sh_eth_set_multicast_list(struct net_device *ndev) 2078{ 2079 struct sh_eth_private *mdp = netdev_priv(ndev); 2080 u32 ecmr_bits; 2081 int mcast_all = 0; 2082 unsigned long flags; 2083 2084 spin_lock_irqsave(&mdp->lock, flags); 2085 /* 2086 * Initial condition is MCT = 1, PRM = 0. 2087 * Depending on ndev->flags, set PRM or clear MCT 2088 */ 2089 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT; 2090 2091 if (!(ndev->flags & IFF_MULTICAST)) { 2092 sh_eth_tsu_purge_mcast(ndev); 2093 mcast_all = 1; 2094 } 2095 if (ndev->flags & IFF_ALLMULTI) { 2096 sh_eth_tsu_purge_mcast(ndev); 2097 ecmr_bits &= ~ECMR_MCT; 2098 mcast_all = 1; 2099 } 2100 2101 if (ndev->flags & IFF_PROMISC) { 2102 sh_eth_tsu_purge_all(ndev); 2103 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2104 } else if (mdp->cd->tsu) { 2105 struct netdev_hw_addr *ha; 2106 netdev_for_each_mc_addr(ha, ndev) { 2107 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2108 continue; 2109 2110 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2111 if (!mcast_all) { 2112 sh_eth_tsu_purge_mcast(ndev); 2113 ecmr_bits &= ~ECMR_MCT; 2114 mcast_all = 1; 2115 } 2116 } 2117 } 2118 } else { 2119 /* Normal, unicast/broadcast-only mode. */ 2120 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT; 2121 } 2122 2123 /* update the ethernet mode */ 2124 sh_eth_write(ndev, ecmr_bits, ECMR); 2125 2126 spin_unlock_irqrestore(&mdp->lock, flags); 2127} 2128 2129static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2130{ 2131 if (!mdp->port) 2132 return TSU_VTAG0; 2133 else 2134 return TSU_VTAG1; 2135} 2136 2137static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, u16 vid) 2138{ 2139 struct sh_eth_private *mdp = netdev_priv(ndev); 2140 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2141 2142 if (unlikely(!mdp->cd->tsu)) 2143 return -EPERM; 2144 2145 /* No filtering if vid = 0 */ 2146 if (!vid) 2147 return 0; 2148 2149 mdp->vlan_num_ids++; 2150 2151 /* 2152 * The controller has one VLAN tag HW filter. So, if the filter is 2153 * already enabled, the driver disables it and the filte 2154 */ 2155 if (mdp->vlan_num_ids > 1) { 2156 /* disable VLAN filter */ 2157 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2158 return 0; 2159 } 2160 2161 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2162 vtag_reg_index); 2163 2164 return 0; 2165} 2166 2167static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, u16 vid) 2168{ 2169 struct sh_eth_private *mdp = netdev_priv(ndev); 2170 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2171 2172 if (unlikely(!mdp->cd->tsu)) 2173 return -EPERM; 2174 2175 /* No filtering if vid = 0 */ 2176 if (!vid) 2177 return 0; 2178 2179 mdp->vlan_num_ids--; 2180 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2181 2182 return 0; 2183} 2184#endif /* SH_ETH_HAS_TSU */ 2185 2186/* SuperH's TSU register init function */ 2187static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2188{ 2189 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2190 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2191 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2192 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2193 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2194 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2195 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2196 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2197 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2198 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2199 if (sh_eth_is_gether(mdp)) { 2200 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2201 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2202 } else { 2203 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2204 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2205 } 2206 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2207 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2208 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2209 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2210 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2211 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2212 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2213} 2214 2215/* MDIO bus release function */ 2216static int sh_mdio_release(struct net_device *ndev) 2217{ 2218 struct sh_eth_private *mdp = netdev_priv(ndev); 2219 struct mii_bus *bus = dev_get_drvdata(&ndev->dev); 2220 2221 /* unregister mdio bus */ 2222 mdiobus_unregister(bus); 2223 2224 /* remove mdio bus info from net_device */ 2225 dev_set_drvdata(&ndev->dev, NULL); 2226 2227 /* free interrupts memory */ 2228 kfree(bus->irq); 2229 2230 /* free bitbang info */ 2231 free_mdio_bitbang(bus); 2232 2233 /* free bitbang memory */ 2234 kfree(mdp->bitbang); 2235 2236 return 0; 2237} 2238 2239/* MDIO bus init function */ 2240static int sh_mdio_init(struct net_device *ndev, int id, 2241 struct sh_eth_plat_data *pd) 2242{ 2243 int ret, i; 2244 struct bb_info *bitbang; 2245 struct sh_eth_private *mdp = netdev_priv(ndev); 2246 2247 /* create bit control struct for PHY */ 2248 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL); 2249 if (!bitbang) { 2250 ret = -ENOMEM; 2251 goto out; 2252 } 2253 2254 /* bitbang init */ 2255 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2256 bitbang->set_gate = pd->set_mdio_gate; 2257 bitbang->mdi_msk = PIR_MDI; 2258 bitbang->mdo_msk = PIR_MDO; 2259 bitbang->mmd_msk = PIR_MMD; 2260 bitbang->mdc_msk = PIR_MDC; 2261 bitbang->ctrl.ops = &bb_ops; 2262 2263 /* MII controller setting */ 2264 mdp->bitbang = bitbang; 2265 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2266 if (!mdp->mii_bus) { 2267 ret = -ENOMEM; 2268 goto out_free_bitbang; 2269 } 2270 2271 /* Hook up MII support for ethtool */ 2272 mdp->mii_bus->name = "sh_mii"; 2273 mdp->mii_bus->parent = &ndev->dev; 2274 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2275 mdp->pdev->name, id); 2276 2277 /* PHY IRQ */ 2278 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); 2279 if (!mdp->mii_bus->irq) { 2280 ret = -ENOMEM; 2281 goto out_free_bus; 2282 } 2283 2284 for (i = 0; i < PHY_MAX_ADDR; i++) 2285 mdp->mii_bus->irq[i] = PHY_POLL; 2286 2287 /* register mdio bus */ 2288 ret = mdiobus_register(mdp->mii_bus); 2289 if (ret) 2290 goto out_free_irq; 2291 2292 dev_set_drvdata(&ndev->dev, mdp->mii_bus); 2293 2294 return 0; 2295 2296out_free_irq: 2297 kfree(mdp->mii_bus->irq); 2298 2299out_free_bus: 2300 free_mdio_bitbang(mdp->mii_bus); 2301 2302out_free_bitbang: 2303 kfree(bitbang); 2304 2305out: 2306 return ret; 2307} 2308 2309static const u16 *sh_eth_get_register_offset(int register_type) 2310{ 2311 const u16 *reg_offset = NULL; 2312 2313 switch (register_type) { 2314 case SH_ETH_REG_GIGABIT: 2315 reg_offset = sh_eth_offset_gigabit; 2316 break; 2317 case SH_ETH_REG_FAST_SH4: 2318 reg_offset = sh_eth_offset_fast_sh4; 2319 break; 2320 case SH_ETH_REG_FAST_SH3_SH2: 2321 reg_offset = sh_eth_offset_fast_sh3_sh2; 2322 break; 2323 default: 2324 pr_err("Unknown register type (%d)\n", register_type); 2325 break; 2326 } 2327 2328 return reg_offset; 2329} 2330 2331static const struct net_device_ops sh_eth_netdev_ops = { 2332 .ndo_open = sh_eth_open, 2333 .ndo_stop = sh_eth_close, 2334 .ndo_start_xmit = sh_eth_start_xmit, 2335 .ndo_get_stats = sh_eth_get_stats, 2336#if defined(SH_ETH_HAS_TSU) 2337 .ndo_set_rx_mode = sh_eth_set_multicast_list, 2338 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 2339 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 2340#endif 2341 .ndo_tx_timeout = sh_eth_tx_timeout, 2342 .ndo_do_ioctl = sh_eth_do_ioctl, 2343 .ndo_validate_addr = eth_validate_addr, 2344 .ndo_set_mac_address = eth_mac_addr, 2345 .ndo_change_mtu = eth_change_mtu, 2346}; 2347 2348static int sh_eth_drv_probe(struct platform_device *pdev) 2349{ 2350 int ret, devno = 0; 2351 struct resource *res; 2352 struct net_device *ndev = NULL; 2353 struct sh_eth_private *mdp = NULL; 2354 struct sh_eth_plat_data *pd = pdev->dev.platform_data; 2355 2356 /* get base addr */ 2357 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2358 if (unlikely(res == NULL)) { 2359 dev_err(&pdev->dev, "invalid resource\n"); 2360 ret = -EINVAL; 2361 goto out; 2362 } 2363 2364 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 2365 if (!ndev) { 2366 ret = -ENOMEM; 2367 goto out; 2368 } 2369 2370 /* The sh Ether-specific entries in the device structure. */ 2371 ndev->base_addr = res->start; 2372 devno = pdev->id; 2373 if (devno < 0) 2374 devno = 0; 2375 2376 ndev->dma = -1; 2377 ret = platform_get_irq(pdev, 0); 2378 if (ret < 0) { 2379 ret = -ENODEV; 2380 goto out_release; 2381 } 2382 ndev->irq = ret; 2383 2384 SET_NETDEV_DEV(ndev, &pdev->dev); 2385 2386 /* Fill in the fields of the device structure with ethernet values. */ 2387 ether_setup(ndev); 2388 2389 mdp = netdev_priv(ndev); 2390 mdp->num_tx_ring = TX_RING_SIZE; 2391 mdp->num_rx_ring = RX_RING_SIZE; 2392 mdp->addr = ioremap(res->start, resource_size(res)); 2393 if (mdp->addr == NULL) { 2394 ret = -ENOMEM; 2395 dev_err(&pdev->dev, "ioremap failed.\n"); 2396 goto out_release; 2397 } 2398 2399 spin_lock_init(&mdp->lock); 2400 mdp->pdev = pdev; 2401 pm_runtime_enable(&pdev->dev); 2402 pm_runtime_resume(&pdev->dev); 2403 2404 /* get PHY ID */ 2405 mdp->phy_id = pd->phy; 2406 mdp->phy_interface = pd->phy_interface; 2407 /* EDMAC endian */ 2408 mdp->edmac_endian = pd->edmac_endian; 2409 mdp->no_ether_link = pd->no_ether_link; 2410 mdp->ether_link_active_low = pd->ether_link_active_low; 2411 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type); 2412 2413 /* set cpu data */ 2414#if defined(SH_ETH_HAS_BOTH_MODULES) 2415 mdp->cd = sh_eth_get_cpu_data(mdp); 2416#else 2417 mdp->cd = &sh_eth_my_cpu_data; 2418#endif 2419 sh_eth_set_default_cpu_data(mdp->cd); 2420 2421 /* set function */ 2422 ndev->netdev_ops = &sh_eth_netdev_ops; 2423 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); 2424 ndev->watchdog_timeo = TX_TIMEOUT; 2425 2426 /* debug message level */ 2427 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 2428 2429 /* read and set MAC address */ 2430 read_mac_address(ndev, pd->mac_addr); 2431 2432 /* ioremap the TSU registers */ 2433 if (mdp->cd->tsu) { 2434 struct resource *rtsu; 2435 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2436 if (!rtsu) { 2437 dev_err(&pdev->dev, "Not found TSU resource\n"); 2438 ret = -ENODEV; 2439 goto out_release; 2440 } 2441 mdp->tsu_addr = ioremap(rtsu->start, 2442 resource_size(rtsu)); 2443 if (mdp->tsu_addr == NULL) { 2444 ret = -ENOMEM; 2445 dev_err(&pdev->dev, "TSU ioremap failed.\n"); 2446 goto out_release; 2447 } 2448 mdp->port = devno % 2; 2449 ndev->features = NETIF_F_HW_VLAN_FILTER; 2450 } 2451 2452 /* initialize first or needed device */ 2453 if (!devno || pd->needs_init) { 2454 if (mdp->cd->chip_reset) 2455 mdp->cd->chip_reset(ndev); 2456 2457 if (mdp->cd->tsu) { 2458 /* TSU init (Init only)*/ 2459 sh_eth_tsu_init(mdp); 2460 } 2461 } 2462 2463 /* network device register */ 2464 ret = register_netdev(ndev); 2465 if (ret) 2466 goto out_release; 2467 2468 /* mdio bus init */ 2469 ret = sh_mdio_init(ndev, pdev->id, pd); 2470 if (ret) 2471 goto out_unregister; 2472 2473 /* print device information */ 2474 pr_info("Base address at 0x%x, %pM, IRQ %d.\n", 2475 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2476 2477 platform_set_drvdata(pdev, ndev); 2478 2479 return ret; 2480 2481out_unregister: 2482 unregister_netdev(ndev); 2483 2484out_release: 2485 /* net_dev free */ 2486 if (mdp && mdp->addr) 2487 iounmap(mdp->addr); 2488 if (mdp && mdp->tsu_addr) 2489 iounmap(mdp->tsu_addr); 2490 if (ndev) 2491 free_netdev(ndev); 2492 2493out: 2494 return ret; 2495} 2496 2497static int sh_eth_drv_remove(struct platform_device *pdev) 2498{ 2499 struct net_device *ndev = platform_get_drvdata(pdev); 2500 struct sh_eth_private *mdp = netdev_priv(ndev); 2501 2502 if (mdp->cd->tsu) 2503 iounmap(mdp->tsu_addr); 2504 sh_mdio_release(ndev); 2505 unregister_netdev(ndev); 2506 pm_runtime_disable(&pdev->dev); 2507 iounmap(mdp->addr); 2508 free_netdev(ndev); 2509 platform_set_drvdata(pdev, NULL); 2510 2511 return 0; 2512} 2513 2514static int sh_eth_runtime_nop(struct device *dev) 2515{ 2516 /* 2517 * Runtime PM callback shared between ->runtime_suspend() 2518 * and ->runtime_resume(). Simply returns success. 2519 * 2520 * This driver re-initializes all registers after 2521 * pm_runtime_get_sync() anyway so there is no need 2522 * to save and restore registers here. 2523 */ 2524 return 0; 2525} 2526 2527static struct dev_pm_ops sh_eth_dev_pm_ops = { 2528 .runtime_suspend = sh_eth_runtime_nop, 2529 .runtime_resume = sh_eth_runtime_nop, 2530}; 2531 2532static struct platform_driver sh_eth_driver = { 2533 .probe = sh_eth_drv_probe, 2534 .remove = sh_eth_drv_remove, 2535 .driver = { 2536 .name = CARDNAME, 2537 .pm = &sh_eth_dev_pm_ops, 2538 }, 2539}; 2540 2541module_platform_driver(sh_eth_driver); 2542 2543MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 2544MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 2545MODULE_LICENSE("GPL v2"); 2546