sh_eth.c revision 7bbe150d8c57c59689c8c50fd7b9915f4a7e10da
1/* 2 * SuperH Ethernet device driver 3 * 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 */ 23 24#include <linux/init.h> 25#include <linux/module.h> 26#include <linux/kernel.h> 27#include <linux/spinlock.h> 28#include <linux/interrupt.h> 29#include <linux/dma-mapping.h> 30#include <linux/etherdevice.h> 31#include <linux/delay.h> 32#include <linux/platform_device.h> 33#include <linux/mdio-bitbang.h> 34#include <linux/netdevice.h> 35#include <linux/phy.h> 36#include <linux/cache.h> 37#include <linux/io.h> 38#include <linux/pm_runtime.h> 39#include <linux/slab.h> 40#include <linux/ethtool.h> 41#include <linux/if_vlan.h> 42#include <linux/clk.h> 43#include <linux/sh_eth.h> 44 45#include "sh_eth.h" 46 47#define SH_ETH_DEF_MSG_ENABLE \ 48 (NETIF_MSG_LINK | \ 49 NETIF_MSG_TIMER | \ 50 NETIF_MSG_RX_ERR| \ 51 NETIF_MSG_TX_ERR) 52 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 54 [EDSR] = 0x0000, 55 [EDMR] = 0x0400, 56 [EDTRR] = 0x0408, 57 [EDRRR] = 0x0410, 58 [EESR] = 0x0428, 59 [EESIPR] = 0x0430, 60 [TDLAR] = 0x0010, 61 [TDFAR] = 0x0014, 62 [TDFXR] = 0x0018, 63 [TDFFR] = 0x001c, 64 [RDLAR] = 0x0030, 65 [RDFAR] = 0x0034, 66 [RDFXR] = 0x0038, 67 [RDFFR] = 0x003c, 68 [TRSCER] = 0x0438, 69 [RMFCR] = 0x0440, 70 [TFTR] = 0x0448, 71 [FDR] = 0x0450, 72 [RMCR] = 0x0458, 73 [RPADIR] = 0x0460, 74 [FCFTR] = 0x0468, 75 [CSMR] = 0x04E4, 76 77 [ECMR] = 0x0500, 78 [ECSR] = 0x0510, 79 [ECSIPR] = 0x0518, 80 [PIR] = 0x0520, 81 [PSR] = 0x0528, 82 [PIPR] = 0x052c, 83 [RFLR] = 0x0508, 84 [APR] = 0x0554, 85 [MPR] = 0x0558, 86 [PFTCR] = 0x055c, 87 [PFRCR] = 0x0560, 88 [TPAUSER] = 0x0564, 89 [GECMR] = 0x05b0, 90 [BCULR] = 0x05b4, 91 [MAHR] = 0x05c0, 92 [MALR] = 0x05c8, 93 [TROCR] = 0x0700, 94 [CDCR] = 0x0708, 95 [LCCR] = 0x0710, 96 [CEFCR] = 0x0740, 97 [FRECR] = 0x0748, 98 [TSFRCR] = 0x0750, 99 [TLFRCR] = 0x0758, 100 [RFCR] = 0x0760, 101 [CERCR] = 0x0768, 102 [CEECR] = 0x0770, 103 [MAFCR] = 0x0778, 104 [RMII_MII] = 0x0790, 105 106 [ARSTR] = 0x0000, 107 [TSU_CTRST] = 0x0004, 108 [TSU_FWEN0] = 0x0010, 109 [TSU_FWEN1] = 0x0014, 110 [TSU_FCM] = 0x0018, 111 [TSU_BSYSL0] = 0x0020, 112 [TSU_BSYSL1] = 0x0024, 113 [TSU_PRISL0] = 0x0028, 114 [TSU_PRISL1] = 0x002c, 115 [TSU_FWSL0] = 0x0030, 116 [TSU_FWSL1] = 0x0034, 117 [TSU_FWSLC] = 0x0038, 118 [TSU_QTAG0] = 0x0040, 119 [TSU_QTAG1] = 0x0044, 120 [TSU_FWSR] = 0x0050, 121 [TSU_FWINMK] = 0x0054, 122 [TSU_ADQT0] = 0x0048, 123 [TSU_ADQT1] = 0x004c, 124 [TSU_VTAG0] = 0x0058, 125 [TSU_VTAG1] = 0x005c, 126 [TSU_ADSBSY] = 0x0060, 127 [TSU_TEN] = 0x0064, 128 [TSU_POST1] = 0x0070, 129 [TSU_POST2] = 0x0074, 130 [TSU_POST3] = 0x0078, 131 [TSU_POST4] = 0x007c, 132 [TSU_ADRH0] = 0x0100, 133 [TSU_ADRL0] = 0x0104, 134 [TSU_ADRH31] = 0x01f8, 135 [TSU_ADRL31] = 0x01fc, 136 137 [TXNLCR0] = 0x0080, 138 [TXALCR0] = 0x0084, 139 [RXNLCR0] = 0x0088, 140 [RXALCR0] = 0x008c, 141 [FWNLCR0] = 0x0090, 142 [FWALCR0] = 0x0094, 143 [TXNLCR1] = 0x00a0, 144 [TXALCR1] = 0x00a0, 145 [RXNLCR1] = 0x00a8, 146 [RXALCR1] = 0x00ac, 147 [FWNLCR1] = 0x00b0, 148 [FWALCR1] = 0x00b4, 149}; 150 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 152 [ECMR] = 0x0300, 153 [RFLR] = 0x0308, 154 [ECSR] = 0x0310, 155 [ECSIPR] = 0x0318, 156 [PIR] = 0x0320, 157 [PSR] = 0x0328, 158 [RDMLR] = 0x0340, 159 [IPGR] = 0x0350, 160 [APR] = 0x0354, 161 [MPR] = 0x0358, 162 [RFCF] = 0x0360, 163 [TPAUSER] = 0x0364, 164 [TPAUSECR] = 0x0368, 165 [MAHR] = 0x03c0, 166 [MALR] = 0x03c8, 167 [TROCR] = 0x03d0, 168 [CDCR] = 0x03d4, 169 [LCCR] = 0x03d8, 170 [CNDCR] = 0x03dc, 171 [CEFCR] = 0x03e4, 172 [FRECR] = 0x03e8, 173 [TSFRCR] = 0x03ec, 174 [TLFRCR] = 0x03f0, 175 [RFCR] = 0x03f4, 176 [MAFCR] = 0x03f8, 177 178 [EDMR] = 0x0200, 179 [EDTRR] = 0x0208, 180 [EDRRR] = 0x0210, 181 [TDLAR] = 0x0218, 182 [RDLAR] = 0x0220, 183 [EESR] = 0x0228, 184 [EESIPR] = 0x0230, 185 [TRSCER] = 0x0238, 186 [RMFCR] = 0x0240, 187 [TFTR] = 0x0248, 188 [FDR] = 0x0250, 189 [RMCR] = 0x0258, 190 [TFUCR] = 0x0264, 191 [RFOCR] = 0x0268, 192 [FCFTR] = 0x0270, 193 [TRIMD] = 0x027c, 194}; 195 196static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 197 [ECMR] = 0x0100, 198 [RFLR] = 0x0108, 199 [ECSR] = 0x0110, 200 [ECSIPR] = 0x0118, 201 [PIR] = 0x0120, 202 [PSR] = 0x0128, 203 [RDMLR] = 0x0140, 204 [IPGR] = 0x0150, 205 [APR] = 0x0154, 206 [MPR] = 0x0158, 207 [TPAUSER] = 0x0164, 208 [RFCF] = 0x0160, 209 [TPAUSECR] = 0x0168, 210 [BCFRR] = 0x016c, 211 [MAHR] = 0x01c0, 212 [MALR] = 0x01c8, 213 [TROCR] = 0x01d0, 214 [CDCR] = 0x01d4, 215 [LCCR] = 0x01d8, 216 [CNDCR] = 0x01dc, 217 [CEFCR] = 0x01e4, 218 [FRECR] = 0x01e8, 219 [TSFRCR] = 0x01ec, 220 [TLFRCR] = 0x01f0, 221 [RFCR] = 0x01f4, 222 [MAFCR] = 0x01f8, 223 [RTRATE] = 0x01fc, 224 225 [EDMR] = 0x0000, 226 [EDTRR] = 0x0008, 227 [EDRRR] = 0x0010, 228 [TDLAR] = 0x0018, 229 [RDLAR] = 0x0020, 230 [EESR] = 0x0028, 231 [EESIPR] = 0x0030, 232 [TRSCER] = 0x0038, 233 [RMFCR] = 0x0040, 234 [TFTR] = 0x0048, 235 [FDR] = 0x0050, 236 [RMCR] = 0x0058, 237 [TFUCR] = 0x0064, 238 [RFOCR] = 0x0068, 239 [FCFTR] = 0x0070, 240 [RPADIR] = 0x0078, 241 [TRIMD] = 0x007c, 242 [RBWAR] = 0x00c8, 243 [RDFAR] = 0x00cc, 244 [TBRAR] = 0x00d4, 245 [TDFAR] = 0x00d8, 246}; 247 248static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 249 [ECMR] = 0x0160, 250 [ECSR] = 0x0164, 251 [ECSIPR] = 0x0168, 252 [PIR] = 0x016c, 253 [MAHR] = 0x0170, 254 [MALR] = 0x0174, 255 [RFLR] = 0x0178, 256 [PSR] = 0x017c, 257 [TROCR] = 0x0180, 258 [CDCR] = 0x0184, 259 [LCCR] = 0x0188, 260 [CNDCR] = 0x018c, 261 [CEFCR] = 0x0194, 262 [FRECR] = 0x0198, 263 [TSFRCR] = 0x019c, 264 [TLFRCR] = 0x01a0, 265 [RFCR] = 0x01a4, 266 [MAFCR] = 0x01a8, 267 [IPGR] = 0x01b4, 268 [APR] = 0x01b8, 269 [MPR] = 0x01bc, 270 [TPAUSER] = 0x01c4, 271 [BCFR] = 0x01cc, 272 273 [ARSTR] = 0x0000, 274 [TSU_CTRST] = 0x0004, 275 [TSU_FWEN0] = 0x0010, 276 [TSU_FWEN1] = 0x0014, 277 [TSU_FCM] = 0x0018, 278 [TSU_BSYSL0] = 0x0020, 279 [TSU_BSYSL1] = 0x0024, 280 [TSU_PRISL0] = 0x0028, 281 [TSU_PRISL1] = 0x002c, 282 [TSU_FWSL0] = 0x0030, 283 [TSU_FWSL1] = 0x0034, 284 [TSU_FWSLC] = 0x0038, 285 [TSU_QTAGM0] = 0x0040, 286 [TSU_QTAGM1] = 0x0044, 287 [TSU_ADQT0] = 0x0048, 288 [TSU_ADQT1] = 0x004c, 289 [TSU_FWSR] = 0x0050, 290 [TSU_FWINMK] = 0x0054, 291 [TSU_ADSBSY] = 0x0060, 292 [TSU_TEN] = 0x0064, 293 [TSU_POST1] = 0x0070, 294 [TSU_POST2] = 0x0074, 295 [TSU_POST3] = 0x0078, 296 [TSU_POST4] = 0x007c, 297 298 [TXNLCR0] = 0x0080, 299 [TXALCR0] = 0x0084, 300 [RXNLCR0] = 0x0088, 301 [RXALCR0] = 0x008c, 302 [FWNLCR0] = 0x0090, 303 [FWALCR0] = 0x0094, 304 [TXNLCR1] = 0x00a0, 305 [TXALCR1] = 0x00a0, 306 [RXNLCR1] = 0x00a8, 307 [RXALCR1] = 0x00ac, 308 [FWNLCR1] = 0x00b0, 309 [FWALCR1] = 0x00b4, 310 311 [TSU_ADRH0] = 0x0100, 312 [TSU_ADRL0] = 0x0104, 313 [TSU_ADRL31] = 0x01fc, 314}; 315 316static int sh_eth_is_gether(struct sh_eth_private *mdp) 317{ 318 if (mdp->reg_offset == sh_eth_offset_gigabit) 319 return 1; 320 else 321 return 0; 322} 323 324static void __maybe_unused sh_eth_select_mii(struct net_device *ndev) 325{ 326 u32 value = 0x0; 327 struct sh_eth_private *mdp = netdev_priv(ndev); 328 329 switch (mdp->phy_interface) { 330 case PHY_INTERFACE_MODE_GMII: 331 value = 0x2; 332 break; 333 case PHY_INTERFACE_MODE_MII: 334 value = 0x1; 335 break; 336 case PHY_INTERFACE_MODE_RMII: 337 value = 0x0; 338 break; 339 default: 340 pr_warn("PHY interface mode was not setup. Set to MII.\n"); 341 value = 0x1; 342 break; 343 } 344 345 sh_eth_write(ndev, value, RMII_MII); 346} 347 348static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev) 349{ 350 struct sh_eth_private *mdp = netdev_priv(ndev); 351 352 if (mdp->duplex) /* Full */ 353 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 354 else /* Half */ 355 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 356} 357 358/* There is CPU dependent code */ 359#if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779) 360static void sh_eth_set_rate(struct net_device *ndev) 361{ 362 struct sh_eth_private *mdp = netdev_priv(ndev); 363 364 switch (mdp->speed) { 365 case 10: /* 10BASE */ 366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR); 367 break; 368 case 100:/* 100BASE */ 369 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR); 370 break; 371 default: 372 break; 373 } 374} 375 376/* R8A7778/9 */ 377static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 378 .set_duplex = sh_eth_set_duplex, 379 .set_rate = sh_eth_set_rate, 380 381 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 382 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 383 .eesipr_value = 0x01ff009f, 384 385 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 386 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 387 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 388 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 389 390 .apr = 1, 391 .mpr = 1, 392 .tpauser = 1, 393 .hw_swap = 1, 394}; 395#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 396 397static void sh_eth_set_rate(struct net_device *ndev) 398{ 399 struct sh_eth_private *mdp = netdev_priv(ndev); 400 401 switch (mdp->speed) { 402 case 10: /* 10BASE */ 403 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 404 break; 405 case 100:/* 100BASE */ 406 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 407 break; 408 default: 409 break; 410 } 411} 412 413/* SH7724 */ 414static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 415 .set_duplex = sh_eth_set_duplex, 416 .set_rate = sh_eth_set_rate, 417 418 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 419 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 420 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f, 421 422 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 423 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 424 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 425 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 426 427 .apr = 1, 428 .mpr = 1, 429 .tpauser = 1, 430 .hw_swap = 1, 431 .rpadir = 1, 432 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 433}; 434#elif defined(CONFIG_CPU_SUBTYPE_SH7757) 435#define SH_ETH_HAS_BOTH_MODULES 1 436 437static void sh_eth_set_rate(struct net_device *ndev) 438{ 439 struct sh_eth_private *mdp = netdev_priv(ndev); 440 441 switch (mdp->speed) { 442 case 10: /* 10BASE */ 443 sh_eth_write(ndev, 0, RTRATE); 444 break; 445 case 100:/* 100BASE */ 446 sh_eth_write(ndev, 1, RTRATE); 447 break; 448 default: 449 break; 450 } 451} 452 453/* SH7757 */ 454static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 455 .set_duplex = sh_eth_set_duplex, 456 .set_rate = sh_eth_set_rate, 457 458 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 459 .rmcr_value = 0x00000001, 460 461 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 462 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 463 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 464 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 465 466 .irq_flags = IRQF_SHARED, 467 .apr = 1, 468 .mpr = 1, 469 .tpauser = 1, 470 .hw_swap = 1, 471 .no_ade = 1, 472 .rpadir = 1, 473 .rpadir_value = 2 << 16, 474}; 475 476#define SH_GIGA_ETH_BASE 0xfee00000 477#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 478#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 479static void sh_eth_chip_reset_giga(struct net_device *ndev) 480{ 481 int i; 482 unsigned long mahr[2], malr[2]; 483 484 /* save MAHR and MALR */ 485 for (i = 0; i < 2; i++) { 486 malr[i] = ioread32((void *)GIGA_MALR(i)); 487 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 488 } 489 490 /* reset device */ 491 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 492 mdelay(1); 493 494 /* restore MAHR and MALR */ 495 for (i = 0; i < 2; i++) { 496 iowrite32(malr[i], (void *)GIGA_MALR(i)); 497 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 498 } 499} 500 501static void sh_eth_set_rate_giga(struct net_device *ndev) 502{ 503 struct sh_eth_private *mdp = netdev_priv(ndev); 504 505 switch (mdp->speed) { 506 case 10: /* 10BASE */ 507 sh_eth_write(ndev, 0x00000000, GECMR); 508 break; 509 case 100:/* 100BASE */ 510 sh_eth_write(ndev, 0x00000010, GECMR); 511 break; 512 case 1000: /* 1000BASE */ 513 sh_eth_write(ndev, 0x00000020, GECMR); 514 break; 515 default: 516 break; 517 } 518} 519 520/* SH7757(GETHERC) */ 521static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = { 522 .chip_reset = sh_eth_chip_reset_giga, 523 .set_duplex = sh_eth_set_duplex, 524 .set_rate = sh_eth_set_rate_giga, 525 526 .ecsr_value = ECSR_ICD | ECSR_MPD, 527 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 528 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 529 530 .tx_check = EESR_TC1 | EESR_FTC, 531 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 532 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 533 EESR_ECI, 534 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 535 EESR_TFE, 536 .fdr_value = 0x0000072f, 537 .rmcr_value = 0x00000001, 538 539 .irq_flags = IRQF_SHARED, 540 .apr = 1, 541 .mpr = 1, 542 .tpauser = 1, 543 .bculr = 1, 544 .hw_swap = 1, 545 .rpadir = 1, 546 .rpadir_value = 2 << 16, 547 .no_trimd = 1, 548 .no_ade = 1, 549 .tsu = 1, 550}; 551 552static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp) 553{ 554 if (sh_eth_is_gether(mdp)) 555 return &sh_eth_my_cpu_data_giga; 556 else 557 return &sh_eth_my_cpu_data; 558} 559 560#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) 561 562static void sh_eth_chip_reset(struct net_device *ndev) 563{ 564 struct sh_eth_private *mdp = netdev_priv(ndev); 565 566 /* reset device */ 567 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 568 mdelay(1); 569} 570 571static void sh_eth_set_rate(struct net_device *ndev) 572{ 573 struct sh_eth_private *mdp = netdev_priv(ndev); 574 575 switch (mdp->speed) { 576 case 10: /* 10BASE */ 577 sh_eth_write(ndev, GECMR_10, GECMR); 578 break; 579 case 100:/* 100BASE */ 580 sh_eth_write(ndev, GECMR_100, GECMR); 581 break; 582 case 1000: /* 1000BASE */ 583 sh_eth_write(ndev, GECMR_1000, GECMR); 584 break; 585 default: 586 break; 587 } 588} 589 590/* sh7763 */ 591static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 592 .chip_reset = sh_eth_chip_reset, 593 .set_duplex = sh_eth_set_duplex, 594 .set_rate = sh_eth_set_rate, 595 596 .ecsr_value = ECSR_ICD | ECSR_MPD, 597 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 598 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 599 600 .tx_check = EESR_TC1 | EESR_FTC, 601 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 602 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 603 EESR_ECI, 604 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 605 EESR_TFE, 606 607 .apr = 1, 608 .mpr = 1, 609 .tpauser = 1, 610 .bculr = 1, 611 .hw_swap = 1, 612 .no_trimd = 1, 613 .no_ade = 1, 614 .tsu = 1, 615#if defined(CONFIG_CPU_SUBTYPE_SH7734) 616 .hw_crc = 1, 617 .select_mii = 1, 618#else 619 .irq_flags = IRQF_SHARED, 620#endif 621}; 622 623 624#elif defined(CONFIG_ARCH_R8A7740) 625 626static void sh_eth_chip_reset(struct net_device *ndev) 627{ 628 struct sh_eth_private *mdp = netdev_priv(ndev); 629 630 /* reset device */ 631 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 632 mdelay(1); 633 634 sh_eth_select_mii(ndev); 635} 636 637static void sh_eth_set_rate(struct net_device *ndev) 638{ 639 struct sh_eth_private *mdp = netdev_priv(ndev); 640 641 switch (mdp->speed) { 642 case 10: /* 10BASE */ 643 sh_eth_write(ndev, GECMR_10, GECMR); 644 break; 645 case 100:/* 100BASE */ 646 sh_eth_write(ndev, GECMR_100, GECMR); 647 break; 648 case 1000: /* 1000BASE */ 649 sh_eth_write(ndev, GECMR_1000, GECMR); 650 break; 651 default: 652 break; 653 } 654} 655 656/* R8A7740 */ 657static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 658 .chip_reset = sh_eth_chip_reset, 659 .set_duplex = sh_eth_set_duplex, 660 .set_rate = sh_eth_set_rate, 661 662 .ecsr_value = ECSR_ICD | ECSR_MPD, 663 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 664 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 665 666 .tx_check = EESR_TC1 | EESR_FTC, 667 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 668 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 669 EESR_ECI, 670 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 671 EESR_TFE, 672 673 .apr = 1, 674 .mpr = 1, 675 .tpauser = 1, 676 .bculr = 1, 677 .hw_swap = 1, 678 .no_trimd = 1, 679 .no_ade = 1, 680 .tsu = 1, 681 .select_mii = 1, 682}; 683 684#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 685static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 686 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 687 688 .apr = 1, 689 .mpr = 1, 690 .tpauser = 1, 691 .hw_swap = 1, 692}; 693#endif 694 695static struct sh_eth_cpu_data sh771x_data = { 696 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 697 .tsu = 1, 698}; 699 700static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 701{ 702 if (!cd->ecsr_value) 703 cd->ecsr_value = DEFAULT_ECSR_INIT; 704 705 if (!cd->ecsipr_value) 706 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 707 708 if (!cd->fcftr_value) 709 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \ 710 DEFAULT_FIFO_F_D_RFD; 711 712 if (!cd->fdr_value) 713 cd->fdr_value = DEFAULT_FDR_INIT; 714 715 if (!cd->rmcr_value) 716 cd->rmcr_value = DEFAULT_RMCR_VALUE; 717 718 if (!cd->tx_check) 719 cd->tx_check = DEFAULT_TX_CHECK; 720 721 if (!cd->eesr_err_check) 722 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 723 724 if (!cd->tx_error_check) 725 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; 726} 727 728static int sh_eth_check_reset(struct net_device *ndev) 729{ 730 int ret = 0; 731 int cnt = 100; 732 733 while (cnt > 0) { 734 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 735 break; 736 mdelay(1); 737 cnt--; 738 } 739 if (cnt < 0) { 740 pr_err("Device reset fail\n"); 741 ret = -ETIMEDOUT; 742 } 743 return ret; 744} 745 746static int sh_eth_reset(struct net_device *ndev) 747{ 748 struct sh_eth_private *mdp = netdev_priv(ndev); 749 int ret = 0; 750 751 if (sh_eth_is_gether(mdp)) { 752 sh_eth_write(ndev, EDSR_ENALL, EDSR); 753 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 754 EDMR); 755 756 ret = sh_eth_check_reset(ndev); 757 if (ret) 758 goto out; 759 760 /* Table Init */ 761 sh_eth_write(ndev, 0x0, TDLAR); 762 sh_eth_write(ndev, 0x0, TDFAR); 763 sh_eth_write(ndev, 0x0, TDFXR); 764 sh_eth_write(ndev, 0x0, TDFFR); 765 sh_eth_write(ndev, 0x0, RDLAR); 766 sh_eth_write(ndev, 0x0, RDFAR); 767 sh_eth_write(ndev, 0x0, RDFXR); 768 sh_eth_write(ndev, 0x0, RDFFR); 769 770 /* Reset HW CRC register */ 771 if (mdp->cd->hw_crc) 772 sh_eth_write(ndev, 0x0, CSMR); 773 774 /* Select MII mode */ 775 if (mdp->cd->select_mii) 776 sh_eth_select_mii(ndev); 777 } else { 778 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 779 EDMR); 780 mdelay(3); 781 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 782 EDMR); 783 } 784 785out: 786 return ret; 787} 788 789#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 790static void sh_eth_set_receive_align(struct sk_buff *skb) 791{ 792 int reserve; 793 794 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); 795 if (reserve) 796 skb_reserve(skb, reserve); 797} 798#else 799static void sh_eth_set_receive_align(struct sk_buff *skb) 800{ 801 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); 802} 803#endif 804 805 806/* CPU <-> EDMAC endian convert */ 807static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 808{ 809 switch (mdp->edmac_endian) { 810 case EDMAC_LITTLE_ENDIAN: 811 return cpu_to_le32(x); 812 case EDMAC_BIG_ENDIAN: 813 return cpu_to_be32(x); 814 } 815 return x; 816} 817 818static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) 819{ 820 switch (mdp->edmac_endian) { 821 case EDMAC_LITTLE_ENDIAN: 822 return le32_to_cpu(x); 823 case EDMAC_BIG_ENDIAN: 824 return be32_to_cpu(x); 825 } 826 return x; 827} 828 829/* 830 * Program the hardware MAC address from dev->dev_addr. 831 */ 832static void update_mac_address(struct net_device *ndev) 833{ 834 sh_eth_write(ndev, 835 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 836 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 837 sh_eth_write(ndev, 838 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 839} 840 841/* 842 * Get MAC address from SuperH MAC address register 843 * 844 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 845 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 846 * When you want use this device, you must set MAC address in bootloader. 847 * 848 */ 849static void read_mac_address(struct net_device *ndev, unsigned char *mac) 850{ 851 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 852 memcpy(ndev->dev_addr, mac, 6); 853 } else { 854 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24); 855 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF; 856 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF; 857 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF); 858 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF; 859 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF); 860 } 861} 862 863static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 864{ 865 if (sh_eth_is_gether(mdp)) 866 return EDTRR_TRNS_GETHER; 867 else 868 return EDTRR_TRNS_ETHER; 869} 870 871struct bb_info { 872 void (*set_gate)(void *addr); 873 struct mdiobb_ctrl ctrl; 874 void *addr; 875 u32 mmd_msk;/* MMD */ 876 u32 mdo_msk; 877 u32 mdi_msk; 878 u32 mdc_msk; 879}; 880 881/* PHY bit set */ 882static void bb_set(void *addr, u32 msk) 883{ 884 iowrite32(ioread32(addr) | msk, addr); 885} 886 887/* PHY bit clear */ 888static void bb_clr(void *addr, u32 msk) 889{ 890 iowrite32((ioread32(addr) & ~msk), addr); 891} 892 893/* PHY bit read */ 894static int bb_read(void *addr, u32 msk) 895{ 896 return (ioread32(addr) & msk) != 0; 897} 898 899/* Data I/O pin control */ 900static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 901{ 902 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 903 904 if (bitbang->set_gate) 905 bitbang->set_gate(bitbang->addr); 906 907 if (bit) 908 bb_set(bitbang->addr, bitbang->mmd_msk); 909 else 910 bb_clr(bitbang->addr, bitbang->mmd_msk); 911} 912 913/* Set bit data*/ 914static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 915{ 916 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 917 918 if (bitbang->set_gate) 919 bitbang->set_gate(bitbang->addr); 920 921 if (bit) 922 bb_set(bitbang->addr, bitbang->mdo_msk); 923 else 924 bb_clr(bitbang->addr, bitbang->mdo_msk); 925} 926 927/* Get bit data*/ 928static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 929{ 930 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 931 932 if (bitbang->set_gate) 933 bitbang->set_gate(bitbang->addr); 934 935 return bb_read(bitbang->addr, bitbang->mdi_msk); 936} 937 938/* MDC pin control */ 939static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 940{ 941 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 942 943 if (bitbang->set_gate) 944 bitbang->set_gate(bitbang->addr); 945 946 if (bit) 947 bb_set(bitbang->addr, bitbang->mdc_msk); 948 else 949 bb_clr(bitbang->addr, bitbang->mdc_msk); 950} 951 952/* mdio bus control struct */ 953static struct mdiobb_ops bb_ops = { 954 .owner = THIS_MODULE, 955 .set_mdc = sh_mdc_ctrl, 956 .set_mdio_dir = sh_mmd_ctrl, 957 .set_mdio_data = sh_set_mdio, 958 .get_mdio_data = sh_get_mdio, 959}; 960 961/* free skb and descriptor buffer */ 962static void sh_eth_ring_free(struct net_device *ndev) 963{ 964 struct sh_eth_private *mdp = netdev_priv(ndev); 965 int i; 966 967 /* Free Rx skb ringbuffer */ 968 if (mdp->rx_skbuff) { 969 for (i = 0; i < mdp->num_rx_ring; i++) { 970 if (mdp->rx_skbuff[i]) 971 dev_kfree_skb(mdp->rx_skbuff[i]); 972 } 973 } 974 kfree(mdp->rx_skbuff); 975 mdp->rx_skbuff = NULL; 976 977 /* Free Tx skb ringbuffer */ 978 if (mdp->tx_skbuff) { 979 for (i = 0; i < mdp->num_tx_ring; i++) { 980 if (mdp->tx_skbuff[i]) 981 dev_kfree_skb(mdp->tx_skbuff[i]); 982 } 983 } 984 kfree(mdp->tx_skbuff); 985 mdp->tx_skbuff = NULL; 986} 987 988/* format skb and descriptor buffer */ 989static void sh_eth_ring_format(struct net_device *ndev) 990{ 991 struct sh_eth_private *mdp = netdev_priv(ndev); 992 int i; 993 struct sk_buff *skb; 994 struct sh_eth_rxdesc *rxdesc = NULL; 995 struct sh_eth_txdesc *txdesc = NULL; 996 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 997 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 998 999 mdp->cur_rx = mdp->cur_tx = 0; 1000 mdp->dirty_rx = mdp->dirty_tx = 0; 1001 1002 memset(mdp->rx_ring, 0, rx_ringsize); 1003 1004 /* build Rx ring buffer */ 1005 for (i = 0; i < mdp->num_rx_ring; i++) { 1006 /* skb */ 1007 mdp->rx_skbuff[i] = NULL; 1008 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1009 mdp->rx_skbuff[i] = skb; 1010 if (skb == NULL) 1011 break; 1012 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1013 DMA_FROM_DEVICE); 1014 sh_eth_set_receive_align(skb); 1015 1016 /* RX descriptor */ 1017 rxdesc = &mdp->rx_ring[i]; 1018 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1019 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1020 1021 /* The size of the buffer is 16 byte boundary. */ 1022 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1023 /* Rx descriptor address set */ 1024 if (i == 0) { 1025 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1026 if (sh_eth_is_gether(mdp)) 1027 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1028 } 1029 } 1030 1031 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1032 1033 /* Mark the last entry as wrapping the ring. */ 1034 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); 1035 1036 memset(mdp->tx_ring, 0, tx_ringsize); 1037 1038 /* build Tx ring buffer */ 1039 for (i = 0; i < mdp->num_tx_ring; i++) { 1040 mdp->tx_skbuff[i] = NULL; 1041 txdesc = &mdp->tx_ring[i]; 1042 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1043 txdesc->buffer_length = 0; 1044 if (i == 0) { 1045 /* Tx descriptor address set */ 1046 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1047 if (sh_eth_is_gether(mdp)) 1048 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1049 } 1050 } 1051 1052 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1053} 1054 1055/* Get skb and descriptor buffer */ 1056static int sh_eth_ring_init(struct net_device *ndev) 1057{ 1058 struct sh_eth_private *mdp = netdev_priv(ndev); 1059 int rx_ringsize, tx_ringsize, ret = 0; 1060 1061 /* 1062 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1063 * card needs room to do 8 byte alignment, +2 so we can reserve 1064 * the first 2 bytes, and +16 gets room for the status word from the 1065 * card. 1066 */ 1067 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1068 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1069 if (mdp->cd->rpadir) 1070 mdp->rx_buf_sz += NET_IP_ALIGN; 1071 1072 /* Allocate RX and TX skb rings */ 1073 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring, 1074 sizeof(*mdp->rx_skbuff), GFP_KERNEL); 1075 if (!mdp->rx_skbuff) { 1076 ret = -ENOMEM; 1077 return ret; 1078 } 1079 1080 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring, 1081 sizeof(*mdp->tx_skbuff), GFP_KERNEL); 1082 if (!mdp->tx_skbuff) { 1083 ret = -ENOMEM; 1084 goto skb_ring_free; 1085 } 1086 1087 /* Allocate all Rx descriptors. */ 1088 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1089 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 1090 GFP_KERNEL); 1091 if (!mdp->rx_ring) { 1092 ret = -ENOMEM; 1093 goto desc_ring_free; 1094 } 1095 1096 mdp->dirty_rx = 0; 1097 1098 /* Allocate all Tx descriptors. */ 1099 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1100 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 1101 GFP_KERNEL); 1102 if (!mdp->tx_ring) { 1103 ret = -ENOMEM; 1104 goto desc_ring_free; 1105 } 1106 return ret; 1107 1108desc_ring_free: 1109 /* free DMA buffer */ 1110 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); 1111 1112skb_ring_free: 1113 /* Free Rx and Tx skb ring buffer */ 1114 sh_eth_ring_free(ndev); 1115 mdp->tx_ring = NULL; 1116 mdp->rx_ring = NULL; 1117 1118 return ret; 1119} 1120 1121static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp) 1122{ 1123 int ringsize; 1124 1125 if (mdp->rx_ring) { 1126 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1127 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 1128 mdp->rx_desc_dma); 1129 mdp->rx_ring = NULL; 1130 } 1131 1132 if (mdp->tx_ring) { 1133 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1134 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 1135 mdp->tx_desc_dma); 1136 mdp->tx_ring = NULL; 1137 } 1138} 1139 1140static int sh_eth_dev_init(struct net_device *ndev, bool start) 1141{ 1142 int ret = 0; 1143 struct sh_eth_private *mdp = netdev_priv(ndev); 1144 u32 val; 1145 1146 /* Soft Reset */ 1147 ret = sh_eth_reset(ndev); 1148 if (ret) 1149 goto out; 1150 1151 /* Descriptor format */ 1152 sh_eth_ring_format(ndev); 1153 if (mdp->cd->rpadir) 1154 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1155 1156 /* all sh_eth int mask */ 1157 sh_eth_write(ndev, 0, EESIPR); 1158 1159#if defined(__LITTLE_ENDIAN) 1160 if (mdp->cd->hw_swap) 1161 sh_eth_write(ndev, EDMR_EL, EDMR); 1162 else 1163#endif 1164 sh_eth_write(ndev, 0, EDMR); 1165 1166 /* FIFO size set */ 1167 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1168 sh_eth_write(ndev, 0, TFTR); 1169 1170 /* Frame recv control */ 1171 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR); 1172 1173 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER); 1174 1175 if (mdp->cd->bculr) 1176 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1177 1178 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1179 1180 if (!mdp->cd->no_trimd) 1181 sh_eth_write(ndev, 0, TRIMD); 1182 1183 /* Recv frame limit set register */ 1184 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1185 RFLR); 1186 1187 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 1188 if (start) 1189 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1190 1191 /* PAUSE Prohibition */ 1192 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | 1193 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 1194 1195 sh_eth_write(ndev, val, ECMR); 1196 1197 if (mdp->cd->set_rate) 1198 mdp->cd->set_rate(ndev); 1199 1200 /* E-MAC Status Register clear */ 1201 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1202 1203 /* E-MAC Interrupt Enable register */ 1204 if (start) 1205 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1206 1207 /* Set MAC address */ 1208 update_mac_address(ndev); 1209 1210 /* mask reset */ 1211 if (mdp->cd->apr) 1212 sh_eth_write(ndev, APR_AP, APR); 1213 if (mdp->cd->mpr) 1214 sh_eth_write(ndev, MPR_MP, MPR); 1215 if (mdp->cd->tpauser) 1216 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1217 1218 if (start) { 1219 /* Setting the Rx mode will start the Rx process. */ 1220 sh_eth_write(ndev, EDRRR_R, EDRRR); 1221 1222 netif_start_queue(ndev); 1223 } 1224 1225out: 1226 return ret; 1227} 1228 1229/* free Tx skb function */ 1230static int sh_eth_txfree(struct net_device *ndev) 1231{ 1232 struct sh_eth_private *mdp = netdev_priv(ndev); 1233 struct sh_eth_txdesc *txdesc; 1234 int freeNum = 0; 1235 int entry = 0; 1236 1237 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1238 entry = mdp->dirty_tx % mdp->num_tx_ring; 1239 txdesc = &mdp->tx_ring[entry]; 1240 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 1241 break; 1242 /* Free the original skb. */ 1243 if (mdp->tx_skbuff[entry]) { 1244 dma_unmap_single(&ndev->dev, txdesc->addr, 1245 txdesc->buffer_length, DMA_TO_DEVICE); 1246 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1247 mdp->tx_skbuff[entry] = NULL; 1248 freeNum++; 1249 } 1250 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1251 if (entry >= mdp->num_tx_ring - 1) 1252 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1253 1254 ndev->stats.tx_packets++; 1255 ndev->stats.tx_bytes += txdesc->buffer_length; 1256 } 1257 return freeNum; 1258} 1259 1260/* Packet receive function */ 1261static int sh_eth_rx(struct net_device *ndev, u32 intr_status) 1262{ 1263 struct sh_eth_private *mdp = netdev_priv(ndev); 1264 struct sh_eth_rxdesc *rxdesc; 1265 1266 int entry = mdp->cur_rx % mdp->num_rx_ring; 1267 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1268 struct sk_buff *skb; 1269 u16 pkt_len = 0; 1270 u32 desc_status; 1271 1272 rxdesc = &mdp->rx_ring[entry]; 1273 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1274 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1275 pkt_len = rxdesc->frame_length; 1276 1277#if defined(CONFIG_ARCH_R8A7740) 1278 desc_status >>= 16; 1279#endif 1280 1281 if (--boguscnt < 0) 1282 break; 1283 1284 if (!(desc_status & RDFEND)) 1285 ndev->stats.rx_length_errors++; 1286 1287 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1288 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1289 ndev->stats.rx_errors++; 1290 if (desc_status & RD_RFS1) 1291 ndev->stats.rx_crc_errors++; 1292 if (desc_status & RD_RFS2) 1293 ndev->stats.rx_frame_errors++; 1294 if (desc_status & RD_RFS3) 1295 ndev->stats.rx_length_errors++; 1296 if (desc_status & RD_RFS4) 1297 ndev->stats.rx_length_errors++; 1298 if (desc_status & RD_RFS6) 1299 ndev->stats.rx_missed_errors++; 1300 if (desc_status & RD_RFS10) 1301 ndev->stats.rx_over_errors++; 1302 } else { 1303 if (!mdp->cd->hw_swap) 1304 sh_eth_soft_swap( 1305 phys_to_virt(ALIGN(rxdesc->addr, 4)), 1306 pkt_len + 2); 1307 skb = mdp->rx_skbuff[entry]; 1308 mdp->rx_skbuff[entry] = NULL; 1309 if (mdp->cd->rpadir) 1310 skb_reserve(skb, NET_IP_ALIGN); 1311 skb_put(skb, pkt_len); 1312 skb->protocol = eth_type_trans(skb, ndev); 1313 netif_rx(skb); 1314 ndev->stats.rx_packets++; 1315 ndev->stats.rx_bytes += pkt_len; 1316 } 1317 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); 1318 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1319 rxdesc = &mdp->rx_ring[entry]; 1320 } 1321 1322 /* Refill the Rx ring buffers. */ 1323 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1324 entry = mdp->dirty_rx % mdp->num_rx_ring; 1325 rxdesc = &mdp->rx_ring[entry]; 1326 /* The size of the buffer is 16 byte boundary. */ 1327 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1328 1329 if (mdp->rx_skbuff[entry] == NULL) { 1330 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1331 mdp->rx_skbuff[entry] = skb; 1332 if (skb == NULL) 1333 break; /* Better luck next round. */ 1334 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1335 DMA_FROM_DEVICE); 1336 sh_eth_set_receive_align(skb); 1337 1338 skb_checksum_none_assert(skb); 1339 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1340 } 1341 if (entry >= mdp->num_rx_ring - 1) 1342 rxdesc->status |= 1343 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1344 else 1345 rxdesc->status |= 1346 cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1347 } 1348 1349 /* Restart Rx engine if stopped. */ 1350 /* If we don't need to check status, don't. -KDU */ 1351 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1352 /* fix the values for the next receiving if RDE is set */ 1353 if (intr_status & EESR_RDE) 1354 mdp->cur_rx = mdp->dirty_rx = 1355 (sh_eth_read(ndev, RDFAR) - 1356 sh_eth_read(ndev, RDLAR)) >> 4; 1357 sh_eth_write(ndev, EDRRR_R, EDRRR); 1358 } 1359 1360 return 0; 1361} 1362 1363static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1364{ 1365 /* disable tx and rx */ 1366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1367 ~(ECMR_RE | ECMR_TE), ECMR); 1368} 1369 1370static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1371{ 1372 /* enable tx and rx */ 1373 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1374 (ECMR_RE | ECMR_TE), ECMR); 1375} 1376 1377/* error control function */ 1378static void sh_eth_error(struct net_device *ndev, int intr_status) 1379{ 1380 struct sh_eth_private *mdp = netdev_priv(ndev); 1381 u32 felic_stat; 1382 u32 link_stat; 1383 u32 mask; 1384 1385 if (intr_status & EESR_ECI) { 1386 felic_stat = sh_eth_read(ndev, ECSR); 1387 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1388 if (felic_stat & ECSR_ICD) 1389 ndev->stats.tx_carrier_errors++; 1390 if (felic_stat & ECSR_LCHNG) { 1391 /* Link Changed */ 1392 if (mdp->cd->no_psr || mdp->no_ether_link) { 1393 goto ignore_link; 1394 } else { 1395 link_stat = (sh_eth_read(ndev, PSR)); 1396 if (mdp->ether_link_active_low) 1397 link_stat = ~link_stat; 1398 } 1399 if (!(link_stat & PHY_ST_LINK)) 1400 sh_eth_rcv_snd_disable(ndev); 1401 else { 1402 /* Link Up */ 1403 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1404 ~DMAC_M_ECI, EESIPR); 1405 /*clear int */ 1406 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1407 ECSR); 1408 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1409 DMAC_M_ECI, EESIPR); 1410 /* enable tx and rx */ 1411 sh_eth_rcv_snd_enable(ndev); 1412 } 1413 } 1414 } 1415 1416ignore_link: 1417 if (intr_status & EESR_TWB) { 1418 /* Write buck end. unused write back interrupt */ 1419 if (intr_status & EESR_TABT) /* Transmit Abort int */ 1420 ndev->stats.tx_aborted_errors++; 1421 if (netif_msg_tx_err(mdp)) 1422 dev_err(&ndev->dev, "Transmit Abort\n"); 1423 } 1424 1425 if (intr_status & EESR_RABT) { 1426 /* Receive Abort int */ 1427 if (intr_status & EESR_RFRMER) { 1428 /* Receive Frame Overflow int */ 1429 ndev->stats.rx_frame_errors++; 1430 if (netif_msg_rx_err(mdp)) 1431 dev_err(&ndev->dev, "Receive Abort\n"); 1432 } 1433 } 1434 1435 if (intr_status & EESR_TDE) { 1436 /* Transmit Descriptor Empty int */ 1437 ndev->stats.tx_fifo_errors++; 1438 if (netif_msg_tx_err(mdp)) 1439 dev_err(&ndev->dev, "Transmit Descriptor Empty\n"); 1440 } 1441 1442 if (intr_status & EESR_TFE) { 1443 /* FIFO under flow */ 1444 ndev->stats.tx_fifo_errors++; 1445 if (netif_msg_tx_err(mdp)) 1446 dev_err(&ndev->dev, "Transmit FIFO Under flow\n"); 1447 } 1448 1449 if (intr_status & EESR_RDE) { 1450 /* Receive Descriptor Empty int */ 1451 ndev->stats.rx_over_errors++; 1452 1453 if (netif_msg_rx_err(mdp)) 1454 dev_err(&ndev->dev, "Receive Descriptor Empty\n"); 1455 } 1456 1457 if (intr_status & EESR_RFE) { 1458 /* Receive FIFO Overflow int */ 1459 ndev->stats.rx_fifo_errors++; 1460 if (netif_msg_rx_err(mdp)) 1461 dev_err(&ndev->dev, "Receive FIFO Overflow\n"); 1462 } 1463 1464 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1465 /* Address Error */ 1466 ndev->stats.tx_fifo_errors++; 1467 if (netif_msg_tx_err(mdp)) 1468 dev_err(&ndev->dev, "Address Error\n"); 1469 } 1470 1471 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1472 if (mdp->cd->no_ade) 1473 mask &= ~EESR_ADE; 1474 if (intr_status & mask) { 1475 /* Tx error */ 1476 u32 edtrr = sh_eth_read(ndev, EDTRR); 1477 /* dmesg */ 1478 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ", 1479 intr_status, mdp->cur_tx); 1480 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1481 mdp->dirty_tx, (u32) ndev->state, edtrr); 1482 /* dirty buffer free */ 1483 sh_eth_txfree(ndev); 1484 1485 /* SH7712 BUG */ 1486 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1487 /* tx dma start */ 1488 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1489 } 1490 /* wakeup */ 1491 netif_wake_queue(ndev); 1492 } 1493} 1494 1495static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1496{ 1497 struct net_device *ndev = netdev; 1498 struct sh_eth_private *mdp = netdev_priv(ndev); 1499 struct sh_eth_cpu_data *cd = mdp->cd; 1500 irqreturn_t ret = IRQ_NONE; 1501 unsigned long intr_status; 1502 1503 spin_lock(&mdp->lock); 1504 1505 /* Get interrupt status */ 1506 intr_status = sh_eth_read(ndev, EESR); 1507 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1508 * enabled since it's the one that comes thru regardless of the mask, 1509 * and we need to fully handle it in sh_eth_error() in order to quench 1510 * it as it doesn't get cleared by just writing 1 to the ECI bit... 1511 */ 1512 intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI; 1513 /* Clear interrupt */ 1514 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | 1515 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | 1516 cd->tx_check | cd->eesr_err_check)) { 1517 sh_eth_write(ndev, intr_status, EESR); 1518 ret = IRQ_HANDLED; 1519 } else 1520 goto other_irq; 1521 1522 if (intr_status & (EESR_FRC | /* Frame recv*/ 1523 EESR_RMAF | /* Multi cast address recv*/ 1524 EESR_RRF | /* Bit frame recv */ 1525 EESR_RTLF | /* Long frame recv*/ 1526 EESR_RTSF | /* short frame recv */ 1527 EESR_PRE | /* PHY-LSI recv error */ 1528 EESR_CERF)){ /* recv frame CRC error */ 1529 sh_eth_rx(ndev, intr_status); 1530 } 1531 1532 /* Tx Check */ 1533 if (intr_status & cd->tx_check) { 1534 sh_eth_txfree(ndev); 1535 netif_wake_queue(ndev); 1536 } 1537 1538 if (intr_status & cd->eesr_err_check) 1539 sh_eth_error(ndev, intr_status); 1540 1541other_irq: 1542 spin_unlock(&mdp->lock); 1543 1544 return ret; 1545} 1546 1547/* PHY state control function */ 1548static void sh_eth_adjust_link(struct net_device *ndev) 1549{ 1550 struct sh_eth_private *mdp = netdev_priv(ndev); 1551 struct phy_device *phydev = mdp->phydev; 1552 int new_state = 0; 1553 1554 if (phydev->link) { 1555 if (phydev->duplex != mdp->duplex) { 1556 new_state = 1; 1557 mdp->duplex = phydev->duplex; 1558 if (mdp->cd->set_duplex) 1559 mdp->cd->set_duplex(ndev); 1560 } 1561 1562 if (phydev->speed != mdp->speed) { 1563 new_state = 1; 1564 mdp->speed = phydev->speed; 1565 if (mdp->cd->set_rate) 1566 mdp->cd->set_rate(ndev); 1567 } 1568 if (!mdp->link) { 1569 sh_eth_write(ndev, 1570 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR); 1571 new_state = 1; 1572 mdp->link = phydev->link; 1573 if (mdp->cd->no_psr || mdp->no_ether_link) 1574 sh_eth_rcv_snd_enable(ndev); 1575 } 1576 } else if (mdp->link) { 1577 new_state = 1; 1578 mdp->link = 0; 1579 mdp->speed = 0; 1580 mdp->duplex = -1; 1581 if (mdp->cd->no_psr || mdp->no_ether_link) 1582 sh_eth_rcv_snd_disable(ndev); 1583 } 1584 1585 if (new_state && netif_msg_link(mdp)) 1586 phy_print_status(phydev); 1587} 1588 1589/* PHY init function */ 1590static int sh_eth_phy_init(struct net_device *ndev) 1591{ 1592 struct sh_eth_private *mdp = netdev_priv(ndev); 1593 char phy_id[MII_BUS_ID_SIZE + 3]; 1594 struct phy_device *phydev = NULL; 1595 1596 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1597 mdp->mii_bus->id , mdp->phy_id); 1598 1599 mdp->link = 0; 1600 mdp->speed = 0; 1601 mdp->duplex = -1; 1602 1603 /* Try connect to PHY */ 1604 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1605 mdp->phy_interface); 1606 if (IS_ERR(phydev)) { 1607 dev_err(&ndev->dev, "phy_connect failed\n"); 1608 return PTR_ERR(phydev); 1609 } 1610 1611 dev_info(&ndev->dev, "attached phy %i to driver %s\n", 1612 phydev->addr, phydev->drv->name); 1613 1614 mdp->phydev = phydev; 1615 1616 return 0; 1617} 1618 1619/* PHY control start function */ 1620static int sh_eth_phy_start(struct net_device *ndev) 1621{ 1622 struct sh_eth_private *mdp = netdev_priv(ndev); 1623 int ret; 1624 1625 ret = sh_eth_phy_init(ndev); 1626 if (ret) 1627 return ret; 1628 1629 /* reset phy - this also wakes it from PDOWN */ 1630 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET); 1631 phy_start(mdp->phydev); 1632 1633 return 0; 1634} 1635 1636static int sh_eth_get_settings(struct net_device *ndev, 1637 struct ethtool_cmd *ecmd) 1638{ 1639 struct sh_eth_private *mdp = netdev_priv(ndev); 1640 unsigned long flags; 1641 int ret; 1642 1643 spin_lock_irqsave(&mdp->lock, flags); 1644 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1645 spin_unlock_irqrestore(&mdp->lock, flags); 1646 1647 return ret; 1648} 1649 1650static int sh_eth_set_settings(struct net_device *ndev, 1651 struct ethtool_cmd *ecmd) 1652{ 1653 struct sh_eth_private *mdp = netdev_priv(ndev); 1654 unsigned long flags; 1655 int ret; 1656 1657 spin_lock_irqsave(&mdp->lock, flags); 1658 1659 /* disable tx and rx */ 1660 sh_eth_rcv_snd_disable(ndev); 1661 1662 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1663 if (ret) 1664 goto error_exit; 1665 1666 if (ecmd->duplex == DUPLEX_FULL) 1667 mdp->duplex = 1; 1668 else 1669 mdp->duplex = 0; 1670 1671 if (mdp->cd->set_duplex) 1672 mdp->cd->set_duplex(ndev); 1673 1674error_exit: 1675 mdelay(1); 1676 1677 /* enable tx and rx */ 1678 sh_eth_rcv_snd_enable(ndev); 1679 1680 spin_unlock_irqrestore(&mdp->lock, flags); 1681 1682 return ret; 1683} 1684 1685static int sh_eth_nway_reset(struct net_device *ndev) 1686{ 1687 struct sh_eth_private *mdp = netdev_priv(ndev); 1688 unsigned long flags; 1689 int ret; 1690 1691 spin_lock_irqsave(&mdp->lock, flags); 1692 ret = phy_start_aneg(mdp->phydev); 1693 spin_unlock_irqrestore(&mdp->lock, flags); 1694 1695 return ret; 1696} 1697 1698static u32 sh_eth_get_msglevel(struct net_device *ndev) 1699{ 1700 struct sh_eth_private *mdp = netdev_priv(ndev); 1701 return mdp->msg_enable; 1702} 1703 1704static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 1705{ 1706 struct sh_eth_private *mdp = netdev_priv(ndev); 1707 mdp->msg_enable = value; 1708} 1709 1710static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 1711 "rx_current", "tx_current", 1712 "rx_dirty", "tx_dirty", 1713}; 1714#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 1715 1716static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 1717{ 1718 switch (sset) { 1719 case ETH_SS_STATS: 1720 return SH_ETH_STATS_LEN; 1721 default: 1722 return -EOPNOTSUPP; 1723 } 1724} 1725 1726static void sh_eth_get_ethtool_stats(struct net_device *ndev, 1727 struct ethtool_stats *stats, u64 *data) 1728{ 1729 struct sh_eth_private *mdp = netdev_priv(ndev); 1730 int i = 0; 1731 1732 /* device-specific stats */ 1733 data[i++] = mdp->cur_rx; 1734 data[i++] = mdp->cur_tx; 1735 data[i++] = mdp->dirty_rx; 1736 data[i++] = mdp->dirty_tx; 1737} 1738 1739static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1740{ 1741 switch (stringset) { 1742 case ETH_SS_STATS: 1743 memcpy(data, *sh_eth_gstrings_stats, 1744 sizeof(sh_eth_gstrings_stats)); 1745 break; 1746 } 1747} 1748 1749static void sh_eth_get_ringparam(struct net_device *ndev, 1750 struct ethtool_ringparam *ring) 1751{ 1752 struct sh_eth_private *mdp = netdev_priv(ndev); 1753 1754 ring->rx_max_pending = RX_RING_MAX; 1755 ring->tx_max_pending = TX_RING_MAX; 1756 ring->rx_pending = mdp->num_rx_ring; 1757 ring->tx_pending = mdp->num_tx_ring; 1758} 1759 1760static int sh_eth_set_ringparam(struct net_device *ndev, 1761 struct ethtool_ringparam *ring) 1762{ 1763 struct sh_eth_private *mdp = netdev_priv(ndev); 1764 int ret; 1765 1766 if (ring->tx_pending > TX_RING_MAX || 1767 ring->rx_pending > RX_RING_MAX || 1768 ring->tx_pending < TX_RING_MIN || 1769 ring->rx_pending < RX_RING_MIN) 1770 return -EINVAL; 1771 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1772 return -EINVAL; 1773 1774 if (netif_running(ndev)) { 1775 netif_tx_disable(ndev); 1776 /* Disable interrupts by clearing the interrupt mask. */ 1777 sh_eth_write(ndev, 0x0000, EESIPR); 1778 /* Stop the chip's Tx and Rx processes. */ 1779 sh_eth_write(ndev, 0, EDTRR); 1780 sh_eth_write(ndev, 0, EDRRR); 1781 synchronize_irq(ndev->irq); 1782 } 1783 1784 /* Free all the skbuffs in the Rx queue. */ 1785 sh_eth_ring_free(ndev); 1786 /* Free DMA buffer */ 1787 sh_eth_free_dma_buffer(mdp); 1788 1789 /* Set new parameters */ 1790 mdp->num_rx_ring = ring->rx_pending; 1791 mdp->num_tx_ring = ring->tx_pending; 1792 1793 ret = sh_eth_ring_init(ndev); 1794 if (ret < 0) { 1795 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__); 1796 return ret; 1797 } 1798 ret = sh_eth_dev_init(ndev, false); 1799 if (ret < 0) { 1800 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__); 1801 return ret; 1802 } 1803 1804 if (netif_running(ndev)) { 1805 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1806 /* Setting the Rx mode will start the Rx process. */ 1807 sh_eth_write(ndev, EDRRR_R, EDRRR); 1808 netif_wake_queue(ndev); 1809 } 1810 1811 return 0; 1812} 1813 1814static const struct ethtool_ops sh_eth_ethtool_ops = { 1815 .get_settings = sh_eth_get_settings, 1816 .set_settings = sh_eth_set_settings, 1817 .nway_reset = sh_eth_nway_reset, 1818 .get_msglevel = sh_eth_get_msglevel, 1819 .set_msglevel = sh_eth_set_msglevel, 1820 .get_link = ethtool_op_get_link, 1821 .get_strings = sh_eth_get_strings, 1822 .get_ethtool_stats = sh_eth_get_ethtool_stats, 1823 .get_sset_count = sh_eth_get_sset_count, 1824 .get_ringparam = sh_eth_get_ringparam, 1825 .set_ringparam = sh_eth_set_ringparam, 1826}; 1827 1828/* network device open function */ 1829static int sh_eth_open(struct net_device *ndev) 1830{ 1831 int ret = 0; 1832 struct sh_eth_private *mdp = netdev_priv(ndev); 1833 1834 pm_runtime_get_sync(&mdp->pdev->dev); 1835 1836 ret = request_irq(ndev->irq, sh_eth_interrupt, 1837 mdp->cd->irq_flags, ndev->name, ndev); 1838 if (ret) { 1839 dev_err(&ndev->dev, "Can not assign IRQ number\n"); 1840 return ret; 1841 } 1842 1843 /* Descriptor set */ 1844 ret = sh_eth_ring_init(ndev); 1845 if (ret) 1846 goto out_free_irq; 1847 1848 /* device init */ 1849 ret = sh_eth_dev_init(ndev, true); 1850 if (ret) 1851 goto out_free_irq; 1852 1853 /* PHY control start*/ 1854 ret = sh_eth_phy_start(ndev); 1855 if (ret) 1856 goto out_free_irq; 1857 1858 return ret; 1859 1860out_free_irq: 1861 free_irq(ndev->irq, ndev); 1862 pm_runtime_put_sync(&mdp->pdev->dev); 1863 return ret; 1864} 1865 1866/* Timeout function */ 1867static void sh_eth_tx_timeout(struct net_device *ndev) 1868{ 1869 struct sh_eth_private *mdp = netdev_priv(ndev); 1870 struct sh_eth_rxdesc *rxdesc; 1871 int i; 1872 1873 netif_stop_queue(ndev); 1874 1875 if (netif_msg_timer(mdp)) 1876 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x," 1877 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR)); 1878 1879 /* tx_errors count up */ 1880 ndev->stats.tx_errors++; 1881 1882 /* Free all the skbuffs in the Rx queue. */ 1883 for (i = 0; i < mdp->num_rx_ring; i++) { 1884 rxdesc = &mdp->rx_ring[i]; 1885 rxdesc->status = 0; 1886 rxdesc->addr = 0xBADF00D0; 1887 if (mdp->rx_skbuff[i]) 1888 dev_kfree_skb(mdp->rx_skbuff[i]); 1889 mdp->rx_skbuff[i] = NULL; 1890 } 1891 for (i = 0; i < mdp->num_tx_ring; i++) { 1892 if (mdp->tx_skbuff[i]) 1893 dev_kfree_skb(mdp->tx_skbuff[i]); 1894 mdp->tx_skbuff[i] = NULL; 1895 } 1896 1897 /* device init */ 1898 sh_eth_dev_init(ndev, true); 1899} 1900 1901/* Packet transmit function */ 1902static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1903{ 1904 struct sh_eth_private *mdp = netdev_priv(ndev); 1905 struct sh_eth_txdesc *txdesc; 1906 u32 entry; 1907 unsigned long flags; 1908 1909 spin_lock_irqsave(&mdp->lock, flags); 1910 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 1911 if (!sh_eth_txfree(ndev)) { 1912 if (netif_msg_tx_queued(mdp)) 1913 dev_warn(&ndev->dev, "TxFD exhausted.\n"); 1914 netif_stop_queue(ndev); 1915 spin_unlock_irqrestore(&mdp->lock, flags); 1916 return NETDEV_TX_BUSY; 1917 } 1918 } 1919 spin_unlock_irqrestore(&mdp->lock, flags); 1920 1921 entry = mdp->cur_tx % mdp->num_tx_ring; 1922 mdp->tx_skbuff[entry] = skb; 1923 txdesc = &mdp->tx_ring[entry]; 1924 /* soft swap. */ 1925 if (!mdp->cd->hw_swap) 1926 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), 1927 skb->len + 2); 1928 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, 1929 DMA_TO_DEVICE); 1930 if (skb->len < ETHERSMALL) 1931 txdesc->buffer_length = ETHERSMALL; 1932 else 1933 txdesc->buffer_length = skb->len; 1934 1935 if (entry >= mdp->num_tx_ring - 1) 1936 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 1937 else 1938 txdesc->status |= cpu_to_edmac(mdp, TD_TACT); 1939 1940 mdp->cur_tx++; 1941 1942 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 1943 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1944 1945 return NETDEV_TX_OK; 1946} 1947 1948/* device close function */ 1949static int sh_eth_close(struct net_device *ndev) 1950{ 1951 struct sh_eth_private *mdp = netdev_priv(ndev); 1952 1953 netif_stop_queue(ndev); 1954 1955 /* Disable interrupts by clearing the interrupt mask. */ 1956 sh_eth_write(ndev, 0x0000, EESIPR); 1957 1958 /* Stop the chip's Tx and Rx processes. */ 1959 sh_eth_write(ndev, 0, EDTRR); 1960 sh_eth_write(ndev, 0, EDRRR); 1961 1962 /* PHY Disconnect */ 1963 if (mdp->phydev) { 1964 phy_stop(mdp->phydev); 1965 phy_disconnect(mdp->phydev); 1966 } 1967 1968 free_irq(ndev->irq, ndev); 1969 1970 /* Free all the skbuffs in the Rx queue. */ 1971 sh_eth_ring_free(ndev); 1972 1973 /* free DMA buffer */ 1974 sh_eth_free_dma_buffer(mdp); 1975 1976 pm_runtime_put_sync(&mdp->pdev->dev); 1977 1978 return 0; 1979} 1980 1981static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 1982{ 1983 struct sh_eth_private *mdp = netdev_priv(ndev); 1984 1985 pm_runtime_get_sync(&mdp->pdev->dev); 1986 1987 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR); 1988 sh_eth_write(ndev, 0, TROCR); /* (write clear) */ 1989 ndev->stats.collisions += sh_eth_read(ndev, CDCR); 1990 sh_eth_write(ndev, 0, CDCR); /* (write clear) */ 1991 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); 1992 sh_eth_write(ndev, 0, LCCR); /* (write clear) */ 1993 if (sh_eth_is_gether(mdp)) { 1994 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR); 1995 sh_eth_write(ndev, 0, CERCR); /* (write clear) */ 1996 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR); 1997 sh_eth_write(ndev, 0, CEECR); /* (write clear) */ 1998 } else { 1999 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); 2000 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ 2001 } 2002 pm_runtime_put_sync(&mdp->pdev->dev); 2003 2004 return &ndev->stats; 2005} 2006 2007/* ioctl to device function */ 2008static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, 2009 int cmd) 2010{ 2011 struct sh_eth_private *mdp = netdev_priv(ndev); 2012 struct phy_device *phydev = mdp->phydev; 2013 2014 if (!netif_running(ndev)) 2015 return -EINVAL; 2016 2017 if (!phydev) 2018 return -ENODEV; 2019 2020 return phy_mii_ioctl(phydev, rq, cmd); 2021} 2022 2023/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2024static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2025 int entry) 2026{ 2027 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2028} 2029 2030static u32 sh_eth_tsu_get_post_mask(int entry) 2031{ 2032 return 0x0f << (28 - ((entry % 8) * 4)); 2033} 2034 2035static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2036{ 2037 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2038} 2039 2040static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2041 int entry) 2042{ 2043 struct sh_eth_private *mdp = netdev_priv(ndev); 2044 u32 tmp; 2045 void *reg_offset; 2046 2047 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2048 tmp = ioread32(reg_offset); 2049 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2050} 2051 2052static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2053 int entry) 2054{ 2055 struct sh_eth_private *mdp = netdev_priv(ndev); 2056 u32 post_mask, ref_mask, tmp; 2057 void *reg_offset; 2058 2059 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2060 post_mask = sh_eth_tsu_get_post_mask(entry); 2061 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2062 2063 tmp = ioread32(reg_offset); 2064 iowrite32(tmp & ~post_mask, reg_offset); 2065 2066 /* If other port enables, the function returns "true" */ 2067 return tmp & ref_mask; 2068} 2069 2070static int sh_eth_tsu_busy(struct net_device *ndev) 2071{ 2072 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2073 struct sh_eth_private *mdp = netdev_priv(ndev); 2074 2075 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2076 udelay(10); 2077 timeout--; 2078 if (timeout <= 0) { 2079 dev_err(&ndev->dev, "%s: timeout\n", __func__); 2080 return -ETIMEDOUT; 2081 } 2082 } 2083 2084 return 0; 2085} 2086 2087static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2088 const u8 *addr) 2089{ 2090 u32 val; 2091 2092 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2093 iowrite32(val, reg); 2094 if (sh_eth_tsu_busy(ndev) < 0) 2095 return -EBUSY; 2096 2097 val = addr[4] << 8 | addr[5]; 2098 iowrite32(val, reg + 4); 2099 if (sh_eth_tsu_busy(ndev) < 0) 2100 return -EBUSY; 2101 2102 return 0; 2103} 2104 2105static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2106{ 2107 u32 val; 2108 2109 val = ioread32(reg); 2110 addr[0] = (val >> 24) & 0xff; 2111 addr[1] = (val >> 16) & 0xff; 2112 addr[2] = (val >> 8) & 0xff; 2113 addr[3] = val & 0xff; 2114 val = ioread32(reg + 4); 2115 addr[4] = (val >> 8) & 0xff; 2116 addr[5] = val & 0xff; 2117} 2118 2119 2120static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2121{ 2122 struct sh_eth_private *mdp = netdev_priv(ndev); 2123 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2124 int i; 2125 u8 c_addr[ETH_ALEN]; 2126 2127 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2128 sh_eth_tsu_read_entry(reg_offset, c_addr); 2129 if (memcmp(addr, c_addr, ETH_ALEN) == 0) 2130 return i; 2131 } 2132 2133 return -ENOENT; 2134} 2135 2136static int sh_eth_tsu_find_empty(struct net_device *ndev) 2137{ 2138 u8 blank[ETH_ALEN]; 2139 int entry; 2140 2141 memset(blank, 0, sizeof(blank)); 2142 entry = sh_eth_tsu_find_entry(ndev, blank); 2143 return (entry < 0) ? -ENOMEM : entry; 2144} 2145 2146static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2147 int entry) 2148{ 2149 struct sh_eth_private *mdp = netdev_priv(ndev); 2150 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2151 int ret; 2152 u8 blank[ETH_ALEN]; 2153 2154 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2155 ~(1 << (31 - entry)), TSU_TEN); 2156 2157 memset(blank, 0, sizeof(blank)); 2158 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2159 if (ret < 0) 2160 return ret; 2161 return 0; 2162} 2163 2164static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2165{ 2166 struct sh_eth_private *mdp = netdev_priv(ndev); 2167 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2168 int i, ret; 2169 2170 if (!mdp->cd->tsu) 2171 return 0; 2172 2173 i = sh_eth_tsu_find_entry(ndev, addr); 2174 if (i < 0) { 2175 /* No entry found, create one */ 2176 i = sh_eth_tsu_find_empty(ndev); 2177 if (i < 0) 2178 return -ENOMEM; 2179 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2180 if (ret < 0) 2181 return ret; 2182 2183 /* Enable the entry */ 2184 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2185 (1 << (31 - i)), TSU_TEN); 2186 } 2187 2188 /* Entry found or created, enable POST */ 2189 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2190 2191 return 0; 2192} 2193 2194static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2195{ 2196 struct sh_eth_private *mdp = netdev_priv(ndev); 2197 int i, ret; 2198 2199 if (!mdp->cd->tsu) 2200 return 0; 2201 2202 i = sh_eth_tsu_find_entry(ndev, addr); 2203 if (i) { 2204 /* Entry found */ 2205 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2206 goto done; 2207 2208 /* Disable the entry if both ports was disabled */ 2209 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2210 if (ret < 0) 2211 return ret; 2212 } 2213done: 2214 return 0; 2215} 2216 2217static int sh_eth_tsu_purge_all(struct net_device *ndev) 2218{ 2219 struct sh_eth_private *mdp = netdev_priv(ndev); 2220 int i, ret; 2221 2222 if (unlikely(!mdp->cd->tsu)) 2223 return 0; 2224 2225 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2226 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2227 continue; 2228 2229 /* Disable the entry if both ports was disabled */ 2230 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2231 if (ret < 0) 2232 return ret; 2233 } 2234 2235 return 0; 2236} 2237 2238static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2239{ 2240 struct sh_eth_private *mdp = netdev_priv(ndev); 2241 u8 addr[ETH_ALEN]; 2242 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2243 int i; 2244 2245 if (unlikely(!mdp->cd->tsu)) 2246 return; 2247 2248 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2249 sh_eth_tsu_read_entry(reg_offset, addr); 2250 if (is_multicast_ether_addr(addr)) 2251 sh_eth_tsu_del_entry(ndev, addr); 2252 } 2253} 2254 2255/* Multicast reception directions set */ 2256static void sh_eth_set_multicast_list(struct net_device *ndev) 2257{ 2258 struct sh_eth_private *mdp = netdev_priv(ndev); 2259 u32 ecmr_bits; 2260 int mcast_all = 0; 2261 unsigned long flags; 2262 2263 spin_lock_irqsave(&mdp->lock, flags); 2264 /* 2265 * Initial condition is MCT = 1, PRM = 0. 2266 * Depending on ndev->flags, set PRM or clear MCT 2267 */ 2268 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT; 2269 2270 if (!(ndev->flags & IFF_MULTICAST)) { 2271 sh_eth_tsu_purge_mcast(ndev); 2272 mcast_all = 1; 2273 } 2274 if (ndev->flags & IFF_ALLMULTI) { 2275 sh_eth_tsu_purge_mcast(ndev); 2276 ecmr_bits &= ~ECMR_MCT; 2277 mcast_all = 1; 2278 } 2279 2280 if (ndev->flags & IFF_PROMISC) { 2281 sh_eth_tsu_purge_all(ndev); 2282 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2283 } else if (mdp->cd->tsu) { 2284 struct netdev_hw_addr *ha; 2285 netdev_for_each_mc_addr(ha, ndev) { 2286 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2287 continue; 2288 2289 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2290 if (!mcast_all) { 2291 sh_eth_tsu_purge_mcast(ndev); 2292 ecmr_bits &= ~ECMR_MCT; 2293 mcast_all = 1; 2294 } 2295 } 2296 } 2297 } else { 2298 /* Normal, unicast/broadcast-only mode. */ 2299 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT; 2300 } 2301 2302 /* update the ethernet mode */ 2303 sh_eth_write(ndev, ecmr_bits, ECMR); 2304 2305 spin_unlock_irqrestore(&mdp->lock, flags); 2306} 2307 2308static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2309{ 2310 if (!mdp->port) 2311 return TSU_VTAG0; 2312 else 2313 return TSU_VTAG1; 2314} 2315 2316static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2317 __be16 proto, u16 vid) 2318{ 2319 struct sh_eth_private *mdp = netdev_priv(ndev); 2320 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2321 2322 if (unlikely(!mdp->cd->tsu)) 2323 return -EPERM; 2324 2325 /* No filtering if vid = 0 */ 2326 if (!vid) 2327 return 0; 2328 2329 mdp->vlan_num_ids++; 2330 2331 /* 2332 * The controller has one VLAN tag HW filter. So, if the filter is 2333 * already enabled, the driver disables it and the filte 2334 */ 2335 if (mdp->vlan_num_ids > 1) { 2336 /* disable VLAN filter */ 2337 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2338 return 0; 2339 } 2340 2341 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2342 vtag_reg_index); 2343 2344 return 0; 2345} 2346 2347static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2348 __be16 proto, u16 vid) 2349{ 2350 struct sh_eth_private *mdp = netdev_priv(ndev); 2351 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2352 2353 if (unlikely(!mdp->cd->tsu)) 2354 return -EPERM; 2355 2356 /* No filtering if vid = 0 */ 2357 if (!vid) 2358 return 0; 2359 2360 mdp->vlan_num_ids--; 2361 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2362 2363 return 0; 2364} 2365 2366/* SuperH's TSU register init function */ 2367static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2368{ 2369 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2370 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2371 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2372 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2373 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2374 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2375 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2376 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2377 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2378 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2379 if (sh_eth_is_gether(mdp)) { 2380 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2381 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2382 } else { 2383 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2384 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2385 } 2386 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2387 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2388 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2389 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2390 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2391 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2392 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2393} 2394 2395/* MDIO bus release function */ 2396static int sh_mdio_release(struct net_device *ndev) 2397{ 2398 struct mii_bus *bus = dev_get_drvdata(&ndev->dev); 2399 2400 /* unregister mdio bus */ 2401 mdiobus_unregister(bus); 2402 2403 /* remove mdio bus info from net_device */ 2404 dev_set_drvdata(&ndev->dev, NULL); 2405 2406 /* free bitbang info */ 2407 free_mdio_bitbang(bus); 2408 2409 return 0; 2410} 2411 2412/* MDIO bus init function */ 2413static int sh_mdio_init(struct net_device *ndev, int id, 2414 struct sh_eth_plat_data *pd) 2415{ 2416 int ret, i; 2417 struct bb_info *bitbang; 2418 struct sh_eth_private *mdp = netdev_priv(ndev); 2419 2420 /* create bit control struct for PHY */ 2421 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info), 2422 GFP_KERNEL); 2423 if (!bitbang) { 2424 ret = -ENOMEM; 2425 goto out; 2426 } 2427 2428 /* bitbang init */ 2429 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2430 bitbang->set_gate = pd->set_mdio_gate; 2431 bitbang->mdi_msk = PIR_MDI; 2432 bitbang->mdo_msk = PIR_MDO; 2433 bitbang->mmd_msk = PIR_MMD; 2434 bitbang->mdc_msk = PIR_MDC; 2435 bitbang->ctrl.ops = &bb_ops; 2436 2437 /* MII controller setting */ 2438 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2439 if (!mdp->mii_bus) { 2440 ret = -ENOMEM; 2441 goto out; 2442 } 2443 2444 /* Hook up MII support for ethtool */ 2445 mdp->mii_bus->name = "sh_mii"; 2446 mdp->mii_bus->parent = &ndev->dev; 2447 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2448 mdp->pdev->name, id); 2449 2450 /* PHY IRQ */ 2451 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev, 2452 sizeof(int) * PHY_MAX_ADDR, 2453 GFP_KERNEL); 2454 if (!mdp->mii_bus->irq) { 2455 ret = -ENOMEM; 2456 goto out_free_bus; 2457 } 2458 2459 for (i = 0; i < PHY_MAX_ADDR; i++) 2460 mdp->mii_bus->irq[i] = PHY_POLL; 2461 2462 /* register mdio bus */ 2463 ret = mdiobus_register(mdp->mii_bus); 2464 if (ret) 2465 goto out_free_bus; 2466 2467 dev_set_drvdata(&ndev->dev, mdp->mii_bus); 2468 2469 return 0; 2470 2471out_free_bus: 2472 free_mdio_bitbang(mdp->mii_bus); 2473 2474out: 2475 return ret; 2476} 2477 2478static const u16 *sh_eth_get_register_offset(int register_type) 2479{ 2480 const u16 *reg_offset = NULL; 2481 2482 switch (register_type) { 2483 case SH_ETH_REG_GIGABIT: 2484 reg_offset = sh_eth_offset_gigabit; 2485 break; 2486 case SH_ETH_REG_FAST_RCAR: 2487 reg_offset = sh_eth_offset_fast_rcar; 2488 break; 2489 case SH_ETH_REG_FAST_SH4: 2490 reg_offset = sh_eth_offset_fast_sh4; 2491 break; 2492 case SH_ETH_REG_FAST_SH3_SH2: 2493 reg_offset = sh_eth_offset_fast_sh3_sh2; 2494 break; 2495 default: 2496 pr_err("Unknown register type (%d)\n", register_type); 2497 break; 2498 } 2499 2500 return reg_offset; 2501} 2502 2503static struct net_device_ops sh_eth_netdev_ops = { 2504 .ndo_open = sh_eth_open, 2505 .ndo_stop = sh_eth_close, 2506 .ndo_start_xmit = sh_eth_start_xmit, 2507 .ndo_get_stats = sh_eth_get_stats, 2508 .ndo_tx_timeout = sh_eth_tx_timeout, 2509 .ndo_do_ioctl = sh_eth_do_ioctl, 2510 .ndo_validate_addr = eth_validate_addr, 2511 .ndo_set_mac_address = eth_mac_addr, 2512 .ndo_change_mtu = eth_change_mtu, 2513}; 2514 2515static int sh_eth_drv_probe(struct platform_device *pdev) 2516{ 2517 int ret, devno = 0; 2518 struct resource *res; 2519 struct net_device *ndev = NULL; 2520 struct sh_eth_private *mdp = NULL; 2521 struct sh_eth_plat_data *pd = pdev->dev.platform_data; 2522 const struct platform_device_id *id = platform_get_device_id(pdev); 2523 2524 /* get base addr */ 2525 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2526 if (unlikely(res == NULL)) { 2527 dev_err(&pdev->dev, "invalid resource\n"); 2528 ret = -EINVAL; 2529 goto out; 2530 } 2531 2532 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 2533 if (!ndev) { 2534 ret = -ENOMEM; 2535 goto out; 2536 } 2537 2538 /* The sh Ether-specific entries in the device structure. */ 2539 ndev->base_addr = res->start; 2540 devno = pdev->id; 2541 if (devno < 0) 2542 devno = 0; 2543 2544 ndev->dma = -1; 2545 ret = platform_get_irq(pdev, 0); 2546 if (ret < 0) { 2547 ret = -ENODEV; 2548 goto out_release; 2549 } 2550 ndev->irq = ret; 2551 2552 SET_NETDEV_DEV(ndev, &pdev->dev); 2553 2554 /* Fill in the fields of the device structure with ethernet values. */ 2555 ether_setup(ndev); 2556 2557 mdp = netdev_priv(ndev); 2558 mdp->num_tx_ring = TX_RING_SIZE; 2559 mdp->num_rx_ring = RX_RING_SIZE; 2560 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 2561 if (IS_ERR(mdp->addr)) { 2562 ret = PTR_ERR(mdp->addr); 2563 goto out_release; 2564 } 2565 2566 spin_lock_init(&mdp->lock); 2567 mdp->pdev = pdev; 2568 pm_runtime_enable(&pdev->dev); 2569 pm_runtime_resume(&pdev->dev); 2570 2571 /* get PHY ID */ 2572 mdp->phy_id = pd->phy; 2573 mdp->phy_interface = pd->phy_interface; 2574 /* EDMAC endian */ 2575 mdp->edmac_endian = pd->edmac_endian; 2576 mdp->no_ether_link = pd->no_ether_link; 2577 mdp->ether_link_active_low = pd->ether_link_active_low; 2578 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type); 2579 2580 /* set cpu data */ 2581#if defined(SH_ETH_HAS_BOTH_MODULES) 2582 mdp->cd = sh_eth_get_cpu_data(mdp); 2583#else 2584 mdp->cd = &sh_eth_my_cpu_data; 2585#endif 2586 if (id->driver_data) 2587 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 2588 sh_eth_set_default_cpu_data(mdp->cd); 2589 2590 /* set function */ 2591 if (mdp->cd->tsu) { 2592 sh_eth_netdev_ops.ndo_set_rx_mode = sh_eth_set_multicast_list; 2593 sh_eth_netdev_ops.ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid; 2594 sh_eth_netdev_ops.ndo_vlan_rx_kill_vid = 2595 sh_eth_vlan_rx_kill_vid; 2596 } 2597 2598 ndev->netdev_ops = &sh_eth_netdev_ops; 2599 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); 2600 ndev->watchdog_timeo = TX_TIMEOUT; 2601 2602 /* debug message level */ 2603 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 2604 2605 /* read and set MAC address */ 2606 read_mac_address(ndev, pd->mac_addr); 2607 if (!is_valid_ether_addr(ndev->dev_addr)) { 2608 dev_warn(&pdev->dev, 2609 "no valid MAC address supplied, using a random one.\n"); 2610 eth_hw_addr_random(ndev); 2611 } 2612 2613 /* ioremap the TSU registers */ 2614 if (mdp->cd->tsu) { 2615 struct resource *rtsu; 2616 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2617 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); 2618 if (IS_ERR(mdp->tsu_addr)) { 2619 ret = PTR_ERR(mdp->tsu_addr); 2620 goto out_release; 2621 } 2622 mdp->port = devno % 2; 2623 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 2624 } 2625 2626 /* initialize first or needed device */ 2627 if (!devno || pd->needs_init) { 2628 if (mdp->cd->chip_reset) 2629 mdp->cd->chip_reset(ndev); 2630 2631 if (mdp->cd->tsu) { 2632 /* TSU init (Init only)*/ 2633 sh_eth_tsu_init(mdp); 2634 } 2635 } 2636 2637 /* network device register */ 2638 ret = register_netdev(ndev); 2639 if (ret) 2640 goto out_release; 2641 2642 /* mdio bus init */ 2643 ret = sh_mdio_init(ndev, pdev->id, pd); 2644 if (ret) 2645 goto out_unregister; 2646 2647 /* print device information */ 2648 pr_info("Base address at 0x%x, %pM, IRQ %d.\n", 2649 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2650 2651 platform_set_drvdata(pdev, ndev); 2652 2653 return ret; 2654 2655out_unregister: 2656 unregister_netdev(ndev); 2657 2658out_release: 2659 /* net_dev free */ 2660 if (ndev) 2661 free_netdev(ndev); 2662 2663out: 2664 return ret; 2665} 2666 2667static int sh_eth_drv_remove(struct platform_device *pdev) 2668{ 2669 struct net_device *ndev = platform_get_drvdata(pdev); 2670 2671 sh_mdio_release(ndev); 2672 unregister_netdev(ndev); 2673 pm_runtime_disable(&pdev->dev); 2674 free_netdev(ndev); 2675 2676 return 0; 2677} 2678 2679#ifdef CONFIG_PM 2680static int sh_eth_runtime_nop(struct device *dev) 2681{ 2682 /* 2683 * Runtime PM callback shared between ->runtime_suspend() 2684 * and ->runtime_resume(). Simply returns success. 2685 * 2686 * This driver re-initializes all registers after 2687 * pm_runtime_get_sync() anyway so there is no need 2688 * to save and restore registers here. 2689 */ 2690 return 0; 2691} 2692 2693static const struct dev_pm_ops sh_eth_dev_pm_ops = { 2694 .runtime_suspend = sh_eth_runtime_nop, 2695 .runtime_resume = sh_eth_runtime_nop, 2696}; 2697#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 2698#else 2699#define SH_ETH_PM_OPS NULL 2700#endif 2701 2702static struct platform_device_id sh_eth_id_table[] = { 2703 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 2704 { CARDNAME }, 2705 { } 2706}; 2707MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 2708 2709static struct platform_driver sh_eth_driver = { 2710 .probe = sh_eth_drv_probe, 2711 .remove = sh_eth_drv_remove, 2712 .id_table = sh_eth_id_table, 2713 .driver = { 2714 .name = CARDNAME, 2715 .pm = SH_ETH_PM_OPS, 2716 }, 2717}; 2718 2719module_platform_driver(sh_eth_driver); 2720 2721MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 2722MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 2723MODULE_LICENSE("GPL v2"); 2724