sh_eth.c revision 7db8e0c14c9cb4adb667b4c558d8ffec8d5b40f2
1/* 2 * SuperH Ethernet device driver 3 * 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 */ 23 24#include <linux/init.h> 25#include <linux/module.h> 26#include <linux/kernel.h> 27#include <linux/spinlock.h> 28#include <linux/interrupt.h> 29#include <linux/dma-mapping.h> 30#include <linux/etherdevice.h> 31#include <linux/delay.h> 32#include <linux/platform_device.h> 33#include <linux/mdio-bitbang.h> 34#include <linux/netdevice.h> 35#include <linux/phy.h> 36#include <linux/cache.h> 37#include <linux/io.h> 38#include <linux/pm_runtime.h> 39#include <linux/slab.h> 40#include <linux/ethtool.h> 41#include <linux/if_vlan.h> 42#include <linux/clk.h> 43#include <linux/sh_eth.h> 44 45#include "sh_eth.h" 46 47#define SH_ETH_DEF_MSG_ENABLE \ 48 (NETIF_MSG_LINK | \ 49 NETIF_MSG_TIMER | \ 50 NETIF_MSG_RX_ERR| \ 51 NETIF_MSG_TX_ERR) 52 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 54 [EDSR] = 0x0000, 55 [EDMR] = 0x0400, 56 [EDTRR] = 0x0408, 57 [EDRRR] = 0x0410, 58 [EESR] = 0x0428, 59 [EESIPR] = 0x0430, 60 [TDLAR] = 0x0010, 61 [TDFAR] = 0x0014, 62 [TDFXR] = 0x0018, 63 [TDFFR] = 0x001c, 64 [RDLAR] = 0x0030, 65 [RDFAR] = 0x0034, 66 [RDFXR] = 0x0038, 67 [RDFFR] = 0x003c, 68 [TRSCER] = 0x0438, 69 [RMFCR] = 0x0440, 70 [TFTR] = 0x0448, 71 [FDR] = 0x0450, 72 [RMCR] = 0x0458, 73 [RPADIR] = 0x0460, 74 [FCFTR] = 0x0468, 75 [CSMR] = 0x04E4, 76 77 [ECMR] = 0x0500, 78 [ECSR] = 0x0510, 79 [ECSIPR] = 0x0518, 80 [PIR] = 0x0520, 81 [PSR] = 0x0528, 82 [PIPR] = 0x052c, 83 [RFLR] = 0x0508, 84 [APR] = 0x0554, 85 [MPR] = 0x0558, 86 [PFTCR] = 0x055c, 87 [PFRCR] = 0x0560, 88 [TPAUSER] = 0x0564, 89 [GECMR] = 0x05b0, 90 [BCULR] = 0x05b4, 91 [MAHR] = 0x05c0, 92 [MALR] = 0x05c8, 93 [TROCR] = 0x0700, 94 [CDCR] = 0x0708, 95 [LCCR] = 0x0710, 96 [CEFCR] = 0x0740, 97 [FRECR] = 0x0748, 98 [TSFRCR] = 0x0750, 99 [TLFRCR] = 0x0758, 100 [RFCR] = 0x0760, 101 [CERCR] = 0x0768, 102 [CEECR] = 0x0770, 103 [MAFCR] = 0x0778, 104 [RMII_MII] = 0x0790, 105 106 [ARSTR] = 0x0000, 107 [TSU_CTRST] = 0x0004, 108 [TSU_FWEN0] = 0x0010, 109 [TSU_FWEN1] = 0x0014, 110 [TSU_FCM] = 0x0018, 111 [TSU_BSYSL0] = 0x0020, 112 [TSU_BSYSL1] = 0x0024, 113 [TSU_PRISL0] = 0x0028, 114 [TSU_PRISL1] = 0x002c, 115 [TSU_FWSL0] = 0x0030, 116 [TSU_FWSL1] = 0x0034, 117 [TSU_FWSLC] = 0x0038, 118 [TSU_QTAG0] = 0x0040, 119 [TSU_QTAG1] = 0x0044, 120 [TSU_FWSR] = 0x0050, 121 [TSU_FWINMK] = 0x0054, 122 [TSU_ADQT0] = 0x0048, 123 [TSU_ADQT1] = 0x004c, 124 [TSU_VTAG0] = 0x0058, 125 [TSU_VTAG1] = 0x005c, 126 [TSU_ADSBSY] = 0x0060, 127 [TSU_TEN] = 0x0064, 128 [TSU_POST1] = 0x0070, 129 [TSU_POST2] = 0x0074, 130 [TSU_POST3] = 0x0078, 131 [TSU_POST4] = 0x007c, 132 [TSU_ADRH0] = 0x0100, 133 [TSU_ADRL0] = 0x0104, 134 [TSU_ADRH31] = 0x01f8, 135 [TSU_ADRL31] = 0x01fc, 136 137 [TXNLCR0] = 0x0080, 138 [TXALCR0] = 0x0084, 139 [RXNLCR0] = 0x0088, 140 [RXALCR0] = 0x008c, 141 [FWNLCR0] = 0x0090, 142 [FWALCR0] = 0x0094, 143 [TXNLCR1] = 0x00a0, 144 [TXALCR1] = 0x00a0, 145 [RXNLCR1] = 0x00a8, 146 [RXALCR1] = 0x00ac, 147 [FWNLCR1] = 0x00b0, 148 [FWALCR1] = 0x00b4, 149}; 150 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 152 [ECMR] = 0x0300, 153 [RFLR] = 0x0308, 154 [ECSR] = 0x0310, 155 [ECSIPR] = 0x0318, 156 [PIR] = 0x0320, 157 [PSR] = 0x0328, 158 [RDMLR] = 0x0340, 159 [IPGR] = 0x0350, 160 [APR] = 0x0354, 161 [MPR] = 0x0358, 162 [RFCF] = 0x0360, 163 [TPAUSER] = 0x0364, 164 [TPAUSECR] = 0x0368, 165 [MAHR] = 0x03c0, 166 [MALR] = 0x03c8, 167 [TROCR] = 0x03d0, 168 [CDCR] = 0x03d4, 169 [LCCR] = 0x03d8, 170 [CNDCR] = 0x03dc, 171 [CEFCR] = 0x03e4, 172 [FRECR] = 0x03e8, 173 [TSFRCR] = 0x03ec, 174 [TLFRCR] = 0x03f0, 175 [RFCR] = 0x03f4, 176 [MAFCR] = 0x03f8, 177 178 [EDMR] = 0x0200, 179 [EDTRR] = 0x0208, 180 [EDRRR] = 0x0210, 181 [TDLAR] = 0x0218, 182 [RDLAR] = 0x0220, 183 [EESR] = 0x0228, 184 [EESIPR] = 0x0230, 185 [TRSCER] = 0x0238, 186 [RMFCR] = 0x0240, 187 [TFTR] = 0x0248, 188 [FDR] = 0x0250, 189 [RMCR] = 0x0258, 190 [TFUCR] = 0x0264, 191 [RFOCR] = 0x0268, 192 [RMIIMODE] = 0x026c, 193 [FCFTR] = 0x0270, 194 [TRIMD] = 0x027c, 195}; 196 197static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 198 [ECMR] = 0x0100, 199 [RFLR] = 0x0108, 200 [ECSR] = 0x0110, 201 [ECSIPR] = 0x0118, 202 [PIR] = 0x0120, 203 [PSR] = 0x0128, 204 [RDMLR] = 0x0140, 205 [IPGR] = 0x0150, 206 [APR] = 0x0154, 207 [MPR] = 0x0158, 208 [TPAUSER] = 0x0164, 209 [RFCF] = 0x0160, 210 [TPAUSECR] = 0x0168, 211 [BCFRR] = 0x016c, 212 [MAHR] = 0x01c0, 213 [MALR] = 0x01c8, 214 [TROCR] = 0x01d0, 215 [CDCR] = 0x01d4, 216 [LCCR] = 0x01d8, 217 [CNDCR] = 0x01dc, 218 [CEFCR] = 0x01e4, 219 [FRECR] = 0x01e8, 220 [TSFRCR] = 0x01ec, 221 [TLFRCR] = 0x01f0, 222 [RFCR] = 0x01f4, 223 [MAFCR] = 0x01f8, 224 [RTRATE] = 0x01fc, 225 226 [EDMR] = 0x0000, 227 [EDTRR] = 0x0008, 228 [EDRRR] = 0x0010, 229 [TDLAR] = 0x0018, 230 [RDLAR] = 0x0020, 231 [EESR] = 0x0028, 232 [EESIPR] = 0x0030, 233 [TRSCER] = 0x0038, 234 [RMFCR] = 0x0040, 235 [TFTR] = 0x0048, 236 [FDR] = 0x0050, 237 [RMCR] = 0x0058, 238 [TFUCR] = 0x0064, 239 [RFOCR] = 0x0068, 240 [FCFTR] = 0x0070, 241 [RPADIR] = 0x0078, 242 [TRIMD] = 0x007c, 243 [RBWAR] = 0x00c8, 244 [RDFAR] = 0x00cc, 245 [TBRAR] = 0x00d4, 246 [TDFAR] = 0x00d8, 247}; 248 249static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 250 [ECMR] = 0x0160, 251 [ECSR] = 0x0164, 252 [ECSIPR] = 0x0168, 253 [PIR] = 0x016c, 254 [MAHR] = 0x0170, 255 [MALR] = 0x0174, 256 [RFLR] = 0x0178, 257 [PSR] = 0x017c, 258 [TROCR] = 0x0180, 259 [CDCR] = 0x0184, 260 [LCCR] = 0x0188, 261 [CNDCR] = 0x018c, 262 [CEFCR] = 0x0194, 263 [FRECR] = 0x0198, 264 [TSFRCR] = 0x019c, 265 [TLFRCR] = 0x01a0, 266 [RFCR] = 0x01a4, 267 [MAFCR] = 0x01a8, 268 [IPGR] = 0x01b4, 269 [APR] = 0x01b8, 270 [MPR] = 0x01bc, 271 [TPAUSER] = 0x01c4, 272 [BCFR] = 0x01cc, 273 274 [ARSTR] = 0x0000, 275 [TSU_CTRST] = 0x0004, 276 [TSU_FWEN0] = 0x0010, 277 [TSU_FWEN1] = 0x0014, 278 [TSU_FCM] = 0x0018, 279 [TSU_BSYSL0] = 0x0020, 280 [TSU_BSYSL1] = 0x0024, 281 [TSU_PRISL0] = 0x0028, 282 [TSU_PRISL1] = 0x002c, 283 [TSU_FWSL0] = 0x0030, 284 [TSU_FWSL1] = 0x0034, 285 [TSU_FWSLC] = 0x0038, 286 [TSU_QTAGM0] = 0x0040, 287 [TSU_QTAGM1] = 0x0044, 288 [TSU_ADQT0] = 0x0048, 289 [TSU_ADQT1] = 0x004c, 290 [TSU_FWSR] = 0x0050, 291 [TSU_FWINMK] = 0x0054, 292 [TSU_ADSBSY] = 0x0060, 293 [TSU_TEN] = 0x0064, 294 [TSU_POST1] = 0x0070, 295 [TSU_POST2] = 0x0074, 296 [TSU_POST3] = 0x0078, 297 [TSU_POST4] = 0x007c, 298 299 [TXNLCR0] = 0x0080, 300 [TXALCR0] = 0x0084, 301 [RXNLCR0] = 0x0088, 302 [RXALCR0] = 0x008c, 303 [FWNLCR0] = 0x0090, 304 [FWALCR0] = 0x0094, 305 [TXNLCR1] = 0x00a0, 306 [TXALCR1] = 0x00a0, 307 [RXNLCR1] = 0x00a8, 308 [RXALCR1] = 0x00ac, 309 [FWNLCR1] = 0x00b0, 310 [FWALCR1] = 0x00b4, 311 312 [TSU_ADRH0] = 0x0100, 313 [TSU_ADRL0] = 0x0104, 314 [TSU_ADRL31] = 0x01fc, 315}; 316 317static int sh_eth_is_gether(struct sh_eth_private *mdp) 318{ 319 if (mdp->reg_offset == sh_eth_offset_gigabit) 320 return 1; 321 else 322 return 0; 323} 324 325static void sh_eth_select_mii(struct net_device *ndev) 326{ 327 u32 value = 0x0; 328 struct sh_eth_private *mdp = netdev_priv(ndev); 329 330 switch (mdp->phy_interface) { 331 case PHY_INTERFACE_MODE_GMII: 332 value = 0x2; 333 break; 334 case PHY_INTERFACE_MODE_MII: 335 value = 0x1; 336 break; 337 case PHY_INTERFACE_MODE_RMII: 338 value = 0x0; 339 break; 340 default: 341 pr_warn("PHY interface mode was not setup. Set to MII.\n"); 342 value = 0x1; 343 break; 344 } 345 346 sh_eth_write(ndev, value, RMII_MII); 347} 348 349static void sh_eth_set_duplex(struct net_device *ndev) 350{ 351 struct sh_eth_private *mdp = netdev_priv(ndev); 352 353 if (mdp->duplex) /* Full */ 354 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 355 else /* Half */ 356 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 357} 358 359/* There is CPU dependent code */ 360static void sh_eth_set_rate_r8a777x(struct net_device *ndev) 361{ 362 struct sh_eth_private *mdp = netdev_priv(ndev); 363 364 switch (mdp->speed) { 365 case 10: /* 10BASE */ 366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR); 367 break; 368 case 100:/* 100BASE */ 369 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR); 370 break; 371 default: 372 break; 373 } 374} 375 376/* R8A7778/9 */ 377static struct sh_eth_cpu_data r8a777x_data = { 378 .set_duplex = sh_eth_set_duplex, 379 .set_rate = sh_eth_set_rate_r8a777x, 380 381 .register_type = SH_ETH_REG_FAST_RCAR, 382 383 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 384 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 385 .eesipr_value = 0x01ff009f, 386 387 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 388 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 389 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 390 EESR_ECI, 391 392 .apr = 1, 393 .mpr = 1, 394 .tpauser = 1, 395 .hw_swap = 1, 396}; 397 398/* R8A7790 */ 399static struct sh_eth_cpu_data r8a7790_data = { 400 .set_duplex = sh_eth_set_duplex, 401 .set_rate = sh_eth_set_rate_r8a777x, 402 403 .register_type = SH_ETH_REG_FAST_RCAR, 404 405 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 406 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 407 .eesipr_value = 0x01ff009f, 408 409 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 410 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 411 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 412 EESR_ECI, 413 414 .apr = 1, 415 .mpr = 1, 416 .tpauser = 1, 417 .hw_swap = 1, 418 .rmiimode = 1, 419}; 420 421static void sh_eth_set_rate_sh7724(struct net_device *ndev) 422{ 423 struct sh_eth_private *mdp = netdev_priv(ndev); 424 425 switch (mdp->speed) { 426 case 10: /* 10BASE */ 427 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 428 break; 429 case 100:/* 100BASE */ 430 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 431 break; 432 default: 433 break; 434 } 435} 436 437/* SH7724 */ 438static struct sh_eth_cpu_data sh7724_data = { 439 .set_duplex = sh_eth_set_duplex, 440 .set_rate = sh_eth_set_rate_sh7724, 441 442 .register_type = SH_ETH_REG_FAST_SH4, 443 444 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 445 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 446 .eesipr_value = 0x01ff009f, 447 448 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 449 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 450 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 451 EESR_ECI, 452 453 .apr = 1, 454 .mpr = 1, 455 .tpauser = 1, 456 .hw_swap = 1, 457 .rpadir = 1, 458 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 459}; 460 461static void sh_eth_set_rate_sh7757(struct net_device *ndev) 462{ 463 struct sh_eth_private *mdp = netdev_priv(ndev); 464 465 switch (mdp->speed) { 466 case 10: /* 10BASE */ 467 sh_eth_write(ndev, 0, RTRATE); 468 break; 469 case 100:/* 100BASE */ 470 sh_eth_write(ndev, 1, RTRATE); 471 break; 472 default: 473 break; 474 } 475} 476 477/* SH7757 */ 478static struct sh_eth_cpu_data sh7757_data = { 479 .set_duplex = sh_eth_set_duplex, 480 .set_rate = sh_eth_set_rate_sh7757, 481 482 .register_type = SH_ETH_REG_FAST_SH4, 483 484 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 485 .rmcr_value = 0x00000001, 486 487 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 488 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 489 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 490 EESR_ECI, 491 492 .irq_flags = IRQF_SHARED, 493 .apr = 1, 494 .mpr = 1, 495 .tpauser = 1, 496 .hw_swap = 1, 497 .no_ade = 1, 498 .rpadir = 1, 499 .rpadir_value = 2 << 16, 500}; 501 502#define SH_GIGA_ETH_BASE 0xfee00000UL 503#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 504#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 505static void sh_eth_chip_reset_giga(struct net_device *ndev) 506{ 507 int i; 508 unsigned long mahr[2], malr[2]; 509 510 /* save MAHR and MALR */ 511 for (i = 0; i < 2; i++) { 512 malr[i] = ioread32((void *)GIGA_MALR(i)); 513 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 514 } 515 516 /* reset device */ 517 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 518 mdelay(1); 519 520 /* restore MAHR and MALR */ 521 for (i = 0; i < 2; i++) { 522 iowrite32(malr[i], (void *)GIGA_MALR(i)); 523 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 524 } 525} 526 527static void sh_eth_set_rate_giga(struct net_device *ndev) 528{ 529 struct sh_eth_private *mdp = netdev_priv(ndev); 530 531 switch (mdp->speed) { 532 case 10: /* 10BASE */ 533 sh_eth_write(ndev, 0x00000000, GECMR); 534 break; 535 case 100:/* 100BASE */ 536 sh_eth_write(ndev, 0x00000010, GECMR); 537 break; 538 case 1000: /* 1000BASE */ 539 sh_eth_write(ndev, 0x00000020, GECMR); 540 break; 541 default: 542 break; 543 } 544} 545 546/* SH7757(GETHERC) */ 547static struct sh_eth_cpu_data sh7757_data_giga = { 548 .chip_reset = sh_eth_chip_reset_giga, 549 .set_duplex = sh_eth_set_duplex, 550 .set_rate = sh_eth_set_rate_giga, 551 552 .register_type = SH_ETH_REG_GIGABIT, 553 554 .ecsr_value = ECSR_ICD | ECSR_MPD, 555 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 556 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 557 558 .tx_check = EESR_TC1 | EESR_FTC, 559 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 560 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 561 EESR_TDE | EESR_ECI, 562 .fdr_value = 0x0000072f, 563 .rmcr_value = 0x00000001, 564 565 .irq_flags = IRQF_SHARED, 566 .apr = 1, 567 .mpr = 1, 568 .tpauser = 1, 569 .bculr = 1, 570 .hw_swap = 1, 571 .rpadir = 1, 572 .rpadir_value = 2 << 16, 573 .no_trimd = 1, 574 .no_ade = 1, 575 .tsu = 1, 576}; 577 578static void sh_eth_chip_reset(struct net_device *ndev) 579{ 580 struct sh_eth_private *mdp = netdev_priv(ndev); 581 582 /* reset device */ 583 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 584 mdelay(1); 585} 586 587static void sh_eth_set_rate_gether(struct net_device *ndev) 588{ 589 struct sh_eth_private *mdp = netdev_priv(ndev); 590 591 switch (mdp->speed) { 592 case 10: /* 10BASE */ 593 sh_eth_write(ndev, GECMR_10, GECMR); 594 break; 595 case 100:/* 100BASE */ 596 sh_eth_write(ndev, GECMR_100, GECMR); 597 break; 598 case 1000: /* 1000BASE */ 599 sh_eth_write(ndev, GECMR_1000, GECMR); 600 break; 601 default: 602 break; 603 } 604} 605 606/* SH7734 */ 607static struct sh_eth_cpu_data sh7734_data = { 608 .chip_reset = sh_eth_chip_reset, 609 .set_duplex = sh_eth_set_duplex, 610 .set_rate = sh_eth_set_rate_gether, 611 612 .register_type = SH_ETH_REG_GIGABIT, 613 614 .ecsr_value = ECSR_ICD | ECSR_MPD, 615 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 616 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 617 618 .tx_check = EESR_TC1 | EESR_FTC, 619 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 620 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 621 EESR_TDE | EESR_ECI, 622 623 .apr = 1, 624 .mpr = 1, 625 .tpauser = 1, 626 .bculr = 1, 627 .hw_swap = 1, 628 .no_trimd = 1, 629 .no_ade = 1, 630 .tsu = 1, 631 .hw_crc = 1, 632 .select_mii = 1, 633}; 634 635/* SH7763 */ 636static struct sh_eth_cpu_data sh7763_data = { 637 .chip_reset = sh_eth_chip_reset, 638 .set_duplex = sh_eth_set_duplex, 639 .set_rate = sh_eth_set_rate_gether, 640 641 .register_type = SH_ETH_REG_GIGABIT, 642 643 .ecsr_value = ECSR_ICD | ECSR_MPD, 644 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 645 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 646 647 .tx_check = EESR_TC1 | EESR_FTC, 648 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 649 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 650 EESR_ECI, 651 652 .apr = 1, 653 .mpr = 1, 654 .tpauser = 1, 655 .bculr = 1, 656 .hw_swap = 1, 657 .no_trimd = 1, 658 .no_ade = 1, 659 .tsu = 1, 660 .irq_flags = IRQF_SHARED, 661}; 662 663static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 664{ 665 struct sh_eth_private *mdp = netdev_priv(ndev); 666 667 /* reset device */ 668 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 669 mdelay(1); 670 671 sh_eth_select_mii(ndev); 672} 673 674/* R8A7740 */ 675static struct sh_eth_cpu_data r8a7740_data = { 676 .chip_reset = sh_eth_chip_reset_r8a7740, 677 .set_duplex = sh_eth_set_duplex, 678 .set_rate = sh_eth_set_rate_gether, 679 680 .register_type = SH_ETH_REG_GIGABIT, 681 682 .ecsr_value = ECSR_ICD | ECSR_MPD, 683 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 684 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 685 686 .tx_check = EESR_TC1 | EESR_FTC, 687 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 688 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 689 EESR_TDE | EESR_ECI, 690 691 .apr = 1, 692 .mpr = 1, 693 .tpauser = 1, 694 .bculr = 1, 695 .hw_swap = 1, 696 .no_trimd = 1, 697 .no_ade = 1, 698 .tsu = 1, 699 .select_mii = 1, 700 .shift_rd0 = 1, 701}; 702 703static struct sh_eth_cpu_data sh7619_data = { 704 .register_type = SH_ETH_REG_FAST_SH3_SH2, 705 706 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 707 708 .apr = 1, 709 .mpr = 1, 710 .tpauser = 1, 711 .hw_swap = 1, 712}; 713 714static struct sh_eth_cpu_data sh771x_data = { 715 .register_type = SH_ETH_REG_FAST_SH3_SH2, 716 717 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 718 .tsu = 1, 719}; 720 721static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 722{ 723 if (!cd->ecsr_value) 724 cd->ecsr_value = DEFAULT_ECSR_INIT; 725 726 if (!cd->ecsipr_value) 727 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 728 729 if (!cd->fcftr_value) 730 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \ 731 DEFAULT_FIFO_F_D_RFD; 732 733 if (!cd->fdr_value) 734 cd->fdr_value = DEFAULT_FDR_INIT; 735 736 if (!cd->rmcr_value) 737 cd->rmcr_value = DEFAULT_RMCR_VALUE; 738 739 if (!cd->tx_check) 740 cd->tx_check = DEFAULT_TX_CHECK; 741 742 if (!cd->eesr_err_check) 743 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 744} 745 746static int sh_eth_check_reset(struct net_device *ndev) 747{ 748 int ret = 0; 749 int cnt = 100; 750 751 while (cnt > 0) { 752 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 753 break; 754 mdelay(1); 755 cnt--; 756 } 757 if (cnt <= 0) { 758 pr_err("Device reset failed\n"); 759 ret = -ETIMEDOUT; 760 } 761 return ret; 762} 763 764static int sh_eth_reset(struct net_device *ndev) 765{ 766 struct sh_eth_private *mdp = netdev_priv(ndev); 767 int ret = 0; 768 769 if (sh_eth_is_gether(mdp)) { 770 sh_eth_write(ndev, EDSR_ENALL, EDSR); 771 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 772 EDMR); 773 774 ret = sh_eth_check_reset(ndev); 775 if (ret) 776 goto out; 777 778 /* Table Init */ 779 sh_eth_write(ndev, 0x0, TDLAR); 780 sh_eth_write(ndev, 0x0, TDFAR); 781 sh_eth_write(ndev, 0x0, TDFXR); 782 sh_eth_write(ndev, 0x0, TDFFR); 783 sh_eth_write(ndev, 0x0, RDLAR); 784 sh_eth_write(ndev, 0x0, RDFAR); 785 sh_eth_write(ndev, 0x0, RDFXR); 786 sh_eth_write(ndev, 0x0, RDFFR); 787 788 /* Reset HW CRC register */ 789 if (mdp->cd->hw_crc) 790 sh_eth_write(ndev, 0x0, CSMR); 791 792 /* Select MII mode */ 793 if (mdp->cd->select_mii) 794 sh_eth_select_mii(ndev); 795 } else { 796 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 797 EDMR); 798 mdelay(3); 799 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 800 EDMR); 801 } 802 803out: 804 return ret; 805} 806 807#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 808static void sh_eth_set_receive_align(struct sk_buff *skb) 809{ 810 int reserve; 811 812 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); 813 if (reserve) 814 skb_reserve(skb, reserve); 815} 816#else 817static void sh_eth_set_receive_align(struct sk_buff *skb) 818{ 819 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); 820} 821#endif 822 823 824/* CPU <-> EDMAC endian convert */ 825static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 826{ 827 switch (mdp->edmac_endian) { 828 case EDMAC_LITTLE_ENDIAN: 829 return cpu_to_le32(x); 830 case EDMAC_BIG_ENDIAN: 831 return cpu_to_be32(x); 832 } 833 return x; 834} 835 836static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) 837{ 838 switch (mdp->edmac_endian) { 839 case EDMAC_LITTLE_ENDIAN: 840 return le32_to_cpu(x); 841 case EDMAC_BIG_ENDIAN: 842 return be32_to_cpu(x); 843 } 844 return x; 845} 846 847/* 848 * Program the hardware MAC address from dev->dev_addr. 849 */ 850static void update_mac_address(struct net_device *ndev) 851{ 852 sh_eth_write(ndev, 853 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 854 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 855 sh_eth_write(ndev, 856 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 857} 858 859/* 860 * Get MAC address from SuperH MAC address register 861 * 862 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 863 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 864 * When you want use this device, you must set MAC address in bootloader. 865 * 866 */ 867static void read_mac_address(struct net_device *ndev, unsigned char *mac) 868{ 869 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 870 memcpy(ndev->dev_addr, mac, 6); 871 } else { 872 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24); 873 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF; 874 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF; 875 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF); 876 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF; 877 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF); 878 } 879} 880 881static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 882{ 883 if (sh_eth_is_gether(mdp)) 884 return EDTRR_TRNS_GETHER; 885 else 886 return EDTRR_TRNS_ETHER; 887} 888 889struct bb_info { 890 void (*set_gate)(void *addr); 891 struct mdiobb_ctrl ctrl; 892 void *addr; 893 u32 mmd_msk;/* MMD */ 894 u32 mdo_msk; 895 u32 mdi_msk; 896 u32 mdc_msk; 897}; 898 899/* PHY bit set */ 900static void bb_set(void *addr, u32 msk) 901{ 902 iowrite32(ioread32(addr) | msk, addr); 903} 904 905/* PHY bit clear */ 906static void bb_clr(void *addr, u32 msk) 907{ 908 iowrite32((ioread32(addr) & ~msk), addr); 909} 910 911/* PHY bit read */ 912static int bb_read(void *addr, u32 msk) 913{ 914 return (ioread32(addr) & msk) != 0; 915} 916 917/* Data I/O pin control */ 918static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 919{ 920 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 921 922 if (bitbang->set_gate) 923 bitbang->set_gate(bitbang->addr); 924 925 if (bit) 926 bb_set(bitbang->addr, bitbang->mmd_msk); 927 else 928 bb_clr(bitbang->addr, bitbang->mmd_msk); 929} 930 931/* Set bit data*/ 932static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 933{ 934 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 935 936 if (bitbang->set_gate) 937 bitbang->set_gate(bitbang->addr); 938 939 if (bit) 940 bb_set(bitbang->addr, bitbang->mdo_msk); 941 else 942 bb_clr(bitbang->addr, bitbang->mdo_msk); 943} 944 945/* Get bit data*/ 946static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 947{ 948 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 949 950 if (bitbang->set_gate) 951 bitbang->set_gate(bitbang->addr); 952 953 return bb_read(bitbang->addr, bitbang->mdi_msk); 954} 955 956/* MDC pin control */ 957static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 958{ 959 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 960 961 if (bitbang->set_gate) 962 bitbang->set_gate(bitbang->addr); 963 964 if (bit) 965 bb_set(bitbang->addr, bitbang->mdc_msk); 966 else 967 bb_clr(bitbang->addr, bitbang->mdc_msk); 968} 969 970/* mdio bus control struct */ 971static struct mdiobb_ops bb_ops = { 972 .owner = THIS_MODULE, 973 .set_mdc = sh_mdc_ctrl, 974 .set_mdio_dir = sh_mmd_ctrl, 975 .set_mdio_data = sh_set_mdio, 976 .get_mdio_data = sh_get_mdio, 977}; 978 979/* free skb and descriptor buffer */ 980static void sh_eth_ring_free(struct net_device *ndev) 981{ 982 struct sh_eth_private *mdp = netdev_priv(ndev); 983 int i; 984 985 /* Free Rx skb ringbuffer */ 986 if (mdp->rx_skbuff) { 987 for (i = 0; i < mdp->num_rx_ring; i++) { 988 if (mdp->rx_skbuff[i]) 989 dev_kfree_skb(mdp->rx_skbuff[i]); 990 } 991 } 992 kfree(mdp->rx_skbuff); 993 mdp->rx_skbuff = NULL; 994 995 /* Free Tx skb ringbuffer */ 996 if (mdp->tx_skbuff) { 997 for (i = 0; i < mdp->num_tx_ring; i++) { 998 if (mdp->tx_skbuff[i]) 999 dev_kfree_skb(mdp->tx_skbuff[i]); 1000 } 1001 } 1002 kfree(mdp->tx_skbuff); 1003 mdp->tx_skbuff = NULL; 1004} 1005 1006/* format skb and descriptor buffer */ 1007static void sh_eth_ring_format(struct net_device *ndev) 1008{ 1009 struct sh_eth_private *mdp = netdev_priv(ndev); 1010 int i; 1011 struct sk_buff *skb; 1012 struct sh_eth_rxdesc *rxdesc = NULL; 1013 struct sh_eth_txdesc *txdesc = NULL; 1014 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1015 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1016 1017 mdp->cur_rx = mdp->cur_tx = 0; 1018 mdp->dirty_rx = mdp->dirty_tx = 0; 1019 1020 memset(mdp->rx_ring, 0, rx_ringsize); 1021 1022 /* build Rx ring buffer */ 1023 for (i = 0; i < mdp->num_rx_ring; i++) { 1024 /* skb */ 1025 mdp->rx_skbuff[i] = NULL; 1026 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1027 mdp->rx_skbuff[i] = skb; 1028 if (skb == NULL) 1029 break; 1030 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1031 DMA_FROM_DEVICE); 1032 sh_eth_set_receive_align(skb); 1033 1034 /* RX descriptor */ 1035 rxdesc = &mdp->rx_ring[i]; 1036 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1037 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1038 1039 /* The size of the buffer is 16 byte boundary. */ 1040 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1041 /* Rx descriptor address set */ 1042 if (i == 0) { 1043 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1044 if (sh_eth_is_gether(mdp)) 1045 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1046 } 1047 } 1048 1049 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1050 1051 /* Mark the last entry as wrapping the ring. */ 1052 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); 1053 1054 memset(mdp->tx_ring, 0, tx_ringsize); 1055 1056 /* build Tx ring buffer */ 1057 for (i = 0; i < mdp->num_tx_ring; i++) { 1058 mdp->tx_skbuff[i] = NULL; 1059 txdesc = &mdp->tx_ring[i]; 1060 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1061 txdesc->buffer_length = 0; 1062 if (i == 0) { 1063 /* Tx descriptor address set */ 1064 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1065 if (sh_eth_is_gether(mdp)) 1066 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1067 } 1068 } 1069 1070 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1071} 1072 1073/* Get skb and descriptor buffer */ 1074static int sh_eth_ring_init(struct net_device *ndev) 1075{ 1076 struct sh_eth_private *mdp = netdev_priv(ndev); 1077 int rx_ringsize, tx_ringsize, ret = 0; 1078 1079 /* 1080 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1081 * card needs room to do 8 byte alignment, +2 so we can reserve 1082 * the first 2 bytes, and +16 gets room for the status word from the 1083 * card. 1084 */ 1085 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1086 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1087 if (mdp->cd->rpadir) 1088 mdp->rx_buf_sz += NET_IP_ALIGN; 1089 1090 /* Allocate RX and TX skb rings */ 1091 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring, 1092 sizeof(*mdp->rx_skbuff), GFP_KERNEL); 1093 if (!mdp->rx_skbuff) { 1094 ret = -ENOMEM; 1095 return ret; 1096 } 1097 1098 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring, 1099 sizeof(*mdp->tx_skbuff), GFP_KERNEL); 1100 if (!mdp->tx_skbuff) { 1101 ret = -ENOMEM; 1102 goto skb_ring_free; 1103 } 1104 1105 /* Allocate all Rx descriptors. */ 1106 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1107 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 1108 GFP_KERNEL); 1109 if (!mdp->rx_ring) { 1110 ret = -ENOMEM; 1111 goto desc_ring_free; 1112 } 1113 1114 mdp->dirty_rx = 0; 1115 1116 /* Allocate all Tx descriptors. */ 1117 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1118 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 1119 GFP_KERNEL); 1120 if (!mdp->tx_ring) { 1121 ret = -ENOMEM; 1122 goto desc_ring_free; 1123 } 1124 return ret; 1125 1126desc_ring_free: 1127 /* free DMA buffer */ 1128 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); 1129 1130skb_ring_free: 1131 /* Free Rx and Tx skb ring buffer */ 1132 sh_eth_ring_free(ndev); 1133 mdp->tx_ring = NULL; 1134 mdp->rx_ring = NULL; 1135 1136 return ret; 1137} 1138 1139static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp) 1140{ 1141 int ringsize; 1142 1143 if (mdp->rx_ring) { 1144 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1145 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 1146 mdp->rx_desc_dma); 1147 mdp->rx_ring = NULL; 1148 } 1149 1150 if (mdp->tx_ring) { 1151 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1152 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 1153 mdp->tx_desc_dma); 1154 mdp->tx_ring = NULL; 1155 } 1156} 1157 1158static int sh_eth_dev_init(struct net_device *ndev, bool start) 1159{ 1160 int ret = 0; 1161 struct sh_eth_private *mdp = netdev_priv(ndev); 1162 u32 val; 1163 1164 /* Soft Reset */ 1165 ret = sh_eth_reset(ndev); 1166 if (ret) 1167 goto out; 1168 1169 if (mdp->cd->rmiimode) 1170 sh_eth_write(ndev, 0x1, RMIIMODE); 1171 1172 /* Descriptor format */ 1173 sh_eth_ring_format(ndev); 1174 if (mdp->cd->rpadir) 1175 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1176 1177 /* all sh_eth int mask */ 1178 sh_eth_write(ndev, 0, EESIPR); 1179 1180#if defined(__LITTLE_ENDIAN) 1181 if (mdp->cd->hw_swap) 1182 sh_eth_write(ndev, EDMR_EL, EDMR); 1183 else 1184#endif 1185 sh_eth_write(ndev, 0, EDMR); 1186 1187 /* FIFO size set */ 1188 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1189 sh_eth_write(ndev, 0, TFTR); 1190 1191 /* Frame recv control */ 1192 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR); 1193 1194 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER); 1195 1196 if (mdp->cd->bculr) 1197 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1198 1199 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1200 1201 if (!mdp->cd->no_trimd) 1202 sh_eth_write(ndev, 0, TRIMD); 1203 1204 /* Recv frame limit set register */ 1205 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1206 RFLR); 1207 1208 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 1209 if (start) 1210 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1211 1212 /* PAUSE Prohibition */ 1213 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | 1214 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 1215 1216 sh_eth_write(ndev, val, ECMR); 1217 1218 if (mdp->cd->set_rate) 1219 mdp->cd->set_rate(ndev); 1220 1221 /* E-MAC Status Register clear */ 1222 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1223 1224 /* E-MAC Interrupt Enable register */ 1225 if (start) 1226 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1227 1228 /* Set MAC address */ 1229 update_mac_address(ndev); 1230 1231 /* mask reset */ 1232 if (mdp->cd->apr) 1233 sh_eth_write(ndev, APR_AP, APR); 1234 if (mdp->cd->mpr) 1235 sh_eth_write(ndev, MPR_MP, MPR); 1236 if (mdp->cd->tpauser) 1237 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1238 1239 if (start) { 1240 /* Setting the Rx mode will start the Rx process. */ 1241 sh_eth_write(ndev, EDRRR_R, EDRRR); 1242 1243 netif_start_queue(ndev); 1244 } 1245 1246out: 1247 return ret; 1248} 1249 1250/* free Tx skb function */ 1251static int sh_eth_txfree(struct net_device *ndev) 1252{ 1253 struct sh_eth_private *mdp = netdev_priv(ndev); 1254 struct sh_eth_txdesc *txdesc; 1255 int freeNum = 0; 1256 int entry = 0; 1257 1258 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1259 entry = mdp->dirty_tx % mdp->num_tx_ring; 1260 txdesc = &mdp->tx_ring[entry]; 1261 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 1262 break; 1263 /* Free the original skb. */ 1264 if (mdp->tx_skbuff[entry]) { 1265 dma_unmap_single(&ndev->dev, txdesc->addr, 1266 txdesc->buffer_length, DMA_TO_DEVICE); 1267 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1268 mdp->tx_skbuff[entry] = NULL; 1269 freeNum++; 1270 } 1271 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1272 if (entry >= mdp->num_tx_ring - 1) 1273 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1274 1275 ndev->stats.tx_packets++; 1276 ndev->stats.tx_bytes += txdesc->buffer_length; 1277 } 1278 return freeNum; 1279} 1280 1281/* Packet receive function */ 1282static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1283{ 1284 struct sh_eth_private *mdp = netdev_priv(ndev); 1285 struct sh_eth_rxdesc *rxdesc; 1286 1287 int entry = mdp->cur_rx % mdp->num_rx_ring; 1288 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1289 struct sk_buff *skb; 1290 int exceeded = 0; 1291 u16 pkt_len = 0; 1292 u32 desc_status; 1293 1294 rxdesc = &mdp->rx_ring[entry]; 1295 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1296 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1297 pkt_len = rxdesc->frame_length; 1298 1299 if (--boguscnt < 0) 1300 break; 1301 1302 if (*quota <= 0) { 1303 exceeded = 1; 1304 break; 1305 } 1306 (*quota)--; 1307 1308 if (!(desc_status & RDFEND)) 1309 ndev->stats.rx_length_errors++; 1310 1311 /* 1312 * In case of almost all GETHER/ETHERs, the Receive Frame State 1313 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1314 * bit 0. However, in case of the R8A7740's GETHER, the RFS 1315 * bits are from bit 25 to bit 16. So, the driver needs right 1316 * shifting by 16. 1317 */ 1318 if (mdp->cd->shift_rd0) 1319 desc_status >>= 16; 1320 1321 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1322 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1323 ndev->stats.rx_errors++; 1324 if (desc_status & RD_RFS1) 1325 ndev->stats.rx_crc_errors++; 1326 if (desc_status & RD_RFS2) 1327 ndev->stats.rx_frame_errors++; 1328 if (desc_status & RD_RFS3) 1329 ndev->stats.rx_length_errors++; 1330 if (desc_status & RD_RFS4) 1331 ndev->stats.rx_length_errors++; 1332 if (desc_status & RD_RFS6) 1333 ndev->stats.rx_missed_errors++; 1334 if (desc_status & RD_RFS10) 1335 ndev->stats.rx_over_errors++; 1336 } else { 1337 if (!mdp->cd->hw_swap) 1338 sh_eth_soft_swap( 1339 phys_to_virt(ALIGN(rxdesc->addr, 4)), 1340 pkt_len + 2); 1341 skb = mdp->rx_skbuff[entry]; 1342 mdp->rx_skbuff[entry] = NULL; 1343 if (mdp->cd->rpadir) 1344 skb_reserve(skb, NET_IP_ALIGN); 1345 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr, 1346 mdp->rx_buf_sz, 1347 DMA_FROM_DEVICE); 1348 skb_put(skb, pkt_len); 1349 skb->protocol = eth_type_trans(skb, ndev); 1350 netif_rx(skb); 1351 ndev->stats.rx_packets++; 1352 ndev->stats.rx_bytes += pkt_len; 1353 } 1354 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); 1355 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1356 rxdesc = &mdp->rx_ring[entry]; 1357 } 1358 1359 /* Refill the Rx ring buffers. */ 1360 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1361 entry = mdp->dirty_rx % mdp->num_rx_ring; 1362 rxdesc = &mdp->rx_ring[entry]; 1363 /* The size of the buffer is 16 byte boundary. */ 1364 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1365 1366 if (mdp->rx_skbuff[entry] == NULL) { 1367 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1368 mdp->rx_skbuff[entry] = skb; 1369 if (skb == NULL) 1370 break; /* Better luck next round. */ 1371 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1372 DMA_FROM_DEVICE); 1373 sh_eth_set_receive_align(skb); 1374 1375 skb_checksum_none_assert(skb); 1376 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1377 } 1378 if (entry >= mdp->num_rx_ring - 1) 1379 rxdesc->status |= 1380 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1381 else 1382 rxdesc->status |= 1383 cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1384 } 1385 1386 /* Restart Rx engine if stopped. */ 1387 /* If we don't need to check status, don't. -KDU */ 1388 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1389 /* fix the values for the next receiving if RDE is set */ 1390 if (intr_status & EESR_RDE) 1391 mdp->cur_rx = mdp->dirty_rx = 1392 (sh_eth_read(ndev, RDFAR) - 1393 sh_eth_read(ndev, RDLAR)) >> 4; 1394 sh_eth_write(ndev, EDRRR_R, EDRRR); 1395 } 1396 1397 return exceeded; 1398} 1399 1400static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1401{ 1402 /* disable tx and rx */ 1403 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1404 ~(ECMR_RE | ECMR_TE), ECMR); 1405} 1406 1407static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1408{ 1409 /* enable tx and rx */ 1410 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1411 (ECMR_RE | ECMR_TE), ECMR); 1412} 1413 1414/* error control function */ 1415static void sh_eth_error(struct net_device *ndev, int intr_status) 1416{ 1417 struct sh_eth_private *mdp = netdev_priv(ndev); 1418 u32 felic_stat; 1419 u32 link_stat; 1420 u32 mask; 1421 1422 if (intr_status & EESR_ECI) { 1423 felic_stat = sh_eth_read(ndev, ECSR); 1424 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1425 if (felic_stat & ECSR_ICD) 1426 ndev->stats.tx_carrier_errors++; 1427 if (felic_stat & ECSR_LCHNG) { 1428 /* Link Changed */ 1429 if (mdp->cd->no_psr || mdp->no_ether_link) { 1430 goto ignore_link; 1431 } else { 1432 link_stat = (sh_eth_read(ndev, PSR)); 1433 if (mdp->ether_link_active_low) 1434 link_stat = ~link_stat; 1435 } 1436 if (!(link_stat & PHY_ST_LINK)) 1437 sh_eth_rcv_snd_disable(ndev); 1438 else { 1439 /* Link Up */ 1440 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1441 ~DMAC_M_ECI, EESIPR); 1442 /*clear int */ 1443 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1444 ECSR); 1445 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1446 DMAC_M_ECI, EESIPR); 1447 /* enable tx and rx */ 1448 sh_eth_rcv_snd_enable(ndev); 1449 } 1450 } 1451 } 1452 1453ignore_link: 1454 if (intr_status & EESR_TWB) { 1455 /* Unused write back interrupt */ 1456 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1457 ndev->stats.tx_aborted_errors++; 1458 if (netif_msg_tx_err(mdp)) 1459 dev_err(&ndev->dev, "Transmit Abort\n"); 1460 } 1461 } 1462 1463 if (intr_status & EESR_RABT) { 1464 /* Receive Abort int */ 1465 if (intr_status & EESR_RFRMER) { 1466 /* Receive Frame Overflow int */ 1467 ndev->stats.rx_frame_errors++; 1468 if (netif_msg_rx_err(mdp)) 1469 dev_err(&ndev->dev, "Receive Abort\n"); 1470 } 1471 } 1472 1473 if (intr_status & EESR_TDE) { 1474 /* Transmit Descriptor Empty int */ 1475 ndev->stats.tx_fifo_errors++; 1476 if (netif_msg_tx_err(mdp)) 1477 dev_err(&ndev->dev, "Transmit Descriptor Empty\n"); 1478 } 1479 1480 if (intr_status & EESR_TFE) { 1481 /* FIFO under flow */ 1482 ndev->stats.tx_fifo_errors++; 1483 if (netif_msg_tx_err(mdp)) 1484 dev_err(&ndev->dev, "Transmit FIFO Under flow\n"); 1485 } 1486 1487 if (intr_status & EESR_RDE) { 1488 /* Receive Descriptor Empty int */ 1489 ndev->stats.rx_over_errors++; 1490 1491 if (netif_msg_rx_err(mdp)) 1492 dev_err(&ndev->dev, "Receive Descriptor Empty\n"); 1493 } 1494 1495 if (intr_status & EESR_RFE) { 1496 /* Receive FIFO Overflow int */ 1497 ndev->stats.rx_fifo_errors++; 1498 if (netif_msg_rx_err(mdp)) 1499 dev_err(&ndev->dev, "Receive FIFO Overflow\n"); 1500 } 1501 1502 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1503 /* Address Error */ 1504 ndev->stats.tx_fifo_errors++; 1505 if (netif_msg_tx_err(mdp)) 1506 dev_err(&ndev->dev, "Address Error\n"); 1507 } 1508 1509 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1510 if (mdp->cd->no_ade) 1511 mask &= ~EESR_ADE; 1512 if (intr_status & mask) { 1513 /* Tx error */ 1514 u32 edtrr = sh_eth_read(ndev, EDTRR); 1515 /* dmesg */ 1516 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ", 1517 intr_status, mdp->cur_tx); 1518 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1519 mdp->dirty_tx, (u32) ndev->state, edtrr); 1520 /* dirty buffer free */ 1521 sh_eth_txfree(ndev); 1522 1523 /* SH7712 BUG */ 1524 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1525 /* tx dma start */ 1526 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1527 } 1528 /* wakeup */ 1529 netif_wake_queue(ndev); 1530 } 1531} 1532 1533static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1534{ 1535 struct net_device *ndev = netdev; 1536 struct sh_eth_private *mdp = netdev_priv(ndev); 1537 struct sh_eth_cpu_data *cd = mdp->cd; 1538 irqreturn_t ret = IRQ_NONE; 1539 unsigned long intr_status, intr_enable; 1540 1541 spin_lock(&mdp->lock); 1542 1543 /* Get interrupt status */ 1544 intr_status = sh_eth_read(ndev, EESR); 1545 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1546 * enabled since it's the one that comes thru regardless of the mask, 1547 * and we need to fully handle it in sh_eth_error() in order to quench 1548 * it as it doesn't get cleared by just writing 1 to the ECI bit... 1549 */ 1550 intr_enable = sh_eth_read(ndev, EESIPR); 1551 intr_status &= intr_enable | DMAC_M_ECI; 1552 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) 1553 ret = IRQ_HANDLED; 1554 else 1555 goto other_irq; 1556 1557 if (intr_status & EESR_RX_CHECK) { 1558 if (napi_schedule_prep(&mdp->napi)) { 1559 /* Mask Rx interrupts */ 1560 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1561 EESIPR); 1562 __napi_schedule(&mdp->napi); 1563 } else { 1564 dev_warn(&ndev->dev, 1565 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n", 1566 intr_status, intr_enable); 1567 } 1568 } 1569 1570 /* Tx Check */ 1571 if (intr_status & cd->tx_check) { 1572 /* Clear Tx interrupts */ 1573 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1574 1575 sh_eth_txfree(ndev); 1576 netif_wake_queue(ndev); 1577 } 1578 1579 if (intr_status & cd->eesr_err_check) { 1580 /* Clear error interrupts */ 1581 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1582 1583 sh_eth_error(ndev, intr_status); 1584 } 1585 1586other_irq: 1587 spin_unlock(&mdp->lock); 1588 1589 return ret; 1590} 1591 1592static int sh_eth_poll(struct napi_struct *napi, int budget) 1593{ 1594 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1595 napi); 1596 struct net_device *ndev = napi->dev; 1597 int quota = budget; 1598 unsigned long intr_status; 1599 1600 for (;;) { 1601 intr_status = sh_eth_read(ndev, EESR); 1602 if (!(intr_status & EESR_RX_CHECK)) 1603 break; 1604 /* Clear Rx interrupts */ 1605 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1606 1607 if (sh_eth_rx(ndev, intr_status, "a)) 1608 goto out; 1609 } 1610 1611 napi_complete(napi); 1612 1613 /* Reenable Rx interrupts */ 1614 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1615out: 1616 return budget - quota; 1617} 1618 1619/* PHY state control function */ 1620static void sh_eth_adjust_link(struct net_device *ndev) 1621{ 1622 struct sh_eth_private *mdp = netdev_priv(ndev); 1623 struct phy_device *phydev = mdp->phydev; 1624 int new_state = 0; 1625 1626 if (phydev->link) { 1627 if (phydev->duplex != mdp->duplex) { 1628 new_state = 1; 1629 mdp->duplex = phydev->duplex; 1630 if (mdp->cd->set_duplex) 1631 mdp->cd->set_duplex(ndev); 1632 } 1633 1634 if (phydev->speed != mdp->speed) { 1635 new_state = 1; 1636 mdp->speed = phydev->speed; 1637 if (mdp->cd->set_rate) 1638 mdp->cd->set_rate(ndev); 1639 } 1640 if (!mdp->link) { 1641 sh_eth_write(ndev, 1642 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR); 1643 new_state = 1; 1644 mdp->link = phydev->link; 1645 if (mdp->cd->no_psr || mdp->no_ether_link) 1646 sh_eth_rcv_snd_enable(ndev); 1647 } 1648 } else if (mdp->link) { 1649 new_state = 1; 1650 mdp->link = 0; 1651 mdp->speed = 0; 1652 mdp->duplex = -1; 1653 if (mdp->cd->no_psr || mdp->no_ether_link) 1654 sh_eth_rcv_snd_disable(ndev); 1655 } 1656 1657 if (new_state && netif_msg_link(mdp)) 1658 phy_print_status(phydev); 1659} 1660 1661/* PHY init function */ 1662static int sh_eth_phy_init(struct net_device *ndev) 1663{ 1664 struct sh_eth_private *mdp = netdev_priv(ndev); 1665 char phy_id[MII_BUS_ID_SIZE + 3]; 1666 struct phy_device *phydev = NULL; 1667 1668 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1669 mdp->mii_bus->id , mdp->phy_id); 1670 1671 mdp->link = 0; 1672 mdp->speed = 0; 1673 mdp->duplex = -1; 1674 1675 /* Try connect to PHY */ 1676 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1677 mdp->phy_interface); 1678 if (IS_ERR(phydev)) { 1679 dev_err(&ndev->dev, "phy_connect failed\n"); 1680 return PTR_ERR(phydev); 1681 } 1682 1683 dev_info(&ndev->dev, "attached phy %i to driver %s\n", 1684 phydev->addr, phydev->drv->name); 1685 1686 mdp->phydev = phydev; 1687 1688 return 0; 1689} 1690 1691/* PHY control start function */ 1692static int sh_eth_phy_start(struct net_device *ndev) 1693{ 1694 struct sh_eth_private *mdp = netdev_priv(ndev); 1695 int ret; 1696 1697 ret = sh_eth_phy_init(ndev); 1698 if (ret) 1699 return ret; 1700 1701 /* reset phy - this also wakes it from PDOWN */ 1702 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET); 1703 phy_start(mdp->phydev); 1704 1705 return 0; 1706} 1707 1708static int sh_eth_get_settings(struct net_device *ndev, 1709 struct ethtool_cmd *ecmd) 1710{ 1711 struct sh_eth_private *mdp = netdev_priv(ndev); 1712 unsigned long flags; 1713 int ret; 1714 1715 spin_lock_irqsave(&mdp->lock, flags); 1716 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1717 spin_unlock_irqrestore(&mdp->lock, flags); 1718 1719 return ret; 1720} 1721 1722static int sh_eth_set_settings(struct net_device *ndev, 1723 struct ethtool_cmd *ecmd) 1724{ 1725 struct sh_eth_private *mdp = netdev_priv(ndev); 1726 unsigned long flags; 1727 int ret; 1728 1729 spin_lock_irqsave(&mdp->lock, flags); 1730 1731 /* disable tx and rx */ 1732 sh_eth_rcv_snd_disable(ndev); 1733 1734 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1735 if (ret) 1736 goto error_exit; 1737 1738 if (ecmd->duplex == DUPLEX_FULL) 1739 mdp->duplex = 1; 1740 else 1741 mdp->duplex = 0; 1742 1743 if (mdp->cd->set_duplex) 1744 mdp->cd->set_duplex(ndev); 1745 1746error_exit: 1747 mdelay(1); 1748 1749 /* enable tx and rx */ 1750 sh_eth_rcv_snd_enable(ndev); 1751 1752 spin_unlock_irqrestore(&mdp->lock, flags); 1753 1754 return ret; 1755} 1756 1757static int sh_eth_nway_reset(struct net_device *ndev) 1758{ 1759 struct sh_eth_private *mdp = netdev_priv(ndev); 1760 unsigned long flags; 1761 int ret; 1762 1763 spin_lock_irqsave(&mdp->lock, flags); 1764 ret = phy_start_aneg(mdp->phydev); 1765 spin_unlock_irqrestore(&mdp->lock, flags); 1766 1767 return ret; 1768} 1769 1770static u32 sh_eth_get_msglevel(struct net_device *ndev) 1771{ 1772 struct sh_eth_private *mdp = netdev_priv(ndev); 1773 return mdp->msg_enable; 1774} 1775 1776static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 1777{ 1778 struct sh_eth_private *mdp = netdev_priv(ndev); 1779 mdp->msg_enable = value; 1780} 1781 1782static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 1783 "rx_current", "tx_current", 1784 "rx_dirty", "tx_dirty", 1785}; 1786#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 1787 1788static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 1789{ 1790 switch (sset) { 1791 case ETH_SS_STATS: 1792 return SH_ETH_STATS_LEN; 1793 default: 1794 return -EOPNOTSUPP; 1795 } 1796} 1797 1798static void sh_eth_get_ethtool_stats(struct net_device *ndev, 1799 struct ethtool_stats *stats, u64 *data) 1800{ 1801 struct sh_eth_private *mdp = netdev_priv(ndev); 1802 int i = 0; 1803 1804 /* device-specific stats */ 1805 data[i++] = mdp->cur_rx; 1806 data[i++] = mdp->cur_tx; 1807 data[i++] = mdp->dirty_rx; 1808 data[i++] = mdp->dirty_tx; 1809} 1810 1811static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1812{ 1813 switch (stringset) { 1814 case ETH_SS_STATS: 1815 memcpy(data, *sh_eth_gstrings_stats, 1816 sizeof(sh_eth_gstrings_stats)); 1817 break; 1818 } 1819} 1820 1821static void sh_eth_get_ringparam(struct net_device *ndev, 1822 struct ethtool_ringparam *ring) 1823{ 1824 struct sh_eth_private *mdp = netdev_priv(ndev); 1825 1826 ring->rx_max_pending = RX_RING_MAX; 1827 ring->tx_max_pending = TX_RING_MAX; 1828 ring->rx_pending = mdp->num_rx_ring; 1829 ring->tx_pending = mdp->num_tx_ring; 1830} 1831 1832static int sh_eth_set_ringparam(struct net_device *ndev, 1833 struct ethtool_ringparam *ring) 1834{ 1835 struct sh_eth_private *mdp = netdev_priv(ndev); 1836 int ret; 1837 1838 if (ring->tx_pending > TX_RING_MAX || 1839 ring->rx_pending > RX_RING_MAX || 1840 ring->tx_pending < TX_RING_MIN || 1841 ring->rx_pending < RX_RING_MIN) 1842 return -EINVAL; 1843 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1844 return -EINVAL; 1845 1846 if (netif_running(ndev)) { 1847 netif_tx_disable(ndev); 1848 /* Disable interrupts by clearing the interrupt mask. */ 1849 sh_eth_write(ndev, 0x0000, EESIPR); 1850 /* Stop the chip's Tx and Rx processes. */ 1851 sh_eth_write(ndev, 0, EDTRR); 1852 sh_eth_write(ndev, 0, EDRRR); 1853 synchronize_irq(ndev->irq); 1854 } 1855 1856 /* Free all the skbuffs in the Rx queue. */ 1857 sh_eth_ring_free(ndev); 1858 /* Free DMA buffer */ 1859 sh_eth_free_dma_buffer(mdp); 1860 1861 /* Set new parameters */ 1862 mdp->num_rx_ring = ring->rx_pending; 1863 mdp->num_tx_ring = ring->tx_pending; 1864 1865 ret = sh_eth_ring_init(ndev); 1866 if (ret < 0) { 1867 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__); 1868 return ret; 1869 } 1870 ret = sh_eth_dev_init(ndev, false); 1871 if (ret < 0) { 1872 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__); 1873 return ret; 1874 } 1875 1876 if (netif_running(ndev)) { 1877 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1878 /* Setting the Rx mode will start the Rx process. */ 1879 sh_eth_write(ndev, EDRRR_R, EDRRR); 1880 netif_wake_queue(ndev); 1881 } 1882 1883 return 0; 1884} 1885 1886static const struct ethtool_ops sh_eth_ethtool_ops = { 1887 .get_settings = sh_eth_get_settings, 1888 .set_settings = sh_eth_set_settings, 1889 .nway_reset = sh_eth_nway_reset, 1890 .get_msglevel = sh_eth_get_msglevel, 1891 .set_msglevel = sh_eth_set_msglevel, 1892 .get_link = ethtool_op_get_link, 1893 .get_strings = sh_eth_get_strings, 1894 .get_ethtool_stats = sh_eth_get_ethtool_stats, 1895 .get_sset_count = sh_eth_get_sset_count, 1896 .get_ringparam = sh_eth_get_ringparam, 1897 .set_ringparam = sh_eth_set_ringparam, 1898}; 1899 1900/* network device open function */ 1901static int sh_eth_open(struct net_device *ndev) 1902{ 1903 int ret = 0; 1904 struct sh_eth_private *mdp = netdev_priv(ndev); 1905 1906 pm_runtime_get_sync(&mdp->pdev->dev); 1907 1908 ret = request_irq(ndev->irq, sh_eth_interrupt, 1909 mdp->cd->irq_flags, ndev->name, ndev); 1910 if (ret) { 1911 dev_err(&ndev->dev, "Can not assign IRQ number\n"); 1912 return ret; 1913 } 1914 1915 /* Descriptor set */ 1916 ret = sh_eth_ring_init(ndev); 1917 if (ret) 1918 goto out_free_irq; 1919 1920 /* device init */ 1921 ret = sh_eth_dev_init(ndev, true); 1922 if (ret) 1923 goto out_free_irq; 1924 1925 /* PHY control start*/ 1926 ret = sh_eth_phy_start(ndev); 1927 if (ret) 1928 goto out_free_irq; 1929 1930 napi_enable(&mdp->napi); 1931 1932 return ret; 1933 1934out_free_irq: 1935 free_irq(ndev->irq, ndev); 1936 pm_runtime_put_sync(&mdp->pdev->dev); 1937 return ret; 1938} 1939 1940/* Timeout function */ 1941static void sh_eth_tx_timeout(struct net_device *ndev) 1942{ 1943 struct sh_eth_private *mdp = netdev_priv(ndev); 1944 struct sh_eth_rxdesc *rxdesc; 1945 int i; 1946 1947 netif_stop_queue(ndev); 1948 1949 if (netif_msg_timer(mdp)) 1950 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x," 1951 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR)); 1952 1953 /* tx_errors count up */ 1954 ndev->stats.tx_errors++; 1955 1956 /* Free all the skbuffs in the Rx queue. */ 1957 for (i = 0; i < mdp->num_rx_ring; i++) { 1958 rxdesc = &mdp->rx_ring[i]; 1959 rxdesc->status = 0; 1960 rxdesc->addr = 0xBADF00D0; 1961 if (mdp->rx_skbuff[i]) 1962 dev_kfree_skb(mdp->rx_skbuff[i]); 1963 mdp->rx_skbuff[i] = NULL; 1964 } 1965 for (i = 0; i < mdp->num_tx_ring; i++) { 1966 if (mdp->tx_skbuff[i]) 1967 dev_kfree_skb(mdp->tx_skbuff[i]); 1968 mdp->tx_skbuff[i] = NULL; 1969 } 1970 1971 /* device init */ 1972 sh_eth_dev_init(ndev, true); 1973} 1974 1975/* Packet transmit function */ 1976static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1977{ 1978 struct sh_eth_private *mdp = netdev_priv(ndev); 1979 struct sh_eth_txdesc *txdesc; 1980 u32 entry; 1981 unsigned long flags; 1982 1983 spin_lock_irqsave(&mdp->lock, flags); 1984 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 1985 if (!sh_eth_txfree(ndev)) { 1986 if (netif_msg_tx_queued(mdp)) 1987 dev_warn(&ndev->dev, "TxFD exhausted.\n"); 1988 netif_stop_queue(ndev); 1989 spin_unlock_irqrestore(&mdp->lock, flags); 1990 return NETDEV_TX_BUSY; 1991 } 1992 } 1993 spin_unlock_irqrestore(&mdp->lock, flags); 1994 1995 entry = mdp->cur_tx % mdp->num_tx_ring; 1996 mdp->tx_skbuff[entry] = skb; 1997 txdesc = &mdp->tx_ring[entry]; 1998 /* soft swap. */ 1999 if (!mdp->cd->hw_swap) 2000 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), 2001 skb->len + 2); 2002 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, 2003 DMA_TO_DEVICE); 2004 if (skb->len < ETHERSMALL) 2005 txdesc->buffer_length = ETHERSMALL; 2006 else 2007 txdesc->buffer_length = skb->len; 2008 2009 if (entry >= mdp->num_tx_ring - 1) 2010 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 2011 else 2012 txdesc->status |= cpu_to_edmac(mdp, TD_TACT); 2013 2014 mdp->cur_tx++; 2015 2016 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 2017 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 2018 2019 return NETDEV_TX_OK; 2020} 2021 2022/* device close function */ 2023static int sh_eth_close(struct net_device *ndev) 2024{ 2025 struct sh_eth_private *mdp = netdev_priv(ndev); 2026 2027 napi_disable(&mdp->napi); 2028 2029 netif_stop_queue(ndev); 2030 2031 /* Disable interrupts by clearing the interrupt mask. */ 2032 sh_eth_write(ndev, 0x0000, EESIPR); 2033 2034 /* Stop the chip's Tx and Rx processes. */ 2035 sh_eth_write(ndev, 0, EDTRR); 2036 sh_eth_write(ndev, 0, EDRRR); 2037 2038 /* PHY Disconnect */ 2039 if (mdp->phydev) { 2040 phy_stop(mdp->phydev); 2041 phy_disconnect(mdp->phydev); 2042 } 2043 2044 free_irq(ndev->irq, ndev); 2045 2046 /* Free all the skbuffs in the Rx queue. */ 2047 sh_eth_ring_free(ndev); 2048 2049 /* free DMA buffer */ 2050 sh_eth_free_dma_buffer(mdp); 2051 2052 pm_runtime_put_sync(&mdp->pdev->dev); 2053 2054 return 0; 2055} 2056 2057static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2058{ 2059 struct sh_eth_private *mdp = netdev_priv(ndev); 2060 2061 pm_runtime_get_sync(&mdp->pdev->dev); 2062 2063 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR); 2064 sh_eth_write(ndev, 0, TROCR); /* (write clear) */ 2065 ndev->stats.collisions += sh_eth_read(ndev, CDCR); 2066 sh_eth_write(ndev, 0, CDCR); /* (write clear) */ 2067 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); 2068 sh_eth_write(ndev, 0, LCCR); /* (write clear) */ 2069 if (sh_eth_is_gether(mdp)) { 2070 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR); 2071 sh_eth_write(ndev, 0, CERCR); /* (write clear) */ 2072 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR); 2073 sh_eth_write(ndev, 0, CEECR); /* (write clear) */ 2074 } else { 2075 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); 2076 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ 2077 } 2078 pm_runtime_put_sync(&mdp->pdev->dev); 2079 2080 return &ndev->stats; 2081} 2082 2083/* ioctl to device function */ 2084static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, 2085 int cmd) 2086{ 2087 struct sh_eth_private *mdp = netdev_priv(ndev); 2088 struct phy_device *phydev = mdp->phydev; 2089 2090 if (!netif_running(ndev)) 2091 return -EINVAL; 2092 2093 if (!phydev) 2094 return -ENODEV; 2095 2096 return phy_mii_ioctl(phydev, rq, cmd); 2097} 2098 2099/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2100static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2101 int entry) 2102{ 2103 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2104} 2105 2106static u32 sh_eth_tsu_get_post_mask(int entry) 2107{ 2108 return 0x0f << (28 - ((entry % 8) * 4)); 2109} 2110 2111static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2112{ 2113 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2114} 2115 2116static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2117 int entry) 2118{ 2119 struct sh_eth_private *mdp = netdev_priv(ndev); 2120 u32 tmp; 2121 void *reg_offset; 2122 2123 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2124 tmp = ioread32(reg_offset); 2125 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2126} 2127 2128static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2129 int entry) 2130{ 2131 struct sh_eth_private *mdp = netdev_priv(ndev); 2132 u32 post_mask, ref_mask, tmp; 2133 void *reg_offset; 2134 2135 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2136 post_mask = sh_eth_tsu_get_post_mask(entry); 2137 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2138 2139 tmp = ioread32(reg_offset); 2140 iowrite32(tmp & ~post_mask, reg_offset); 2141 2142 /* If other port enables, the function returns "true" */ 2143 return tmp & ref_mask; 2144} 2145 2146static int sh_eth_tsu_busy(struct net_device *ndev) 2147{ 2148 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2149 struct sh_eth_private *mdp = netdev_priv(ndev); 2150 2151 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2152 udelay(10); 2153 timeout--; 2154 if (timeout <= 0) { 2155 dev_err(&ndev->dev, "%s: timeout\n", __func__); 2156 return -ETIMEDOUT; 2157 } 2158 } 2159 2160 return 0; 2161} 2162 2163static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2164 const u8 *addr) 2165{ 2166 u32 val; 2167 2168 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2169 iowrite32(val, reg); 2170 if (sh_eth_tsu_busy(ndev) < 0) 2171 return -EBUSY; 2172 2173 val = addr[4] << 8 | addr[5]; 2174 iowrite32(val, reg + 4); 2175 if (sh_eth_tsu_busy(ndev) < 0) 2176 return -EBUSY; 2177 2178 return 0; 2179} 2180 2181static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2182{ 2183 u32 val; 2184 2185 val = ioread32(reg); 2186 addr[0] = (val >> 24) & 0xff; 2187 addr[1] = (val >> 16) & 0xff; 2188 addr[2] = (val >> 8) & 0xff; 2189 addr[3] = val & 0xff; 2190 val = ioread32(reg + 4); 2191 addr[4] = (val >> 8) & 0xff; 2192 addr[5] = val & 0xff; 2193} 2194 2195 2196static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2197{ 2198 struct sh_eth_private *mdp = netdev_priv(ndev); 2199 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2200 int i; 2201 u8 c_addr[ETH_ALEN]; 2202 2203 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2204 sh_eth_tsu_read_entry(reg_offset, c_addr); 2205 if (memcmp(addr, c_addr, ETH_ALEN) == 0) 2206 return i; 2207 } 2208 2209 return -ENOENT; 2210} 2211 2212static int sh_eth_tsu_find_empty(struct net_device *ndev) 2213{ 2214 u8 blank[ETH_ALEN]; 2215 int entry; 2216 2217 memset(blank, 0, sizeof(blank)); 2218 entry = sh_eth_tsu_find_entry(ndev, blank); 2219 return (entry < 0) ? -ENOMEM : entry; 2220} 2221 2222static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2223 int entry) 2224{ 2225 struct sh_eth_private *mdp = netdev_priv(ndev); 2226 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2227 int ret; 2228 u8 blank[ETH_ALEN]; 2229 2230 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2231 ~(1 << (31 - entry)), TSU_TEN); 2232 2233 memset(blank, 0, sizeof(blank)); 2234 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2235 if (ret < 0) 2236 return ret; 2237 return 0; 2238} 2239 2240static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2241{ 2242 struct sh_eth_private *mdp = netdev_priv(ndev); 2243 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2244 int i, ret; 2245 2246 if (!mdp->cd->tsu) 2247 return 0; 2248 2249 i = sh_eth_tsu_find_entry(ndev, addr); 2250 if (i < 0) { 2251 /* No entry found, create one */ 2252 i = sh_eth_tsu_find_empty(ndev); 2253 if (i < 0) 2254 return -ENOMEM; 2255 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2256 if (ret < 0) 2257 return ret; 2258 2259 /* Enable the entry */ 2260 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2261 (1 << (31 - i)), TSU_TEN); 2262 } 2263 2264 /* Entry found or created, enable POST */ 2265 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2266 2267 return 0; 2268} 2269 2270static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2271{ 2272 struct sh_eth_private *mdp = netdev_priv(ndev); 2273 int i, ret; 2274 2275 if (!mdp->cd->tsu) 2276 return 0; 2277 2278 i = sh_eth_tsu_find_entry(ndev, addr); 2279 if (i) { 2280 /* Entry found */ 2281 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2282 goto done; 2283 2284 /* Disable the entry if both ports was disabled */ 2285 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2286 if (ret < 0) 2287 return ret; 2288 } 2289done: 2290 return 0; 2291} 2292 2293static int sh_eth_tsu_purge_all(struct net_device *ndev) 2294{ 2295 struct sh_eth_private *mdp = netdev_priv(ndev); 2296 int i, ret; 2297 2298 if (unlikely(!mdp->cd->tsu)) 2299 return 0; 2300 2301 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2302 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2303 continue; 2304 2305 /* Disable the entry if both ports was disabled */ 2306 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2307 if (ret < 0) 2308 return ret; 2309 } 2310 2311 return 0; 2312} 2313 2314static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2315{ 2316 struct sh_eth_private *mdp = netdev_priv(ndev); 2317 u8 addr[ETH_ALEN]; 2318 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2319 int i; 2320 2321 if (unlikely(!mdp->cd->tsu)) 2322 return; 2323 2324 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2325 sh_eth_tsu_read_entry(reg_offset, addr); 2326 if (is_multicast_ether_addr(addr)) 2327 sh_eth_tsu_del_entry(ndev, addr); 2328 } 2329} 2330 2331/* Multicast reception directions set */ 2332static void sh_eth_set_multicast_list(struct net_device *ndev) 2333{ 2334 struct sh_eth_private *mdp = netdev_priv(ndev); 2335 u32 ecmr_bits; 2336 int mcast_all = 0; 2337 unsigned long flags; 2338 2339 spin_lock_irqsave(&mdp->lock, flags); 2340 /* 2341 * Initial condition is MCT = 1, PRM = 0. 2342 * Depending on ndev->flags, set PRM or clear MCT 2343 */ 2344 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT; 2345 2346 if (!(ndev->flags & IFF_MULTICAST)) { 2347 sh_eth_tsu_purge_mcast(ndev); 2348 mcast_all = 1; 2349 } 2350 if (ndev->flags & IFF_ALLMULTI) { 2351 sh_eth_tsu_purge_mcast(ndev); 2352 ecmr_bits &= ~ECMR_MCT; 2353 mcast_all = 1; 2354 } 2355 2356 if (ndev->flags & IFF_PROMISC) { 2357 sh_eth_tsu_purge_all(ndev); 2358 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2359 } else if (mdp->cd->tsu) { 2360 struct netdev_hw_addr *ha; 2361 netdev_for_each_mc_addr(ha, ndev) { 2362 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2363 continue; 2364 2365 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2366 if (!mcast_all) { 2367 sh_eth_tsu_purge_mcast(ndev); 2368 ecmr_bits &= ~ECMR_MCT; 2369 mcast_all = 1; 2370 } 2371 } 2372 } 2373 } else { 2374 /* Normal, unicast/broadcast-only mode. */ 2375 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT; 2376 } 2377 2378 /* update the ethernet mode */ 2379 sh_eth_write(ndev, ecmr_bits, ECMR); 2380 2381 spin_unlock_irqrestore(&mdp->lock, flags); 2382} 2383 2384static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2385{ 2386 if (!mdp->port) 2387 return TSU_VTAG0; 2388 else 2389 return TSU_VTAG1; 2390} 2391 2392static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2393 __be16 proto, u16 vid) 2394{ 2395 struct sh_eth_private *mdp = netdev_priv(ndev); 2396 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2397 2398 if (unlikely(!mdp->cd->tsu)) 2399 return -EPERM; 2400 2401 /* No filtering if vid = 0 */ 2402 if (!vid) 2403 return 0; 2404 2405 mdp->vlan_num_ids++; 2406 2407 /* 2408 * The controller has one VLAN tag HW filter. So, if the filter is 2409 * already enabled, the driver disables it and the filte 2410 */ 2411 if (mdp->vlan_num_ids > 1) { 2412 /* disable VLAN filter */ 2413 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2414 return 0; 2415 } 2416 2417 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2418 vtag_reg_index); 2419 2420 return 0; 2421} 2422 2423static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2424 __be16 proto, u16 vid) 2425{ 2426 struct sh_eth_private *mdp = netdev_priv(ndev); 2427 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2428 2429 if (unlikely(!mdp->cd->tsu)) 2430 return -EPERM; 2431 2432 /* No filtering if vid = 0 */ 2433 if (!vid) 2434 return 0; 2435 2436 mdp->vlan_num_ids--; 2437 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2438 2439 return 0; 2440} 2441 2442/* SuperH's TSU register init function */ 2443static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2444{ 2445 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2446 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2447 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2448 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2449 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2450 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2451 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2452 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2453 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2454 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2455 if (sh_eth_is_gether(mdp)) { 2456 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2457 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2458 } else { 2459 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2460 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2461 } 2462 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2463 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2464 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2465 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2466 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2467 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2468 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2469} 2470 2471/* MDIO bus release function */ 2472static int sh_mdio_release(struct net_device *ndev) 2473{ 2474 struct mii_bus *bus = dev_get_drvdata(&ndev->dev); 2475 2476 /* unregister mdio bus */ 2477 mdiobus_unregister(bus); 2478 2479 /* remove mdio bus info from net_device */ 2480 dev_set_drvdata(&ndev->dev, NULL); 2481 2482 /* free bitbang info */ 2483 free_mdio_bitbang(bus); 2484 2485 return 0; 2486} 2487 2488/* MDIO bus init function */ 2489static int sh_mdio_init(struct net_device *ndev, int id, 2490 struct sh_eth_plat_data *pd) 2491{ 2492 int ret, i; 2493 struct bb_info *bitbang; 2494 struct sh_eth_private *mdp = netdev_priv(ndev); 2495 2496 /* create bit control struct for PHY */ 2497 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info), 2498 GFP_KERNEL); 2499 if (!bitbang) { 2500 ret = -ENOMEM; 2501 goto out; 2502 } 2503 2504 /* bitbang init */ 2505 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2506 bitbang->set_gate = pd->set_mdio_gate; 2507 bitbang->mdi_msk = PIR_MDI; 2508 bitbang->mdo_msk = PIR_MDO; 2509 bitbang->mmd_msk = PIR_MMD; 2510 bitbang->mdc_msk = PIR_MDC; 2511 bitbang->ctrl.ops = &bb_ops; 2512 2513 /* MII controller setting */ 2514 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2515 if (!mdp->mii_bus) { 2516 ret = -ENOMEM; 2517 goto out; 2518 } 2519 2520 /* Hook up MII support for ethtool */ 2521 mdp->mii_bus->name = "sh_mii"; 2522 mdp->mii_bus->parent = &ndev->dev; 2523 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2524 mdp->pdev->name, id); 2525 2526 /* PHY IRQ */ 2527 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev, 2528 sizeof(int) * PHY_MAX_ADDR, 2529 GFP_KERNEL); 2530 if (!mdp->mii_bus->irq) { 2531 ret = -ENOMEM; 2532 goto out_free_bus; 2533 } 2534 2535 for (i = 0; i < PHY_MAX_ADDR; i++) 2536 mdp->mii_bus->irq[i] = PHY_POLL; 2537 2538 /* register mdio bus */ 2539 ret = mdiobus_register(mdp->mii_bus); 2540 if (ret) 2541 goto out_free_bus; 2542 2543 dev_set_drvdata(&ndev->dev, mdp->mii_bus); 2544 2545 return 0; 2546 2547out_free_bus: 2548 free_mdio_bitbang(mdp->mii_bus); 2549 2550out: 2551 return ret; 2552} 2553 2554static const u16 *sh_eth_get_register_offset(int register_type) 2555{ 2556 const u16 *reg_offset = NULL; 2557 2558 switch (register_type) { 2559 case SH_ETH_REG_GIGABIT: 2560 reg_offset = sh_eth_offset_gigabit; 2561 break; 2562 case SH_ETH_REG_FAST_RCAR: 2563 reg_offset = sh_eth_offset_fast_rcar; 2564 break; 2565 case SH_ETH_REG_FAST_SH4: 2566 reg_offset = sh_eth_offset_fast_sh4; 2567 break; 2568 case SH_ETH_REG_FAST_SH3_SH2: 2569 reg_offset = sh_eth_offset_fast_sh3_sh2; 2570 break; 2571 default: 2572 pr_err("Unknown register type (%d)\n", register_type); 2573 break; 2574 } 2575 2576 return reg_offset; 2577} 2578 2579static const struct net_device_ops sh_eth_netdev_ops = { 2580 .ndo_open = sh_eth_open, 2581 .ndo_stop = sh_eth_close, 2582 .ndo_start_xmit = sh_eth_start_xmit, 2583 .ndo_get_stats = sh_eth_get_stats, 2584 .ndo_tx_timeout = sh_eth_tx_timeout, 2585 .ndo_do_ioctl = sh_eth_do_ioctl, 2586 .ndo_validate_addr = eth_validate_addr, 2587 .ndo_set_mac_address = eth_mac_addr, 2588 .ndo_change_mtu = eth_change_mtu, 2589}; 2590 2591static const struct net_device_ops sh_eth_netdev_ops_tsu = { 2592 .ndo_open = sh_eth_open, 2593 .ndo_stop = sh_eth_close, 2594 .ndo_start_xmit = sh_eth_start_xmit, 2595 .ndo_get_stats = sh_eth_get_stats, 2596 .ndo_set_rx_mode = sh_eth_set_multicast_list, 2597 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 2598 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 2599 .ndo_tx_timeout = sh_eth_tx_timeout, 2600 .ndo_do_ioctl = sh_eth_do_ioctl, 2601 .ndo_validate_addr = eth_validate_addr, 2602 .ndo_set_mac_address = eth_mac_addr, 2603 .ndo_change_mtu = eth_change_mtu, 2604}; 2605 2606static int sh_eth_drv_probe(struct platform_device *pdev) 2607{ 2608 int ret, devno = 0; 2609 struct resource *res; 2610 struct net_device *ndev = NULL; 2611 struct sh_eth_private *mdp = NULL; 2612 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 2613 const struct platform_device_id *id = platform_get_device_id(pdev); 2614 2615 /* get base addr */ 2616 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2617 if (unlikely(res == NULL)) { 2618 dev_err(&pdev->dev, "invalid resource\n"); 2619 ret = -EINVAL; 2620 goto out; 2621 } 2622 2623 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 2624 if (!ndev) { 2625 ret = -ENOMEM; 2626 goto out; 2627 } 2628 2629 /* The sh Ether-specific entries in the device structure. */ 2630 ndev->base_addr = res->start; 2631 devno = pdev->id; 2632 if (devno < 0) 2633 devno = 0; 2634 2635 ndev->dma = -1; 2636 ret = platform_get_irq(pdev, 0); 2637 if (ret < 0) { 2638 ret = -ENODEV; 2639 goto out_release; 2640 } 2641 ndev->irq = ret; 2642 2643 SET_NETDEV_DEV(ndev, &pdev->dev); 2644 2645 mdp = netdev_priv(ndev); 2646 mdp->num_tx_ring = TX_RING_SIZE; 2647 mdp->num_rx_ring = RX_RING_SIZE; 2648 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 2649 if (IS_ERR(mdp->addr)) { 2650 ret = PTR_ERR(mdp->addr); 2651 goto out_release; 2652 } 2653 2654 spin_lock_init(&mdp->lock); 2655 mdp->pdev = pdev; 2656 pm_runtime_enable(&pdev->dev); 2657 pm_runtime_resume(&pdev->dev); 2658 2659 /* get PHY ID */ 2660 mdp->phy_id = pd->phy; 2661 mdp->phy_interface = pd->phy_interface; 2662 /* EDMAC endian */ 2663 mdp->edmac_endian = pd->edmac_endian; 2664 mdp->no_ether_link = pd->no_ether_link; 2665 mdp->ether_link_active_low = pd->ether_link_active_low; 2666 2667 /* set cpu data */ 2668 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 2669 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 2670 sh_eth_set_default_cpu_data(mdp->cd); 2671 2672 /* set function */ 2673 if (mdp->cd->tsu) 2674 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 2675 else 2676 ndev->netdev_ops = &sh_eth_netdev_ops; 2677 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); 2678 ndev->watchdog_timeo = TX_TIMEOUT; 2679 2680 /* debug message level */ 2681 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 2682 2683 /* read and set MAC address */ 2684 read_mac_address(ndev, pd->mac_addr); 2685 if (!is_valid_ether_addr(ndev->dev_addr)) { 2686 dev_warn(&pdev->dev, 2687 "no valid MAC address supplied, using a random one.\n"); 2688 eth_hw_addr_random(ndev); 2689 } 2690 2691 /* ioremap the TSU registers */ 2692 if (mdp->cd->tsu) { 2693 struct resource *rtsu; 2694 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2695 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); 2696 if (IS_ERR(mdp->tsu_addr)) { 2697 ret = PTR_ERR(mdp->tsu_addr); 2698 goto out_release; 2699 } 2700 mdp->port = devno % 2; 2701 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 2702 } 2703 2704 /* initialize first or needed device */ 2705 if (!devno || pd->needs_init) { 2706 if (mdp->cd->chip_reset) 2707 mdp->cd->chip_reset(ndev); 2708 2709 if (mdp->cd->tsu) { 2710 /* TSU init (Init only)*/ 2711 sh_eth_tsu_init(mdp); 2712 } 2713 } 2714 2715 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 2716 2717 /* network device register */ 2718 ret = register_netdev(ndev); 2719 if (ret) 2720 goto out_napi_del; 2721 2722 /* mdio bus init */ 2723 ret = sh_mdio_init(ndev, pdev->id, pd); 2724 if (ret) 2725 goto out_unregister; 2726 2727 /* print device information */ 2728 pr_info("Base address at 0x%x, %pM, IRQ %d.\n", 2729 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2730 2731 platform_set_drvdata(pdev, ndev); 2732 2733 return ret; 2734 2735out_unregister: 2736 unregister_netdev(ndev); 2737 2738out_napi_del: 2739 netif_napi_del(&mdp->napi); 2740 2741out_release: 2742 /* net_dev free */ 2743 if (ndev) 2744 free_netdev(ndev); 2745 2746out: 2747 return ret; 2748} 2749 2750static int sh_eth_drv_remove(struct platform_device *pdev) 2751{ 2752 struct net_device *ndev = platform_get_drvdata(pdev); 2753 struct sh_eth_private *mdp = netdev_priv(ndev); 2754 2755 sh_mdio_release(ndev); 2756 unregister_netdev(ndev); 2757 netif_napi_del(&mdp->napi); 2758 pm_runtime_disable(&pdev->dev); 2759 free_netdev(ndev); 2760 2761 return 0; 2762} 2763 2764#ifdef CONFIG_PM 2765static int sh_eth_runtime_nop(struct device *dev) 2766{ 2767 /* 2768 * Runtime PM callback shared between ->runtime_suspend() 2769 * and ->runtime_resume(). Simply returns success. 2770 * 2771 * This driver re-initializes all registers after 2772 * pm_runtime_get_sync() anyway so there is no need 2773 * to save and restore registers here. 2774 */ 2775 return 0; 2776} 2777 2778static const struct dev_pm_ops sh_eth_dev_pm_ops = { 2779 .runtime_suspend = sh_eth_runtime_nop, 2780 .runtime_resume = sh_eth_runtime_nop, 2781}; 2782#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 2783#else 2784#define SH_ETH_PM_OPS NULL 2785#endif 2786 2787static struct platform_device_id sh_eth_id_table[] = { 2788 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 2789 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 2790 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 2791 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 2792 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 2793 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 2794 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 2795 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, 2796 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data }, 2797 { "r8a7790-ether", (kernel_ulong_t)&r8a7790_data }, 2798 { } 2799}; 2800MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 2801 2802static struct platform_driver sh_eth_driver = { 2803 .probe = sh_eth_drv_probe, 2804 .remove = sh_eth_drv_remove, 2805 .id_table = sh_eth_id_table, 2806 .driver = { 2807 .name = CARDNAME, 2808 .pm = SH_ETH_PM_OPS, 2809 }, 2810}; 2811 2812module_platform_driver(sh_eth_driver); 2813 2814MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 2815MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 2816MODULE_LICENSE("GPL v2"); 2817