sh_eth.c revision 8f728d7934c77f63e89abcc96b46a7a98416d5c1
1/* 2 * SuperH Ethernet device driver 3 * 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 */ 23 24#include <linux/init.h> 25#include <linux/module.h> 26#include <linux/kernel.h> 27#include <linux/spinlock.h> 28#include <linux/interrupt.h> 29#include <linux/dma-mapping.h> 30#include <linux/etherdevice.h> 31#include <linux/delay.h> 32#include <linux/platform_device.h> 33#include <linux/mdio-bitbang.h> 34#include <linux/netdevice.h> 35#include <linux/phy.h> 36#include <linux/cache.h> 37#include <linux/io.h> 38#include <linux/pm_runtime.h> 39#include <linux/slab.h> 40#include <linux/ethtool.h> 41#include <linux/if_vlan.h> 42#include <linux/clk.h> 43#include <linux/sh_eth.h> 44 45#include "sh_eth.h" 46 47#define SH_ETH_DEF_MSG_ENABLE \ 48 (NETIF_MSG_LINK | \ 49 NETIF_MSG_TIMER | \ 50 NETIF_MSG_RX_ERR| \ 51 NETIF_MSG_TX_ERR) 52 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 54 [EDSR] = 0x0000, 55 [EDMR] = 0x0400, 56 [EDTRR] = 0x0408, 57 [EDRRR] = 0x0410, 58 [EESR] = 0x0428, 59 [EESIPR] = 0x0430, 60 [TDLAR] = 0x0010, 61 [TDFAR] = 0x0014, 62 [TDFXR] = 0x0018, 63 [TDFFR] = 0x001c, 64 [RDLAR] = 0x0030, 65 [RDFAR] = 0x0034, 66 [RDFXR] = 0x0038, 67 [RDFFR] = 0x003c, 68 [TRSCER] = 0x0438, 69 [RMFCR] = 0x0440, 70 [TFTR] = 0x0448, 71 [FDR] = 0x0450, 72 [RMCR] = 0x0458, 73 [RPADIR] = 0x0460, 74 [FCFTR] = 0x0468, 75 [CSMR] = 0x04E4, 76 77 [ECMR] = 0x0500, 78 [ECSR] = 0x0510, 79 [ECSIPR] = 0x0518, 80 [PIR] = 0x0520, 81 [PSR] = 0x0528, 82 [PIPR] = 0x052c, 83 [RFLR] = 0x0508, 84 [APR] = 0x0554, 85 [MPR] = 0x0558, 86 [PFTCR] = 0x055c, 87 [PFRCR] = 0x0560, 88 [TPAUSER] = 0x0564, 89 [GECMR] = 0x05b0, 90 [BCULR] = 0x05b4, 91 [MAHR] = 0x05c0, 92 [MALR] = 0x05c8, 93 [TROCR] = 0x0700, 94 [CDCR] = 0x0708, 95 [LCCR] = 0x0710, 96 [CEFCR] = 0x0740, 97 [FRECR] = 0x0748, 98 [TSFRCR] = 0x0750, 99 [TLFRCR] = 0x0758, 100 [RFCR] = 0x0760, 101 [CERCR] = 0x0768, 102 [CEECR] = 0x0770, 103 [MAFCR] = 0x0778, 104 [RMII_MII] = 0x0790, 105 106 [ARSTR] = 0x0000, 107 [TSU_CTRST] = 0x0004, 108 [TSU_FWEN0] = 0x0010, 109 [TSU_FWEN1] = 0x0014, 110 [TSU_FCM] = 0x0018, 111 [TSU_BSYSL0] = 0x0020, 112 [TSU_BSYSL1] = 0x0024, 113 [TSU_PRISL0] = 0x0028, 114 [TSU_PRISL1] = 0x002c, 115 [TSU_FWSL0] = 0x0030, 116 [TSU_FWSL1] = 0x0034, 117 [TSU_FWSLC] = 0x0038, 118 [TSU_QTAG0] = 0x0040, 119 [TSU_QTAG1] = 0x0044, 120 [TSU_FWSR] = 0x0050, 121 [TSU_FWINMK] = 0x0054, 122 [TSU_ADQT0] = 0x0048, 123 [TSU_ADQT1] = 0x004c, 124 [TSU_VTAG0] = 0x0058, 125 [TSU_VTAG1] = 0x005c, 126 [TSU_ADSBSY] = 0x0060, 127 [TSU_TEN] = 0x0064, 128 [TSU_POST1] = 0x0070, 129 [TSU_POST2] = 0x0074, 130 [TSU_POST3] = 0x0078, 131 [TSU_POST4] = 0x007c, 132 [TSU_ADRH0] = 0x0100, 133 [TSU_ADRL0] = 0x0104, 134 [TSU_ADRH31] = 0x01f8, 135 [TSU_ADRL31] = 0x01fc, 136 137 [TXNLCR0] = 0x0080, 138 [TXALCR0] = 0x0084, 139 [RXNLCR0] = 0x0088, 140 [RXALCR0] = 0x008c, 141 [FWNLCR0] = 0x0090, 142 [FWALCR0] = 0x0094, 143 [TXNLCR1] = 0x00a0, 144 [TXALCR1] = 0x00a0, 145 [RXNLCR1] = 0x00a8, 146 [RXALCR1] = 0x00ac, 147 [FWNLCR1] = 0x00b0, 148 [FWALCR1] = 0x00b4, 149}; 150 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 152 [ECMR] = 0x0300, 153 [RFLR] = 0x0308, 154 [ECSR] = 0x0310, 155 [ECSIPR] = 0x0318, 156 [PIR] = 0x0320, 157 [PSR] = 0x0328, 158 [RDMLR] = 0x0340, 159 [IPGR] = 0x0350, 160 [APR] = 0x0354, 161 [MPR] = 0x0358, 162 [RFCF] = 0x0360, 163 [TPAUSER] = 0x0364, 164 [TPAUSECR] = 0x0368, 165 [MAHR] = 0x03c0, 166 [MALR] = 0x03c8, 167 [TROCR] = 0x03d0, 168 [CDCR] = 0x03d4, 169 [LCCR] = 0x03d8, 170 [CNDCR] = 0x03dc, 171 [CEFCR] = 0x03e4, 172 [FRECR] = 0x03e8, 173 [TSFRCR] = 0x03ec, 174 [TLFRCR] = 0x03f0, 175 [RFCR] = 0x03f4, 176 [MAFCR] = 0x03f8, 177 178 [EDMR] = 0x0200, 179 [EDTRR] = 0x0208, 180 [EDRRR] = 0x0210, 181 [TDLAR] = 0x0218, 182 [RDLAR] = 0x0220, 183 [EESR] = 0x0228, 184 [EESIPR] = 0x0230, 185 [TRSCER] = 0x0238, 186 [RMFCR] = 0x0240, 187 [TFTR] = 0x0248, 188 [FDR] = 0x0250, 189 [RMCR] = 0x0258, 190 [TFUCR] = 0x0264, 191 [RFOCR] = 0x0268, 192 [FCFTR] = 0x0270, 193 [TRIMD] = 0x027c, 194}; 195 196static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 197 [ECMR] = 0x0100, 198 [RFLR] = 0x0108, 199 [ECSR] = 0x0110, 200 [ECSIPR] = 0x0118, 201 [PIR] = 0x0120, 202 [PSR] = 0x0128, 203 [RDMLR] = 0x0140, 204 [IPGR] = 0x0150, 205 [APR] = 0x0154, 206 [MPR] = 0x0158, 207 [TPAUSER] = 0x0164, 208 [RFCF] = 0x0160, 209 [TPAUSECR] = 0x0168, 210 [BCFRR] = 0x016c, 211 [MAHR] = 0x01c0, 212 [MALR] = 0x01c8, 213 [TROCR] = 0x01d0, 214 [CDCR] = 0x01d4, 215 [LCCR] = 0x01d8, 216 [CNDCR] = 0x01dc, 217 [CEFCR] = 0x01e4, 218 [FRECR] = 0x01e8, 219 [TSFRCR] = 0x01ec, 220 [TLFRCR] = 0x01f0, 221 [RFCR] = 0x01f4, 222 [MAFCR] = 0x01f8, 223 [RTRATE] = 0x01fc, 224 225 [EDMR] = 0x0000, 226 [EDTRR] = 0x0008, 227 [EDRRR] = 0x0010, 228 [TDLAR] = 0x0018, 229 [RDLAR] = 0x0020, 230 [EESR] = 0x0028, 231 [EESIPR] = 0x0030, 232 [TRSCER] = 0x0038, 233 [RMFCR] = 0x0040, 234 [TFTR] = 0x0048, 235 [FDR] = 0x0050, 236 [RMCR] = 0x0058, 237 [TFUCR] = 0x0064, 238 [RFOCR] = 0x0068, 239 [FCFTR] = 0x0070, 240 [RPADIR] = 0x0078, 241 [TRIMD] = 0x007c, 242 [RBWAR] = 0x00c8, 243 [RDFAR] = 0x00cc, 244 [TBRAR] = 0x00d4, 245 [TDFAR] = 0x00d8, 246}; 247 248static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 249 [ECMR] = 0x0160, 250 [ECSR] = 0x0164, 251 [ECSIPR] = 0x0168, 252 [PIR] = 0x016c, 253 [MAHR] = 0x0170, 254 [MALR] = 0x0174, 255 [RFLR] = 0x0178, 256 [PSR] = 0x017c, 257 [TROCR] = 0x0180, 258 [CDCR] = 0x0184, 259 [LCCR] = 0x0188, 260 [CNDCR] = 0x018c, 261 [CEFCR] = 0x0194, 262 [FRECR] = 0x0198, 263 [TSFRCR] = 0x019c, 264 [TLFRCR] = 0x01a0, 265 [RFCR] = 0x01a4, 266 [MAFCR] = 0x01a8, 267 [IPGR] = 0x01b4, 268 [APR] = 0x01b8, 269 [MPR] = 0x01bc, 270 [TPAUSER] = 0x01c4, 271 [BCFR] = 0x01cc, 272 273 [ARSTR] = 0x0000, 274 [TSU_CTRST] = 0x0004, 275 [TSU_FWEN0] = 0x0010, 276 [TSU_FWEN1] = 0x0014, 277 [TSU_FCM] = 0x0018, 278 [TSU_BSYSL0] = 0x0020, 279 [TSU_BSYSL1] = 0x0024, 280 [TSU_PRISL0] = 0x0028, 281 [TSU_PRISL1] = 0x002c, 282 [TSU_FWSL0] = 0x0030, 283 [TSU_FWSL1] = 0x0034, 284 [TSU_FWSLC] = 0x0038, 285 [TSU_QTAGM0] = 0x0040, 286 [TSU_QTAGM1] = 0x0044, 287 [TSU_ADQT0] = 0x0048, 288 [TSU_ADQT1] = 0x004c, 289 [TSU_FWSR] = 0x0050, 290 [TSU_FWINMK] = 0x0054, 291 [TSU_ADSBSY] = 0x0060, 292 [TSU_TEN] = 0x0064, 293 [TSU_POST1] = 0x0070, 294 [TSU_POST2] = 0x0074, 295 [TSU_POST3] = 0x0078, 296 [TSU_POST4] = 0x007c, 297 298 [TXNLCR0] = 0x0080, 299 [TXALCR0] = 0x0084, 300 [RXNLCR0] = 0x0088, 301 [RXALCR0] = 0x008c, 302 [FWNLCR0] = 0x0090, 303 [FWALCR0] = 0x0094, 304 [TXNLCR1] = 0x00a0, 305 [TXALCR1] = 0x00a0, 306 [RXNLCR1] = 0x00a8, 307 [RXALCR1] = 0x00ac, 308 [FWNLCR1] = 0x00b0, 309 [FWALCR1] = 0x00b4, 310 311 [TSU_ADRH0] = 0x0100, 312 [TSU_ADRL0] = 0x0104, 313 [TSU_ADRL31] = 0x01fc, 314}; 315 316static int sh_eth_is_gether(struct sh_eth_private *mdp) 317{ 318 if (mdp->reg_offset == sh_eth_offset_gigabit) 319 return 1; 320 else 321 return 0; 322} 323 324static void __maybe_unused sh_eth_select_mii(struct net_device *ndev) 325{ 326 u32 value = 0x0; 327 struct sh_eth_private *mdp = netdev_priv(ndev); 328 329 switch (mdp->phy_interface) { 330 case PHY_INTERFACE_MODE_GMII: 331 value = 0x2; 332 break; 333 case PHY_INTERFACE_MODE_MII: 334 value = 0x1; 335 break; 336 case PHY_INTERFACE_MODE_RMII: 337 value = 0x0; 338 break; 339 default: 340 pr_warn("PHY interface mode was not setup. Set to MII.\n"); 341 value = 0x1; 342 break; 343 } 344 345 sh_eth_write(ndev, value, RMII_MII); 346} 347 348static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev) 349{ 350 struct sh_eth_private *mdp = netdev_priv(ndev); 351 352 if (mdp->duplex) /* Full */ 353 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 354 else /* Half */ 355 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 356} 357 358/* There is CPU dependent code */ 359static void sh_eth_set_rate_r8a777x(struct net_device *ndev) 360{ 361 struct sh_eth_private *mdp = netdev_priv(ndev); 362 363 switch (mdp->speed) { 364 case 10: /* 10BASE */ 365 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR); 366 break; 367 case 100:/* 100BASE */ 368 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR); 369 break; 370 default: 371 break; 372 } 373} 374 375/* R8A7778/9 */ 376static struct sh_eth_cpu_data r8a777x_data = { 377 .set_duplex = sh_eth_set_duplex, 378 .set_rate = sh_eth_set_rate_r8a777x, 379 380 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 381 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 382 .eesipr_value = 0x01ff009f, 383 384 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 385 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 386 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 387 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 388 389 .apr = 1, 390 .mpr = 1, 391 .tpauser = 1, 392 .hw_swap = 1, 393}; 394 395static void sh_eth_set_rate_sh7724(struct net_device *ndev) 396{ 397 struct sh_eth_private *mdp = netdev_priv(ndev); 398 399 switch (mdp->speed) { 400 case 10: /* 10BASE */ 401 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 402 break; 403 case 100:/* 100BASE */ 404 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 405 break; 406 default: 407 break; 408 } 409} 410 411/* SH7724 */ 412static struct sh_eth_cpu_data sh7724_data = { 413 .set_duplex = sh_eth_set_duplex, 414 .set_rate = sh_eth_set_rate_sh7724, 415 416 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 417 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 418 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f, 419 420 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 421 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 422 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 423 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 424 425 .apr = 1, 426 .mpr = 1, 427 .tpauser = 1, 428 .hw_swap = 1, 429 .rpadir = 1, 430 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 431}; 432 433static void sh_eth_set_rate_sh7757(struct net_device *ndev) 434{ 435 struct sh_eth_private *mdp = netdev_priv(ndev); 436 437 switch (mdp->speed) { 438 case 10: /* 10BASE */ 439 sh_eth_write(ndev, 0, RTRATE); 440 break; 441 case 100:/* 100BASE */ 442 sh_eth_write(ndev, 1, RTRATE); 443 break; 444 default: 445 break; 446 } 447} 448 449/* SH7757 */ 450static struct sh_eth_cpu_data sh7757_data = { 451 .set_duplex = sh_eth_set_duplex, 452 .set_rate = sh_eth_set_rate_sh7757, 453 454 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 455 .rmcr_value = 0x00000001, 456 457 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 458 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 459 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 460 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 461 462 .irq_flags = IRQF_SHARED, 463 .apr = 1, 464 .mpr = 1, 465 .tpauser = 1, 466 .hw_swap = 1, 467 .no_ade = 1, 468 .rpadir = 1, 469 .rpadir_value = 2 << 16, 470}; 471 472#define SH_GIGA_ETH_BASE 0xfee00000UL 473#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 474#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 475static void sh_eth_chip_reset_giga(struct net_device *ndev) 476{ 477 int i; 478 unsigned long mahr[2], malr[2]; 479 480 /* save MAHR and MALR */ 481 for (i = 0; i < 2; i++) { 482 malr[i] = ioread32((void *)GIGA_MALR(i)); 483 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 484 } 485 486 /* reset device */ 487 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 488 mdelay(1); 489 490 /* restore MAHR and MALR */ 491 for (i = 0; i < 2; i++) { 492 iowrite32(malr[i], (void *)GIGA_MALR(i)); 493 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 494 } 495} 496 497static void sh_eth_set_rate_giga(struct net_device *ndev) 498{ 499 struct sh_eth_private *mdp = netdev_priv(ndev); 500 501 switch (mdp->speed) { 502 case 10: /* 10BASE */ 503 sh_eth_write(ndev, 0x00000000, GECMR); 504 break; 505 case 100:/* 100BASE */ 506 sh_eth_write(ndev, 0x00000010, GECMR); 507 break; 508 case 1000: /* 1000BASE */ 509 sh_eth_write(ndev, 0x00000020, GECMR); 510 break; 511 default: 512 break; 513 } 514} 515 516/* SH7757(GETHERC) */ 517static struct sh_eth_cpu_data sh7757_data_giga = { 518 .chip_reset = sh_eth_chip_reset_giga, 519 .set_duplex = sh_eth_set_duplex, 520 .set_rate = sh_eth_set_rate_giga, 521 522 .ecsr_value = ECSR_ICD | ECSR_MPD, 523 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 524 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 525 526 .tx_check = EESR_TC1 | EESR_FTC, 527 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 528 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 529 EESR_ECI, 530 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 531 EESR_TFE, 532 .fdr_value = 0x0000072f, 533 .rmcr_value = 0x00000001, 534 535 .irq_flags = IRQF_SHARED, 536 .apr = 1, 537 .mpr = 1, 538 .tpauser = 1, 539 .bculr = 1, 540 .hw_swap = 1, 541 .rpadir = 1, 542 .rpadir_value = 2 << 16, 543 .no_trimd = 1, 544 .no_ade = 1, 545 .tsu = 1, 546}; 547 548static void sh_eth_chip_reset(struct net_device *ndev) 549{ 550 struct sh_eth_private *mdp = netdev_priv(ndev); 551 552 /* reset device */ 553 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 554 mdelay(1); 555} 556 557static void sh_eth_set_rate_gether(struct net_device *ndev) 558{ 559 struct sh_eth_private *mdp = netdev_priv(ndev); 560 561 switch (mdp->speed) { 562 case 10: /* 10BASE */ 563 sh_eth_write(ndev, GECMR_10, GECMR); 564 break; 565 case 100:/* 100BASE */ 566 sh_eth_write(ndev, GECMR_100, GECMR); 567 break; 568 case 1000: /* 1000BASE */ 569 sh_eth_write(ndev, GECMR_1000, GECMR); 570 break; 571 default: 572 break; 573 } 574} 575 576/* SH7734 */ 577static struct sh_eth_cpu_data sh7734_data = { 578 .chip_reset = sh_eth_chip_reset, 579 .set_duplex = sh_eth_set_duplex, 580 .set_rate = sh_eth_set_rate_gether, 581 582 .ecsr_value = ECSR_ICD | ECSR_MPD, 583 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 584 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 585 586 .tx_check = EESR_TC1 | EESR_FTC, 587 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 588 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 589 EESR_ECI, 590 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 591 EESR_TFE, 592 593 .apr = 1, 594 .mpr = 1, 595 .tpauser = 1, 596 .bculr = 1, 597 .hw_swap = 1, 598 .no_trimd = 1, 599 .no_ade = 1, 600 .tsu = 1, 601 .hw_crc = 1, 602 .select_mii = 1, 603}; 604 605/* SH7763 */ 606static struct sh_eth_cpu_data sh7763_data = { 607 .chip_reset = sh_eth_chip_reset, 608 .set_duplex = sh_eth_set_duplex, 609 .set_rate = sh_eth_set_rate_gether, 610 611 .ecsr_value = ECSR_ICD | ECSR_MPD, 612 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 613 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 614 615 .tx_check = EESR_TC1 | EESR_FTC, 616 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 617 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 618 EESR_ECI, 619 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 620 EESR_TFE, 621 622 .apr = 1, 623 .mpr = 1, 624 .tpauser = 1, 625 .bculr = 1, 626 .hw_swap = 1, 627 .no_trimd = 1, 628 .no_ade = 1, 629 .tsu = 1, 630 .irq_flags = IRQF_SHARED, 631}; 632 633static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 634{ 635 struct sh_eth_private *mdp = netdev_priv(ndev); 636 637 /* reset device */ 638 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 639 mdelay(1); 640 641 sh_eth_select_mii(ndev); 642} 643 644/* R8A7740 */ 645static struct sh_eth_cpu_data r8a7740_data = { 646 .chip_reset = sh_eth_chip_reset_r8a7740, 647 .set_duplex = sh_eth_set_duplex, 648 .set_rate = sh_eth_set_rate_gether, 649 650 .ecsr_value = ECSR_ICD | ECSR_MPD, 651 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 652 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 653 654 .tx_check = EESR_TC1 | EESR_FTC, 655 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 656 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 657 EESR_ECI, 658 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 659 EESR_TFE, 660 661 .apr = 1, 662 .mpr = 1, 663 .tpauser = 1, 664 .bculr = 1, 665 .hw_swap = 1, 666 .no_trimd = 1, 667 .no_ade = 1, 668 .tsu = 1, 669 .select_mii = 1, 670}; 671 672static struct sh_eth_cpu_data sh7619_data = { 673 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 674 675 .apr = 1, 676 .mpr = 1, 677 .tpauser = 1, 678 .hw_swap = 1, 679}; 680 681static struct sh_eth_cpu_data sh771x_data = { 682 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 683 .tsu = 1, 684}; 685 686static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 687{ 688 if (!cd->ecsr_value) 689 cd->ecsr_value = DEFAULT_ECSR_INIT; 690 691 if (!cd->ecsipr_value) 692 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 693 694 if (!cd->fcftr_value) 695 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \ 696 DEFAULT_FIFO_F_D_RFD; 697 698 if (!cd->fdr_value) 699 cd->fdr_value = DEFAULT_FDR_INIT; 700 701 if (!cd->rmcr_value) 702 cd->rmcr_value = DEFAULT_RMCR_VALUE; 703 704 if (!cd->tx_check) 705 cd->tx_check = DEFAULT_TX_CHECK; 706 707 if (!cd->eesr_err_check) 708 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 709 710 if (!cd->tx_error_check) 711 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; 712} 713 714static int sh_eth_check_reset(struct net_device *ndev) 715{ 716 int ret = 0; 717 int cnt = 100; 718 719 while (cnt > 0) { 720 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 721 break; 722 mdelay(1); 723 cnt--; 724 } 725 if (cnt < 0) { 726 pr_err("Device reset fail\n"); 727 ret = -ETIMEDOUT; 728 } 729 return ret; 730} 731 732static int sh_eth_reset(struct net_device *ndev) 733{ 734 struct sh_eth_private *mdp = netdev_priv(ndev); 735 int ret = 0; 736 737 if (sh_eth_is_gether(mdp)) { 738 sh_eth_write(ndev, EDSR_ENALL, EDSR); 739 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 740 EDMR); 741 742 ret = sh_eth_check_reset(ndev); 743 if (ret) 744 goto out; 745 746 /* Table Init */ 747 sh_eth_write(ndev, 0x0, TDLAR); 748 sh_eth_write(ndev, 0x0, TDFAR); 749 sh_eth_write(ndev, 0x0, TDFXR); 750 sh_eth_write(ndev, 0x0, TDFFR); 751 sh_eth_write(ndev, 0x0, RDLAR); 752 sh_eth_write(ndev, 0x0, RDFAR); 753 sh_eth_write(ndev, 0x0, RDFXR); 754 sh_eth_write(ndev, 0x0, RDFFR); 755 756 /* Reset HW CRC register */ 757 if (mdp->cd->hw_crc) 758 sh_eth_write(ndev, 0x0, CSMR); 759 760 /* Select MII mode */ 761 if (mdp->cd->select_mii) 762 sh_eth_select_mii(ndev); 763 } else { 764 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 765 EDMR); 766 mdelay(3); 767 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 768 EDMR); 769 } 770 771out: 772 return ret; 773} 774 775#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 776static void sh_eth_set_receive_align(struct sk_buff *skb) 777{ 778 int reserve; 779 780 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); 781 if (reserve) 782 skb_reserve(skb, reserve); 783} 784#else 785static void sh_eth_set_receive_align(struct sk_buff *skb) 786{ 787 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); 788} 789#endif 790 791 792/* CPU <-> EDMAC endian convert */ 793static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 794{ 795 switch (mdp->edmac_endian) { 796 case EDMAC_LITTLE_ENDIAN: 797 return cpu_to_le32(x); 798 case EDMAC_BIG_ENDIAN: 799 return cpu_to_be32(x); 800 } 801 return x; 802} 803 804static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) 805{ 806 switch (mdp->edmac_endian) { 807 case EDMAC_LITTLE_ENDIAN: 808 return le32_to_cpu(x); 809 case EDMAC_BIG_ENDIAN: 810 return be32_to_cpu(x); 811 } 812 return x; 813} 814 815/* 816 * Program the hardware MAC address from dev->dev_addr. 817 */ 818static void update_mac_address(struct net_device *ndev) 819{ 820 sh_eth_write(ndev, 821 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 822 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 823 sh_eth_write(ndev, 824 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 825} 826 827/* 828 * Get MAC address from SuperH MAC address register 829 * 830 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 831 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 832 * When you want use this device, you must set MAC address in bootloader. 833 * 834 */ 835static void read_mac_address(struct net_device *ndev, unsigned char *mac) 836{ 837 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 838 memcpy(ndev->dev_addr, mac, 6); 839 } else { 840 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24); 841 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF; 842 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF; 843 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF); 844 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF; 845 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF); 846 } 847} 848 849static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 850{ 851 if (sh_eth_is_gether(mdp)) 852 return EDTRR_TRNS_GETHER; 853 else 854 return EDTRR_TRNS_ETHER; 855} 856 857struct bb_info { 858 void (*set_gate)(void *addr); 859 struct mdiobb_ctrl ctrl; 860 void *addr; 861 u32 mmd_msk;/* MMD */ 862 u32 mdo_msk; 863 u32 mdi_msk; 864 u32 mdc_msk; 865}; 866 867/* PHY bit set */ 868static void bb_set(void *addr, u32 msk) 869{ 870 iowrite32(ioread32(addr) | msk, addr); 871} 872 873/* PHY bit clear */ 874static void bb_clr(void *addr, u32 msk) 875{ 876 iowrite32((ioread32(addr) & ~msk), addr); 877} 878 879/* PHY bit read */ 880static int bb_read(void *addr, u32 msk) 881{ 882 return (ioread32(addr) & msk) != 0; 883} 884 885/* Data I/O pin control */ 886static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 887{ 888 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 889 890 if (bitbang->set_gate) 891 bitbang->set_gate(bitbang->addr); 892 893 if (bit) 894 bb_set(bitbang->addr, bitbang->mmd_msk); 895 else 896 bb_clr(bitbang->addr, bitbang->mmd_msk); 897} 898 899/* Set bit data*/ 900static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 901{ 902 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 903 904 if (bitbang->set_gate) 905 bitbang->set_gate(bitbang->addr); 906 907 if (bit) 908 bb_set(bitbang->addr, bitbang->mdo_msk); 909 else 910 bb_clr(bitbang->addr, bitbang->mdo_msk); 911} 912 913/* Get bit data*/ 914static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 915{ 916 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 917 918 if (bitbang->set_gate) 919 bitbang->set_gate(bitbang->addr); 920 921 return bb_read(bitbang->addr, bitbang->mdi_msk); 922} 923 924/* MDC pin control */ 925static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 926{ 927 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 928 929 if (bitbang->set_gate) 930 bitbang->set_gate(bitbang->addr); 931 932 if (bit) 933 bb_set(bitbang->addr, bitbang->mdc_msk); 934 else 935 bb_clr(bitbang->addr, bitbang->mdc_msk); 936} 937 938/* mdio bus control struct */ 939static struct mdiobb_ops bb_ops = { 940 .owner = THIS_MODULE, 941 .set_mdc = sh_mdc_ctrl, 942 .set_mdio_dir = sh_mmd_ctrl, 943 .set_mdio_data = sh_set_mdio, 944 .get_mdio_data = sh_get_mdio, 945}; 946 947/* free skb and descriptor buffer */ 948static void sh_eth_ring_free(struct net_device *ndev) 949{ 950 struct sh_eth_private *mdp = netdev_priv(ndev); 951 int i; 952 953 /* Free Rx skb ringbuffer */ 954 if (mdp->rx_skbuff) { 955 for (i = 0; i < mdp->num_rx_ring; i++) { 956 if (mdp->rx_skbuff[i]) 957 dev_kfree_skb(mdp->rx_skbuff[i]); 958 } 959 } 960 kfree(mdp->rx_skbuff); 961 mdp->rx_skbuff = NULL; 962 963 /* Free Tx skb ringbuffer */ 964 if (mdp->tx_skbuff) { 965 for (i = 0; i < mdp->num_tx_ring; i++) { 966 if (mdp->tx_skbuff[i]) 967 dev_kfree_skb(mdp->tx_skbuff[i]); 968 } 969 } 970 kfree(mdp->tx_skbuff); 971 mdp->tx_skbuff = NULL; 972} 973 974/* format skb and descriptor buffer */ 975static void sh_eth_ring_format(struct net_device *ndev) 976{ 977 struct sh_eth_private *mdp = netdev_priv(ndev); 978 int i; 979 struct sk_buff *skb; 980 struct sh_eth_rxdesc *rxdesc = NULL; 981 struct sh_eth_txdesc *txdesc = NULL; 982 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 983 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 984 985 mdp->cur_rx = mdp->cur_tx = 0; 986 mdp->dirty_rx = mdp->dirty_tx = 0; 987 988 memset(mdp->rx_ring, 0, rx_ringsize); 989 990 /* build Rx ring buffer */ 991 for (i = 0; i < mdp->num_rx_ring; i++) { 992 /* skb */ 993 mdp->rx_skbuff[i] = NULL; 994 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 995 mdp->rx_skbuff[i] = skb; 996 if (skb == NULL) 997 break; 998 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 999 DMA_FROM_DEVICE); 1000 sh_eth_set_receive_align(skb); 1001 1002 /* RX descriptor */ 1003 rxdesc = &mdp->rx_ring[i]; 1004 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1005 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1006 1007 /* The size of the buffer is 16 byte boundary. */ 1008 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1009 /* Rx descriptor address set */ 1010 if (i == 0) { 1011 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1012 if (sh_eth_is_gether(mdp)) 1013 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1014 } 1015 } 1016 1017 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1018 1019 /* Mark the last entry as wrapping the ring. */ 1020 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); 1021 1022 memset(mdp->tx_ring, 0, tx_ringsize); 1023 1024 /* build Tx ring buffer */ 1025 for (i = 0; i < mdp->num_tx_ring; i++) { 1026 mdp->tx_skbuff[i] = NULL; 1027 txdesc = &mdp->tx_ring[i]; 1028 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1029 txdesc->buffer_length = 0; 1030 if (i == 0) { 1031 /* Tx descriptor address set */ 1032 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1033 if (sh_eth_is_gether(mdp)) 1034 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1035 } 1036 } 1037 1038 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1039} 1040 1041/* Get skb and descriptor buffer */ 1042static int sh_eth_ring_init(struct net_device *ndev) 1043{ 1044 struct sh_eth_private *mdp = netdev_priv(ndev); 1045 int rx_ringsize, tx_ringsize, ret = 0; 1046 1047 /* 1048 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1049 * card needs room to do 8 byte alignment, +2 so we can reserve 1050 * the first 2 bytes, and +16 gets room for the status word from the 1051 * card. 1052 */ 1053 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1054 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1055 if (mdp->cd->rpadir) 1056 mdp->rx_buf_sz += NET_IP_ALIGN; 1057 1058 /* Allocate RX and TX skb rings */ 1059 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring, 1060 sizeof(*mdp->rx_skbuff), GFP_KERNEL); 1061 if (!mdp->rx_skbuff) { 1062 ret = -ENOMEM; 1063 return ret; 1064 } 1065 1066 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring, 1067 sizeof(*mdp->tx_skbuff), GFP_KERNEL); 1068 if (!mdp->tx_skbuff) { 1069 ret = -ENOMEM; 1070 goto skb_ring_free; 1071 } 1072 1073 /* Allocate all Rx descriptors. */ 1074 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1075 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 1076 GFP_KERNEL); 1077 if (!mdp->rx_ring) { 1078 ret = -ENOMEM; 1079 goto desc_ring_free; 1080 } 1081 1082 mdp->dirty_rx = 0; 1083 1084 /* Allocate all Tx descriptors. */ 1085 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1086 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 1087 GFP_KERNEL); 1088 if (!mdp->tx_ring) { 1089 ret = -ENOMEM; 1090 goto desc_ring_free; 1091 } 1092 return ret; 1093 1094desc_ring_free: 1095 /* free DMA buffer */ 1096 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); 1097 1098skb_ring_free: 1099 /* Free Rx and Tx skb ring buffer */ 1100 sh_eth_ring_free(ndev); 1101 mdp->tx_ring = NULL; 1102 mdp->rx_ring = NULL; 1103 1104 return ret; 1105} 1106 1107static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp) 1108{ 1109 int ringsize; 1110 1111 if (mdp->rx_ring) { 1112 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1113 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 1114 mdp->rx_desc_dma); 1115 mdp->rx_ring = NULL; 1116 } 1117 1118 if (mdp->tx_ring) { 1119 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1120 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 1121 mdp->tx_desc_dma); 1122 mdp->tx_ring = NULL; 1123 } 1124} 1125 1126static int sh_eth_dev_init(struct net_device *ndev, bool start) 1127{ 1128 int ret = 0; 1129 struct sh_eth_private *mdp = netdev_priv(ndev); 1130 u32 val; 1131 1132 /* Soft Reset */ 1133 ret = sh_eth_reset(ndev); 1134 if (ret) 1135 goto out; 1136 1137 /* Descriptor format */ 1138 sh_eth_ring_format(ndev); 1139 if (mdp->cd->rpadir) 1140 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1141 1142 /* all sh_eth int mask */ 1143 sh_eth_write(ndev, 0, EESIPR); 1144 1145#if defined(__LITTLE_ENDIAN) 1146 if (mdp->cd->hw_swap) 1147 sh_eth_write(ndev, EDMR_EL, EDMR); 1148 else 1149#endif 1150 sh_eth_write(ndev, 0, EDMR); 1151 1152 /* FIFO size set */ 1153 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1154 sh_eth_write(ndev, 0, TFTR); 1155 1156 /* Frame recv control */ 1157 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR); 1158 1159 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER); 1160 1161 if (mdp->cd->bculr) 1162 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1163 1164 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1165 1166 if (!mdp->cd->no_trimd) 1167 sh_eth_write(ndev, 0, TRIMD); 1168 1169 /* Recv frame limit set register */ 1170 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1171 RFLR); 1172 1173 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 1174 if (start) 1175 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1176 1177 /* PAUSE Prohibition */ 1178 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | 1179 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 1180 1181 sh_eth_write(ndev, val, ECMR); 1182 1183 if (mdp->cd->set_rate) 1184 mdp->cd->set_rate(ndev); 1185 1186 /* E-MAC Status Register clear */ 1187 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1188 1189 /* E-MAC Interrupt Enable register */ 1190 if (start) 1191 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1192 1193 /* Set MAC address */ 1194 update_mac_address(ndev); 1195 1196 /* mask reset */ 1197 if (mdp->cd->apr) 1198 sh_eth_write(ndev, APR_AP, APR); 1199 if (mdp->cd->mpr) 1200 sh_eth_write(ndev, MPR_MP, MPR); 1201 if (mdp->cd->tpauser) 1202 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1203 1204 if (start) { 1205 /* Setting the Rx mode will start the Rx process. */ 1206 sh_eth_write(ndev, EDRRR_R, EDRRR); 1207 1208 netif_start_queue(ndev); 1209 } 1210 1211out: 1212 return ret; 1213} 1214 1215/* free Tx skb function */ 1216static int sh_eth_txfree(struct net_device *ndev) 1217{ 1218 struct sh_eth_private *mdp = netdev_priv(ndev); 1219 struct sh_eth_txdesc *txdesc; 1220 int freeNum = 0; 1221 int entry = 0; 1222 1223 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1224 entry = mdp->dirty_tx % mdp->num_tx_ring; 1225 txdesc = &mdp->tx_ring[entry]; 1226 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 1227 break; 1228 /* Free the original skb. */ 1229 if (mdp->tx_skbuff[entry]) { 1230 dma_unmap_single(&ndev->dev, txdesc->addr, 1231 txdesc->buffer_length, DMA_TO_DEVICE); 1232 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1233 mdp->tx_skbuff[entry] = NULL; 1234 freeNum++; 1235 } 1236 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1237 if (entry >= mdp->num_tx_ring - 1) 1238 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1239 1240 ndev->stats.tx_packets++; 1241 ndev->stats.tx_bytes += txdesc->buffer_length; 1242 } 1243 return freeNum; 1244} 1245 1246/* Packet receive function */ 1247static int sh_eth_rx(struct net_device *ndev, u32 intr_status) 1248{ 1249 struct sh_eth_private *mdp = netdev_priv(ndev); 1250 struct sh_eth_rxdesc *rxdesc; 1251 1252 int entry = mdp->cur_rx % mdp->num_rx_ring; 1253 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1254 struct sk_buff *skb; 1255 u16 pkt_len = 0; 1256 u32 desc_status; 1257 1258 rxdesc = &mdp->rx_ring[entry]; 1259 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1260 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1261 pkt_len = rxdesc->frame_length; 1262 1263#if defined(CONFIG_ARCH_R8A7740) 1264 desc_status >>= 16; 1265#endif 1266 1267 if (--boguscnt < 0) 1268 break; 1269 1270 if (!(desc_status & RDFEND)) 1271 ndev->stats.rx_length_errors++; 1272 1273 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1274 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1275 ndev->stats.rx_errors++; 1276 if (desc_status & RD_RFS1) 1277 ndev->stats.rx_crc_errors++; 1278 if (desc_status & RD_RFS2) 1279 ndev->stats.rx_frame_errors++; 1280 if (desc_status & RD_RFS3) 1281 ndev->stats.rx_length_errors++; 1282 if (desc_status & RD_RFS4) 1283 ndev->stats.rx_length_errors++; 1284 if (desc_status & RD_RFS6) 1285 ndev->stats.rx_missed_errors++; 1286 if (desc_status & RD_RFS10) 1287 ndev->stats.rx_over_errors++; 1288 } else { 1289 if (!mdp->cd->hw_swap) 1290 sh_eth_soft_swap( 1291 phys_to_virt(ALIGN(rxdesc->addr, 4)), 1292 pkt_len + 2); 1293 skb = mdp->rx_skbuff[entry]; 1294 mdp->rx_skbuff[entry] = NULL; 1295 if (mdp->cd->rpadir) 1296 skb_reserve(skb, NET_IP_ALIGN); 1297 skb_put(skb, pkt_len); 1298 skb->protocol = eth_type_trans(skb, ndev); 1299 netif_rx(skb); 1300 ndev->stats.rx_packets++; 1301 ndev->stats.rx_bytes += pkt_len; 1302 } 1303 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); 1304 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1305 rxdesc = &mdp->rx_ring[entry]; 1306 } 1307 1308 /* Refill the Rx ring buffers. */ 1309 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1310 entry = mdp->dirty_rx % mdp->num_rx_ring; 1311 rxdesc = &mdp->rx_ring[entry]; 1312 /* The size of the buffer is 16 byte boundary. */ 1313 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1314 1315 if (mdp->rx_skbuff[entry] == NULL) { 1316 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1317 mdp->rx_skbuff[entry] = skb; 1318 if (skb == NULL) 1319 break; /* Better luck next round. */ 1320 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1321 DMA_FROM_DEVICE); 1322 sh_eth_set_receive_align(skb); 1323 1324 skb_checksum_none_assert(skb); 1325 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1326 } 1327 if (entry >= mdp->num_rx_ring - 1) 1328 rxdesc->status |= 1329 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1330 else 1331 rxdesc->status |= 1332 cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1333 } 1334 1335 /* Restart Rx engine if stopped. */ 1336 /* If we don't need to check status, don't. -KDU */ 1337 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1338 /* fix the values for the next receiving if RDE is set */ 1339 if (intr_status & EESR_RDE) 1340 mdp->cur_rx = mdp->dirty_rx = 1341 (sh_eth_read(ndev, RDFAR) - 1342 sh_eth_read(ndev, RDLAR)) >> 4; 1343 sh_eth_write(ndev, EDRRR_R, EDRRR); 1344 } 1345 1346 return 0; 1347} 1348 1349static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1350{ 1351 /* disable tx and rx */ 1352 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1353 ~(ECMR_RE | ECMR_TE), ECMR); 1354} 1355 1356static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1357{ 1358 /* enable tx and rx */ 1359 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1360 (ECMR_RE | ECMR_TE), ECMR); 1361} 1362 1363/* error control function */ 1364static void sh_eth_error(struct net_device *ndev, int intr_status) 1365{ 1366 struct sh_eth_private *mdp = netdev_priv(ndev); 1367 u32 felic_stat; 1368 u32 link_stat; 1369 u32 mask; 1370 1371 if (intr_status & EESR_ECI) { 1372 felic_stat = sh_eth_read(ndev, ECSR); 1373 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1374 if (felic_stat & ECSR_ICD) 1375 ndev->stats.tx_carrier_errors++; 1376 if (felic_stat & ECSR_LCHNG) { 1377 /* Link Changed */ 1378 if (mdp->cd->no_psr || mdp->no_ether_link) { 1379 goto ignore_link; 1380 } else { 1381 link_stat = (sh_eth_read(ndev, PSR)); 1382 if (mdp->ether_link_active_low) 1383 link_stat = ~link_stat; 1384 } 1385 if (!(link_stat & PHY_ST_LINK)) 1386 sh_eth_rcv_snd_disable(ndev); 1387 else { 1388 /* Link Up */ 1389 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1390 ~DMAC_M_ECI, EESIPR); 1391 /*clear int */ 1392 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1393 ECSR); 1394 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1395 DMAC_M_ECI, EESIPR); 1396 /* enable tx and rx */ 1397 sh_eth_rcv_snd_enable(ndev); 1398 } 1399 } 1400 } 1401 1402ignore_link: 1403 if (intr_status & EESR_TWB) { 1404 /* Write buck end. unused write back interrupt */ 1405 if (intr_status & EESR_TABT) /* Transmit Abort int */ 1406 ndev->stats.tx_aborted_errors++; 1407 if (netif_msg_tx_err(mdp)) 1408 dev_err(&ndev->dev, "Transmit Abort\n"); 1409 } 1410 1411 if (intr_status & EESR_RABT) { 1412 /* Receive Abort int */ 1413 if (intr_status & EESR_RFRMER) { 1414 /* Receive Frame Overflow int */ 1415 ndev->stats.rx_frame_errors++; 1416 if (netif_msg_rx_err(mdp)) 1417 dev_err(&ndev->dev, "Receive Abort\n"); 1418 } 1419 } 1420 1421 if (intr_status & EESR_TDE) { 1422 /* Transmit Descriptor Empty int */ 1423 ndev->stats.tx_fifo_errors++; 1424 if (netif_msg_tx_err(mdp)) 1425 dev_err(&ndev->dev, "Transmit Descriptor Empty\n"); 1426 } 1427 1428 if (intr_status & EESR_TFE) { 1429 /* FIFO under flow */ 1430 ndev->stats.tx_fifo_errors++; 1431 if (netif_msg_tx_err(mdp)) 1432 dev_err(&ndev->dev, "Transmit FIFO Under flow\n"); 1433 } 1434 1435 if (intr_status & EESR_RDE) { 1436 /* Receive Descriptor Empty int */ 1437 ndev->stats.rx_over_errors++; 1438 1439 if (netif_msg_rx_err(mdp)) 1440 dev_err(&ndev->dev, "Receive Descriptor Empty\n"); 1441 } 1442 1443 if (intr_status & EESR_RFE) { 1444 /* Receive FIFO Overflow int */ 1445 ndev->stats.rx_fifo_errors++; 1446 if (netif_msg_rx_err(mdp)) 1447 dev_err(&ndev->dev, "Receive FIFO Overflow\n"); 1448 } 1449 1450 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1451 /* Address Error */ 1452 ndev->stats.tx_fifo_errors++; 1453 if (netif_msg_tx_err(mdp)) 1454 dev_err(&ndev->dev, "Address Error\n"); 1455 } 1456 1457 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1458 if (mdp->cd->no_ade) 1459 mask &= ~EESR_ADE; 1460 if (intr_status & mask) { 1461 /* Tx error */ 1462 u32 edtrr = sh_eth_read(ndev, EDTRR); 1463 /* dmesg */ 1464 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ", 1465 intr_status, mdp->cur_tx); 1466 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1467 mdp->dirty_tx, (u32) ndev->state, edtrr); 1468 /* dirty buffer free */ 1469 sh_eth_txfree(ndev); 1470 1471 /* SH7712 BUG */ 1472 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1473 /* tx dma start */ 1474 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1475 } 1476 /* wakeup */ 1477 netif_wake_queue(ndev); 1478 } 1479} 1480 1481static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1482{ 1483 struct net_device *ndev = netdev; 1484 struct sh_eth_private *mdp = netdev_priv(ndev); 1485 struct sh_eth_cpu_data *cd = mdp->cd; 1486 irqreturn_t ret = IRQ_NONE; 1487 unsigned long intr_status; 1488 1489 spin_lock(&mdp->lock); 1490 1491 /* Get interrupt status */ 1492 intr_status = sh_eth_read(ndev, EESR); 1493 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1494 * enabled since it's the one that comes thru regardless of the mask, 1495 * and we need to fully handle it in sh_eth_error() in order to quench 1496 * it as it doesn't get cleared by just writing 1 to the ECI bit... 1497 */ 1498 intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI; 1499 /* Clear interrupt */ 1500 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | 1501 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | 1502 cd->tx_check | cd->eesr_err_check)) { 1503 sh_eth_write(ndev, intr_status, EESR); 1504 ret = IRQ_HANDLED; 1505 } else 1506 goto other_irq; 1507 1508 if (intr_status & (EESR_FRC | /* Frame recv*/ 1509 EESR_RMAF | /* Multi cast address recv*/ 1510 EESR_RRF | /* Bit frame recv */ 1511 EESR_RTLF | /* Long frame recv*/ 1512 EESR_RTSF | /* short frame recv */ 1513 EESR_PRE | /* PHY-LSI recv error */ 1514 EESR_CERF)){ /* recv frame CRC error */ 1515 sh_eth_rx(ndev, intr_status); 1516 } 1517 1518 /* Tx Check */ 1519 if (intr_status & cd->tx_check) { 1520 sh_eth_txfree(ndev); 1521 netif_wake_queue(ndev); 1522 } 1523 1524 if (intr_status & cd->eesr_err_check) 1525 sh_eth_error(ndev, intr_status); 1526 1527other_irq: 1528 spin_unlock(&mdp->lock); 1529 1530 return ret; 1531} 1532 1533/* PHY state control function */ 1534static void sh_eth_adjust_link(struct net_device *ndev) 1535{ 1536 struct sh_eth_private *mdp = netdev_priv(ndev); 1537 struct phy_device *phydev = mdp->phydev; 1538 int new_state = 0; 1539 1540 if (phydev->link) { 1541 if (phydev->duplex != mdp->duplex) { 1542 new_state = 1; 1543 mdp->duplex = phydev->duplex; 1544 if (mdp->cd->set_duplex) 1545 mdp->cd->set_duplex(ndev); 1546 } 1547 1548 if (phydev->speed != mdp->speed) { 1549 new_state = 1; 1550 mdp->speed = phydev->speed; 1551 if (mdp->cd->set_rate) 1552 mdp->cd->set_rate(ndev); 1553 } 1554 if (!mdp->link) { 1555 sh_eth_write(ndev, 1556 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR); 1557 new_state = 1; 1558 mdp->link = phydev->link; 1559 if (mdp->cd->no_psr || mdp->no_ether_link) 1560 sh_eth_rcv_snd_enable(ndev); 1561 } 1562 } else if (mdp->link) { 1563 new_state = 1; 1564 mdp->link = 0; 1565 mdp->speed = 0; 1566 mdp->duplex = -1; 1567 if (mdp->cd->no_psr || mdp->no_ether_link) 1568 sh_eth_rcv_snd_disable(ndev); 1569 } 1570 1571 if (new_state && netif_msg_link(mdp)) 1572 phy_print_status(phydev); 1573} 1574 1575/* PHY init function */ 1576static int sh_eth_phy_init(struct net_device *ndev) 1577{ 1578 struct sh_eth_private *mdp = netdev_priv(ndev); 1579 char phy_id[MII_BUS_ID_SIZE + 3]; 1580 struct phy_device *phydev = NULL; 1581 1582 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1583 mdp->mii_bus->id , mdp->phy_id); 1584 1585 mdp->link = 0; 1586 mdp->speed = 0; 1587 mdp->duplex = -1; 1588 1589 /* Try connect to PHY */ 1590 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1591 mdp->phy_interface); 1592 if (IS_ERR(phydev)) { 1593 dev_err(&ndev->dev, "phy_connect failed\n"); 1594 return PTR_ERR(phydev); 1595 } 1596 1597 dev_info(&ndev->dev, "attached phy %i to driver %s\n", 1598 phydev->addr, phydev->drv->name); 1599 1600 mdp->phydev = phydev; 1601 1602 return 0; 1603} 1604 1605/* PHY control start function */ 1606static int sh_eth_phy_start(struct net_device *ndev) 1607{ 1608 struct sh_eth_private *mdp = netdev_priv(ndev); 1609 int ret; 1610 1611 ret = sh_eth_phy_init(ndev); 1612 if (ret) 1613 return ret; 1614 1615 /* reset phy - this also wakes it from PDOWN */ 1616 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET); 1617 phy_start(mdp->phydev); 1618 1619 return 0; 1620} 1621 1622static int sh_eth_get_settings(struct net_device *ndev, 1623 struct ethtool_cmd *ecmd) 1624{ 1625 struct sh_eth_private *mdp = netdev_priv(ndev); 1626 unsigned long flags; 1627 int ret; 1628 1629 spin_lock_irqsave(&mdp->lock, flags); 1630 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1631 spin_unlock_irqrestore(&mdp->lock, flags); 1632 1633 return ret; 1634} 1635 1636static int sh_eth_set_settings(struct net_device *ndev, 1637 struct ethtool_cmd *ecmd) 1638{ 1639 struct sh_eth_private *mdp = netdev_priv(ndev); 1640 unsigned long flags; 1641 int ret; 1642 1643 spin_lock_irqsave(&mdp->lock, flags); 1644 1645 /* disable tx and rx */ 1646 sh_eth_rcv_snd_disable(ndev); 1647 1648 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1649 if (ret) 1650 goto error_exit; 1651 1652 if (ecmd->duplex == DUPLEX_FULL) 1653 mdp->duplex = 1; 1654 else 1655 mdp->duplex = 0; 1656 1657 if (mdp->cd->set_duplex) 1658 mdp->cd->set_duplex(ndev); 1659 1660error_exit: 1661 mdelay(1); 1662 1663 /* enable tx and rx */ 1664 sh_eth_rcv_snd_enable(ndev); 1665 1666 spin_unlock_irqrestore(&mdp->lock, flags); 1667 1668 return ret; 1669} 1670 1671static int sh_eth_nway_reset(struct net_device *ndev) 1672{ 1673 struct sh_eth_private *mdp = netdev_priv(ndev); 1674 unsigned long flags; 1675 int ret; 1676 1677 spin_lock_irqsave(&mdp->lock, flags); 1678 ret = phy_start_aneg(mdp->phydev); 1679 spin_unlock_irqrestore(&mdp->lock, flags); 1680 1681 return ret; 1682} 1683 1684static u32 sh_eth_get_msglevel(struct net_device *ndev) 1685{ 1686 struct sh_eth_private *mdp = netdev_priv(ndev); 1687 return mdp->msg_enable; 1688} 1689 1690static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 1691{ 1692 struct sh_eth_private *mdp = netdev_priv(ndev); 1693 mdp->msg_enable = value; 1694} 1695 1696static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 1697 "rx_current", "tx_current", 1698 "rx_dirty", "tx_dirty", 1699}; 1700#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 1701 1702static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 1703{ 1704 switch (sset) { 1705 case ETH_SS_STATS: 1706 return SH_ETH_STATS_LEN; 1707 default: 1708 return -EOPNOTSUPP; 1709 } 1710} 1711 1712static void sh_eth_get_ethtool_stats(struct net_device *ndev, 1713 struct ethtool_stats *stats, u64 *data) 1714{ 1715 struct sh_eth_private *mdp = netdev_priv(ndev); 1716 int i = 0; 1717 1718 /* device-specific stats */ 1719 data[i++] = mdp->cur_rx; 1720 data[i++] = mdp->cur_tx; 1721 data[i++] = mdp->dirty_rx; 1722 data[i++] = mdp->dirty_tx; 1723} 1724 1725static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1726{ 1727 switch (stringset) { 1728 case ETH_SS_STATS: 1729 memcpy(data, *sh_eth_gstrings_stats, 1730 sizeof(sh_eth_gstrings_stats)); 1731 break; 1732 } 1733} 1734 1735static void sh_eth_get_ringparam(struct net_device *ndev, 1736 struct ethtool_ringparam *ring) 1737{ 1738 struct sh_eth_private *mdp = netdev_priv(ndev); 1739 1740 ring->rx_max_pending = RX_RING_MAX; 1741 ring->tx_max_pending = TX_RING_MAX; 1742 ring->rx_pending = mdp->num_rx_ring; 1743 ring->tx_pending = mdp->num_tx_ring; 1744} 1745 1746static int sh_eth_set_ringparam(struct net_device *ndev, 1747 struct ethtool_ringparam *ring) 1748{ 1749 struct sh_eth_private *mdp = netdev_priv(ndev); 1750 int ret; 1751 1752 if (ring->tx_pending > TX_RING_MAX || 1753 ring->rx_pending > RX_RING_MAX || 1754 ring->tx_pending < TX_RING_MIN || 1755 ring->rx_pending < RX_RING_MIN) 1756 return -EINVAL; 1757 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1758 return -EINVAL; 1759 1760 if (netif_running(ndev)) { 1761 netif_tx_disable(ndev); 1762 /* Disable interrupts by clearing the interrupt mask. */ 1763 sh_eth_write(ndev, 0x0000, EESIPR); 1764 /* Stop the chip's Tx and Rx processes. */ 1765 sh_eth_write(ndev, 0, EDTRR); 1766 sh_eth_write(ndev, 0, EDRRR); 1767 synchronize_irq(ndev->irq); 1768 } 1769 1770 /* Free all the skbuffs in the Rx queue. */ 1771 sh_eth_ring_free(ndev); 1772 /* Free DMA buffer */ 1773 sh_eth_free_dma_buffer(mdp); 1774 1775 /* Set new parameters */ 1776 mdp->num_rx_ring = ring->rx_pending; 1777 mdp->num_tx_ring = ring->tx_pending; 1778 1779 ret = sh_eth_ring_init(ndev); 1780 if (ret < 0) { 1781 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__); 1782 return ret; 1783 } 1784 ret = sh_eth_dev_init(ndev, false); 1785 if (ret < 0) { 1786 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__); 1787 return ret; 1788 } 1789 1790 if (netif_running(ndev)) { 1791 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1792 /* Setting the Rx mode will start the Rx process. */ 1793 sh_eth_write(ndev, EDRRR_R, EDRRR); 1794 netif_wake_queue(ndev); 1795 } 1796 1797 return 0; 1798} 1799 1800static const struct ethtool_ops sh_eth_ethtool_ops = { 1801 .get_settings = sh_eth_get_settings, 1802 .set_settings = sh_eth_set_settings, 1803 .nway_reset = sh_eth_nway_reset, 1804 .get_msglevel = sh_eth_get_msglevel, 1805 .set_msglevel = sh_eth_set_msglevel, 1806 .get_link = ethtool_op_get_link, 1807 .get_strings = sh_eth_get_strings, 1808 .get_ethtool_stats = sh_eth_get_ethtool_stats, 1809 .get_sset_count = sh_eth_get_sset_count, 1810 .get_ringparam = sh_eth_get_ringparam, 1811 .set_ringparam = sh_eth_set_ringparam, 1812}; 1813 1814/* network device open function */ 1815static int sh_eth_open(struct net_device *ndev) 1816{ 1817 int ret = 0; 1818 struct sh_eth_private *mdp = netdev_priv(ndev); 1819 1820 pm_runtime_get_sync(&mdp->pdev->dev); 1821 1822 ret = request_irq(ndev->irq, sh_eth_interrupt, 1823 mdp->cd->irq_flags, ndev->name, ndev); 1824 if (ret) { 1825 dev_err(&ndev->dev, "Can not assign IRQ number\n"); 1826 return ret; 1827 } 1828 1829 /* Descriptor set */ 1830 ret = sh_eth_ring_init(ndev); 1831 if (ret) 1832 goto out_free_irq; 1833 1834 /* device init */ 1835 ret = sh_eth_dev_init(ndev, true); 1836 if (ret) 1837 goto out_free_irq; 1838 1839 /* PHY control start*/ 1840 ret = sh_eth_phy_start(ndev); 1841 if (ret) 1842 goto out_free_irq; 1843 1844 return ret; 1845 1846out_free_irq: 1847 free_irq(ndev->irq, ndev); 1848 pm_runtime_put_sync(&mdp->pdev->dev); 1849 return ret; 1850} 1851 1852/* Timeout function */ 1853static void sh_eth_tx_timeout(struct net_device *ndev) 1854{ 1855 struct sh_eth_private *mdp = netdev_priv(ndev); 1856 struct sh_eth_rxdesc *rxdesc; 1857 int i; 1858 1859 netif_stop_queue(ndev); 1860 1861 if (netif_msg_timer(mdp)) 1862 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x," 1863 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR)); 1864 1865 /* tx_errors count up */ 1866 ndev->stats.tx_errors++; 1867 1868 /* Free all the skbuffs in the Rx queue. */ 1869 for (i = 0; i < mdp->num_rx_ring; i++) { 1870 rxdesc = &mdp->rx_ring[i]; 1871 rxdesc->status = 0; 1872 rxdesc->addr = 0xBADF00D0; 1873 if (mdp->rx_skbuff[i]) 1874 dev_kfree_skb(mdp->rx_skbuff[i]); 1875 mdp->rx_skbuff[i] = NULL; 1876 } 1877 for (i = 0; i < mdp->num_tx_ring; i++) { 1878 if (mdp->tx_skbuff[i]) 1879 dev_kfree_skb(mdp->tx_skbuff[i]); 1880 mdp->tx_skbuff[i] = NULL; 1881 } 1882 1883 /* device init */ 1884 sh_eth_dev_init(ndev, true); 1885} 1886 1887/* Packet transmit function */ 1888static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1889{ 1890 struct sh_eth_private *mdp = netdev_priv(ndev); 1891 struct sh_eth_txdesc *txdesc; 1892 u32 entry; 1893 unsigned long flags; 1894 1895 spin_lock_irqsave(&mdp->lock, flags); 1896 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 1897 if (!sh_eth_txfree(ndev)) { 1898 if (netif_msg_tx_queued(mdp)) 1899 dev_warn(&ndev->dev, "TxFD exhausted.\n"); 1900 netif_stop_queue(ndev); 1901 spin_unlock_irqrestore(&mdp->lock, flags); 1902 return NETDEV_TX_BUSY; 1903 } 1904 } 1905 spin_unlock_irqrestore(&mdp->lock, flags); 1906 1907 entry = mdp->cur_tx % mdp->num_tx_ring; 1908 mdp->tx_skbuff[entry] = skb; 1909 txdesc = &mdp->tx_ring[entry]; 1910 /* soft swap. */ 1911 if (!mdp->cd->hw_swap) 1912 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), 1913 skb->len + 2); 1914 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, 1915 DMA_TO_DEVICE); 1916 if (skb->len < ETHERSMALL) 1917 txdesc->buffer_length = ETHERSMALL; 1918 else 1919 txdesc->buffer_length = skb->len; 1920 1921 if (entry >= mdp->num_tx_ring - 1) 1922 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 1923 else 1924 txdesc->status |= cpu_to_edmac(mdp, TD_TACT); 1925 1926 mdp->cur_tx++; 1927 1928 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 1929 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1930 1931 return NETDEV_TX_OK; 1932} 1933 1934/* device close function */ 1935static int sh_eth_close(struct net_device *ndev) 1936{ 1937 struct sh_eth_private *mdp = netdev_priv(ndev); 1938 1939 netif_stop_queue(ndev); 1940 1941 /* Disable interrupts by clearing the interrupt mask. */ 1942 sh_eth_write(ndev, 0x0000, EESIPR); 1943 1944 /* Stop the chip's Tx and Rx processes. */ 1945 sh_eth_write(ndev, 0, EDTRR); 1946 sh_eth_write(ndev, 0, EDRRR); 1947 1948 /* PHY Disconnect */ 1949 if (mdp->phydev) { 1950 phy_stop(mdp->phydev); 1951 phy_disconnect(mdp->phydev); 1952 } 1953 1954 free_irq(ndev->irq, ndev); 1955 1956 /* Free all the skbuffs in the Rx queue. */ 1957 sh_eth_ring_free(ndev); 1958 1959 /* free DMA buffer */ 1960 sh_eth_free_dma_buffer(mdp); 1961 1962 pm_runtime_put_sync(&mdp->pdev->dev); 1963 1964 return 0; 1965} 1966 1967static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 1968{ 1969 struct sh_eth_private *mdp = netdev_priv(ndev); 1970 1971 pm_runtime_get_sync(&mdp->pdev->dev); 1972 1973 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR); 1974 sh_eth_write(ndev, 0, TROCR); /* (write clear) */ 1975 ndev->stats.collisions += sh_eth_read(ndev, CDCR); 1976 sh_eth_write(ndev, 0, CDCR); /* (write clear) */ 1977 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); 1978 sh_eth_write(ndev, 0, LCCR); /* (write clear) */ 1979 if (sh_eth_is_gether(mdp)) { 1980 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR); 1981 sh_eth_write(ndev, 0, CERCR); /* (write clear) */ 1982 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR); 1983 sh_eth_write(ndev, 0, CEECR); /* (write clear) */ 1984 } else { 1985 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); 1986 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ 1987 } 1988 pm_runtime_put_sync(&mdp->pdev->dev); 1989 1990 return &ndev->stats; 1991} 1992 1993/* ioctl to device function */ 1994static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, 1995 int cmd) 1996{ 1997 struct sh_eth_private *mdp = netdev_priv(ndev); 1998 struct phy_device *phydev = mdp->phydev; 1999 2000 if (!netif_running(ndev)) 2001 return -EINVAL; 2002 2003 if (!phydev) 2004 return -ENODEV; 2005 2006 return phy_mii_ioctl(phydev, rq, cmd); 2007} 2008 2009/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2010static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2011 int entry) 2012{ 2013 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2014} 2015 2016static u32 sh_eth_tsu_get_post_mask(int entry) 2017{ 2018 return 0x0f << (28 - ((entry % 8) * 4)); 2019} 2020 2021static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2022{ 2023 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2024} 2025 2026static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2027 int entry) 2028{ 2029 struct sh_eth_private *mdp = netdev_priv(ndev); 2030 u32 tmp; 2031 void *reg_offset; 2032 2033 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2034 tmp = ioread32(reg_offset); 2035 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2036} 2037 2038static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2039 int entry) 2040{ 2041 struct sh_eth_private *mdp = netdev_priv(ndev); 2042 u32 post_mask, ref_mask, tmp; 2043 void *reg_offset; 2044 2045 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2046 post_mask = sh_eth_tsu_get_post_mask(entry); 2047 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2048 2049 tmp = ioread32(reg_offset); 2050 iowrite32(tmp & ~post_mask, reg_offset); 2051 2052 /* If other port enables, the function returns "true" */ 2053 return tmp & ref_mask; 2054} 2055 2056static int sh_eth_tsu_busy(struct net_device *ndev) 2057{ 2058 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2059 struct sh_eth_private *mdp = netdev_priv(ndev); 2060 2061 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2062 udelay(10); 2063 timeout--; 2064 if (timeout <= 0) { 2065 dev_err(&ndev->dev, "%s: timeout\n", __func__); 2066 return -ETIMEDOUT; 2067 } 2068 } 2069 2070 return 0; 2071} 2072 2073static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2074 const u8 *addr) 2075{ 2076 u32 val; 2077 2078 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2079 iowrite32(val, reg); 2080 if (sh_eth_tsu_busy(ndev) < 0) 2081 return -EBUSY; 2082 2083 val = addr[4] << 8 | addr[5]; 2084 iowrite32(val, reg + 4); 2085 if (sh_eth_tsu_busy(ndev) < 0) 2086 return -EBUSY; 2087 2088 return 0; 2089} 2090 2091static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2092{ 2093 u32 val; 2094 2095 val = ioread32(reg); 2096 addr[0] = (val >> 24) & 0xff; 2097 addr[1] = (val >> 16) & 0xff; 2098 addr[2] = (val >> 8) & 0xff; 2099 addr[3] = val & 0xff; 2100 val = ioread32(reg + 4); 2101 addr[4] = (val >> 8) & 0xff; 2102 addr[5] = val & 0xff; 2103} 2104 2105 2106static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2107{ 2108 struct sh_eth_private *mdp = netdev_priv(ndev); 2109 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2110 int i; 2111 u8 c_addr[ETH_ALEN]; 2112 2113 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2114 sh_eth_tsu_read_entry(reg_offset, c_addr); 2115 if (memcmp(addr, c_addr, ETH_ALEN) == 0) 2116 return i; 2117 } 2118 2119 return -ENOENT; 2120} 2121 2122static int sh_eth_tsu_find_empty(struct net_device *ndev) 2123{ 2124 u8 blank[ETH_ALEN]; 2125 int entry; 2126 2127 memset(blank, 0, sizeof(blank)); 2128 entry = sh_eth_tsu_find_entry(ndev, blank); 2129 return (entry < 0) ? -ENOMEM : entry; 2130} 2131 2132static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2133 int entry) 2134{ 2135 struct sh_eth_private *mdp = netdev_priv(ndev); 2136 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2137 int ret; 2138 u8 blank[ETH_ALEN]; 2139 2140 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2141 ~(1 << (31 - entry)), TSU_TEN); 2142 2143 memset(blank, 0, sizeof(blank)); 2144 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2145 if (ret < 0) 2146 return ret; 2147 return 0; 2148} 2149 2150static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2151{ 2152 struct sh_eth_private *mdp = netdev_priv(ndev); 2153 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2154 int i, ret; 2155 2156 if (!mdp->cd->tsu) 2157 return 0; 2158 2159 i = sh_eth_tsu_find_entry(ndev, addr); 2160 if (i < 0) { 2161 /* No entry found, create one */ 2162 i = sh_eth_tsu_find_empty(ndev); 2163 if (i < 0) 2164 return -ENOMEM; 2165 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2166 if (ret < 0) 2167 return ret; 2168 2169 /* Enable the entry */ 2170 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2171 (1 << (31 - i)), TSU_TEN); 2172 } 2173 2174 /* Entry found or created, enable POST */ 2175 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2176 2177 return 0; 2178} 2179 2180static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2181{ 2182 struct sh_eth_private *mdp = netdev_priv(ndev); 2183 int i, ret; 2184 2185 if (!mdp->cd->tsu) 2186 return 0; 2187 2188 i = sh_eth_tsu_find_entry(ndev, addr); 2189 if (i) { 2190 /* Entry found */ 2191 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2192 goto done; 2193 2194 /* Disable the entry if both ports was disabled */ 2195 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2196 if (ret < 0) 2197 return ret; 2198 } 2199done: 2200 return 0; 2201} 2202 2203static int sh_eth_tsu_purge_all(struct net_device *ndev) 2204{ 2205 struct sh_eth_private *mdp = netdev_priv(ndev); 2206 int i, ret; 2207 2208 if (unlikely(!mdp->cd->tsu)) 2209 return 0; 2210 2211 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2212 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2213 continue; 2214 2215 /* Disable the entry if both ports was disabled */ 2216 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2217 if (ret < 0) 2218 return ret; 2219 } 2220 2221 return 0; 2222} 2223 2224static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2225{ 2226 struct sh_eth_private *mdp = netdev_priv(ndev); 2227 u8 addr[ETH_ALEN]; 2228 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2229 int i; 2230 2231 if (unlikely(!mdp->cd->tsu)) 2232 return; 2233 2234 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2235 sh_eth_tsu_read_entry(reg_offset, addr); 2236 if (is_multicast_ether_addr(addr)) 2237 sh_eth_tsu_del_entry(ndev, addr); 2238 } 2239} 2240 2241/* Multicast reception directions set */ 2242static void sh_eth_set_multicast_list(struct net_device *ndev) 2243{ 2244 struct sh_eth_private *mdp = netdev_priv(ndev); 2245 u32 ecmr_bits; 2246 int mcast_all = 0; 2247 unsigned long flags; 2248 2249 spin_lock_irqsave(&mdp->lock, flags); 2250 /* 2251 * Initial condition is MCT = 1, PRM = 0. 2252 * Depending on ndev->flags, set PRM or clear MCT 2253 */ 2254 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT; 2255 2256 if (!(ndev->flags & IFF_MULTICAST)) { 2257 sh_eth_tsu_purge_mcast(ndev); 2258 mcast_all = 1; 2259 } 2260 if (ndev->flags & IFF_ALLMULTI) { 2261 sh_eth_tsu_purge_mcast(ndev); 2262 ecmr_bits &= ~ECMR_MCT; 2263 mcast_all = 1; 2264 } 2265 2266 if (ndev->flags & IFF_PROMISC) { 2267 sh_eth_tsu_purge_all(ndev); 2268 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2269 } else if (mdp->cd->tsu) { 2270 struct netdev_hw_addr *ha; 2271 netdev_for_each_mc_addr(ha, ndev) { 2272 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2273 continue; 2274 2275 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2276 if (!mcast_all) { 2277 sh_eth_tsu_purge_mcast(ndev); 2278 ecmr_bits &= ~ECMR_MCT; 2279 mcast_all = 1; 2280 } 2281 } 2282 } 2283 } else { 2284 /* Normal, unicast/broadcast-only mode. */ 2285 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT; 2286 } 2287 2288 /* update the ethernet mode */ 2289 sh_eth_write(ndev, ecmr_bits, ECMR); 2290 2291 spin_unlock_irqrestore(&mdp->lock, flags); 2292} 2293 2294static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2295{ 2296 if (!mdp->port) 2297 return TSU_VTAG0; 2298 else 2299 return TSU_VTAG1; 2300} 2301 2302static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2303 __be16 proto, u16 vid) 2304{ 2305 struct sh_eth_private *mdp = netdev_priv(ndev); 2306 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2307 2308 if (unlikely(!mdp->cd->tsu)) 2309 return -EPERM; 2310 2311 /* No filtering if vid = 0 */ 2312 if (!vid) 2313 return 0; 2314 2315 mdp->vlan_num_ids++; 2316 2317 /* 2318 * The controller has one VLAN tag HW filter. So, if the filter is 2319 * already enabled, the driver disables it and the filte 2320 */ 2321 if (mdp->vlan_num_ids > 1) { 2322 /* disable VLAN filter */ 2323 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2324 return 0; 2325 } 2326 2327 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2328 vtag_reg_index); 2329 2330 return 0; 2331} 2332 2333static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2334 __be16 proto, u16 vid) 2335{ 2336 struct sh_eth_private *mdp = netdev_priv(ndev); 2337 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2338 2339 if (unlikely(!mdp->cd->tsu)) 2340 return -EPERM; 2341 2342 /* No filtering if vid = 0 */ 2343 if (!vid) 2344 return 0; 2345 2346 mdp->vlan_num_ids--; 2347 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2348 2349 return 0; 2350} 2351 2352/* SuperH's TSU register init function */ 2353static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2354{ 2355 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2356 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2357 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2358 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2359 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2360 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2361 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2362 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2363 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2364 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2365 if (sh_eth_is_gether(mdp)) { 2366 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2367 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2368 } else { 2369 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2370 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2371 } 2372 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2373 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2374 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2375 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2376 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2377 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2378 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2379} 2380 2381/* MDIO bus release function */ 2382static int sh_mdio_release(struct net_device *ndev) 2383{ 2384 struct mii_bus *bus = dev_get_drvdata(&ndev->dev); 2385 2386 /* unregister mdio bus */ 2387 mdiobus_unregister(bus); 2388 2389 /* remove mdio bus info from net_device */ 2390 dev_set_drvdata(&ndev->dev, NULL); 2391 2392 /* free bitbang info */ 2393 free_mdio_bitbang(bus); 2394 2395 return 0; 2396} 2397 2398/* MDIO bus init function */ 2399static int sh_mdio_init(struct net_device *ndev, int id, 2400 struct sh_eth_plat_data *pd) 2401{ 2402 int ret, i; 2403 struct bb_info *bitbang; 2404 struct sh_eth_private *mdp = netdev_priv(ndev); 2405 2406 /* create bit control struct for PHY */ 2407 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info), 2408 GFP_KERNEL); 2409 if (!bitbang) { 2410 ret = -ENOMEM; 2411 goto out; 2412 } 2413 2414 /* bitbang init */ 2415 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2416 bitbang->set_gate = pd->set_mdio_gate; 2417 bitbang->mdi_msk = PIR_MDI; 2418 bitbang->mdo_msk = PIR_MDO; 2419 bitbang->mmd_msk = PIR_MMD; 2420 bitbang->mdc_msk = PIR_MDC; 2421 bitbang->ctrl.ops = &bb_ops; 2422 2423 /* MII controller setting */ 2424 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2425 if (!mdp->mii_bus) { 2426 ret = -ENOMEM; 2427 goto out; 2428 } 2429 2430 /* Hook up MII support for ethtool */ 2431 mdp->mii_bus->name = "sh_mii"; 2432 mdp->mii_bus->parent = &ndev->dev; 2433 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2434 mdp->pdev->name, id); 2435 2436 /* PHY IRQ */ 2437 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev, 2438 sizeof(int) * PHY_MAX_ADDR, 2439 GFP_KERNEL); 2440 if (!mdp->mii_bus->irq) { 2441 ret = -ENOMEM; 2442 goto out_free_bus; 2443 } 2444 2445 for (i = 0; i < PHY_MAX_ADDR; i++) 2446 mdp->mii_bus->irq[i] = PHY_POLL; 2447 2448 /* register mdio bus */ 2449 ret = mdiobus_register(mdp->mii_bus); 2450 if (ret) 2451 goto out_free_bus; 2452 2453 dev_set_drvdata(&ndev->dev, mdp->mii_bus); 2454 2455 return 0; 2456 2457out_free_bus: 2458 free_mdio_bitbang(mdp->mii_bus); 2459 2460out: 2461 return ret; 2462} 2463 2464static const u16 *sh_eth_get_register_offset(int register_type) 2465{ 2466 const u16 *reg_offset = NULL; 2467 2468 switch (register_type) { 2469 case SH_ETH_REG_GIGABIT: 2470 reg_offset = sh_eth_offset_gigabit; 2471 break; 2472 case SH_ETH_REG_FAST_RCAR: 2473 reg_offset = sh_eth_offset_fast_rcar; 2474 break; 2475 case SH_ETH_REG_FAST_SH4: 2476 reg_offset = sh_eth_offset_fast_sh4; 2477 break; 2478 case SH_ETH_REG_FAST_SH3_SH2: 2479 reg_offset = sh_eth_offset_fast_sh3_sh2; 2480 break; 2481 default: 2482 pr_err("Unknown register type (%d)\n", register_type); 2483 break; 2484 } 2485 2486 return reg_offset; 2487} 2488 2489static const struct net_device_ops sh_eth_netdev_ops = { 2490 .ndo_open = sh_eth_open, 2491 .ndo_stop = sh_eth_close, 2492 .ndo_start_xmit = sh_eth_start_xmit, 2493 .ndo_get_stats = sh_eth_get_stats, 2494 .ndo_tx_timeout = sh_eth_tx_timeout, 2495 .ndo_do_ioctl = sh_eth_do_ioctl, 2496 .ndo_validate_addr = eth_validate_addr, 2497 .ndo_set_mac_address = eth_mac_addr, 2498 .ndo_change_mtu = eth_change_mtu, 2499}; 2500 2501static const struct net_device_ops sh_eth_netdev_ops_tsu = { 2502 .ndo_open = sh_eth_open, 2503 .ndo_stop = sh_eth_close, 2504 .ndo_start_xmit = sh_eth_start_xmit, 2505 .ndo_get_stats = sh_eth_get_stats, 2506 .ndo_set_rx_mode = sh_eth_set_multicast_list, 2507 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 2508 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 2509 .ndo_tx_timeout = sh_eth_tx_timeout, 2510 .ndo_do_ioctl = sh_eth_do_ioctl, 2511 .ndo_validate_addr = eth_validate_addr, 2512 .ndo_set_mac_address = eth_mac_addr, 2513 .ndo_change_mtu = eth_change_mtu, 2514}; 2515 2516static int sh_eth_drv_probe(struct platform_device *pdev) 2517{ 2518 int ret, devno = 0; 2519 struct resource *res; 2520 struct net_device *ndev = NULL; 2521 struct sh_eth_private *mdp = NULL; 2522 struct sh_eth_plat_data *pd = pdev->dev.platform_data; 2523 const struct platform_device_id *id = platform_get_device_id(pdev); 2524 2525 /* get base addr */ 2526 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2527 if (unlikely(res == NULL)) { 2528 dev_err(&pdev->dev, "invalid resource\n"); 2529 ret = -EINVAL; 2530 goto out; 2531 } 2532 2533 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 2534 if (!ndev) { 2535 ret = -ENOMEM; 2536 goto out; 2537 } 2538 2539 /* The sh Ether-specific entries in the device structure. */ 2540 ndev->base_addr = res->start; 2541 devno = pdev->id; 2542 if (devno < 0) 2543 devno = 0; 2544 2545 ndev->dma = -1; 2546 ret = platform_get_irq(pdev, 0); 2547 if (ret < 0) { 2548 ret = -ENODEV; 2549 goto out_release; 2550 } 2551 ndev->irq = ret; 2552 2553 SET_NETDEV_DEV(ndev, &pdev->dev); 2554 2555 /* Fill in the fields of the device structure with ethernet values. */ 2556 ether_setup(ndev); 2557 2558 mdp = netdev_priv(ndev); 2559 mdp->num_tx_ring = TX_RING_SIZE; 2560 mdp->num_rx_ring = RX_RING_SIZE; 2561 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 2562 if (IS_ERR(mdp->addr)) { 2563 ret = PTR_ERR(mdp->addr); 2564 goto out_release; 2565 } 2566 2567 spin_lock_init(&mdp->lock); 2568 mdp->pdev = pdev; 2569 pm_runtime_enable(&pdev->dev); 2570 pm_runtime_resume(&pdev->dev); 2571 2572 /* get PHY ID */ 2573 mdp->phy_id = pd->phy; 2574 mdp->phy_interface = pd->phy_interface; 2575 /* EDMAC endian */ 2576 mdp->edmac_endian = pd->edmac_endian; 2577 mdp->no_ether_link = pd->no_ether_link; 2578 mdp->ether_link_active_low = pd->ether_link_active_low; 2579 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type); 2580 2581 /* set cpu data */ 2582 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 2583 sh_eth_set_default_cpu_data(mdp->cd); 2584 2585 /* set function */ 2586 if (mdp->cd->tsu) 2587 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 2588 else 2589 ndev->netdev_ops = &sh_eth_netdev_ops; 2590 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); 2591 ndev->watchdog_timeo = TX_TIMEOUT; 2592 2593 /* debug message level */ 2594 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 2595 2596 /* read and set MAC address */ 2597 read_mac_address(ndev, pd->mac_addr); 2598 if (!is_valid_ether_addr(ndev->dev_addr)) { 2599 dev_warn(&pdev->dev, 2600 "no valid MAC address supplied, using a random one.\n"); 2601 eth_hw_addr_random(ndev); 2602 } 2603 2604 /* ioremap the TSU registers */ 2605 if (mdp->cd->tsu) { 2606 struct resource *rtsu; 2607 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2608 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); 2609 if (IS_ERR(mdp->tsu_addr)) { 2610 ret = PTR_ERR(mdp->tsu_addr); 2611 goto out_release; 2612 } 2613 mdp->port = devno % 2; 2614 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 2615 } 2616 2617 /* initialize first or needed device */ 2618 if (!devno || pd->needs_init) { 2619 if (mdp->cd->chip_reset) 2620 mdp->cd->chip_reset(ndev); 2621 2622 if (mdp->cd->tsu) { 2623 /* TSU init (Init only)*/ 2624 sh_eth_tsu_init(mdp); 2625 } 2626 } 2627 2628 /* network device register */ 2629 ret = register_netdev(ndev); 2630 if (ret) 2631 goto out_release; 2632 2633 /* mdio bus init */ 2634 ret = sh_mdio_init(ndev, pdev->id, pd); 2635 if (ret) 2636 goto out_unregister; 2637 2638 /* print device information */ 2639 pr_info("Base address at 0x%x, %pM, IRQ %d.\n", 2640 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2641 2642 platform_set_drvdata(pdev, ndev); 2643 2644 return ret; 2645 2646out_unregister: 2647 unregister_netdev(ndev); 2648 2649out_release: 2650 /* net_dev free */ 2651 if (ndev) 2652 free_netdev(ndev); 2653 2654out: 2655 return ret; 2656} 2657 2658static int sh_eth_drv_remove(struct platform_device *pdev) 2659{ 2660 struct net_device *ndev = platform_get_drvdata(pdev); 2661 2662 sh_mdio_release(ndev); 2663 unregister_netdev(ndev); 2664 pm_runtime_disable(&pdev->dev); 2665 free_netdev(ndev); 2666 2667 return 0; 2668} 2669 2670#ifdef CONFIG_PM 2671static int sh_eth_runtime_nop(struct device *dev) 2672{ 2673 /* 2674 * Runtime PM callback shared between ->runtime_suspend() 2675 * and ->runtime_resume(). Simply returns success. 2676 * 2677 * This driver re-initializes all registers after 2678 * pm_runtime_get_sync() anyway so there is no need 2679 * to save and restore registers here. 2680 */ 2681 return 0; 2682} 2683 2684static const struct dev_pm_ops sh_eth_dev_pm_ops = { 2685 .runtime_suspend = sh_eth_runtime_nop, 2686 .runtime_resume = sh_eth_runtime_nop, 2687}; 2688#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 2689#else 2690#define SH_ETH_PM_OPS NULL 2691#endif 2692 2693static struct platform_device_id sh_eth_id_table[] = { 2694 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 2695 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 2696 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 2697 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 2698 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 2699 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 2700 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 2701 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, 2702 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data }, 2703 { } 2704}; 2705MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 2706 2707static struct platform_driver sh_eth_driver = { 2708 .probe = sh_eth_drv_probe, 2709 .remove = sh_eth_drv_remove, 2710 .id_table = sh_eth_id_table, 2711 .driver = { 2712 .name = CARDNAME, 2713 .pm = SH_ETH_PM_OPS, 2714 }, 2715}; 2716 2717module_platform_driver(sh_eth_driver); 2718 2719MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 2720MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 2721MODULE_LICENSE("GPL v2"); 2722