sh_eth.c revision a18e08bdcf845efb7344cea146e683df746bbfb4
1/* 2 * SuperH Ethernet device driver 3 * 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2012 Renesas Solutions Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 */ 22 23#include <linux/init.h> 24#include <linux/module.h> 25#include <linux/kernel.h> 26#include <linux/spinlock.h> 27#include <linux/interrupt.h> 28#include <linux/dma-mapping.h> 29#include <linux/etherdevice.h> 30#include <linux/delay.h> 31#include <linux/platform_device.h> 32#include <linux/mdio-bitbang.h> 33#include <linux/netdevice.h> 34#include <linux/phy.h> 35#include <linux/cache.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38#include <linux/slab.h> 39#include <linux/ethtool.h> 40#include <linux/if_vlan.h> 41#include <linux/clk.h> 42#include <linux/sh_eth.h> 43 44#include "sh_eth.h" 45 46#define SH_ETH_DEF_MSG_ENABLE \ 47 (NETIF_MSG_LINK | \ 48 NETIF_MSG_TIMER | \ 49 NETIF_MSG_RX_ERR| \ 50 NETIF_MSG_TX_ERR) 51 52/* There is CPU dependent code */ 53#if defined(CONFIG_CPU_SUBTYPE_SH7724) 54#define SH_ETH_RESET_DEFAULT 1 55static void sh_eth_set_duplex(struct net_device *ndev) 56{ 57 struct sh_eth_private *mdp = netdev_priv(ndev); 58 59 if (mdp->duplex) /* Full */ 60 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 61 else /* Half */ 62 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 63} 64 65static void sh_eth_set_rate(struct net_device *ndev) 66{ 67 struct sh_eth_private *mdp = netdev_priv(ndev); 68 69 switch (mdp->speed) { 70 case 10: /* 10BASE */ 71 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 72 break; 73 case 100:/* 100BASE */ 74 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 75 break; 76 default: 77 break; 78 } 79} 80 81/* SH7724 */ 82static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 83 .set_duplex = sh_eth_set_duplex, 84 .set_rate = sh_eth_set_rate, 85 86 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 87 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 88 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f, 89 90 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 91 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 92 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 93 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 94 95 .apr = 1, 96 .mpr = 1, 97 .tpauser = 1, 98 .hw_swap = 1, 99 .rpadir = 1, 100 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 101}; 102#elif defined(CONFIG_CPU_SUBTYPE_SH7757) 103#define SH_ETH_HAS_BOTH_MODULES 1 104#define SH_ETH_HAS_TSU 1 105static void sh_eth_set_duplex(struct net_device *ndev) 106{ 107 struct sh_eth_private *mdp = netdev_priv(ndev); 108 109 if (mdp->duplex) /* Full */ 110 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 111 else /* Half */ 112 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 113} 114 115static void sh_eth_set_rate(struct net_device *ndev) 116{ 117 struct sh_eth_private *mdp = netdev_priv(ndev); 118 119 switch (mdp->speed) { 120 case 10: /* 10BASE */ 121 sh_eth_write(ndev, 0, RTRATE); 122 break; 123 case 100:/* 100BASE */ 124 sh_eth_write(ndev, 1, RTRATE); 125 break; 126 default: 127 break; 128 } 129} 130 131/* SH7757 */ 132static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 133 .set_duplex = sh_eth_set_duplex, 134 .set_rate = sh_eth_set_rate, 135 136 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 137 .rmcr_value = 0x00000001, 138 139 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 140 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | 141 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, 142 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, 143 144 .apr = 1, 145 .mpr = 1, 146 .tpauser = 1, 147 .hw_swap = 1, 148 .no_ade = 1, 149 .rpadir = 1, 150 .rpadir_value = 2 << 16, 151}; 152 153#define SH_GIGA_ETH_BASE 0xfee00000 154#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 155#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 156static void sh_eth_chip_reset_giga(struct net_device *ndev) 157{ 158 int i; 159 unsigned long mahr[2], malr[2]; 160 161 /* save MAHR and MALR */ 162 for (i = 0; i < 2; i++) { 163 malr[i] = ioread32((void *)GIGA_MALR(i)); 164 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 165 } 166 167 /* reset device */ 168 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 169 mdelay(1); 170 171 /* restore MAHR and MALR */ 172 for (i = 0; i < 2; i++) { 173 iowrite32(malr[i], (void *)GIGA_MALR(i)); 174 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 175 } 176} 177 178static int sh_eth_is_gether(struct sh_eth_private *mdp); 179static void sh_eth_reset(struct net_device *ndev) 180{ 181 struct sh_eth_private *mdp = netdev_priv(ndev); 182 int cnt = 100; 183 184 if (sh_eth_is_gether(mdp)) { 185 sh_eth_write(ndev, 0x03, EDSR); 186 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 187 EDMR); 188 while (cnt > 0) { 189 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 190 break; 191 mdelay(1); 192 cnt--; 193 } 194 if (cnt < 0) 195 printk(KERN_ERR "Device reset fail\n"); 196 197 /* Table Init */ 198 sh_eth_write(ndev, 0x0, TDLAR); 199 sh_eth_write(ndev, 0x0, TDFAR); 200 sh_eth_write(ndev, 0x0, TDFXR); 201 sh_eth_write(ndev, 0x0, TDFFR); 202 sh_eth_write(ndev, 0x0, RDLAR); 203 sh_eth_write(ndev, 0x0, RDFAR); 204 sh_eth_write(ndev, 0x0, RDFXR); 205 sh_eth_write(ndev, 0x0, RDFFR); 206 } else { 207 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 208 EDMR); 209 mdelay(3); 210 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 211 EDMR); 212 } 213} 214 215static void sh_eth_set_duplex_giga(struct net_device *ndev) 216{ 217 struct sh_eth_private *mdp = netdev_priv(ndev); 218 219 if (mdp->duplex) /* Full */ 220 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 221 else /* Half */ 222 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 223} 224 225static void sh_eth_set_rate_giga(struct net_device *ndev) 226{ 227 struct sh_eth_private *mdp = netdev_priv(ndev); 228 229 switch (mdp->speed) { 230 case 10: /* 10BASE */ 231 sh_eth_write(ndev, 0x00000000, GECMR); 232 break; 233 case 100:/* 100BASE */ 234 sh_eth_write(ndev, 0x00000010, GECMR); 235 break; 236 case 1000: /* 1000BASE */ 237 sh_eth_write(ndev, 0x00000020, GECMR); 238 break; 239 default: 240 break; 241 } 242} 243 244/* SH7757(GETHERC) */ 245static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = { 246 .chip_reset = sh_eth_chip_reset_giga, 247 .set_duplex = sh_eth_set_duplex_giga, 248 .set_rate = sh_eth_set_rate_giga, 249 250 .ecsr_value = ECSR_ICD | ECSR_MPD, 251 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 252 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 253 254 .tx_check = EESR_TC1 | EESR_FTC, 255 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 256 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 257 EESR_ECI, 258 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 259 EESR_TFE, 260 .fdr_value = 0x0000072f, 261 .rmcr_value = 0x00000001, 262 263 .apr = 1, 264 .mpr = 1, 265 .tpauser = 1, 266 .bculr = 1, 267 .hw_swap = 1, 268 .rpadir = 1, 269 .rpadir_value = 2 << 16, 270 .no_trimd = 1, 271 .no_ade = 1, 272 .tsu = 1, 273}; 274 275static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp) 276{ 277 if (sh_eth_is_gether(mdp)) 278 return &sh_eth_my_cpu_data_giga; 279 else 280 return &sh_eth_my_cpu_data; 281} 282 283#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) 284#define SH_ETH_HAS_TSU 1 285static void sh_eth_reset_hw_crc(struct net_device *ndev); 286static void sh_eth_chip_reset(struct net_device *ndev) 287{ 288 struct sh_eth_private *mdp = netdev_priv(ndev); 289 290 /* reset device */ 291 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 292 mdelay(1); 293} 294 295static void sh_eth_reset(struct net_device *ndev) 296{ 297 int cnt = 100; 298 299 sh_eth_write(ndev, EDSR_ENALL, EDSR); 300 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); 301 while (cnt > 0) { 302 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 303 break; 304 mdelay(1); 305 cnt--; 306 } 307 if (cnt == 0) 308 printk(KERN_ERR "Device reset fail\n"); 309 310 /* Table Init */ 311 sh_eth_write(ndev, 0x0, TDLAR); 312 sh_eth_write(ndev, 0x0, TDFAR); 313 sh_eth_write(ndev, 0x0, TDFXR); 314 sh_eth_write(ndev, 0x0, TDFFR); 315 sh_eth_write(ndev, 0x0, RDLAR); 316 sh_eth_write(ndev, 0x0, RDFAR); 317 sh_eth_write(ndev, 0x0, RDFXR); 318 sh_eth_write(ndev, 0x0, RDFFR); 319 320 /* Reset HW CRC register */ 321 sh_eth_reset_hw_crc(ndev); 322} 323 324static void sh_eth_set_duplex(struct net_device *ndev) 325{ 326 struct sh_eth_private *mdp = netdev_priv(ndev); 327 328 if (mdp->duplex) /* Full */ 329 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 330 else /* Half */ 331 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 332} 333 334static void sh_eth_set_rate(struct net_device *ndev) 335{ 336 struct sh_eth_private *mdp = netdev_priv(ndev); 337 338 switch (mdp->speed) { 339 case 10: /* 10BASE */ 340 sh_eth_write(ndev, GECMR_10, GECMR); 341 break; 342 case 100:/* 100BASE */ 343 sh_eth_write(ndev, GECMR_100, GECMR); 344 break; 345 case 1000: /* 1000BASE */ 346 sh_eth_write(ndev, GECMR_1000, GECMR); 347 break; 348 default: 349 break; 350 } 351} 352 353/* sh7763 */ 354static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 355 .chip_reset = sh_eth_chip_reset, 356 .set_duplex = sh_eth_set_duplex, 357 .set_rate = sh_eth_set_rate, 358 359 .ecsr_value = ECSR_ICD | ECSR_MPD, 360 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 361 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 362 363 .tx_check = EESR_TC1 | EESR_FTC, 364 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 365 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 366 EESR_ECI, 367 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 368 EESR_TFE, 369 370 .apr = 1, 371 .mpr = 1, 372 .tpauser = 1, 373 .bculr = 1, 374 .hw_swap = 1, 375 .no_trimd = 1, 376 .no_ade = 1, 377 .tsu = 1, 378#if defined(CONFIG_CPU_SUBTYPE_SH7734) 379 .hw_crc = 1, 380#endif 381}; 382 383static void sh_eth_reset_hw_crc(struct net_device *ndev) 384{ 385 if (sh_eth_my_cpu_data.hw_crc) 386 sh_eth_write(ndev, 0x0, CSMR); 387} 388 389#elif defined(CONFIG_ARCH_R8A7740) 390#define SH_ETH_HAS_TSU 1 391static void sh_eth_chip_reset(struct net_device *ndev) 392{ 393 struct sh_eth_private *mdp = netdev_priv(ndev); 394 unsigned long mii; 395 396 /* reset device */ 397 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 398 mdelay(1); 399 400 switch (mdp->phy_interface) { 401 case PHY_INTERFACE_MODE_GMII: 402 mii = 2; 403 break; 404 case PHY_INTERFACE_MODE_MII: 405 mii = 1; 406 break; 407 case PHY_INTERFACE_MODE_RMII: 408 default: 409 mii = 0; 410 break; 411 } 412 sh_eth_write(ndev, mii, RMII_MII); 413} 414 415static void sh_eth_reset(struct net_device *ndev) 416{ 417 int cnt = 100; 418 419 sh_eth_write(ndev, EDSR_ENALL, EDSR); 420 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); 421 while (cnt > 0) { 422 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 423 break; 424 mdelay(1); 425 cnt--; 426 } 427 if (cnt == 0) 428 printk(KERN_ERR "Device reset fail\n"); 429 430 /* Table Init */ 431 sh_eth_write(ndev, 0x0, TDLAR); 432 sh_eth_write(ndev, 0x0, TDFAR); 433 sh_eth_write(ndev, 0x0, TDFXR); 434 sh_eth_write(ndev, 0x0, TDFFR); 435 sh_eth_write(ndev, 0x0, RDLAR); 436 sh_eth_write(ndev, 0x0, RDFAR); 437 sh_eth_write(ndev, 0x0, RDFXR); 438 sh_eth_write(ndev, 0x0, RDFFR); 439} 440 441static void sh_eth_set_duplex(struct net_device *ndev) 442{ 443 struct sh_eth_private *mdp = netdev_priv(ndev); 444 445 if (mdp->duplex) /* Full */ 446 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 447 else /* Half */ 448 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 449} 450 451static void sh_eth_set_rate(struct net_device *ndev) 452{ 453 struct sh_eth_private *mdp = netdev_priv(ndev); 454 455 switch (mdp->speed) { 456 case 10: /* 10BASE */ 457 sh_eth_write(ndev, GECMR_10, GECMR); 458 break; 459 case 100:/* 100BASE */ 460 sh_eth_write(ndev, GECMR_100, GECMR); 461 break; 462 case 1000: /* 1000BASE */ 463 sh_eth_write(ndev, GECMR_1000, GECMR); 464 break; 465 default: 466 break; 467 } 468} 469 470/* R8A7740 */ 471static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 472 .chip_reset = sh_eth_chip_reset, 473 .set_duplex = sh_eth_set_duplex, 474 .set_rate = sh_eth_set_rate, 475 476 .ecsr_value = ECSR_ICD | ECSR_MPD, 477 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 478 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 479 480 .tx_check = EESR_TC1 | EESR_FTC, 481 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 482 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 483 EESR_ECI, 484 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ 485 EESR_TFE, 486 487 .apr = 1, 488 .mpr = 1, 489 .tpauser = 1, 490 .bculr = 1, 491 .hw_swap = 1, 492 .no_trimd = 1, 493 .no_ade = 1, 494 .tsu = 1, 495}; 496 497#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 498#define SH_ETH_RESET_DEFAULT 1 499static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 500 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 501 502 .apr = 1, 503 .mpr = 1, 504 .tpauser = 1, 505 .hw_swap = 1, 506}; 507#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 508#define SH_ETH_RESET_DEFAULT 1 509#define SH_ETH_HAS_TSU 1 510static struct sh_eth_cpu_data sh_eth_my_cpu_data = { 511 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 512 .tsu = 1, 513}; 514#endif 515 516static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 517{ 518 if (!cd->ecsr_value) 519 cd->ecsr_value = DEFAULT_ECSR_INIT; 520 521 if (!cd->ecsipr_value) 522 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 523 524 if (!cd->fcftr_value) 525 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \ 526 DEFAULT_FIFO_F_D_RFD; 527 528 if (!cd->fdr_value) 529 cd->fdr_value = DEFAULT_FDR_INIT; 530 531 if (!cd->rmcr_value) 532 cd->rmcr_value = DEFAULT_RMCR_VALUE; 533 534 if (!cd->tx_check) 535 cd->tx_check = DEFAULT_TX_CHECK; 536 537 if (!cd->eesr_err_check) 538 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 539 540 if (!cd->tx_error_check) 541 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; 542} 543 544#if defined(SH_ETH_RESET_DEFAULT) 545/* Chip Reset */ 546static void sh_eth_reset(struct net_device *ndev) 547{ 548 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR); 549 mdelay(3); 550 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR); 551} 552#endif 553 554#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 555static void sh_eth_set_receive_align(struct sk_buff *skb) 556{ 557 int reserve; 558 559 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); 560 if (reserve) 561 skb_reserve(skb, reserve); 562} 563#else 564static void sh_eth_set_receive_align(struct sk_buff *skb) 565{ 566 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); 567} 568#endif 569 570 571/* CPU <-> EDMAC endian convert */ 572static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 573{ 574 switch (mdp->edmac_endian) { 575 case EDMAC_LITTLE_ENDIAN: 576 return cpu_to_le32(x); 577 case EDMAC_BIG_ENDIAN: 578 return cpu_to_be32(x); 579 } 580 return x; 581} 582 583static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) 584{ 585 switch (mdp->edmac_endian) { 586 case EDMAC_LITTLE_ENDIAN: 587 return le32_to_cpu(x); 588 case EDMAC_BIG_ENDIAN: 589 return be32_to_cpu(x); 590 } 591 return x; 592} 593 594/* 595 * Program the hardware MAC address from dev->dev_addr. 596 */ 597static void update_mac_address(struct net_device *ndev) 598{ 599 sh_eth_write(ndev, 600 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 601 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 602 sh_eth_write(ndev, 603 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 604} 605 606/* 607 * Get MAC address from SuperH MAC address register 608 * 609 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 610 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 611 * When you want use this device, you must set MAC address in bootloader. 612 * 613 */ 614static void read_mac_address(struct net_device *ndev, unsigned char *mac) 615{ 616 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 617 memcpy(ndev->dev_addr, mac, 6); 618 } else { 619 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24); 620 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF; 621 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF; 622 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF); 623 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF; 624 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF); 625 } 626} 627 628static int sh_eth_is_gether(struct sh_eth_private *mdp) 629{ 630 if (mdp->reg_offset == sh_eth_offset_gigabit) 631 return 1; 632 else 633 return 0; 634} 635 636static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 637{ 638 if (sh_eth_is_gether(mdp)) 639 return EDTRR_TRNS_GETHER; 640 else 641 return EDTRR_TRNS_ETHER; 642} 643 644struct bb_info { 645 void (*set_gate)(void *addr); 646 struct mdiobb_ctrl ctrl; 647 void *addr; 648 u32 mmd_msk;/* MMD */ 649 u32 mdo_msk; 650 u32 mdi_msk; 651 u32 mdc_msk; 652}; 653 654/* PHY bit set */ 655static void bb_set(void *addr, u32 msk) 656{ 657 iowrite32(ioread32(addr) | msk, addr); 658} 659 660/* PHY bit clear */ 661static void bb_clr(void *addr, u32 msk) 662{ 663 iowrite32((ioread32(addr) & ~msk), addr); 664} 665 666/* PHY bit read */ 667static int bb_read(void *addr, u32 msk) 668{ 669 return (ioread32(addr) & msk) != 0; 670} 671 672/* Data I/O pin control */ 673static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 674{ 675 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 676 677 if (bitbang->set_gate) 678 bitbang->set_gate(bitbang->addr); 679 680 if (bit) 681 bb_set(bitbang->addr, bitbang->mmd_msk); 682 else 683 bb_clr(bitbang->addr, bitbang->mmd_msk); 684} 685 686/* Set bit data*/ 687static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 688{ 689 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 690 691 if (bitbang->set_gate) 692 bitbang->set_gate(bitbang->addr); 693 694 if (bit) 695 bb_set(bitbang->addr, bitbang->mdo_msk); 696 else 697 bb_clr(bitbang->addr, bitbang->mdo_msk); 698} 699 700/* Get bit data*/ 701static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 702{ 703 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 704 705 if (bitbang->set_gate) 706 bitbang->set_gate(bitbang->addr); 707 708 return bb_read(bitbang->addr, bitbang->mdi_msk); 709} 710 711/* MDC pin control */ 712static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 713{ 714 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 715 716 if (bitbang->set_gate) 717 bitbang->set_gate(bitbang->addr); 718 719 if (bit) 720 bb_set(bitbang->addr, bitbang->mdc_msk); 721 else 722 bb_clr(bitbang->addr, bitbang->mdc_msk); 723} 724 725/* mdio bus control struct */ 726static struct mdiobb_ops bb_ops = { 727 .owner = THIS_MODULE, 728 .set_mdc = sh_mdc_ctrl, 729 .set_mdio_dir = sh_mmd_ctrl, 730 .set_mdio_data = sh_set_mdio, 731 .get_mdio_data = sh_get_mdio, 732}; 733 734/* free skb and descriptor buffer */ 735static void sh_eth_ring_free(struct net_device *ndev) 736{ 737 struct sh_eth_private *mdp = netdev_priv(ndev); 738 int i; 739 740 /* Free Rx skb ringbuffer */ 741 if (mdp->rx_skbuff) { 742 for (i = 0; i < RX_RING_SIZE; i++) { 743 if (mdp->rx_skbuff[i]) 744 dev_kfree_skb(mdp->rx_skbuff[i]); 745 } 746 } 747 kfree(mdp->rx_skbuff); 748 749 /* Free Tx skb ringbuffer */ 750 if (mdp->tx_skbuff) { 751 for (i = 0; i < TX_RING_SIZE; i++) { 752 if (mdp->tx_skbuff[i]) 753 dev_kfree_skb(mdp->tx_skbuff[i]); 754 } 755 } 756 kfree(mdp->tx_skbuff); 757} 758 759/* format skb and descriptor buffer */ 760static void sh_eth_ring_format(struct net_device *ndev) 761{ 762 struct sh_eth_private *mdp = netdev_priv(ndev); 763 int i; 764 struct sk_buff *skb; 765 struct sh_eth_rxdesc *rxdesc = NULL; 766 struct sh_eth_txdesc *txdesc = NULL; 767 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE; 768 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE; 769 770 mdp->cur_rx = mdp->cur_tx = 0; 771 mdp->dirty_rx = mdp->dirty_tx = 0; 772 773 memset(mdp->rx_ring, 0, rx_ringsize); 774 775 /* build Rx ring buffer */ 776 for (i = 0; i < RX_RING_SIZE; i++) { 777 /* skb */ 778 mdp->rx_skbuff[i] = NULL; 779 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 780 mdp->rx_skbuff[i] = skb; 781 if (skb == NULL) 782 break; 783 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 784 DMA_FROM_DEVICE); 785 sh_eth_set_receive_align(skb); 786 787 /* RX descriptor */ 788 rxdesc = &mdp->rx_ring[i]; 789 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 790 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); 791 792 /* The size of the buffer is 16 byte boundary. */ 793 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 794 /* Rx descriptor address set */ 795 if (i == 0) { 796 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 797 if (sh_eth_is_gether(mdp)) 798 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 799 } 800 } 801 802 mdp->dirty_rx = (u32) (i - RX_RING_SIZE); 803 804 /* Mark the last entry as wrapping the ring. */ 805 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); 806 807 memset(mdp->tx_ring, 0, tx_ringsize); 808 809 /* build Tx ring buffer */ 810 for (i = 0; i < TX_RING_SIZE; i++) { 811 mdp->tx_skbuff[i] = NULL; 812 txdesc = &mdp->tx_ring[i]; 813 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 814 txdesc->buffer_length = 0; 815 if (i == 0) { 816 /* Tx descriptor address set */ 817 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 818 if (sh_eth_is_gether(mdp)) 819 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 820 } 821 } 822 823 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 824} 825 826/* Get skb and descriptor buffer */ 827static int sh_eth_ring_init(struct net_device *ndev) 828{ 829 struct sh_eth_private *mdp = netdev_priv(ndev); 830 int rx_ringsize, tx_ringsize, ret = 0; 831 832 /* 833 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 834 * card needs room to do 8 byte alignment, +2 so we can reserve 835 * the first 2 bytes, and +16 gets room for the status word from the 836 * card. 837 */ 838 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 839 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 840 if (mdp->cd->rpadir) 841 mdp->rx_buf_sz += NET_IP_ALIGN; 842 843 /* Allocate RX and TX skb rings */ 844 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE, 845 GFP_KERNEL); 846 if (!mdp->rx_skbuff) { 847 dev_err(&ndev->dev, "Cannot allocate Rx skb\n"); 848 ret = -ENOMEM; 849 return ret; 850 } 851 852 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE, 853 GFP_KERNEL); 854 if (!mdp->tx_skbuff) { 855 dev_err(&ndev->dev, "Cannot allocate Tx skb\n"); 856 ret = -ENOMEM; 857 goto skb_ring_free; 858 } 859 860 /* Allocate all Rx descriptors. */ 861 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE; 862 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 863 GFP_KERNEL); 864 865 if (!mdp->rx_ring) { 866 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n", 867 rx_ringsize); 868 ret = -ENOMEM; 869 goto desc_ring_free; 870 } 871 872 mdp->dirty_rx = 0; 873 874 /* Allocate all Tx descriptors. */ 875 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE; 876 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 877 GFP_KERNEL); 878 if (!mdp->tx_ring) { 879 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n", 880 tx_ringsize); 881 ret = -ENOMEM; 882 goto desc_ring_free; 883 } 884 return ret; 885 886desc_ring_free: 887 /* free DMA buffer */ 888 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); 889 890skb_ring_free: 891 /* Free Rx and Tx skb ring buffer */ 892 sh_eth_ring_free(ndev); 893 894 return ret; 895} 896 897static int sh_eth_dev_init(struct net_device *ndev) 898{ 899 int ret = 0; 900 struct sh_eth_private *mdp = netdev_priv(ndev); 901 u_int32_t rx_int_var, tx_int_var; 902 u32 val; 903 904 /* Soft Reset */ 905 sh_eth_reset(ndev); 906 907 /* Descriptor format */ 908 sh_eth_ring_format(ndev); 909 if (mdp->cd->rpadir) 910 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 911 912 /* all sh_eth int mask */ 913 sh_eth_write(ndev, 0, EESIPR); 914 915#if defined(__LITTLE_ENDIAN) 916 if (mdp->cd->hw_swap) 917 sh_eth_write(ndev, EDMR_EL, EDMR); 918 else 919#endif 920 sh_eth_write(ndev, 0, EDMR); 921 922 /* FIFO size set */ 923 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 924 sh_eth_write(ndev, 0, TFTR); 925 926 /* Frame recv control */ 927 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR); 928 929 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5; 930 tx_int_var = mdp->tx_int_var = DESC_I_TINT2; 931 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER); 932 933 if (mdp->cd->bculr) 934 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 935 936 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 937 938 if (!mdp->cd->no_trimd) 939 sh_eth_write(ndev, 0, TRIMD); 940 941 /* Recv frame limit set register */ 942 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 943 RFLR); 944 945 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 946 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 947 948 /* PAUSE Prohibition */ 949 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | 950 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 951 952 sh_eth_write(ndev, val, ECMR); 953 954 if (mdp->cd->set_rate) 955 mdp->cd->set_rate(ndev); 956 957 /* E-MAC Status Register clear */ 958 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 959 960 /* E-MAC Interrupt Enable register */ 961 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 962 963 /* Set MAC address */ 964 update_mac_address(ndev); 965 966 /* mask reset */ 967 if (mdp->cd->apr) 968 sh_eth_write(ndev, APR_AP, APR); 969 if (mdp->cd->mpr) 970 sh_eth_write(ndev, MPR_MP, MPR); 971 if (mdp->cd->tpauser) 972 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 973 974 /* Setting the Rx mode will start the Rx process. */ 975 sh_eth_write(ndev, EDRRR_R, EDRRR); 976 977 netif_start_queue(ndev); 978 979 return ret; 980} 981 982/* free Tx skb function */ 983static int sh_eth_txfree(struct net_device *ndev) 984{ 985 struct sh_eth_private *mdp = netdev_priv(ndev); 986 struct sh_eth_txdesc *txdesc; 987 int freeNum = 0; 988 int entry = 0; 989 990 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 991 entry = mdp->dirty_tx % TX_RING_SIZE; 992 txdesc = &mdp->tx_ring[entry]; 993 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 994 break; 995 /* Free the original skb. */ 996 if (mdp->tx_skbuff[entry]) { 997 dma_unmap_single(&ndev->dev, txdesc->addr, 998 txdesc->buffer_length, DMA_TO_DEVICE); 999 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1000 mdp->tx_skbuff[entry] = NULL; 1001 freeNum++; 1002 } 1003 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1004 if (entry >= TX_RING_SIZE - 1) 1005 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1006 1007 ndev->stats.tx_packets++; 1008 ndev->stats.tx_bytes += txdesc->buffer_length; 1009 } 1010 return freeNum; 1011} 1012 1013/* Packet receive function */ 1014static int sh_eth_rx(struct net_device *ndev, u32 intr_status) 1015{ 1016 struct sh_eth_private *mdp = netdev_priv(ndev); 1017 struct sh_eth_rxdesc *rxdesc; 1018 1019 int entry = mdp->cur_rx % RX_RING_SIZE; 1020 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx; 1021 struct sk_buff *skb; 1022 u16 pkt_len = 0; 1023 u32 desc_status; 1024 1025 rxdesc = &mdp->rx_ring[entry]; 1026 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1027 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1028 pkt_len = rxdesc->frame_length; 1029 1030#if defined(CONFIG_ARCH_R8A7740) 1031 desc_status >>= 16; 1032#endif 1033 1034 if (--boguscnt < 0) 1035 break; 1036 1037 if (!(desc_status & RDFEND)) 1038 ndev->stats.rx_length_errors++; 1039 1040 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1041 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1042 ndev->stats.rx_errors++; 1043 if (desc_status & RD_RFS1) 1044 ndev->stats.rx_crc_errors++; 1045 if (desc_status & RD_RFS2) 1046 ndev->stats.rx_frame_errors++; 1047 if (desc_status & RD_RFS3) 1048 ndev->stats.rx_length_errors++; 1049 if (desc_status & RD_RFS4) 1050 ndev->stats.rx_length_errors++; 1051 if (desc_status & RD_RFS6) 1052 ndev->stats.rx_missed_errors++; 1053 if (desc_status & RD_RFS10) 1054 ndev->stats.rx_over_errors++; 1055 } else { 1056 if (!mdp->cd->hw_swap) 1057 sh_eth_soft_swap( 1058 phys_to_virt(ALIGN(rxdesc->addr, 4)), 1059 pkt_len + 2); 1060 skb = mdp->rx_skbuff[entry]; 1061 mdp->rx_skbuff[entry] = NULL; 1062 if (mdp->cd->rpadir) 1063 skb_reserve(skb, NET_IP_ALIGN); 1064 skb_put(skb, pkt_len); 1065 skb->protocol = eth_type_trans(skb, ndev); 1066 netif_rx(skb); 1067 ndev->stats.rx_packets++; 1068 ndev->stats.rx_bytes += pkt_len; 1069 } 1070 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); 1071 entry = (++mdp->cur_rx) % RX_RING_SIZE; 1072 rxdesc = &mdp->rx_ring[entry]; 1073 } 1074 1075 /* Refill the Rx ring buffers. */ 1076 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1077 entry = mdp->dirty_rx % RX_RING_SIZE; 1078 rxdesc = &mdp->rx_ring[entry]; 1079 /* The size of the buffer is 16 byte boundary. */ 1080 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1081 1082 if (mdp->rx_skbuff[entry] == NULL) { 1083 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1084 mdp->rx_skbuff[entry] = skb; 1085 if (skb == NULL) 1086 break; /* Better luck next round. */ 1087 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1088 DMA_FROM_DEVICE); 1089 sh_eth_set_receive_align(skb); 1090 1091 skb_checksum_none_assert(skb); 1092 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1093 } 1094 if (entry >= RX_RING_SIZE - 1) 1095 rxdesc->status |= 1096 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1097 else 1098 rxdesc->status |= 1099 cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1100 } 1101 1102 /* Restart Rx engine if stopped. */ 1103 /* If we don't need to check status, don't. -KDU */ 1104 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1105 /* fix the values for the next receiving if RDE is set */ 1106 if (intr_status & EESR_RDE) 1107 mdp->cur_rx = mdp->dirty_rx = 1108 (sh_eth_read(ndev, RDFAR) - 1109 sh_eth_read(ndev, RDLAR)) >> 4; 1110 sh_eth_write(ndev, EDRRR_R, EDRRR); 1111 } 1112 1113 return 0; 1114} 1115 1116static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1117{ 1118 /* disable tx and rx */ 1119 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1120 ~(ECMR_RE | ECMR_TE), ECMR); 1121} 1122 1123static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1124{ 1125 /* enable tx and rx */ 1126 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1127 (ECMR_RE | ECMR_TE), ECMR); 1128} 1129 1130/* error control function */ 1131static void sh_eth_error(struct net_device *ndev, int intr_status) 1132{ 1133 struct sh_eth_private *mdp = netdev_priv(ndev); 1134 u32 felic_stat; 1135 u32 link_stat; 1136 u32 mask; 1137 1138 if (intr_status & EESR_ECI) { 1139 felic_stat = sh_eth_read(ndev, ECSR); 1140 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1141 if (felic_stat & ECSR_ICD) 1142 ndev->stats.tx_carrier_errors++; 1143 if (felic_stat & ECSR_LCHNG) { 1144 /* Link Changed */ 1145 if (mdp->cd->no_psr || mdp->no_ether_link) { 1146 if (mdp->link == PHY_DOWN) 1147 link_stat = 0; 1148 else 1149 link_stat = PHY_ST_LINK; 1150 } else { 1151 link_stat = (sh_eth_read(ndev, PSR)); 1152 if (mdp->ether_link_active_low) 1153 link_stat = ~link_stat; 1154 } 1155 if (!(link_stat & PHY_ST_LINK)) 1156 sh_eth_rcv_snd_disable(ndev); 1157 else { 1158 /* Link Up */ 1159 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1160 ~DMAC_M_ECI, EESIPR); 1161 /*clear int */ 1162 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1163 ECSR); 1164 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1165 DMAC_M_ECI, EESIPR); 1166 /* enable tx and rx */ 1167 sh_eth_rcv_snd_enable(ndev); 1168 } 1169 } 1170 } 1171 1172 if (intr_status & EESR_TWB) { 1173 /* Write buck end. unused write back interrupt */ 1174 if (intr_status & EESR_TABT) /* Transmit Abort int */ 1175 ndev->stats.tx_aborted_errors++; 1176 if (netif_msg_tx_err(mdp)) 1177 dev_err(&ndev->dev, "Transmit Abort\n"); 1178 } 1179 1180 if (intr_status & EESR_RABT) { 1181 /* Receive Abort int */ 1182 if (intr_status & EESR_RFRMER) { 1183 /* Receive Frame Overflow int */ 1184 ndev->stats.rx_frame_errors++; 1185 if (netif_msg_rx_err(mdp)) 1186 dev_err(&ndev->dev, "Receive Abort\n"); 1187 } 1188 } 1189 1190 if (intr_status & EESR_TDE) { 1191 /* Transmit Descriptor Empty int */ 1192 ndev->stats.tx_fifo_errors++; 1193 if (netif_msg_tx_err(mdp)) 1194 dev_err(&ndev->dev, "Transmit Descriptor Empty\n"); 1195 } 1196 1197 if (intr_status & EESR_TFE) { 1198 /* FIFO under flow */ 1199 ndev->stats.tx_fifo_errors++; 1200 if (netif_msg_tx_err(mdp)) 1201 dev_err(&ndev->dev, "Transmit FIFO Under flow\n"); 1202 } 1203 1204 if (intr_status & EESR_RDE) { 1205 /* Receive Descriptor Empty int */ 1206 ndev->stats.rx_over_errors++; 1207 1208 if (netif_msg_rx_err(mdp)) 1209 dev_err(&ndev->dev, "Receive Descriptor Empty\n"); 1210 } 1211 1212 if (intr_status & EESR_RFE) { 1213 /* Receive FIFO Overflow int */ 1214 ndev->stats.rx_fifo_errors++; 1215 if (netif_msg_rx_err(mdp)) 1216 dev_err(&ndev->dev, "Receive FIFO Overflow\n"); 1217 } 1218 1219 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1220 /* Address Error */ 1221 ndev->stats.tx_fifo_errors++; 1222 if (netif_msg_tx_err(mdp)) 1223 dev_err(&ndev->dev, "Address Error\n"); 1224 } 1225 1226 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1227 if (mdp->cd->no_ade) 1228 mask &= ~EESR_ADE; 1229 if (intr_status & mask) { 1230 /* Tx error */ 1231 u32 edtrr = sh_eth_read(ndev, EDTRR); 1232 /* dmesg */ 1233 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ", 1234 intr_status, mdp->cur_tx); 1235 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1236 mdp->dirty_tx, (u32) ndev->state, edtrr); 1237 /* dirty buffer free */ 1238 sh_eth_txfree(ndev); 1239 1240 /* SH7712 BUG */ 1241 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1242 /* tx dma start */ 1243 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1244 } 1245 /* wakeup */ 1246 netif_wake_queue(ndev); 1247 } 1248} 1249 1250static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1251{ 1252 struct net_device *ndev = netdev; 1253 struct sh_eth_private *mdp = netdev_priv(ndev); 1254 struct sh_eth_cpu_data *cd = mdp->cd; 1255 irqreturn_t ret = IRQ_NONE; 1256 u32 intr_status = 0; 1257 1258 spin_lock(&mdp->lock); 1259 1260 /* Get interrpt stat */ 1261 intr_status = sh_eth_read(ndev, EESR); 1262 /* Clear interrupt */ 1263 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | 1264 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | 1265 cd->tx_check | cd->eesr_err_check)) { 1266 sh_eth_write(ndev, intr_status, EESR); 1267 ret = IRQ_HANDLED; 1268 } else 1269 goto other_irq; 1270 1271 if (intr_status & (EESR_FRC | /* Frame recv*/ 1272 EESR_RMAF | /* Multi cast address recv*/ 1273 EESR_RRF | /* Bit frame recv */ 1274 EESR_RTLF | /* Long frame recv*/ 1275 EESR_RTSF | /* short frame recv */ 1276 EESR_PRE | /* PHY-LSI recv error */ 1277 EESR_CERF)){ /* recv frame CRC error */ 1278 sh_eth_rx(ndev, intr_status); 1279 } 1280 1281 /* Tx Check */ 1282 if (intr_status & cd->tx_check) { 1283 sh_eth_txfree(ndev); 1284 netif_wake_queue(ndev); 1285 } 1286 1287 if (intr_status & cd->eesr_err_check) 1288 sh_eth_error(ndev, intr_status); 1289 1290other_irq: 1291 spin_unlock(&mdp->lock); 1292 1293 return ret; 1294} 1295 1296static void sh_eth_timer(unsigned long data) 1297{ 1298 struct net_device *ndev = (struct net_device *)data; 1299 struct sh_eth_private *mdp = netdev_priv(ndev); 1300 1301 mod_timer(&mdp->timer, jiffies + (10 * HZ)); 1302} 1303 1304/* PHY state control function */ 1305static void sh_eth_adjust_link(struct net_device *ndev) 1306{ 1307 struct sh_eth_private *mdp = netdev_priv(ndev); 1308 struct phy_device *phydev = mdp->phydev; 1309 int new_state = 0; 1310 1311 if (phydev->link != PHY_DOWN) { 1312 if (phydev->duplex != mdp->duplex) { 1313 new_state = 1; 1314 mdp->duplex = phydev->duplex; 1315 if (mdp->cd->set_duplex) 1316 mdp->cd->set_duplex(ndev); 1317 } 1318 1319 if (phydev->speed != mdp->speed) { 1320 new_state = 1; 1321 mdp->speed = phydev->speed; 1322 if (mdp->cd->set_rate) 1323 mdp->cd->set_rate(ndev); 1324 } 1325 if (mdp->link == PHY_DOWN) { 1326 sh_eth_write(ndev, 1327 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR); 1328 new_state = 1; 1329 mdp->link = phydev->link; 1330 } 1331 } else if (mdp->link) { 1332 new_state = 1; 1333 mdp->link = PHY_DOWN; 1334 mdp->speed = 0; 1335 mdp->duplex = -1; 1336 } 1337 1338 if (new_state && netif_msg_link(mdp)) 1339 phy_print_status(phydev); 1340} 1341 1342/* PHY init function */ 1343static int sh_eth_phy_init(struct net_device *ndev) 1344{ 1345 struct sh_eth_private *mdp = netdev_priv(ndev); 1346 char phy_id[MII_BUS_ID_SIZE + 3]; 1347 struct phy_device *phydev = NULL; 1348 1349 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1350 mdp->mii_bus->id , mdp->phy_id); 1351 1352 mdp->link = PHY_DOWN; 1353 mdp->speed = 0; 1354 mdp->duplex = -1; 1355 1356 /* Try connect to PHY */ 1357 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1358 0, mdp->phy_interface); 1359 if (IS_ERR(phydev)) { 1360 dev_err(&ndev->dev, "phy_connect failed\n"); 1361 return PTR_ERR(phydev); 1362 } 1363 1364 dev_info(&ndev->dev, "attached phy %i to driver %s\n", 1365 phydev->addr, phydev->drv->name); 1366 1367 mdp->phydev = phydev; 1368 1369 return 0; 1370} 1371 1372/* PHY control start function */ 1373static int sh_eth_phy_start(struct net_device *ndev) 1374{ 1375 struct sh_eth_private *mdp = netdev_priv(ndev); 1376 int ret; 1377 1378 ret = sh_eth_phy_init(ndev); 1379 if (ret) 1380 return ret; 1381 1382 /* reset phy - this also wakes it from PDOWN */ 1383 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET); 1384 phy_start(mdp->phydev); 1385 1386 return 0; 1387} 1388 1389static int sh_eth_get_settings(struct net_device *ndev, 1390 struct ethtool_cmd *ecmd) 1391{ 1392 struct sh_eth_private *mdp = netdev_priv(ndev); 1393 unsigned long flags; 1394 int ret; 1395 1396 spin_lock_irqsave(&mdp->lock, flags); 1397 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1398 spin_unlock_irqrestore(&mdp->lock, flags); 1399 1400 return ret; 1401} 1402 1403static int sh_eth_set_settings(struct net_device *ndev, 1404 struct ethtool_cmd *ecmd) 1405{ 1406 struct sh_eth_private *mdp = netdev_priv(ndev); 1407 unsigned long flags; 1408 int ret; 1409 1410 spin_lock_irqsave(&mdp->lock, flags); 1411 1412 /* disable tx and rx */ 1413 sh_eth_rcv_snd_disable(ndev); 1414 1415 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1416 if (ret) 1417 goto error_exit; 1418 1419 if (ecmd->duplex == DUPLEX_FULL) 1420 mdp->duplex = 1; 1421 else 1422 mdp->duplex = 0; 1423 1424 if (mdp->cd->set_duplex) 1425 mdp->cd->set_duplex(ndev); 1426 1427error_exit: 1428 mdelay(1); 1429 1430 /* enable tx and rx */ 1431 sh_eth_rcv_snd_enable(ndev); 1432 1433 spin_unlock_irqrestore(&mdp->lock, flags); 1434 1435 return ret; 1436} 1437 1438static int sh_eth_nway_reset(struct net_device *ndev) 1439{ 1440 struct sh_eth_private *mdp = netdev_priv(ndev); 1441 unsigned long flags; 1442 int ret; 1443 1444 spin_lock_irqsave(&mdp->lock, flags); 1445 ret = phy_start_aneg(mdp->phydev); 1446 spin_unlock_irqrestore(&mdp->lock, flags); 1447 1448 return ret; 1449} 1450 1451static u32 sh_eth_get_msglevel(struct net_device *ndev) 1452{ 1453 struct sh_eth_private *mdp = netdev_priv(ndev); 1454 return mdp->msg_enable; 1455} 1456 1457static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 1458{ 1459 struct sh_eth_private *mdp = netdev_priv(ndev); 1460 mdp->msg_enable = value; 1461} 1462 1463static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 1464 "rx_current", "tx_current", 1465 "rx_dirty", "tx_dirty", 1466}; 1467#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 1468 1469static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 1470{ 1471 switch (sset) { 1472 case ETH_SS_STATS: 1473 return SH_ETH_STATS_LEN; 1474 default: 1475 return -EOPNOTSUPP; 1476 } 1477} 1478 1479static void sh_eth_get_ethtool_stats(struct net_device *ndev, 1480 struct ethtool_stats *stats, u64 *data) 1481{ 1482 struct sh_eth_private *mdp = netdev_priv(ndev); 1483 int i = 0; 1484 1485 /* device-specific stats */ 1486 data[i++] = mdp->cur_rx; 1487 data[i++] = mdp->cur_tx; 1488 data[i++] = mdp->dirty_rx; 1489 data[i++] = mdp->dirty_tx; 1490} 1491 1492static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1493{ 1494 switch (stringset) { 1495 case ETH_SS_STATS: 1496 memcpy(data, *sh_eth_gstrings_stats, 1497 sizeof(sh_eth_gstrings_stats)); 1498 break; 1499 } 1500} 1501 1502static const struct ethtool_ops sh_eth_ethtool_ops = { 1503 .get_settings = sh_eth_get_settings, 1504 .set_settings = sh_eth_set_settings, 1505 .nway_reset = sh_eth_nway_reset, 1506 .get_msglevel = sh_eth_get_msglevel, 1507 .set_msglevel = sh_eth_set_msglevel, 1508 .get_link = ethtool_op_get_link, 1509 .get_strings = sh_eth_get_strings, 1510 .get_ethtool_stats = sh_eth_get_ethtool_stats, 1511 .get_sset_count = sh_eth_get_sset_count, 1512}; 1513 1514/* network device open function */ 1515static int sh_eth_open(struct net_device *ndev) 1516{ 1517 int ret = 0; 1518 struct sh_eth_private *mdp = netdev_priv(ndev); 1519 1520 pm_runtime_get_sync(&mdp->pdev->dev); 1521 1522 ret = request_irq(ndev->irq, sh_eth_interrupt, 1523#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 1524 defined(CONFIG_CPU_SUBTYPE_SH7764) || \ 1525 defined(CONFIG_CPU_SUBTYPE_SH7757) 1526 IRQF_SHARED, 1527#else 1528 0, 1529#endif 1530 ndev->name, ndev); 1531 if (ret) { 1532 dev_err(&ndev->dev, "Can not assign IRQ number\n"); 1533 return ret; 1534 } 1535 1536 /* Descriptor set */ 1537 ret = sh_eth_ring_init(ndev); 1538 if (ret) 1539 goto out_free_irq; 1540 1541 /* device init */ 1542 ret = sh_eth_dev_init(ndev); 1543 if (ret) 1544 goto out_free_irq; 1545 1546 /* PHY control start*/ 1547 ret = sh_eth_phy_start(ndev); 1548 if (ret) 1549 goto out_free_irq; 1550 1551 /* Set the timer to check for link beat. */ 1552 init_timer(&mdp->timer); 1553 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ 1554 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev); 1555 1556 return ret; 1557 1558out_free_irq: 1559 free_irq(ndev->irq, ndev); 1560 pm_runtime_put_sync(&mdp->pdev->dev); 1561 return ret; 1562} 1563 1564/* Timeout function */ 1565static void sh_eth_tx_timeout(struct net_device *ndev) 1566{ 1567 struct sh_eth_private *mdp = netdev_priv(ndev); 1568 struct sh_eth_rxdesc *rxdesc; 1569 int i; 1570 1571 netif_stop_queue(ndev); 1572 1573 if (netif_msg_timer(mdp)) 1574 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x," 1575 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR)); 1576 1577 /* tx_errors count up */ 1578 ndev->stats.tx_errors++; 1579 1580 /* timer off */ 1581 del_timer_sync(&mdp->timer); 1582 1583 /* Free all the skbuffs in the Rx queue. */ 1584 for (i = 0; i < RX_RING_SIZE; i++) { 1585 rxdesc = &mdp->rx_ring[i]; 1586 rxdesc->status = 0; 1587 rxdesc->addr = 0xBADF00D0; 1588 if (mdp->rx_skbuff[i]) 1589 dev_kfree_skb(mdp->rx_skbuff[i]); 1590 mdp->rx_skbuff[i] = NULL; 1591 } 1592 for (i = 0; i < TX_RING_SIZE; i++) { 1593 if (mdp->tx_skbuff[i]) 1594 dev_kfree_skb(mdp->tx_skbuff[i]); 1595 mdp->tx_skbuff[i] = NULL; 1596 } 1597 1598 /* device init */ 1599 sh_eth_dev_init(ndev); 1600 1601 /* timer on */ 1602 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ 1603 add_timer(&mdp->timer); 1604} 1605 1606/* Packet transmit function */ 1607static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1608{ 1609 struct sh_eth_private *mdp = netdev_priv(ndev); 1610 struct sh_eth_txdesc *txdesc; 1611 u32 entry; 1612 unsigned long flags; 1613 1614 spin_lock_irqsave(&mdp->lock, flags); 1615 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) { 1616 if (!sh_eth_txfree(ndev)) { 1617 if (netif_msg_tx_queued(mdp)) 1618 dev_warn(&ndev->dev, "TxFD exhausted.\n"); 1619 netif_stop_queue(ndev); 1620 spin_unlock_irqrestore(&mdp->lock, flags); 1621 return NETDEV_TX_BUSY; 1622 } 1623 } 1624 spin_unlock_irqrestore(&mdp->lock, flags); 1625 1626 entry = mdp->cur_tx % TX_RING_SIZE; 1627 mdp->tx_skbuff[entry] = skb; 1628 txdesc = &mdp->tx_ring[entry]; 1629 /* soft swap. */ 1630 if (!mdp->cd->hw_swap) 1631 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), 1632 skb->len + 2); 1633 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, 1634 DMA_TO_DEVICE); 1635 if (skb->len < ETHERSMALL) 1636 txdesc->buffer_length = ETHERSMALL; 1637 else 1638 txdesc->buffer_length = skb->len; 1639 1640 if (entry >= TX_RING_SIZE - 1) 1641 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 1642 else 1643 txdesc->status |= cpu_to_edmac(mdp, TD_TACT); 1644 1645 mdp->cur_tx++; 1646 1647 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 1648 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1649 1650 return NETDEV_TX_OK; 1651} 1652 1653/* device close function */ 1654static int sh_eth_close(struct net_device *ndev) 1655{ 1656 struct sh_eth_private *mdp = netdev_priv(ndev); 1657 int ringsize; 1658 1659 netif_stop_queue(ndev); 1660 1661 /* Disable interrupts by clearing the interrupt mask. */ 1662 sh_eth_write(ndev, 0x0000, EESIPR); 1663 1664 /* Stop the chip's Tx and Rx processes. */ 1665 sh_eth_write(ndev, 0, EDTRR); 1666 sh_eth_write(ndev, 0, EDRRR); 1667 1668 /* PHY Disconnect */ 1669 if (mdp->phydev) { 1670 phy_stop(mdp->phydev); 1671 phy_disconnect(mdp->phydev); 1672 } 1673 1674 free_irq(ndev->irq, ndev); 1675 1676 del_timer_sync(&mdp->timer); 1677 1678 /* Free all the skbuffs in the Rx queue. */ 1679 sh_eth_ring_free(ndev); 1680 1681 /* free DMA buffer */ 1682 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE; 1683 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma); 1684 1685 /* free DMA buffer */ 1686 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE; 1687 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma); 1688 1689 pm_runtime_put_sync(&mdp->pdev->dev); 1690 1691 return 0; 1692} 1693 1694static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 1695{ 1696 struct sh_eth_private *mdp = netdev_priv(ndev); 1697 1698 pm_runtime_get_sync(&mdp->pdev->dev); 1699 1700 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR); 1701 sh_eth_write(ndev, 0, TROCR); /* (write clear) */ 1702 ndev->stats.collisions += sh_eth_read(ndev, CDCR); 1703 sh_eth_write(ndev, 0, CDCR); /* (write clear) */ 1704 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); 1705 sh_eth_write(ndev, 0, LCCR); /* (write clear) */ 1706 if (sh_eth_is_gether(mdp)) { 1707 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR); 1708 sh_eth_write(ndev, 0, CERCR); /* (write clear) */ 1709 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR); 1710 sh_eth_write(ndev, 0, CEECR); /* (write clear) */ 1711 } else { 1712 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); 1713 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ 1714 } 1715 pm_runtime_put_sync(&mdp->pdev->dev); 1716 1717 return &ndev->stats; 1718} 1719 1720/* ioctl to device function */ 1721static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, 1722 int cmd) 1723{ 1724 struct sh_eth_private *mdp = netdev_priv(ndev); 1725 struct phy_device *phydev = mdp->phydev; 1726 1727 if (!netif_running(ndev)) 1728 return -EINVAL; 1729 1730 if (!phydev) 1731 return -ENODEV; 1732 1733 return phy_mii_ioctl(phydev, rq, cmd); 1734} 1735 1736#if defined(SH_ETH_HAS_TSU) 1737/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 1738static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 1739 int entry) 1740{ 1741 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 1742} 1743 1744static u32 sh_eth_tsu_get_post_mask(int entry) 1745{ 1746 return 0x0f << (28 - ((entry % 8) * 4)); 1747} 1748 1749static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 1750{ 1751 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 1752} 1753 1754static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 1755 int entry) 1756{ 1757 struct sh_eth_private *mdp = netdev_priv(ndev); 1758 u32 tmp; 1759 void *reg_offset; 1760 1761 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 1762 tmp = ioread32(reg_offset); 1763 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 1764} 1765 1766static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 1767 int entry) 1768{ 1769 struct sh_eth_private *mdp = netdev_priv(ndev); 1770 u32 post_mask, ref_mask, tmp; 1771 void *reg_offset; 1772 1773 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 1774 post_mask = sh_eth_tsu_get_post_mask(entry); 1775 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 1776 1777 tmp = ioread32(reg_offset); 1778 iowrite32(tmp & ~post_mask, reg_offset); 1779 1780 /* If other port enables, the function returns "true" */ 1781 return tmp & ref_mask; 1782} 1783 1784static int sh_eth_tsu_busy(struct net_device *ndev) 1785{ 1786 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 1787 struct sh_eth_private *mdp = netdev_priv(ndev); 1788 1789 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 1790 udelay(10); 1791 timeout--; 1792 if (timeout <= 0) { 1793 dev_err(&ndev->dev, "%s: timeout\n", __func__); 1794 return -ETIMEDOUT; 1795 } 1796 } 1797 1798 return 0; 1799} 1800 1801static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 1802 const u8 *addr) 1803{ 1804 u32 val; 1805 1806 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 1807 iowrite32(val, reg); 1808 if (sh_eth_tsu_busy(ndev) < 0) 1809 return -EBUSY; 1810 1811 val = addr[4] << 8 | addr[5]; 1812 iowrite32(val, reg + 4); 1813 if (sh_eth_tsu_busy(ndev) < 0) 1814 return -EBUSY; 1815 1816 return 0; 1817} 1818 1819static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 1820{ 1821 u32 val; 1822 1823 val = ioread32(reg); 1824 addr[0] = (val >> 24) & 0xff; 1825 addr[1] = (val >> 16) & 0xff; 1826 addr[2] = (val >> 8) & 0xff; 1827 addr[3] = val & 0xff; 1828 val = ioread32(reg + 4); 1829 addr[4] = (val >> 8) & 0xff; 1830 addr[5] = val & 0xff; 1831} 1832 1833 1834static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 1835{ 1836 struct sh_eth_private *mdp = netdev_priv(ndev); 1837 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 1838 int i; 1839 u8 c_addr[ETH_ALEN]; 1840 1841 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 1842 sh_eth_tsu_read_entry(reg_offset, c_addr); 1843 if (memcmp(addr, c_addr, ETH_ALEN) == 0) 1844 return i; 1845 } 1846 1847 return -ENOENT; 1848} 1849 1850static int sh_eth_tsu_find_empty(struct net_device *ndev) 1851{ 1852 u8 blank[ETH_ALEN]; 1853 int entry; 1854 1855 memset(blank, 0, sizeof(blank)); 1856 entry = sh_eth_tsu_find_entry(ndev, blank); 1857 return (entry < 0) ? -ENOMEM : entry; 1858} 1859 1860static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 1861 int entry) 1862{ 1863 struct sh_eth_private *mdp = netdev_priv(ndev); 1864 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 1865 int ret; 1866 u8 blank[ETH_ALEN]; 1867 1868 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 1869 ~(1 << (31 - entry)), TSU_TEN); 1870 1871 memset(blank, 0, sizeof(blank)); 1872 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 1873 if (ret < 0) 1874 return ret; 1875 return 0; 1876} 1877 1878static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 1879{ 1880 struct sh_eth_private *mdp = netdev_priv(ndev); 1881 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 1882 int i, ret; 1883 1884 if (!mdp->cd->tsu) 1885 return 0; 1886 1887 i = sh_eth_tsu_find_entry(ndev, addr); 1888 if (i < 0) { 1889 /* No entry found, create one */ 1890 i = sh_eth_tsu_find_empty(ndev); 1891 if (i < 0) 1892 return -ENOMEM; 1893 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 1894 if (ret < 0) 1895 return ret; 1896 1897 /* Enable the entry */ 1898 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 1899 (1 << (31 - i)), TSU_TEN); 1900 } 1901 1902 /* Entry found or created, enable POST */ 1903 sh_eth_tsu_enable_cam_entry_post(ndev, i); 1904 1905 return 0; 1906} 1907 1908static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 1909{ 1910 struct sh_eth_private *mdp = netdev_priv(ndev); 1911 int i, ret; 1912 1913 if (!mdp->cd->tsu) 1914 return 0; 1915 1916 i = sh_eth_tsu_find_entry(ndev, addr); 1917 if (i) { 1918 /* Entry found */ 1919 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 1920 goto done; 1921 1922 /* Disable the entry if both ports was disabled */ 1923 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 1924 if (ret < 0) 1925 return ret; 1926 } 1927done: 1928 return 0; 1929} 1930 1931static int sh_eth_tsu_purge_all(struct net_device *ndev) 1932{ 1933 struct sh_eth_private *mdp = netdev_priv(ndev); 1934 int i, ret; 1935 1936 if (unlikely(!mdp->cd->tsu)) 1937 return 0; 1938 1939 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 1940 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 1941 continue; 1942 1943 /* Disable the entry if both ports was disabled */ 1944 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 1945 if (ret < 0) 1946 return ret; 1947 } 1948 1949 return 0; 1950} 1951 1952static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 1953{ 1954 struct sh_eth_private *mdp = netdev_priv(ndev); 1955 u8 addr[ETH_ALEN]; 1956 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 1957 int i; 1958 1959 if (unlikely(!mdp->cd->tsu)) 1960 return; 1961 1962 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 1963 sh_eth_tsu_read_entry(reg_offset, addr); 1964 if (is_multicast_ether_addr(addr)) 1965 sh_eth_tsu_del_entry(ndev, addr); 1966 } 1967} 1968 1969/* Multicast reception directions set */ 1970static void sh_eth_set_multicast_list(struct net_device *ndev) 1971{ 1972 struct sh_eth_private *mdp = netdev_priv(ndev); 1973 u32 ecmr_bits; 1974 int mcast_all = 0; 1975 unsigned long flags; 1976 1977 spin_lock_irqsave(&mdp->lock, flags); 1978 /* 1979 * Initial condition is MCT = 1, PRM = 0. 1980 * Depending on ndev->flags, set PRM or clear MCT 1981 */ 1982 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT; 1983 1984 if (!(ndev->flags & IFF_MULTICAST)) { 1985 sh_eth_tsu_purge_mcast(ndev); 1986 mcast_all = 1; 1987 } 1988 if (ndev->flags & IFF_ALLMULTI) { 1989 sh_eth_tsu_purge_mcast(ndev); 1990 ecmr_bits &= ~ECMR_MCT; 1991 mcast_all = 1; 1992 } 1993 1994 if (ndev->flags & IFF_PROMISC) { 1995 sh_eth_tsu_purge_all(ndev); 1996 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 1997 } else if (mdp->cd->tsu) { 1998 struct netdev_hw_addr *ha; 1999 netdev_for_each_mc_addr(ha, ndev) { 2000 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2001 continue; 2002 2003 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2004 if (!mcast_all) { 2005 sh_eth_tsu_purge_mcast(ndev); 2006 ecmr_bits &= ~ECMR_MCT; 2007 mcast_all = 1; 2008 } 2009 } 2010 } 2011 } else { 2012 /* Normal, unicast/broadcast-only mode. */ 2013 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT; 2014 } 2015 2016 /* update the ethernet mode */ 2017 sh_eth_write(ndev, ecmr_bits, ECMR); 2018 2019 spin_unlock_irqrestore(&mdp->lock, flags); 2020} 2021 2022static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2023{ 2024 if (!mdp->port) 2025 return TSU_VTAG0; 2026 else 2027 return TSU_VTAG1; 2028} 2029 2030static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, u16 vid) 2031{ 2032 struct sh_eth_private *mdp = netdev_priv(ndev); 2033 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2034 2035 if (unlikely(!mdp->cd->tsu)) 2036 return -EPERM; 2037 2038 /* No filtering if vid = 0 */ 2039 if (!vid) 2040 return 0; 2041 2042 mdp->vlan_num_ids++; 2043 2044 /* 2045 * The controller has one VLAN tag HW filter. So, if the filter is 2046 * already enabled, the driver disables it and the filte 2047 */ 2048 if (mdp->vlan_num_ids > 1) { 2049 /* disable VLAN filter */ 2050 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2051 return 0; 2052 } 2053 2054 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2055 vtag_reg_index); 2056 2057 return 0; 2058} 2059 2060static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, u16 vid) 2061{ 2062 struct sh_eth_private *mdp = netdev_priv(ndev); 2063 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2064 2065 if (unlikely(!mdp->cd->tsu)) 2066 return -EPERM; 2067 2068 /* No filtering if vid = 0 */ 2069 if (!vid) 2070 return 0; 2071 2072 mdp->vlan_num_ids--; 2073 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2074 2075 return 0; 2076} 2077#endif /* SH_ETH_HAS_TSU */ 2078 2079/* SuperH's TSU register init function */ 2080static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2081{ 2082 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2083 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2084 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2085 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2086 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2087 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2088 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2089 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2090 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2091 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2092 if (sh_eth_is_gether(mdp)) { 2093 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2094 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2095 } else { 2096 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2097 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2098 } 2099 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2100 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2101 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2102 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2103 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2104 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2105 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2106} 2107 2108/* MDIO bus release function */ 2109static int sh_mdio_release(struct net_device *ndev) 2110{ 2111 struct mii_bus *bus = dev_get_drvdata(&ndev->dev); 2112 2113 /* unregister mdio bus */ 2114 mdiobus_unregister(bus); 2115 2116 /* remove mdio bus info from net_device */ 2117 dev_set_drvdata(&ndev->dev, NULL); 2118 2119 /* free interrupts memory */ 2120 kfree(bus->irq); 2121 2122 /* free bitbang info */ 2123 free_mdio_bitbang(bus); 2124 2125 return 0; 2126} 2127 2128/* MDIO bus init function */ 2129static int sh_mdio_init(struct net_device *ndev, int id, 2130 struct sh_eth_plat_data *pd) 2131{ 2132 int ret, i; 2133 struct bb_info *bitbang; 2134 struct sh_eth_private *mdp = netdev_priv(ndev); 2135 2136 /* create bit control struct for PHY */ 2137 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL); 2138 if (!bitbang) { 2139 ret = -ENOMEM; 2140 goto out; 2141 } 2142 2143 /* bitbang init */ 2144 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2145 bitbang->set_gate = pd->set_mdio_gate; 2146 bitbang->mdi_msk = 0x08; 2147 bitbang->mdo_msk = 0x04; 2148 bitbang->mmd_msk = 0x02;/* MMD */ 2149 bitbang->mdc_msk = 0x01; 2150 bitbang->ctrl.ops = &bb_ops; 2151 2152 /* MII controller setting */ 2153 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2154 if (!mdp->mii_bus) { 2155 ret = -ENOMEM; 2156 goto out_free_bitbang; 2157 } 2158 2159 /* Hook up MII support for ethtool */ 2160 mdp->mii_bus->name = "sh_mii"; 2161 mdp->mii_bus->parent = &ndev->dev; 2162 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2163 mdp->pdev->name, id); 2164 2165 /* PHY IRQ */ 2166 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); 2167 if (!mdp->mii_bus->irq) { 2168 ret = -ENOMEM; 2169 goto out_free_bus; 2170 } 2171 2172 for (i = 0; i < PHY_MAX_ADDR; i++) 2173 mdp->mii_bus->irq[i] = PHY_POLL; 2174 2175 /* regist mdio bus */ 2176 ret = mdiobus_register(mdp->mii_bus); 2177 if (ret) 2178 goto out_free_irq; 2179 2180 dev_set_drvdata(&ndev->dev, mdp->mii_bus); 2181 2182 return 0; 2183 2184out_free_irq: 2185 kfree(mdp->mii_bus->irq); 2186 2187out_free_bus: 2188 free_mdio_bitbang(mdp->mii_bus); 2189 2190out_free_bitbang: 2191 kfree(bitbang); 2192 2193out: 2194 return ret; 2195} 2196 2197static const u16 *sh_eth_get_register_offset(int register_type) 2198{ 2199 const u16 *reg_offset = NULL; 2200 2201 switch (register_type) { 2202 case SH_ETH_REG_GIGABIT: 2203 reg_offset = sh_eth_offset_gigabit; 2204 break; 2205 case SH_ETH_REG_FAST_SH4: 2206 reg_offset = sh_eth_offset_fast_sh4; 2207 break; 2208 case SH_ETH_REG_FAST_SH3_SH2: 2209 reg_offset = sh_eth_offset_fast_sh3_sh2; 2210 break; 2211 default: 2212 printk(KERN_ERR "Unknown register type (%d)\n", register_type); 2213 break; 2214 } 2215 2216 return reg_offset; 2217} 2218 2219static const struct net_device_ops sh_eth_netdev_ops = { 2220 .ndo_open = sh_eth_open, 2221 .ndo_stop = sh_eth_close, 2222 .ndo_start_xmit = sh_eth_start_xmit, 2223 .ndo_get_stats = sh_eth_get_stats, 2224#if defined(SH_ETH_HAS_TSU) 2225 .ndo_set_rx_mode = sh_eth_set_multicast_list, 2226 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 2227 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 2228#endif 2229 .ndo_tx_timeout = sh_eth_tx_timeout, 2230 .ndo_do_ioctl = sh_eth_do_ioctl, 2231 .ndo_validate_addr = eth_validate_addr, 2232 .ndo_set_mac_address = eth_mac_addr, 2233 .ndo_change_mtu = eth_change_mtu, 2234}; 2235 2236static int sh_eth_drv_probe(struct platform_device *pdev) 2237{ 2238 int ret, devno = 0; 2239 struct resource *res; 2240 struct net_device *ndev = NULL; 2241 struct sh_eth_private *mdp = NULL; 2242 struct sh_eth_plat_data *pd; 2243 2244 /* get base addr */ 2245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2246 if (unlikely(res == NULL)) { 2247 dev_err(&pdev->dev, "invalid resource\n"); 2248 ret = -EINVAL; 2249 goto out; 2250 } 2251 2252 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 2253 if (!ndev) { 2254 ret = -ENOMEM; 2255 goto out; 2256 } 2257 2258 /* The sh Ether-specific entries in the device structure. */ 2259 ndev->base_addr = res->start; 2260 devno = pdev->id; 2261 if (devno < 0) 2262 devno = 0; 2263 2264 ndev->dma = -1; 2265 ret = platform_get_irq(pdev, 0); 2266 if (ret < 0) { 2267 ret = -ENODEV; 2268 goto out_release; 2269 } 2270 ndev->irq = ret; 2271 2272 SET_NETDEV_DEV(ndev, &pdev->dev); 2273 2274 /* Fill in the fields of the device structure with ethernet values. */ 2275 ether_setup(ndev); 2276 2277 mdp = netdev_priv(ndev); 2278 mdp->addr = ioremap(res->start, resource_size(res)); 2279 if (mdp->addr == NULL) { 2280 ret = -ENOMEM; 2281 dev_err(&pdev->dev, "ioremap failed.\n"); 2282 goto out_release; 2283 } 2284 2285 spin_lock_init(&mdp->lock); 2286 mdp->pdev = pdev; 2287 pm_runtime_enable(&pdev->dev); 2288 pm_runtime_resume(&pdev->dev); 2289 2290 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data); 2291 /* get PHY ID */ 2292 mdp->phy_id = pd->phy; 2293 mdp->phy_interface = pd->phy_interface; 2294 /* EDMAC endian */ 2295 mdp->edmac_endian = pd->edmac_endian; 2296 mdp->no_ether_link = pd->no_ether_link; 2297 mdp->ether_link_active_low = pd->ether_link_active_low; 2298 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type); 2299 2300 /* set cpu data */ 2301#if defined(SH_ETH_HAS_BOTH_MODULES) 2302 mdp->cd = sh_eth_get_cpu_data(mdp); 2303#else 2304 mdp->cd = &sh_eth_my_cpu_data; 2305#endif 2306 sh_eth_set_default_cpu_data(mdp->cd); 2307 2308 /* set function */ 2309 ndev->netdev_ops = &sh_eth_netdev_ops; 2310 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); 2311 ndev->watchdog_timeo = TX_TIMEOUT; 2312 2313 /* debug message level */ 2314 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 2315 mdp->post_rx = POST_RX >> (devno << 1); 2316 mdp->post_fw = POST_FW >> (devno << 1); 2317 2318 /* read and set MAC address */ 2319 read_mac_address(ndev, pd->mac_addr); 2320 2321 /* ioremap the TSU registers */ 2322 if (mdp->cd->tsu) { 2323 struct resource *rtsu; 2324 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2325 if (!rtsu) { 2326 dev_err(&pdev->dev, "Not found TSU resource\n"); 2327 goto out_release; 2328 } 2329 mdp->tsu_addr = ioremap(rtsu->start, 2330 resource_size(rtsu)); 2331 mdp->port = devno % 2; 2332 ndev->features = NETIF_F_HW_VLAN_FILTER; 2333 } 2334 2335 /* initialize first or needed device */ 2336 if (!devno || pd->needs_init) { 2337 if (mdp->cd->chip_reset) 2338 mdp->cd->chip_reset(ndev); 2339 2340 if (mdp->cd->tsu) { 2341 /* TSU init (Init only)*/ 2342 sh_eth_tsu_init(mdp); 2343 } 2344 } 2345 2346 /* network device register */ 2347 ret = register_netdev(ndev); 2348 if (ret) 2349 goto out_release; 2350 2351 /* mdio bus init */ 2352 ret = sh_mdio_init(ndev, pdev->id, pd); 2353 if (ret) 2354 goto out_unregister; 2355 2356 /* print device information */ 2357 pr_info("Base address at 0x%x, %pM, IRQ %d.\n", 2358 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2359 2360 platform_set_drvdata(pdev, ndev); 2361 2362 return ret; 2363 2364out_unregister: 2365 unregister_netdev(ndev); 2366 2367out_release: 2368 /* net_dev free */ 2369 if (mdp && mdp->addr) 2370 iounmap(mdp->addr); 2371 if (mdp && mdp->tsu_addr) 2372 iounmap(mdp->tsu_addr); 2373 if (ndev) 2374 free_netdev(ndev); 2375 2376out: 2377 return ret; 2378} 2379 2380static int sh_eth_drv_remove(struct platform_device *pdev) 2381{ 2382 struct net_device *ndev = platform_get_drvdata(pdev); 2383 struct sh_eth_private *mdp = netdev_priv(ndev); 2384 2385 if (mdp->cd->tsu) 2386 iounmap(mdp->tsu_addr); 2387 sh_mdio_release(ndev); 2388 unregister_netdev(ndev); 2389 pm_runtime_disable(&pdev->dev); 2390 iounmap(mdp->addr); 2391 free_netdev(ndev); 2392 platform_set_drvdata(pdev, NULL); 2393 2394 return 0; 2395} 2396 2397static int sh_eth_runtime_nop(struct device *dev) 2398{ 2399 /* 2400 * Runtime PM callback shared between ->runtime_suspend() 2401 * and ->runtime_resume(). Simply returns success. 2402 * 2403 * This driver re-initializes all registers after 2404 * pm_runtime_get_sync() anyway so there is no need 2405 * to save and restore registers here. 2406 */ 2407 return 0; 2408} 2409 2410static struct dev_pm_ops sh_eth_dev_pm_ops = { 2411 .runtime_suspend = sh_eth_runtime_nop, 2412 .runtime_resume = sh_eth_runtime_nop, 2413}; 2414 2415static struct platform_driver sh_eth_driver = { 2416 .probe = sh_eth_drv_probe, 2417 .remove = sh_eth_drv_remove, 2418 .driver = { 2419 .name = CARDNAME, 2420 .pm = &sh_eth_dev_pm_ops, 2421 }, 2422}; 2423 2424module_platform_driver(sh_eth_driver); 2425 2426MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 2427MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 2428MODULE_LICENSE("GPL v2"); 2429