sh_eth.c revision d8b0426af5b67973585712c9af36b86f6ea97815
1/* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 4 * Copyright (C) 2008-2014 Renesas Solutions Corp. 5 * Copyright (C) 2013-2014 Cogent Embedded, Inc. 6 * Copyright (C) 2014 Codethink Limited 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * The full GNU General Public License is included in this distribution in 18 * the file called "COPYING". 19 */ 20 21#include <linux/module.h> 22#include <linux/kernel.h> 23#include <linux/spinlock.h> 24#include <linux/interrupt.h> 25#include <linux/dma-mapping.h> 26#include <linux/etherdevice.h> 27#include <linux/delay.h> 28#include <linux/platform_device.h> 29#include <linux/mdio-bitbang.h> 30#include <linux/netdevice.h> 31#include <linux/of.h> 32#include <linux/of_device.h> 33#include <linux/of_irq.h> 34#include <linux/of_net.h> 35#include <linux/phy.h> 36#include <linux/cache.h> 37#include <linux/io.h> 38#include <linux/pm_runtime.h> 39#include <linux/slab.h> 40#include <linux/ethtool.h> 41#include <linux/if_vlan.h> 42#include <linux/clk.h> 43#include <linux/sh_eth.h> 44#include <linux/of_mdio.h> 45 46#include "sh_eth.h" 47 48#define SH_ETH_DEF_MSG_ENABLE \ 49 (NETIF_MSG_LINK | \ 50 NETIF_MSG_TIMER | \ 51 NETIF_MSG_RX_ERR| \ 52 NETIF_MSG_TX_ERR) 53 54static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 55 [EDSR] = 0x0000, 56 [EDMR] = 0x0400, 57 [EDTRR] = 0x0408, 58 [EDRRR] = 0x0410, 59 [EESR] = 0x0428, 60 [EESIPR] = 0x0430, 61 [TDLAR] = 0x0010, 62 [TDFAR] = 0x0014, 63 [TDFXR] = 0x0018, 64 [TDFFR] = 0x001c, 65 [RDLAR] = 0x0030, 66 [RDFAR] = 0x0034, 67 [RDFXR] = 0x0038, 68 [RDFFR] = 0x003c, 69 [TRSCER] = 0x0438, 70 [RMFCR] = 0x0440, 71 [TFTR] = 0x0448, 72 [FDR] = 0x0450, 73 [RMCR] = 0x0458, 74 [RPADIR] = 0x0460, 75 [FCFTR] = 0x0468, 76 [CSMR] = 0x04E4, 77 78 [ECMR] = 0x0500, 79 [ECSR] = 0x0510, 80 [ECSIPR] = 0x0518, 81 [PIR] = 0x0520, 82 [PSR] = 0x0528, 83 [PIPR] = 0x052c, 84 [RFLR] = 0x0508, 85 [APR] = 0x0554, 86 [MPR] = 0x0558, 87 [PFTCR] = 0x055c, 88 [PFRCR] = 0x0560, 89 [TPAUSER] = 0x0564, 90 [GECMR] = 0x05b0, 91 [BCULR] = 0x05b4, 92 [MAHR] = 0x05c0, 93 [MALR] = 0x05c8, 94 [TROCR] = 0x0700, 95 [CDCR] = 0x0708, 96 [LCCR] = 0x0710, 97 [CEFCR] = 0x0740, 98 [FRECR] = 0x0748, 99 [TSFRCR] = 0x0750, 100 [TLFRCR] = 0x0758, 101 [RFCR] = 0x0760, 102 [CERCR] = 0x0768, 103 [CEECR] = 0x0770, 104 [MAFCR] = 0x0778, 105 [RMII_MII] = 0x0790, 106 107 [ARSTR] = 0x0000, 108 [TSU_CTRST] = 0x0004, 109 [TSU_FWEN0] = 0x0010, 110 [TSU_FWEN1] = 0x0014, 111 [TSU_FCM] = 0x0018, 112 [TSU_BSYSL0] = 0x0020, 113 [TSU_BSYSL1] = 0x0024, 114 [TSU_PRISL0] = 0x0028, 115 [TSU_PRISL1] = 0x002c, 116 [TSU_FWSL0] = 0x0030, 117 [TSU_FWSL1] = 0x0034, 118 [TSU_FWSLC] = 0x0038, 119 [TSU_QTAG0] = 0x0040, 120 [TSU_QTAG1] = 0x0044, 121 [TSU_FWSR] = 0x0050, 122 [TSU_FWINMK] = 0x0054, 123 [TSU_ADQT0] = 0x0048, 124 [TSU_ADQT1] = 0x004c, 125 [TSU_VTAG0] = 0x0058, 126 [TSU_VTAG1] = 0x005c, 127 [TSU_ADSBSY] = 0x0060, 128 [TSU_TEN] = 0x0064, 129 [TSU_POST1] = 0x0070, 130 [TSU_POST2] = 0x0074, 131 [TSU_POST3] = 0x0078, 132 [TSU_POST4] = 0x007c, 133 [TSU_ADRH0] = 0x0100, 134 [TSU_ADRL0] = 0x0104, 135 [TSU_ADRH31] = 0x01f8, 136 [TSU_ADRL31] = 0x01fc, 137 138 [TXNLCR0] = 0x0080, 139 [TXALCR0] = 0x0084, 140 [RXNLCR0] = 0x0088, 141 [RXALCR0] = 0x008c, 142 [FWNLCR0] = 0x0090, 143 [FWALCR0] = 0x0094, 144 [TXNLCR1] = 0x00a0, 145 [TXALCR1] = 0x00a0, 146 [RXNLCR1] = 0x00a8, 147 [RXALCR1] = 0x00ac, 148 [FWNLCR1] = 0x00b0, 149 [FWALCR1] = 0x00b4, 150}; 151 152static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 153 [EDSR] = 0x0000, 154 [EDMR] = 0x0400, 155 [EDTRR] = 0x0408, 156 [EDRRR] = 0x0410, 157 [EESR] = 0x0428, 158 [EESIPR] = 0x0430, 159 [TDLAR] = 0x0010, 160 [TDFAR] = 0x0014, 161 [TDFXR] = 0x0018, 162 [TDFFR] = 0x001c, 163 [RDLAR] = 0x0030, 164 [RDFAR] = 0x0034, 165 [RDFXR] = 0x0038, 166 [RDFFR] = 0x003c, 167 [TRSCER] = 0x0438, 168 [RMFCR] = 0x0440, 169 [TFTR] = 0x0448, 170 [FDR] = 0x0450, 171 [RMCR] = 0x0458, 172 [RPADIR] = 0x0460, 173 [FCFTR] = 0x0468, 174 [CSMR] = 0x04E4, 175 176 [ECMR] = 0x0500, 177 [RFLR] = 0x0508, 178 [ECSR] = 0x0510, 179 [ECSIPR] = 0x0518, 180 [PIR] = 0x0520, 181 [APR] = 0x0554, 182 [MPR] = 0x0558, 183 [PFTCR] = 0x055c, 184 [PFRCR] = 0x0560, 185 [TPAUSER] = 0x0564, 186 [MAHR] = 0x05c0, 187 [MALR] = 0x05c8, 188 [CEFCR] = 0x0740, 189 [FRECR] = 0x0748, 190 [TSFRCR] = 0x0750, 191 [TLFRCR] = 0x0758, 192 [RFCR] = 0x0760, 193 [MAFCR] = 0x0778, 194 195 [ARSTR] = 0x0000, 196 [TSU_CTRST] = 0x0004, 197 [TSU_VTAG0] = 0x0058, 198 [TSU_ADSBSY] = 0x0060, 199 [TSU_TEN] = 0x0064, 200 [TSU_ADRH0] = 0x0100, 201 [TSU_ADRL0] = 0x0104, 202 [TSU_ADRH31] = 0x01f8, 203 [TSU_ADRL31] = 0x01fc, 204 205 [TXNLCR0] = 0x0080, 206 [TXALCR0] = 0x0084, 207 [RXNLCR0] = 0x0088, 208 [RXALCR0] = 0x008C, 209}; 210 211static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 212 [ECMR] = 0x0300, 213 [RFLR] = 0x0308, 214 [ECSR] = 0x0310, 215 [ECSIPR] = 0x0318, 216 [PIR] = 0x0320, 217 [PSR] = 0x0328, 218 [RDMLR] = 0x0340, 219 [IPGR] = 0x0350, 220 [APR] = 0x0354, 221 [MPR] = 0x0358, 222 [RFCF] = 0x0360, 223 [TPAUSER] = 0x0364, 224 [TPAUSECR] = 0x0368, 225 [MAHR] = 0x03c0, 226 [MALR] = 0x03c8, 227 [TROCR] = 0x03d0, 228 [CDCR] = 0x03d4, 229 [LCCR] = 0x03d8, 230 [CNDCR] = 0x03dc, 231 [CEFCR] = 0x03e4, 232 [FRECR] = 0x03e8, 233 [TSFRCR] = 0x03ec, 234 [TLFRCR] = 0x03f0, 235 [RFCR] = 0x03f4, 236 [MAFCR] = 0x03f8, 237 238 [EDMR] = 0x0200, 239 [EDTRR] = 0x0208, 240 [EDRRR] = 0x0210, 241 [TDLAR] = 0x0218, 242 [RDLAR] = 0x0220, 243 [EESR] = 0x0228, 244 [EESIPR] = 0x0230, 245 [TRSCER] = 0x0238, 246 [RMFCR] = 0x0240, 247 [TFTR] = 0x0248, 248 [FDR] = 0x0250, 249 [RMCR] = 0x0258, 250 [TFUCR] = 0x0264, 251 [RFOCR] = 0x0268, 252 [RMIIMODE] = 0x026c, 253 [FCFTR] = 0x0270, 254 [TRIMD] = 0x027c, 255}; 256 257static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 258 [ECMR] = 0x0100, 259 [RFLR] = 0x0108, 260 [ECSR] = 0x0110, 261 [ECSIPR] = 0x0118, 262 [PIR] = 0x0120, 263 [PSR] = 0x0128, 264 [RDMLR] = 0x0140, 265 [IPGR] = 0x0150, 266 [APR] = 0x0154, 267 [MPR] = 0x0158, 268 [TPAUSER] = 0x0164, 269 [RFCF] = 0x0160, 270 [TPAUSECR] = 0x0168, 271 [BCFRR] = 0x016c, 272 [MAHR] = 0x01c0, 273 [MALR] = 0x01c8, 274 [TROCR] = 0x01d0, 275 [CDCR] = 0x01d4, 276 [LCCR] = 0x01d8, 277 [CNDCR] = 0x01dc, 278 [CEFCR] = 0x01e4, 279 [FRECR] = 0x01e8, 280 [TSFRCR] = 0x01ec, 281 [TLFRCR] = 0x01f0, 282 [RFCR] = 0x01f4, 283 [MAFCR] = 0x01f8, 284 [RTRATE] = 0x01fc, 285 286 [EDMR] = 0x0000, 287 [EDTRR] = 0x0008, 288 [EDRRR] = 0x0010, 289 [TDLAR] = 0x0018, 290 [RDLAR] = 0x0020, 291 [EESR] = 0x0028, 292 [EESIPR] = 0x0030, 293 [TRSCER] = 0x0038, 294 [RMFCR] = 0x0040, 295 [TFTR] = 0x0048, 296 [FDR] = 0x0050, 297 [RMCR] = 0x0058, 298 [TFUCR] = 0x0064, 299 [RFOCR] = 0x0068, 300 [FCFTR] = 0x0070, 301 [RPADIR] = 0x0078, 302 [TRIMD] = 0x007c, 303 [RBWAR] = 0x00c8, 304 [RDFAR] = 0x00cc, 305 [TBRAR] = 0x00d4, 306 [TDFAR] = 0x00d8, 307}; 308 309static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 310 [EDMR] = 0x0000, 311 [EDTRR] = 0x0004, 312 [EDRRR] = 0x0008, 313 [TDLAR] = 0x000c, 314 [RDLAR] = 0x0010, 315 [EESR] = 0x0014, 316 [EESIPR] = 0x0018, 317 [TRSCER] = 0x001c, 318 [RMFCR] = 0x0020, 319 [TFTR] = 0x0024, 320 [FDR] = 0x0028, 321 [RMCR] = 0x002c, 322 [EDOCR] = 0x0030, 323 [FCFTR] = 0x0034, 324 [RPADIR] = 0x0038, 325 [TRIMD] = 0x003c, 326 [RBWAR] = 0x0040, 327 [RDFAR] = 0x0044, 328 [TBRAR] = 0x004c, 329 [TDFAR] = 0x0050, 330 331 [ECMR] = 0x0160, 332 [ECSR] = 0x0164, 333 [ECSIPR] = 0x0168, 334 [PIR] = 0x016c, 335 [MAHR] = 0x0170, 336 [MALR] = 0x0174, 337 [RFLR] = 0x0178, 338 [PSR] = 0x017c, 339 [TROCR] = 0x0180, 340 [CDCR] = 0x0184, 341 [LCCR] = 0x0188, 342 [CNDCR] = 0x018c, 343 [CEFCR] = 0x0194, 344 [FRECR] = 0x0198, 345 [TSFRCR] = 0x019c, 346 [TLFRCR] = 0x01a0, 347 [RFCR] = 0x01a4, 348 [MAFCR] = 0x01a8, 349 [IPGR] = 0x01b4, 350 [APR] = 0x01b8, 351 [MPR] = 0x01bc, 352 [TPAUSER] = 0x01c4, 353 [BCFR] = 0x01cc, 354 355 [ARSTR] = 0x0000, 356 [TSU_CTRST] = 0x0004, 357 [TSU_FWEN0] = 0x0010, 358 [TSU_FWEN1] = 0x0014, 359 [TSU_FCM] = 0x0018, 360 [TSU_BSYSL0] = 0x0020, 361 [TSU_BSYSL1] = 0x0024, 362 [TSU_PRISL0] = 0x0028, 363 [TSU_PRISL1] = 0x002c, 364 [TSU_FWSL0] = 0x0030, 365 [TSU_FWSL1] = 0x0034, 366 [TSU_FWSLC] = 0x0038, 367 [TSU_QTAGM0] = 0x0040, 368 [TSU_QTAGM1] = 0x0044, 369 [TSU_ADQT0] = 0x0048, 370 [TSU_ADQT1] = 0x004c, 371 [TSU_FWSR] = 0x0050, 372 [TSU_FWINMK] = 0x0054, 373 [TSU_ADSBSY] = 0x0060, 374 [TSU_TEN] = 0x0064, 375 [TSU_POST1] = 0x0070, 376 [TSU_POST2] = 0x0074, 377 [TSU_POST3] = 0x0078, 378 [TSU_POST4] = 0x007c, 379 380 [TXNLCR0] = 0x0080, 381 [TXALCR0] = 0x0084, 382 [RXNLCR0] = 0x0088, 383 [RXALCR0] = 0x008c, 384 [FWNLCR0] = 0x0090, 385 [FWALCR0] = 0x0094, 386 [TXNLCR1] = 0x00a0, 387 [TXALCR1] = 0x00a0, 388 [RXNLCR1] = 0x00a8, 389 [RXALCR1] = 0x00ac, 390 [FWNLCR1] = 0x00b0, 391 [FWALCR1] = 0x00b4, 392 393 [TSU_ADRH0] = 0x0100, 394 [TSU_ADRL0] = 0x0104, 395 [TSU_ADRL31] = 0x01fc, 396}; 397 398static bool sh_eth_is_gether(struct sh_eth_private *mdp) 399{ 400 return mdp->reg_offset == sh_eth_offset_gigabit; 401} 402 403static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp) 404{ 405 return mdp->reg_offset == sh_eth_offset_fast_rz; 406} 407 408static void sh_eth_select_mii(struct net_device *ndev) 409{ 410 u32 value = 0x0; 411 struct sh_eth_private *mdp = netdev_priv(ndev); 412 413 switch (mdp->phy_interface) { 414 case PHY_INTERFACE_MODE_GMII: 415 value = 0x2; 416 break; 417 case PHY_INTERFACE_MODE_MII: 418 value = 0x1; 419 break; 420 case PHY_INTERFACE_MODE_RMII: 421 value = 0x0; 422 break; 423 default: 424 netdev_warn(ndev, 425 "PHY interface mode was not setup. Set to MII.\n"); 426 value = 0x1; 427 break; 428 } 429 430 sh_eth_write(ndev, value, RMII_MII); 431} 432 433static void sh_eth_set_duplex(struct net_device *ndev) 434{ 435 struct sh_eth_private *mdp = netdev_priv(ndev); 436 437 if (mdp->duplex) /* Full */ 438 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 439 else /* Half */ 440 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 441} 442 443/* There is CPU dependent code */ 444static void sh_eth_set_rate_r8a777x(struct net_device *ndev) 445{ 446 struct sh_eth_private *mdp = netdev_priv(ndev); 447 448 switch (mdp->speed) { 449 case 10: /* 10BASE */ 450 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR); 451 break; 452 case 100:/* 100BASE */ 453 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR); 454 break; 455 default: 456 break; 457 } 458} 459 460/* R8A7778/9 */ 461static struct sh_eth_cpu_data r8a777x_data = { 462 .set_duplex = sh_eth_set_duplex, 463 .set_rate = sh_eth_set_rate_r8a777x, 464 465 .register_type = SH_ETH_REG_FAST_RCAR, 466 467 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 468 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 469 .eesipr_value = 0x01ff009f, 470 471 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 472 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 473 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 474 EESR_ECI, 475 476 .apr = 1, 477 .mpr = 1, 478 .tpauser = 1, 479 .hw_swap = 1, 480}; 481 482/* R8A7790/1 */ 483static struct sh_eth_cpu_data r8a779x_data = { 484 .set_duplex = sh_eth_set_duplex, 485 .set_rate = sh_eth_set_rate_r8a777x, 486 487 .register_type = SH_ETH_REG_FAST_RCAR, 488 489 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 490 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 491 .eesipr_value = 0x01ff009f, 492 493 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 494 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 495 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 496 EESR_ECI, 497 498 .apr = 1, 499 .mpr = 1, 500 .tpauser = 1, 501 .hw_swap = 1, 502 .rmiimode = 1, 503 .shift_rd0 = 1, 504}; 505 506static void sh_eth_set_rate_sh7724(struct net_device *ndev) 507{ 508 struct sh_eth_private *mdp = netdev_priv(ndev); 509 510 switch (mdp->speed) { 511 case 10: /* 10BASE */ 512 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 513 break; 514 case 100:/* 100BASE */ 515 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 516 break; 517 default: 518 break; 519 } 520} 521 522/* SH7724 */ 523static struct sh_eth_cpu_data sh7724_data = { 524 .set_duplex = sh_eth_set_duplex, 525 .set_rate = sh_eth_set_rate_sh7724, 526 527 .register_type = SH_ETH_REG_FAST_SH4, 528 529 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 530 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 531 .eesipr_value = 0x01ff009f, 532 533 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 534 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 535 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 536 EESR_ECI, 537 538 .apr = 1, 539 .mpr = 1, 540 .tpauser = 1, 541 .hw_swap = 1, 542 .rpadir = 1, 543 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 544}; 545 546static void sh_eth_set_rate_sh7757(struct net_device *ndev) 547{ 548 struct sh_eth_private *mdp = netdev_priv(ndev); 549 550 switch (mdp->speed) { 551 case 10: /* 10BASE */ 552 sh_eth_write(ndev, 0, RTRATE); 553 break; 554 case 100:/* 100BASE */ 555 sh_eth_write(ndev, 1, RTRATE); 556 break; 557 default: 558 break; 559 } 560} 561 562/* SH7757 */ 563static struct sh_eth_cpu_data sh7757_data = { 564 .set_duplex = sh_eth_set_duplex, 565 .set_rate = sh_eth_set_rate_sh7757, 566 567 .register_type = SH_ETH_REG_FAST_SH4, 568 569 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 570 571 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 572 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 573 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 574 EESR_ECI, 575 576 .irq_flags = IRQF_SHARED, 577 .apr = 1, 578 .mpr = 1, 579 .tpauser = 1, 580 .hw_swap = 1, 581 .no_ade = 1, 582 .rpadir = 1, 583 .rpadir_value = 2 << 16, 584}; 585 586#define SH_GIGA_ETH_BASE 0xfee00000UL 587#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 588#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 589static void sh_eth_chip_reset_giga(struct net_device *ndev) 590{ 591 int i; 592 unsigned long mahr[2], malr[2]; 593 594 /* save MAHR and MALR */ 595 for (i = 0; i < 2; i++) { 596 malr[i] = ioread32((void *)GIGA_MALR(i)); 597 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 598 } 599 600 /* reset device */ 601 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 602 mdelay(1); 603 604 /* restore MAHR and MALR */ 605 for (i = 0; i < 2; i++) { 606 iowrite32(malr[i], (void *)GIGA_MALR(i)); 607 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 608 } 609} 610 611static void sh_eth_set_rate_giga(struct net_device *ndev) 612{ 613 struct sh_eth_private *mdp = netdev_priv(ndev); 614 615 switch (mdp->speed) { 616 case 10: /* 10BASE */ 617 sh_eth_write(ndev, 0x00000000, GECMR); 618 break; 619 case 100:/* 100BASE */ 620 sh_eth_write(ndev, 0x00000010, GECMR); 621 break; 622 case 1000: /* 1000BASE */ 623 sh_eth_write(ndev, 0x00000020, GECMR); 624 break; 625 default: 626 break; 627 } 628} 629 630/* SH7757(GETHERC) */ 631static struct sh_eth_cpu_data sh7757_data_giga = { 632 .chip_reset = sh_eth_chip_reset_giga, 633 .set_duplex = sh_eth_set_duplex, 634 .set_rate = sh_eth_set_rate_giga, 635 636 .register_type = SH_ETH_REG_GIGABIT, 637 638 .ecsr_value = ECSR_ICD | ECSR_MPD, 639 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 640 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 641 642 .tx_check = EESR_TC1 | EESR_FTC, 643 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 644 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 645 EESR_TDE | EESR_ECI, 646 .fdr_value = 0x0000072f, 647 648 .irq_flags = IRQF_SHARED, 649 .apr = 1, 650 .mpr = 1, 651 .tpauser = 1, 652 .bculr = 1, 653 .hw_swap = 1, 654 .rpadir = 1, 655 .rpadir_value = 2 << 16, 656 .no_trimd = 1, 657 .no_ade = 1, 658 .tsu = 1, 659}; 660 661static void sh_eth_chip_reset(struct net_device *ndev) 662{ 663 struct sh_eth_private *mdp = netdev_priv(ndev); 664 665 /* reset device */ 666 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 667 mdelay(1); 668} 669 670static void sh_eth_set_rate_gether(struct net_device *ndev) 671{ 672 struct sh_eth_private *mdp = netdev_priv(ndev); 673 674 switch (mdp->speed) { 675 case 10: /* 10BASE */ 676 sh_eth_write(ndev, GECMR_10, GECMR); 677 break; 678 case 100:/* 100BASE */ 679 sh_eth_write(ndev, GECMR_100, GECMR); 680 break; 681 case 1000: /* 1000BASE */ 682 sh_eth_write(ndev, GECMR_1000, GECMR); 683 break; 684 default: 685 break; 686 } 687} 688 689/* SH7734 */ 690static struct sh_eth_cpu_data sh7734_data = { 691 .chip_reset = sh_eth_chip_reset, 692 .set_duplex = sh_eth_set_duplex, 693 .set_rate = sh_eth_set_rate_gether, 694 695 .register_type = SH_ETH_REG_GIGABIT, 696 697 .ecsr_value = ECSR_ICD | ECSR_MPD, 698 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 699 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 700 701 .tx_check = EESR_TC1 | EESR_FTC, 702 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 703 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 704 EESR_TDE | EESR_ECI, 705 706 .apr = 1, 707 .mpr = 1, 708 .tpauser = 1, 709 .bculr = 1, 710 .hw_swap = 1, 711 .no_trimd = 1, 712 .no_ade = 1, 713 .tsu = 1, 714 .hw_crc = 1, 715 .select_mii = 1, 716}; 717 718/* SH7763 */ 719static struct sh_eth_cpu_data sh7763_data = { 720 .chip_reset = sh_eth_chip_reset, 721 .set_duplex = sh_eth_set_duplex, 722 .set_rate = sh_eth_set_rate_gether, 723 724 .register_type = SH_ETH_REG_GIGABIT, 725 726 .ecsr_value = ECSR_ICD | ECSR_MPD, 727 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 728 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 729 730 .tx_check = EESR_TC1 | EESR_FTC, 731 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 732 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 733 EESR_ECI, 734 735 .apr = 1, 736 .mpr = 1, 737 .tpauser = 1, 738 .bculr = 1, 739 .hw_swap = 1, 740 .no_trimd = 1, 741 .no_ade = 1, 742 .tsu = 1, 743 .irq_flags = IRQF_SHARED, 744}; 745 746static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 747{ 748 struct sh_eth_private *mdp = netdev_priv(ndev); 749 750 /* reset device */ 751 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 752 mdelay(1); 753 754 sh_eth_select_mii(ndev); 755} 756 757/* R8A7740 */ 758static struct sh_eth_cpu_data r8a7740_data = { 759 .chip_reset = sh_eth_chip_reset_r8a7740, 760 .set_duplex = sh_eth_set_duplex, 761 .set_rate = sh_eth_set_rate_gether, 762 763 .register_type = SH_ETH_REG_GIGABIT, 764 765 .ecsr_value = ECSR_ICD | ECSR_MPD, 766 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 767 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 768 769 .tx_check = EESR_TC1 | EESR_FTC, 770 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 771 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 772 EESR_TDE | EESR_ECI, 773 .fdr_value = 0x0000070f, 774 775 .apr = 1, 776 .mpr = 1, 777 .tpauser = 1, 778 .bculr = 1, 779 .hw_swap = 1, 780 .rpadir = 1, 781 .rpadir_value = 2 << 16, 782 .no_trimd = 1, 783 .no_ade = 1, 784 .tsu = 1, 785 .select_mii = 1, 786 .shift_rd0 = 1, 787}; 788 789/* R7S72100 */ 790static struct sh_eth_cpu_data r7s72100_data = { 791 .chip_reset = sh_eth_chip_reset, 792 .set_duplex = sh_eth_set_duplex, 793 794 .register_type = SH_ETH_REG_FAST_RZ, 795 796 .ecsr_value = ECSR_ICD, 797 .ecsipr_value = ECSIPR_ICDIP, 798 .eesipr_value = 0xff7f009f, 799 800 .tx_check = EESR_TC1 | EESR_FTC, 801 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 802 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 803 EESR_TDE | EESR_ECI, 804 .fdr_value = 0x0000070f, 805 806 .no_psr = 1, 807 .apr = 1, 808 .mpr = 1, 809 .tpauser = 1, 810 .hw_swap = 1, 811 .rpadir = 1, 812 .rpadir_value = 2 << 16, 813 .no_trimd = 1, 814 .no_ade = 1, 815 .hw_crc = 1, 816 .tsu = 1, 817 .shift_rd0 = 1, 818}; 819 820static struct sh_eth_cpu_data sh7619_data = { 821 .register_type = SH_ETH_REG_FAST_SH3_SH2, 822 823 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 824 825 .apr = 1, 826 .mpr = 1, 827 .tpauser = 1, 828 .hw_swap = 1, 829}; 830 831static struct sh_eth_cpu_data sh771x_data = { 832 .register_type = SH_ETH_REG_FAST_SH3_SH2, 833 834 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 835 .tsu = 1, 836}; 837 838static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 839{ 840 if (!cd->ecsr_value) 841 cd->ecsr_value = DEFAULT_ECSR_INIT; 842 843 if (!cd->ecsipr_value) 844 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 845 846 if (!cd->fcftr_value) 847 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 848 DEFAULT_FIFO_F_D_RFD; 849 850 if (!cd->fdr_value) 851 cd->fdr_value = DEFAULT_FDR_INIT; 852 853 if (!cd->tx_check) 854 cd->tx_check = DEFAULT_TX_CHECK; 855 856 if (!cd->eesr_err_check) 857 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 858} 859 860static int sh_eth_check_reset(struct net_device *ndev) 861{ 862 int ret = 0; 863 int cnt = 100; 864 865 while (cnt > 0) { 866 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 867 break; 868 mdelay(1); 869 cnt--; 870 } 871 if (cnt <= 0) { 872 netdev_err(ndev, "Device reset failed\n"); 873 ret = -ETIMEDOUT; 874 } 875 return ret; 876} 877 878static int sh_eth_reset(struct net_device *ndev) 879{ 880 struct sh_eth_private *mdp = netdev_priv(ndev); 881 int ret = 0; 882 883 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) { 884 sh_eth_write(ndev, EDSR_ENALL, EDSR); 885 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 886 EDMR); 887 888 ret = sh_eth_check_reset(ndev); 889 if (ret) 890 return ret; 891 892 /* Table Init */ 893 sh_eth_write(ndev, 0x0, TDLAR); 894 sh_eth_write(ndev, 0x0, TDFAR); 895 sh_eth_write(ndev, 0x0, TDFXR); 896 sh_eth_write(ndev, 0x0, TDFFR); 897 sh_eth_write(ndev, 0x0, RDLAR); 898 sh_eth_write(ndev, 0x0, RDFAR); 899 sh_eth_write(ndev, 0x0, RDFXR); 900 sh_eth_write(ndev, 0x0, RDFFR); 901 902 /* Reset HW CRC register */ 903 if (mdp->cd->hw_crc) 904 sh_eth_write(ndev, 0x0, CSMR); 905 906 /* Select MII mode */ 907 if (mdp->cd->select_mii) 908 sh_eth_select_mii(ndev); 909 } else { 910 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 911 EDMR); 912 mdelay(3); 913 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 914 EDMR); 915 } 916 917 return ret; 918} 919 920#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 921static void sh_eth_set_receive_align(struct sk_buff *skb) 922{ 923 int reserve; 924 925 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); 926 if (reserve) 927 skb_reserve(skb, reserve); 928} 929#else 930static void sh_eth_set_receive_align(struct sk_buff *skb) 931{ 932 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); 933} 934#endif 935 936 937/* CPU <-> EDMAC endian convert */ 938static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 939{ 940 switch (mdp->edmac_endian) { 941 case EDMAC_LITTLE_ENDIAN: 942 return cpu_to_le32(x); 943 case EDMAC_BIG_ENDIAN: 944 return cpu_to_be32(x); 945 } 946 return x; 947} 948 949static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) 950{ 951 switch (mdp->edmac_endian) { 952 case EDMAC_LITTLE_ENDIAN: 953 return le32_to_cpu(x); 954 case EDMAC_BIG_ENDIAN: 955 return be32_to_cpu(x); 956 } 957 return x; 958} 959 960/* Program the hardware MAC address from dev->dev_addr. */ 961static void update_mac_address(struct net_device *ndev) 962{ 963 sh_eth_write(ndev, 964 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 965 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 966 sh_eth_write(ndev, 967 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 968} 969 970/* Get MAC address from SuperH MAC address register 971 * 972 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 973 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 974 * When you want use this device, you must set MAC address in bootloader. 975 * 976 */ 977static void read_mac_address(struct net_device *ndev, unsigned char *mac) 978{ 979 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 980 memcpy(ndev->dev_addr, mac, ETH_ALEN); 981 } else { 982 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24); 983 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF; 984 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF; 985 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF); 986 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF; 987 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF); 988 } 989} 990 991static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 992{ 993 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) 994 return EDTRR_TRNS_GETHER; 995 else 996 return EDTRR_TRNS_ETHER; 997} 998 999struct bb_info { 1000 void (*set_gate)(void *addr); 1001 struct mdiobb_ctrl ctrl; 1002 void *addr; 1003 u32 mmd_msk;/* MMD */ 1004 u32 mdo_msk; 1005 u32 mdi_msk; 1006 u32 mdc_msk; 1007}; 1008 1009/* PHY bit set */ 1010static void bb_set(void *addr, u32 msk) 1011{ 1012 iowrite32(ioread32(addr) | msk, addr); 1013} 1014 1015/* PHY bit clear */ 1016static void bb_clr(void *addr, u32 msk) 1017{ 1018 iowrite32((ioread32(addr) & ~msk), addr); 1019} 1020 1021/* PHY bit read */ 1022static int bb_read(void *addr, u32 msk) 1023{ 1024 return (ioread32(addr) & msk) != 0; 1025} 1026 1027/* Data I/O pin control */ 1028static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1029{ 1030 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1031 1032 if (bitbang->set_gate) 1033 bitbang->set_gate(bitbang->addr); 1034 1035 if (bit) 1036 bb_set(bitbang->addr, bitbang->mmd_msk); 1037 else 1038 bb_clr(bitbang->addr, bitbang->mmd_msk); 1039} 1040 1041/* Set bit data*/ 1042static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1043{ 1044 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1045 1046 if (bitbang->set_gate) 1047 bitbang->set_gate(bitbang->addr); 1048 1049 if (bit) 1050 bb_set(bitbang->addr, bitbang->mdo_msk); 1051 else 1052 bb_clr(bitbang->addr, bitbang->mdo_msk); 1053} 1054 1055/* Get bit data*/ 1056static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1057{ 1058 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1059 1060 if (bitbang->set_gate) 1061 bitbang->set_gate(bitbang->addr); 1062 1063 return bb_read(bitbang->addr, bitbang->mdi_msk); 1064} 1065 1066/* MDC pin control */ 1067static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1068{ 1069 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1070 1071 if (bitbang->set_gate) 1072 bitbang->set_gate(bitbang->addr); 1073 1074 if (bit) 1075 bb_set(bitbang->addr, bitbang->mdc_msk); 1076 else 1077 bb_clr(bitbang->addr, bitbang->mdc_msk); 1078} 1079 1080/* mdio bus control struct */ 1081static struct mdiobb_ops bb_ops = { 1082 .owner = THIS_MODULE, 1083 .set_mdc = sh_mdc_ctrl, 1084 .set_mdio_dir = sh_mmd_ctrl, 1085 .set_mdio_data = sh_set_mdio, 1086 .get_mdio_data = sh_get_mdio, 1087}; 1088 1089/* free skb and descriptor buffer */ 1090static void sh_eth_ring_free(struct net_device *ndev) 1091{ 1092 struct sh_eth_private *mdp = netdev_priv(ndev); 1093 int i; 1094 1095 /* Free Rx skb ringbuffer */ 1096 if (mdp->rx_skbuff) { 1097 for (i = 0; i < mdp->num_rx_ring; i++) { 1098 if (mdp->rx_skbuff[i]) 1099 dev_kfree_skb(mdp->rx_skbuff[i]); 1100 } 1101 } 1102 kfree(mdp->rx_skbuff); 1103 mdp->rx_skbuff = NULL; 1104 1105 /* Free Tx skb ringbuffer */ 1106 if (mdp->tx_skbuff) { 1107 for (i = 0; i < mdp->num_tx_ring; i++) { 1108 if (mdp->tx_skbuff[i]) 1109 dev_kfree_skb(mdp->tx_skbuff[i]); 1110 } 1111 } 1112 kfree(mdp->tx_skbuff); 1113 mdp->tx_skbuff = NULL; 1114} 1115 1116/* format skb and descriptor buffer */ 1117static void sh_eth_ring_format(struct net_device *ndev) 1118{ 1119 struct sh_eth_private *mdp = netdev_priv(ndev); 1120 int i; 1121 struct sk_buff *skb; 1122 struct sh_eth_rxdesc *rxdesc = NULL; 1123 struct sh_eth_txdesc *txdesc = NULL; 1124 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1125 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1126 1127 mdp->cur_rx = 0; 1128 mdp->cur_tx = 0; 1129 mdp->dirty_rx = 0; 1130 mdp->dirty_tx = 0; 1131 1132 memset(mdp->rx_ring, 0, rx_ringsize); 1133 1134 /* build Rx ring buffer */ 1135 for (i = 0; i < mdp->num_rx_ring; i++) { 1136 /* skb */ 1137 mdp->rx_skbuff[i] = NULL; 1138 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1139 mdp->rx_skbuff[i] = skb; 1140 if (skb == NULL) 1141 break; 1142 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1143 DMA_FROM_DEVICE); 1144 sh_eth_set_receive_align(skb); 1145 1146 /* RX descriptor */ 1147 rxdesc = &mdp->rx_ring[i]; 1148 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1149 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1150 1151 /* The size of the buffer is 16 byte boundary. */ 1152 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1153 /* Rx descriptor address set */ 1154 if (i == 0) { 1155 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1156 if (sh_eth_is_gether(mdp) || 1157 sh_eth_is_rz_fast_ether(mdp)) 1158 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1159 } 1160 } 1161 1162 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1163 1164 /* Mark the last entry as wrapping the ring. */ 1165 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); 1166 1167 memset(mdp->tx_ring, 0, tx_ringsize); 1168 1169 /* build Tx ring buffer */ 1170 for (i = 0; i < mdp->num_tx_ring; i++) { 1171 mdp->tx_skbuff[i] = NULL; 1172 txdesc = &mdp->tx_ring[i]; 1173 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1174 txdesc->buffer_length = 0; 1175 if (i == 0) { 1176 /* Tx descriptor address set */ 1177 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1178 if (sh_eth_is_gether(mdp) || 1179 sh_eth_is_rz_fast_ether(mdp)) 1180 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1181 } 1182 } 1183 1184 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1185} 1186 1187/* Get skb and descriptor buffer */ 1188static int sh_eth_ring_init(struct net_device *ndev) 1189{ 1190 struct sh_eth_private *mdp = netdev_priv(ndev); 1191 int rx_ringsize, tx_ringsize, ret = 0; 1192 1193 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1194 * card needs room to do 8 byte alignment, +2 so we can reserve 1195 * the first 2 bytes, and +16 gets room for the status word from the 1196 * card. 1197 */ 1198 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1199 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1200 if (mdp->cd->rpadir) 1201 mdp->rx_buf_sz += NET_IP_ALIGN; 1202 1203 /* Allocate RX and TX skb rings */ 1204 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring, 1205 sizeof(*mdp->rx_skbuff), GFP_KERNEL); 1206 if (!mdp->rx_skbuff) { 1207 ret = -ENOMEM; 1208 return ret; 1209 } 1210 1211 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring, 1212 sizeof(*mdp->tx_skbuff), GFP_KERNEL); 1213 if (!mdp->tx_skbuff) { 1214 ret = -ENOMEM; 1215 goto skb_ring_free; 1216 } 1217 1218 /* Allocate all Rx descriptors. */ 1219 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1220 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 1221 GFP_KERNEL); 1222 if (!mdp->rx_ring) { 1223 ret = -ENOMEM; 1224 goto desc_ring_free; 1225 } 1226 1227 mdp->dirty_rx = 0; 1228 1229 /* Allocate all Tx descriptors. */ 1230 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1231 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 1232 GFP_KERNEL); 1233 if (!mdp->tx_ring) { 1234 ret = -ENOMEM; 1235 goto desc_ring_free; 1236 } 1237 return ret; 1238 1239desc_ring_free: 1240 /* free DMA buffer */ 1241 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); 1242 1243skb_ring_free: 1244 /* Free Rx and Tx skb ring buffer */ 1245 sh_eth_ring_free(ndev); 1246 mdp->tx_ring = NULL; 1247 mdp->rx_ring = NULL; 1248 1249 return ret; 1250} 1251 1252static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp) 1253{ 1254 int ringsize; 1255 1256 if (mdp->rx_ring) { 1257 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1258 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 1259 mdp->rx_desc_dma); 1260 mdp->rx_ring = NULL; 1261 } 1262 1263 if (mdp->tx_ring) { 1264 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1265 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 1266 mdp->tx_desc_dma); 1267 mdp->tx_ring = NULL; 1268 } 1269} 1270 1271static int sh_eth_dev_init(struct net_device *ndev, bool start) 1272{ 1273 int ret = 0; 1274 struct sh_eth_private *mdp = netdev_priv(ndev); 1275 u32 val; 1276 1277 /* Soft Reset */ 1278 ret = sh_eth_reset(ndev); 1279 if (ret) 1280 return ret; 1281 1282 if (mdp->cd->rmiimode) 1283 sh_eth_write(ndev, 0x1, RMIIMODE); 1284 1285 /* Descriptor format */ 1286 sh_eth_ring_format(ndev); 1287 if (mdp->cd->rpadir) 1288 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1289 1290 /* all sh_eth int mask */ 1291 sh_eth_write(ndev, 0, EESIPR); 1292 1293#if defined(__LITTLE_ENDIAN) 1294 if (mdp->cd->hw_swap) 1295 sh_eth_write(ndev, EDMR_EL, EDMR); 1296 else 1297#endif 1298 sh_eth_write(ndev, 0, EDMR); 1299 1300 /* FIFO size set */ 1301 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1302 sh_eth_write(ndev, 0, TFTR); 1303 1304 /* Frame recv control (enable multiple-packets per rx irq) */ 1305 sh_eth_write(ndev, RMCR_RNC, RMCR); 1306 1307 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER); 1308 1309 if (mdp->cd->bculr) 1310 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1311 1312 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1313 1314 if (!mdp->cd->no_trimd) 1315 sh_eth_write(ndev, 0, TRIMD); 1316 1317 /* Recv frame limit set register */ 1318 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1319 RFLR); 1320 1321 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 1322 if (start) 1323 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1324 1325 /* PAUSE Prohibition */ 1326 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | 1327 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 1328 1329 sh_eth_write(ndev, val, ECMR); 1330 1331 if (mdp->cd->set_rate) 1332 mdp->cd->set_rate(ndev); 1333 1334 /* E-MAC Status Register clear */ 1335 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1336 1337 /* E-MAC Interrupt Enable register */ 1338 if (start) 1339 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1340 1341 /* Set MAC address */ 1342 update_mac_address(ndev); 1343 1344 /* mask reset */ 1345 if (mdp->cd->apr) 1346 sh_eth_write(ndev, APR_AP, APR); 1347 if (mdp->cd->mpr) 1348 sh_eth_write(ndev, MPR_MP, MPR); 1349 if (mdp->cd->tpauser) 1350 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1351 1352 if (start) { 1353 /* Setting the Rx mode will start the Rx process. */ 1354 sh_eth_write(ndev, EDRRR_R, EDRRR); 1355 1356 netif_start_queue(ndev); 1357 } 1358 1359 return ret; 1360} 1361 1362/* free Tx skb function */ 1363static int sh_eth_txfree(struct net_device *ndev) 1364{ 1365 struct sh_eth_private *mdp = netdev_priv(ndev); 1366 struct sh_eth_txdesc *txdesc; 1367 int free_num = 0; 1368 int entry = 0; 1369 1370 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1371 entry = mdp->dirty_tx % mdp->num_tx_ring; 1372 txdesc = &mdp->tx_ring[entry]; 1373 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 1374 break; 1375 /* Free the original skb. */ 1376 if (mdp->tx_skbuff[entry]) { 1377 dma_unmap_single(&ndev->dev, txdesc->addr, 1378 txdesc->buffer_length, DMA_TO_DEVICE); 1379 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1380 mdp->tx_skbuff[entry] = NULL; 1381 free_num++; 1382 } 1383 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1384 if (entry >= mdp->num_tx_ring - 1) 1385 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1386 1387 ndev->stats.tx_packets++; 1388 ndev->stats.tx_bytes += txdesc->buffer_length; 1389 } 1390 return free_num; 1391} 1392 1393/* Packet receive function */ 1394static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1395{ 1396 struct sh_eth_private *mdp = netdev_priv(ndev); 1397 struct sh_eth_rxdesc *rxdesc; 1398 1399 int entry = mdp->cur_rx % mdp->num_rx_ring; 1400 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1401 struct sk_buff *skb; 1402 int exceeded = 0; 1403 u16 pkt_len = 0; 1404 u32 desc_status; 1405 1406 rxdesc = &mdp->rx_ring[entry]; 1407 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1408 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1409 pkt_len = rxdesc->frame_length; 1410 1411 if (--boguscnt < 0) 1412 break; 1413 1414 if (*quota <= 0) { 1415 exceeded = 1; 1416 break; 1417 } 1418 (*quota)--; 1419 1420 if (!(desc_status & RDFEND)) 1421 ndev->stats.rx_length_errors++; 1422 1423 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1424 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1425 * bit 0. However, in case of the R8A7740, R8A779x, and 1426 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the 1427 * driver needs right shifting by 16. 1428 */ 1429 if (mdp->cd->shift_rd0) 1430 desc_status >>= 16; 1431 1432 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1433 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1434 ndev->stats.rx_errors++; 1435 if (desc_status & RD_RFS1) 1436 ndev->stats.rx_crc_errors++; 1437 if (desc_status & RD_RFS2) 1438 ndev->stats.rx_frame_errors++; 1439 if (desc_status & RD_RFS3) 1440 ndev->stats.rx_length_errors++; 1441 if (desc_status & RD_RFS4) 1442 ndev->stats.rx_length_errors++; 1443 if (desc_status & RD_RFS6) 1444 ndev->stats.rx_missed_errors++; 1445 if (desc_status & RD_RFS10) 1446 ndev->stats.rx_over_errors++; 1447 } else { 1448 if (!mdp->cd->hw_swap) 1449 sh_eth_soft_swap( 1450 phys_to_virt(ALIGN(rxdesc->addr, 4)), 1451 pkt_len + 2); 1452 skb = mdp->rx_skbuff[entry]; 1453 mdp->rx_skbuff[entry] = NULL; 1454 if (mdp->cd->rpadir) 1455 skb_reserve(skb, NET_IP_ALIGN); 1456 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr, 1457 mdp->rx_buf_sz, 1458 DMA_FROM_DEVICE); 1459 skb_put(skb, pkt_len); 1460 skb->protocol = eth_type_trans(skb, ndev); 1461 netif_receive_skb(skb); 1462 ndev->stats.rx_packets++; 1463 ndev->stats.rx_bytes += pkt_len; 1464 } 1465 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); 1466 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1467 rxdesc = &mdp->rx_ring[entry]; 1468 } 1469 1470 /* Refill the Rx ring buffers. */ 1471 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1472 entry = mdp->dirty_rx % mdp->num_rx_ring; 1473 rxdesc = &mdp->rx_ring[entry]; 1474 /* The size of the buffer is 16 byte boundary. */ 1475 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1476 1477 if (mdp->rx_skbuff[entry] == NULL) { 1478 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1479 mdp->rx_skbuff[entry] = skb; 1480 if (skb == NULL) 1481 break; /* Better luck next round. */ 1482 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1483 DMA_FROM_DEVICE); 1484 sh_eth_set_receive_align(skb); 1485 1486 skb_checksum_none_assert(skb); 1487 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1488 } 1489 if (entry >= mdp->num_rx_ring - 1) 1490 rxdesc->status |= 1491 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1492 else 1493 rxdesc->status |= 1494 cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1495 } 1496 1497 /* Restart Rx engine if stopped. */ 1498 /* If we don't need to check status, don't. -KDU */ 1499 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1500 /* fix the values for the next receiving if RDE is set */ 1501 if (intr_status & EESR_RDE) { 1502 u32 count = (sh_eth_read(ndev, RDFAR) - 1503 sh_eth_read(ndev, RDLAR)) >> 4; 1504 1505 mdp->cur_rx = count; 1506 mdp->dirty_rx = count; 1507 } 1508 sh_eth_write(ndev, EDRRR_R, EDRRR); 1509 } 1510 1511 return exceeded; 1512} 1513 1514static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1515{ 1516 /* disable tx and rx */ 1517 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1518 ~(ECMR_RE | ECMR_TE), ECMR); 1519} 1520 1521static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1522{ 1523 /* enable tx and rx */ 1524 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1525 (ECMR_RE | ECMR_TE), ECMR); 1526} 1527 1528/* error control function */ 1529static void sh_eth_error(struct net_device *ndev, int intr_status) 1530{ 1531 struct sh_eth_private *mdp = netdev_priv(ndev); 1532 u32 felic_stat; 1533 u32 link_stat; 1534 u32 mask; 1535 1536 if (intr_status & EESR_ECI) { 1537 felic_stat = sh_eth_read(ndev, ECSR); 1538 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1539 if (felic_stat & ECSR_ICD) 1540 ndev->stats.tx_carrier_errors++; 1541 if (felic_stat & ECSR_LCHNG) { 1542 /* Link Changed */ 1543 if (mdp->cd->no_psr || mdp->no_ether_link) { 1544 goto ignore_link; 1545 } else { 1546 link_stat = (sh_eth_read(ndev, PSR)); 1547 if (mdp->ether_link_active_low) 1548 link_stat = ~link_stat; 1549 } 1550 if (!(link_stat & PHY_ST_LINK)) { 1551 sh_eth_rcv_snd_disable(ndev); 1552 } else { 1553 /* Link Up */ 1554 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1555 ~DMAC_M_ECI, EESIPR); 1556 /* clear int */ 1557 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1558 ECSR); 1559 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1560 DMAC_M_ECI, EESIPR); 1561 /* enable tx and rx */ 1562 sh_eth_rcv_snd_enable(ndev); 1563 } 1564 } 1565 } 1566 1567ignore_link: 1568 if (intr_status & EESR_TWB) { 1569 /* Unused write back interrupt */ 1570 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1571 ndev->stats.tx_aborted_errors++; 1572 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1573 } 1574 } 1575 1576 if (intr_status & EESR_RABT) { 1577 /* Receive Abort int */ 1578 if (intr_status & EESR_RFRMER) { 1579 /* Receive Frame Overflow int */ 1580 ndev->stats.rx_frame_errors++; 1581 netif_err(mdp, rx_err, ndev, "Receive Abort\n"); 1582 } 1583 } 1584 1585 if (intr_status & EESR_TDE) { 1586 /* Transmit Descriptor Empty int */ 1587 ndev->stats.tx_fifo_errors++; 1588 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1589 } 1590 1591 if (intr_status & EESR_TFE) { 1592 /* FIFO under flow */ 1593 ndev->stats.tx_fifo_errors++; 1594 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1595 } 1596 1597 if (intr_status & EESR_RDE) { 1598 /* Receive Descriptor Empty int */ 1599 ndev->stats.rx_over_errors++; 1600 netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n"); 1601 } 1602 1603 if (intr_status & EESR_RFE) { 1604 /* Receive FIFO Overflow int */ 1605 ndev->stats.rx_fifo_errors++; 1606 netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n"); 1607 } 1608 1609 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1610 /* Address Error */ 1611 ndev->stats.tx_fifo_errors++; 1612 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1613 } 1614 1615 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1616 if (mdp->cd->no_ade) 1617 mask &= ~EESR_ADE; 1618 if (intr_status & mask) { 1619 /* Tx error */ 1620 u32 edtrr = sh_eth_read(ndev, EDTRR); 1621 1622 /* dmesg */ 1623 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1624 intr_status, mdp->cur_tx, mdp->dirty_tx, 1625 (u32)ndev->state, edtrr); 1626 /* dirty buffer free */ 1627 sh_eth_txfree(ndev); 1628 1629 /* SH7712 BUG */ 1630 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1631 /* tx dma start */ 1632 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1633 } 1634 /* wakeup */ 1635 netif_wake_queue(ndev); 1636 } 1637} 1638 1639static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1640{ 1641 struct net_device *ndev = netdev; 1642 struct sh_eth_private *mdp = netdev_priv(ndev); 1643 struct sh_eth_cpu_data *cd = mdp->cd; 1644 irqreturn_t ret = IRQ_NONE; 1645 unsigned long intr_status, intr_enable; 1646 1647 spin_lock(&mdp->lock); 1648 1649 /* Get interrupt status */ 1650 intr_status = sh_eth_read(ndev, EESR); 1651 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1652 * enabled since it's the one that comes thru regardless of the mask, 1653 * and we need to fully handle it in sh_eth_error() in order to quench 1654 * it as it doesn't get cleared by just writing 1 to the ECI bit... 1655 */ 1656 intr_enable = sh_eth_read(ndev, EESIPR); 1657 intr_status &= intr_enable | DMAC_M_ECI; 1658 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) 1659 ret = IRQ_HANDLED; 1660 else 1661 goto other_irq; 1662 1663 if (intr_status & EESR_RX_CHECK) { 1664 if (napi_schedule_prep(&mdp->napi)) { 1665 /* Mask Rx interrupts */ 1666 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1667 EESIPR); 1668 __napi_schedule(&mdp->napi); 1669 } else { 1670 netdev_warn(ndev, 1671 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n", 1672 intr_status, intr_enable); 1673 } 1674 } 1675 1676 /* Tx Check */ 1677 if (intr_status & cd->tx_check) { 1678 /* Clear Tx interrupts */ 1679 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1680 1681 sh_eth_txfree(ndev); 1682 netif_wake_queue(ndev); 1683 } 1684 1685 if (intr_status & cd->eesr_err_check) { 1686 /* Clear error interrupts */ 1687 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1688 1689 sh_eth_error(ndev, intr_status); 1690 } 1691 1692other_irq: 1693 spin_unlock(&mdp->lock); 1694 1695 return ret; 1696} 1697 1698static int sh_eth_poll(struct napi_struct *napi, int budget) 1699{ 1700 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1701 napi); 1702 struct net_device *ndev = napi->dev; 1703 int quota = budget; 1704 unsigned long intr_status; 1705 1706 for (;;) { 1707 intr_status = sh_eth_read(ndev, EESR); 1708 if (!(intr_status & EESR_RX_CHECK)) 1709 break; 1710 /* Clear Rx interrupts */ 1711 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1712 1713 if (sh_eth_rx(ndev, intr_status, "a)) 1714 goto out; 1715 } 1716 1717 napi_complete(napi); 1718 1719 /* Reenable Rx interrupts */ 1720 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1721out: 1722 return budget - quota; 1723} 1724 1725/* PHY state control function */ 1726static void sh_eth_adjust_link(struct net_device *ndev) 1727{ 1728 struct sh_eth_private *mdp = netdev_priv(ndev); 1729 struct phy_device *phydev = mdp->phydev; 1730 int new_state = 0; 1731 1732 if (phydev->link) { 1733 if (phydev->duplex != mdp->duplex) { 1734 new_state = 1; 1735 mdp->duplex = phydev->duplex; 1736 if (mdp->cd->set_duplex) 1737 mdp->cd->set_duplex(ndev); 1738 } 1739 1740 if (phydev->speed != mdp->speed) { 1741 new_state = 1; 1742 mdp->speed = phydev->speed; 1743 if (mdp->cd->set_rate) 1744 mdp->cd->set_rate(ndev); 1745 } 1746 if (!mdp->link) { 1747 sh_eth_write(ndev, 1748 sh_eth_read(ndev, ECMR) & ~ECMR_TXF, 1749 ECMR); 1750 new_state = 1; 1751 mdp->link = phydev->link; 1752 if (mdp->cd->no_psr || mdp->no_ether_link) 1753 sh_eth_rcv_snd_enable(ndev); 1754 } 1755 } else if (mdp->link) { 1756 new_state = 1; 1757 mdp->link = 0; 1758 mdp->speed = 0; 1759 mdp->duplex = -1; 1760 if (mdp->cd->no_psr || mdp->no_ether_link) 1761 sh_eth_rcv_snd_disable(ndev); 1762 } 1763 1764 if (new_state && netif_msg_link(mdp)) 1765 phy_print_status(phydev); 1766} 1767 1768/* PHY init function */ 1769static int sh_eth_phy_init(struct net_device *ndev) 1770{ 1771 struct device_node *np = ndev->dev.parent->of_node; 1772 struct sh_eth_private *mdp = netdev_priv(ndev); 1773 struct phy_device *phydev = NULL; 1774 1775 mdp->link = 0; 1776 mdp->speed = 0; 1777 mdp->duplex = -1; 1778 1779 /* Try connect to PHY */ 1780 if (np) { 1781 struct device_node *pn; 1782 1783 pn = of_parse_phandle(np, "phy-handle", 0); 1784 phydev = of_phy_connect(ndev, pn, 1785 sh_eth_adjust_link, 0, 1786 mdp->phy_interface); 1787 1788 if (!phydev) 1789 phydev = ERR_PTR(-ENOENT); 1790 } else { 1791 char phy_id[MII_BUS_ID_SIZE + 3]; 1792 1793 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1794 mdp->mii_bus->id, mdp->phy_id); 1795 1796 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1797 mdp->phy_interface); 1798 } 1799 1800 if (IS_ERR(phydev)) { 1801 netdev_err(ndev, "failed to connect PHY\n"); 1802 return PTR_ERR(phydev); 1803 } 1804 1805 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n", 1806 phydev->addr, phydev->irq, phydev->drv->name); 1807 1808 mdp->phydev = phydev; 1809 1810 return 0; 1811} 1812 1813/* PHY control start function */ 1814static int sh_eth_phy_start(struct net_device *ndev) 1815{ 1816 struct sh_eth_private *mdp = netdev_priv(ndev); 1817 int ret; 1818 1819 ret = sh_eth_phy_init(ndev); 1820 if (ret) 1821 return ret; 1822 1823 phy_start(mdp->phydev); 1824 1825 return 0; 1826} 1827 1828static int sh_eth_get_settings(struct net_device *ndev, 1829 struct ethtool_cmd *ecmd) 1830{ 1831 struct sh_eth_private *mdp = netdev_priv(ndev); 1832 unsigned long flags; 1833 int ret; 1834 1835 spin_lock_irqsave(&mdp->lock, flags); 1836 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1837 spin_unlock_irqrestore(&mdp->lock, flags); 1838 1839 return ret; 1840} 1841 1842static int sh_eth_set_settings(struct net_device *ndev, 1843 struct ethtool_cmd *ecmd) 1844{ 1845 struct sh_eth_private *mdp = netdev_priv(ndev); 1846 unsigned long flags; 1847 int ret; 1848 1849 spin_lock_irqsave(&mdp->lock, flags); 1850 1851 /* disable tx and rx */ 1852 sh_eth_rcv_snd_disable(ndev); 1853 1854 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1855 if (ret) 1856 goto error_exit; 1857 1858 if (ecmd->duplex == DUPLEX_FULL) 1859 mdp->duplex = 1; 1860 else 1861 mdp->duplex = 0; 1862 1863 if (mdp->cd->set_duplex) 1864 mdp->cd->set_duplex(ndev); 1865 1866error_exit: 1867 mdelay(1); 1868 1869 /* enable tx and rx */ 1870 sh_eth_rcv_snd_enable(ndev); 1871 1872 spin_unlock_irqrestore(&mdp->lock, flags); 1873 1874 return ret; 1875} 1876 1877static int sh_eth_nway_reset(struct net_device *ndev) 1878{ 1879 struct sh_eth_private *mdp = netdev_priv(ndev); 1880 unsigned long flags; 1881 int ret; 1882 1883 spin_lock_irqsave(&mdp->lock, flags); 1884 ret = phy_start_aneg(mdp->phydev); 1885 spin_unlock_irqrestore(&mdp->lock, flags); 1886 1887 return ret; 1888} 1889 1890static u32 sh_eth_get_msglevel(struct net_device *ndev) 1891{ 1892 struct sh_eth_private *mdp = netdev_priv(ndev); 1893 return mdp->msg_enable; 1894} 1895 1896static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 1897{ 1898 struct sh_eth_private *mdp = netdev_priv(ndev); 1899 mdp->msg_enable = value; 1900} 1901 1902static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 1903 "rx_current", "tx_current", 1904 "rx_dirty", "tx_dirty", 1905}; 1906#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 1907 1908static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 1909{ 1910 switch (sset) { 1911 case ETH_SS_STATS: 1912 return SH_ETH_STATS_LEN; 1913 default: 1914 return -EOPNOTSUPP; 1915 } 1916} 1917 1918static void sh_eth_get_ethtool_stats(struct net_device *ndev, 1919 struct ethtool_stats *stats, u64 *data) 1920{ 1921 struct sh_eth_private *mdp = netdev_priv(ndev); 1922 int i = 0; 1923 1924 /* device-specific stats */ 1925 data[i++] = mdp->cur_rx; 1926 data[i++] = mdp->cur_tx; 1927 data[i++] = mdp->dirty_rx; 1928 data[i++] = mdp->dirty_tx; 1929} 1930 1931static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1932{ 1933 switch (stringset) { 1934 case ETH_SS_STATS: 1935 memcpy(data, *sh_eth_gstrings_stats, 1936 sizeof(sh_eth_gstrings_stats)); 1937 break; 1938 } 1939} 1940 1941static void sh_eth_get_ringparam(struct net_device *ndev, 1942 struct ethtool_ringparam *ring) 1943{ 1944 struct sh_eth_private *mdp = netdev_priv(ndev); 1945 1946 ring->rx_max_pending = RX_RING_MAX; 1947 ring->tx_max_pending = TX_RING_MAX; 1948 ring->rx_pending = mdp->num_rx_ring; 1949 ring->tx_pending = mdp->num_tx_ring; 1950} 1951 1952static int sh_eth_set_ringparam(struct net_device *ndev, 1953 struct ethtool_ringparam *ring) 1954{ 1955 struct sh_eth_private *mdp = netdev_priv(ndev); 1956 int ret; 1957 1958 if (ring->tx_pending > TX_RING_MAX || 1959 ring->rx_pending > RX_RING_MAX || 1960 ring->tx_pending < TX_RING_MIN || 1961 ring->rx_pending < RX_RING_MIN) 1962 return -EINVAL; 1963 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1964 return -EINVAL; 1965 1966 if (netif_running(ndev)) { 1967 netif_tx_disable(ndev); 1968 /* Disable interrupts by clearing the interrupt mask. */ 1969 sh_eth_write(ndev, 0x0000, EESIPR); 1970 /* Stop the chip's Tx and Rx processes. */ 1971 sh_eth_write(ndev, 0, EDTRR); 1972 sh_eth_write(ndev, 0, EDRRR); 1973 synchronize_irq(ndev->irq); 1974 } 1975 1976 /* Free all the skbuffs in the Rx queue. */ 1977 sh_eth_ring_free(ndev); 1978 /* Free DMA buffer */ 1979 sh_eth_free_dma_buffer(mdp); 1980 1981 /* Set new parameters */ 1982 mdp->num_rx_ring = ring->rx_pending; 1983 mdp->num_tx_ring = ring->tx_pending; 1984 1985 ret = sh_eth_ring_init(ndev); 1986 if (ret < 0) { 1987 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__); 1988 return ret; 1989 } 1990 ret = sh_eth_dev_init(ndev, false); 1991 if (ret < 0) { 1992 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__); 1993 return ret; 1994 } 1995 1996 if (netif_running(ndev)) { 1997 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1998 /* Setting the Rx mode will start the Rx process. */ 1999 sh_eth_write(ndev, EDRRR_R, EDRRR); 2000 netif_wake_queue(ndev); 2001 } 2002 2003 return 0; 2004} 2005 2006static const struct ethtool_ops sh_eth_ethtool_ops = { 2007 .get_settings = sh_eth_get_settings, 2008 .set_settings = sh_eth_set_settings, 2009 .nway_reset = sh_eth_nway_reset, 2010 .get_msglevel = sh_eth_get_msglevel, 2011 .set_msglevel = sh_eth_set_msglevel, 2012 .get_link = ethtool_op_get_link, 2013 .get_strings = sh_eth_get_strings, 2014 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2015 .get_sset_count = sh_eth_get_sset_count, 2016 .get_ringparam = sh_eth_get_ringparam, 2017 .set_ringparam = sh_eth_set_ringparam, 2018}; 2019 2020/* network device open function */ 2021static int sh_eth_open(struct net_device *ndev) 2022{ 2023 int ret = 0; 2024 struct sh_eth_private *mdp = netdev_priv(ndev); 2025 2026 pm_runtime_get_sync(&mdp->pdev->dev); 2027 2028 napi_enable(&mdp->napi); 2029 2030 ret = request_irq(ndev->irq, sh_eth_interrupt, 2031 mdp->cd->irq_flags, ndev->name, ndev); 2032 if (ret) { 2033 netdev_err(ndev, "Can not assign IRQ number\n"); 2034 goto out_napi_off; 2035 } 2036 2037 /* Descriptor set */ 2038 ret = sh_eth_ring_init(ndev); 2039 if (ret) 2040 goto out_free_irq; 2041 2042 /* device init */ 2043 ret = sh_eth_dev_init(ndev, true); 2044 if (ret) 2045 goto out_free_irq; 2046 2047 /* PHY control start*/ 2048 ret = sh_eth_phy_start(ndev); 2049 if (ret) 2050 goto out_free_irq; 2051 2052 return ret; 2053 2054out_free_irq: 2055 free_irq(ndev->irq, ndev); 2056out_napi_off: 2057 napi_disable(&mdp->napi); 2058 pm_runtime_put_sync(&mdp->pdev->dev); 2059 return ret; 2060} 2061 2062/* Timeout function */ 2063static void sh_eth_tx_timeout(struct net_device *ndev) 2064{ 2065 struct sh_eth_private *mdp = netdev_priv(ndev); 2066 struct sh_eth_rxdesc *rxdesc; 2067 int i; 2068 2069 netif_stop_queue(ndev); 2070 2071 netif_err(mdp, timer, ndev, 2072 "transmit timed out, status %8.8x, resetting...\n", 2073 (int)sh_eth_read(ndev, EESR)); 2074 2075 /* tx_errors count up */ 2076 ndev->stats.tx_errors++; 2077 2078 /* Free all the skbuffs in the Rx queue. */ 2079 for (i = 0; i < mdp->num_rx_ring; i++) { 2080 rxdesc = &mdp->rx_ring[i]; 2081 rxdesc->status = 0; 2082 rxdesc->addr = 0xBADF00D0; 2083 if (mdp->rx_skbuff[i]) 2084 dev_kfree_skb(mdp->rx_skbuff[i]); 2085 mdp->rx_skbuff[i] = NULL; 2086 } 2087 for (i = 0; i < mdp->num_tx_ring; i++) { 2088 if (mdp->tx_skbuff[i]) 2089 dev_kfree_skb(mdp->tx_skbuff[i]); 2090 mdp->tx_skbuff[i] = NULL; 2091 } 2092 2093 /* device init */ 2094 sh_eth_dev_init(ndev, true); 2095} 2096 2097/* Packet transmit function */ 2098static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2099{ 2100 struct sh_eth_private *mdp = netdev_priv(ndev); 2101 struct sh_eth_txdesc *txdesc; 2102 u32 entry; 2103 unsigned long flags; 2104 2105 spin_lock_irqsave(&mdp->lock, flags); 2106 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2107 if (!sh_eth_txfree(ndev)) { 2108 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2109 netif_stop_queue(ndev); 2110 spin_unlock_irqrestore(&mdp->lock, flags); 2111 return NETDEV_TX_BUSY; 2112 } 2113 } 2114 spin_unlock_irqrestore(&mdp->lock, flags); 2115 2116 entry = mdp->cur_tx % mdp->num_tx_ring; 2117 mdp->tx_skbuff[entry] = skb; 2118 txdesc = &mdp->tx_ring[entry]; 2119 /* soft swap. */ 2120 if (!mdp->cd->hw_swap) 2121 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), 2122 skb->len + 2); 2123 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, 2124 DMA_TO_DEVICE); 2125 if (skb->len < ETH_ZLEN) 2126 txdesc->buffer_length = ETH_ZLEN; 2127 else 2128 txdesc->buffer_length = skb->len; 2129 2130 if (entry >= mdp->num_tx_ring - 1) 2131 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 2132 else 2133 txdesc->status |= cpu_to_edmac(mdp, TD_TACT); 2134 2135 mdp->cur_tx++; 2136 2137 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 2138 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 2139 2140 return NETDEV_TX_OK; 2141} 2142 2143/* device close function */ 2144static int sh_eth_close(struct net_device *ndev) 2145{ 2146 struct sh_eth_private *mdp = netdev_priv(ndev); 2147 2148 netif_stop_queue(ndev); 2149 2150 /* Disable interrupts by clearing the interrupt mask. */ 2151 sh_eth_write(ndev, 0x0000, EESIPR); 2152 2153 /* Stop the chip's Tx and Rx processes. */ 2154 sh_eth_write(ndev, 0, EDTRR); 2155 sh_eth_write(ndev, 0, EDRRR); 2156 2157 /* PHY Disconnect */ 2158 if (mdp->phydev) { 2159 phy_stop(mdp->phydev); 2160 phy_disconnect(mdp->phydev); 2161 } 2162 2163 free_irq(ndev->irq, ndev); 2164 2165 napi_disable(&mdp->napi); 2166 2167 /* Free all the skbuffs in the Rx queue. */ 2168 sh_eth_ring_free(ndev); 2169 2170 /* free DMA buffer */ 2171 sh_eth_free_dma_buffer(mdp); 2172 2173 pm_runtime_put_sync(&mdp->pdev->dev); 2174 2175 return 0; 2176} 2177 2178static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2179{ 2180 struct sh_eth_private *mdp = netdev_priv(ndev); 2181 2182 if (sh_eth_is_rz_fast_ether(mdp)) 2183 return &ndev->stats; 2184 2185 pm_runtime_get_sync(&mdp->pdev->dev); 2186 2187 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR); 2188 sh_eth_write(ndev, 0, TROCR); /* (write clear) */ 2189 ndev->stats.collisions += sh_eth_read(ndev, CDCR); 2190 sh_eth_write(ndev, 0, CDCR); /* (write clear) */ 2191 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); 2192 sh_eth_write(ndev, 0, LCCR); /* (write clear) */ 2193 if (sh_eth_is_gether(mdp)) { 2194 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR); 2195 sh_eth_write(ndev, 0, CERCR); /* (write clear) */ 2196 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR); 2197 sh_eth_write(ndev, 0, CEECR); /* (write clear) */ 2198 } else { 2199 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); 2200 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ 2201 } 2202 pm_runtime_put_sync(&mdp->pdev->dev); 2203 2204 return &ndev->stats; 2205} 2206 2207/* ioctl to device function */ 2208static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2209{ 2210 struct sh_eth_private *mdp = netdev_priv(ndev); 2211 struct phy_device *phydev = mdp->phydev; 2212 2213 if (!netif_running(ndev)) 2214 return -EINVAL; 2215 2216 if (!phydev) 2217 return -ENODEV; 2218 2219 return phy_mii_ioctl(phydev, rq, cmd); 2220} 2221 2222/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2223static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2224 int entry) 2225{ 2226 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2227} 2228 2229static u32 sh_eth_tsu_get_post_mask(int entry) 2230{ 2231 return 0x0f << (28 - ((entry % 8) * 4)); 2232} 2233 2234static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2235{ 2236 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2237} 2238 2239static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2240 int entry) 2241{ 2242 struct sh_eth_private *mdp = netdev_priv(ndev); 2243 u32 tmp; 2244 void *reg_offset; 2245 2246 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2247 tmp = ioread32(reg_offset); 2248 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2249} 2250 2251static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2252 int entry) 2253{ 2254 struct sh_eth_private *mdp = netdev_priv(ndev); 2255 u32 post_mask, ref_mask, tmp; 2256 void *reg_offset; 2257 2258 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2259 post_mask = sh_eth_tsu_get_post_mask(entry); 2260 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2261 2262 tmp = ioread32(reg_offset); 2263 iowrite32(tmp & ~post_mask, reg_offset); 2264 2265 /* If other port enables, the function returns "true" */ 2266 return tmp & ref_mask; 2267} 2268 2269static int sh_eth_tsu_busy(struct net_device *ndev) 2270{ 2271 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2272 struct sh_eth_private *mdp = netdev_priv(ndev); 2273 2274 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2275 udelay(10); 2276 timeout--; 2277 if (timeout <= 0) { 2278 netdev_err(ndev, "%s: timeout\n", __func__); 2279 return -ETIMEDOUT; 2280 } 2281 } 2282 2283 return 0; 2284} 2285 2286static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2287 const u8 *addr) 2288{ 2289 u32 val; 2290 2291 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2292 iowrite32(val, reg); 2293 if (sh_eth_tsu_busy(ndev) < 0) 2294 return -EBUSY; 2295 2296 val = addr[4] << 8 | addr[5]; 2297 iowrite32(val, reg + 4); 2298 if (sh_eth_tsu_busy(ndev) < 0) 2299 return -EBUSY; 2300 2301 return 0; 2302} 2303 2304static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2305{ 2306 u32 val; 2307 2308 val = ioread32(reg); 2309 addr[0] = (val >> 24) & 0xff; 2310 addr[1] = (val >> 16) & 0xff; 2311 addr[2] = (val >> 8) & 0xff; 2312 addr[3] = val & 0xff; 2313 val = ioread32(reg + 4); 2314 addr[4] = (val >> 8) & 0xff; 2315 addr[5] = val & 0xff; 2316} 2317 2318 2319static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2320{ 2321 struct sh_eth_private *mdp = netdev_priv(ndev); 2322 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2323 int i; 2324 u8 c_addr[ETH_ALEN]; 2325 2326 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2327 sh_eth_tsu_read_entry(reg_offset, c_addr); 2328 if (ether_addr_equal(addr, c_addr)) 2329 return i; 2330 } 2331 2332 return -ENOENT; 2333} 2334 2335static int sh_eth_tsu_find_empty(struct net_device *ndev) 2336{ 2337 u8 blank[ETH_ALEN]; 2338 int entry; 2339 2340 memset(blank, 0, sizeof(blank)); 2341 entry = sh_eth_tsu_find_entry(ndev, blank); 2342 return (entry < 0) ? -ENOMEM : entry; 2343} 2344 2345static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2346 int entry) 2347{ 2348 struct sh_eth_private *mdp = netdev_priv(ndev); 2349 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2350 int ret; 2351 u8 blank[ETH_ALEN]; 2352 2353 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2354 ~(1 << (31 - entry)), TSU_TEN); 2355 2356 memset(blank, 0, sizeof(blank)); 2357 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2358 if (ret < 0) 2359 return ret; 2360 return 0; 2361} 2362 2363static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2364{ 2365 struct sh_eth_private *mdp = netdev_priv(ndev); 2366 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2367 int i, ret; 2368 2369 if (!mdp->cd->tsu) 2370 return 0; 2371 2372 i = sh_eth_tsu_find_entry(ndev, addr); 2373 if (i < 0) { 2374 /* No entry found, create one */ 2375 i = sh_eth_tsu_find_empty(ndev); 2376 if (i < 0) 2377 return -ENOMEM; 2378 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2379 if (ret < 0) 2380 return ret; 2381 2382 /* Enable the entry */ 2383 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2384 (1 << (31 - i)), TSU_TEN); 2385 } 2386 2387 /* Entry found or created, enable POST */ 2388 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2389 2390 return 0; 2391} 2392 2393static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2394{ 2395 struct sh_eth_private *mdp = netdev_priv(ndev); 2396 int i, ret; 2397 2398 if (!mdp->cd->tsu) 2399 return 0; 2400 2401 i = sh_eth_tsu_find_entry(ndev, addr); 2402 if (i) { 2403 /* Entry found */ 2404 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2405 goto done; 2406 2407 /* Disable the entry if both ports was disabled */ 2408 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2409 if (ret < 0) 2410 return ret; 2411 } 2412done: 2413 return 0; 2414} 2415 2416static int sh_eth_tsu_purge_all(struct net_device *ndev) 2417{ 2418 struct sh_eth_private *mdp = netdev_priv(ndev); 2419 int i, ret; 2420 2421 if (unlikely(!mdp->cd->tsu)) 2422 return 0; 2423 2424 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2425 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2426 continue; 2427 2428 /* Disable the entry if both ports was disabled */ 2429 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2430 if (ret < 0) 2431 return ret; 2432 } 2433 2434 return 0; 2435} 2436 2437static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2438{ 2439 struct sh_eth_private *mdp = netdev_priv(ndev); 2440 u8 addr[ETH_ALEN]; 2441 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2442 int i; 2443 2444 if (unlikely(!mdp->cd->tsu)) 2445 return; 2446 2447 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2448 sh_eth_tsu_read_entry(reg_offset, addr); 2449 if (is_multicast_ether_addr(addr)) 2450 sh_eth_tsu_del_entry(ndev, addr); 2451 } 2452} 2453 2454/* Multicast reception directions set */ 2455static void sh_eth_set_multicast_list(struct net_device *ndev) 2456{ 2457 struct sh_eth_private *mdp = netdev_priv(ndev); 2458 u32 ecmr_bits; 2459 int mcast_all = 0; 2460 unsigned long flags; 2461 2462 spin_lock_irqsave(&mdp->lock, flags); 2463 /* Initial condition is MCT = 1, PRM = 0. 2464 * Depending on ndev->flags, set PRM or clear MCT 2465 */ 2466 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT; 2467 2468 if (!(ndev->flags & IFF_MULTICAST)) { 2469 sh_eth_tsu_purge_mcast(ndev); 2470 mcast_all = 1; 2471 } 2472 if (ndev->flags & IFF_ALLMULTI) { 2473 sh_eth_tsu_purge_mcast(ndev); 2474 ecmr_bits &= ~ECMR_MCT; 2475 mcast_all = 1; 2476 } 2477 2478 if (ndev->flags & IFF_PROMISC) { 2479 sh_eth_tsu_purge_all(ndev); 2480 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2481 } else if (mdp->cd->tsu) { 2482 struct netdev_hw_addr *ha; 2483 netdev_for_each_mc_addr(ha, ndev) { 2484 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2485 continue; 2486 2487 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2488 if (!mcast_all) { 2489 sh_eth_tsu_purge_mcast(ndev); 2490 ecmr_bits &= ~ECMR_MCT; 2491 mcast_all = 1; 2492 } 2493 } 2494 } 2495 } else { 2496 /* Normal, unicast/broadcast-only mode. */ 2497 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT; 2498 } 2499 2500 /* update the ethernet mode */ 2501 sh_eth_write(ndev, ecmr_bits, ECMR); 2502 2503 spin_unlock_irqrestore(&mdp->lock, flags); 2504} 2505 2506static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2507{ 2508 if (!mdp->port) 2509 return TSU_VTAG0; 2510 else 2511 return TSU_VTAG1; 2512} 2513 2514static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2515 __be16 proto, u16 vid) 2516{ 2517 struct sh_eth_private *mdp = netdev_priv(ndev); 2518 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2519 2520 if (unlikely(!mdp->cd->tsu)) 2521 return -EPERM; 2522 2523 /* No filtering if vid = 0 */ 2524 if (!vid) 2525 return 0; 2526 2527 mdp->vlan_num_ids++; 2528 2529 /* The controller has one VLAN tag HW filter. So, if the filter is 2530 * already enabled, the driver disables it and the filte 2531 */ 2532 if (mdp->vlan_num_ids > 1) { 2533 /* disable VLAN filter */ 2534 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2535 return 0; 2536 } 2537 2538 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2539 vtag_reg_index); 2540 2541 return 0; 2542} 2543 2544static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2545 __be16 proto, u16 vid) 2546{ 2547 struct sh_eth_private *mdp = netdev_priv(ndev); 2548 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2549 2550 if (unlikely(!mdp->cd->tsu)) 2551 return -EPERM; 2552 2553 /* No filtering if vid = 0 */ 2554 if (!vid) 2555 return 0; 2556 2557 mdp->vlan_num_ids--; 2558 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2559 2560 return 0; 2561} 2562 2563/* SuperH's TSU register init function */ 2564static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2565{ 2566 if (sh_eth_is_rz_fast_ether(mdp)) { 2567 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2568 return; 2569 } 2570 2571 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2572 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2573 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2574 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2575 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2576 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2577 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2578 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2579 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2580 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2581 if (sh_eth_is_gether(mdp)) { 2582 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2583 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2584 } else { 2585 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2586 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2587 } 2588 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2589 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2590 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2591 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2592 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2593 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2594 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2595} 2596 2597/* MDIO bus release function */ 2598static int sh_mdio_release(struct sh_eth_private *mdp) 2599{ 2600 /* unregister mdio bus */ 2601 mdiobus_unregister(mdp->mii_bus); 2602 2603 /* free bitbang info */ 2604 free_mdio_bitbang(mdp->mii_bus); 2605 2606 return 0; 2607} 2608 2609/* MDIO bus init function */ 2610static int sh_mdio_init(struct sh_eth_private *mdp, 2611 struct sh_eth_plat_data *pd) 2612{ 2613 int ret, i; 2614 struct bb_info *bitbang; 2615 struct platform_device *pdev = mdp->pdev; 2616 struct device *dev = &mdp->pdev->dev; 2617 2618 /* create bit control struct for PHY */ 2619 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 2620 if (!bitbang) 2621 return -ENOMEM; 2622 2623 /* bitbang init */ 2624 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2625 bitbang->set_gate = pd->set_mdio_gate; 2626 bitbang->mdi_msk = PIR_MDI; 2627 bitbang->mdo_msk = PIR_MDO; 2628 bitbang->mmd_msk = PIR_MMD; 2629 bitbang->mdc_msk = PIR_MDC; 2630 bitbang->ctrl.ops = &bb_ops; 2631 2632 /* MII controller setting */ 2633 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2634 if (!mdp->mii_bus) 2635 return -ENOMEM; 2636 2637 /* Hook up MII support for ethtool */ 2638 mdp->mii_bus->name = "sh_mii"; 2639 mdp->mii_bus->parent = dev; 2640 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2641 pdev->name, pdev->id); 2642 2643 /* PHY IRQ */ 2644 mdp->mii_bus->irq = devm_kzalloc(dev, sizeof(int) * PHY_MAX_ADDR, 2645 GFP_KERNEL); 2646 if (!mdp->mii_bus->irq) { 2647 ret = -ENOMEM; 2648 goto out_free_bus; 2649 } 2650 2651 /* register MDIO bus */ 2652 if (dev->of_node) { 2653 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 2654 } else { 2655 for (i = 0; i < PHY_MAX_ADDR; i++) 2656 mdp->mii_bus->irq[i] = PHY_POLL; 2657 if (pd->phy_irq > 0) 2658 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 2659 2660 ret = mdiobus_register(mdp->mii_bus); 2661 } 2662 2663 if (ret) 2664 goto out_free_bus; 2665 2666 return 0; 2667 2668out_free_bus: 2669 free_mdio_bitbang(mdp->mii_bus); 2670 return ret; 2671} 2672 2673static const u16 *sh_eth_get_register_offset(int register_type) 2674{ 2675 const u16 *reg_offset = NULL; 2676 2677 switch (register_type) { 2678 case SH_ETH_REG_GIGABIT: 2679 reg_offset = sh_eth_offset_gigabit; 2680 break; 2681 case SH_ETH_REG_FAST_RZ: 2682 reg_offset = sh_eth_offset_fast_rz; 2683 break; 2684 case SH_ETH_REG_FAST_RCAR: 2685 reg_offset = sh_eth_offset_fast_rcar; 2686 break; 2687 case SH_ETH_REG_FAST_SH4: 2688 reg_offset = sh_eth_offset_fast_sh4; 2689 break; 2690 case SH_ETH_REG_FAST_SH3_SH2: 2691 reg_offset = sh_eth_offset_fast_sh3_sh2; 2692 break; 2693 default: 2694 break; 2695 } 2696 2697 return reg_offset; 2698} 2699 2700static const struct net_device_ops sh_eth_netdev_ops = { 2701 .ndo_open = sh_eth_open, 2702 .ndo_stop = sh_eth_close, 2703 .ndo_start_xmit = sh_eth_start_xmit, 2704 .ndo_get_stats = sh_eth_get_stats, 2705 .ndo_tx_timeout = sh_eth_tx_timeout, 2706 .ndo_do_ioctl = sh_eth_do_ioctl, 2707 .ndo_validate_addr = eth_validate_addr, 2708 .ndo_set_mac_address = eth_mac_addr, 2709 .ndo_change_mtu = eth_change_mtu, 2710}; 2711 2712static const struct net_device_ops sh_eth_netdev_ops_tsu = { 2713 .ndo_open = sh_eth_open, 2714 .ndo_stop = sh_eth_close, 2715 .ndo_start_xmit = sh_eth_start_xmit, 2716 .ndo_get_stats = sh_eth_get_stats, 2717 .ndo_set_rx_mode = sh_eth_set_multicast_list, 2718 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 2719 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 2720 .ndo_tx_timeout = sh_eth_tx_timeout, 2721 .ndo_do_ioctl = sh_eth_do_ioctl, 2722 .ndo_validate_addr = eth_validate_addr, 2723 .ndo_set_mac_address = eth_mac_addr, 2724 .ndo_change_mtu = eth_change_mtu, 2725}; 2726 2727#ifdef CONFIG_OF 2728static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 2729{ 2730 struct device_node *np = dev->of_node; 2731 struct sh_eth_plat_data *pdata; 2732 const char *mac_addr; 2733 2734 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2735 if (!pdata) 2736 return NULL; 2737 2738 pdata->phy_interface = of_get_phy_mode(np); 2739 2740 mac_addr = of_get_mac_address(np); 2741 if (mac_addr) 2742 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 2743 2744 pdata->no_ether_link = 2745 of_property_read_bool(np, "renesas,no-ether-link"); 2746 pdata->ether_link_active_low = 2747 of_property_read_bool(np, "renesas,ether-link-active-low"); 2748 2749 return pdata; 2750} 2751 2752static const struct of_device_id sh_eth_match_table[] = { 2753 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 2754 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data }, 2755 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data }, 2756 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data }, 2757 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data }, 2758 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 2759 { } 2760}; 2761MODULE_DEVICE_TABLE(of, sh_eth_match_table); 2762#else 2763static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 2764{ 2765 return NULL; 2766} 2767#endif 2768 2769static int sh_eth_drv_probe(struct platform_device *pdev) 2770{ 2771 int ret, devno = 0; 2772 struct resource *res; 2773 struct net_device *ndev = NULL; 2774 struct sh_eth_private *mdp = NULL; 2775 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 2776 const struct platform_device_id *id = platform_get_device_id(pdev); 2777 2778 /* get base addr */ 2779 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2780 if (unlikely(res == NULL)) { 2781 dev_err(&pdev->dev, "invalid resource\n"); 2782 return -EINVAL; 2783 } 2784 2785 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 2786 if (!ndev) 2787 return -ENOMEM; 2788 2789 pm_runtime_enable(&pdev->dev); 2790 pm_runtime_get_sync(&pdev->dev); 2791 2792 /* The sh Ether-specific entries in the device structure. */ 2793 ndev->base_addr = res->start; 2794 devno = pdev->id; 2795 if (devno < 0) 2796 devno = 0; 2797 2798 ndev->dma = -1; 2799 ret = platform_get_irq(pdev, 0); 2800 if (ret < 0) { 2801 ret = -ENODEV; 2802 goto out_release; 2803 } 2804 ndev->irq = ret; 2805 2806 SET_NETDEV_DEV(ndev, &pdev->dev); 2807 2808 mdp = netdev_priv(ndev); 2809 mdp->num_tx_ring = TX_RING_SIZE; 2810 mdp->num_rx_ring = RX_RING_SIZE; 2811 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 2812 if (IS_ERR(mdp->addr)) { 2813 ret = PTR_ERR(mdp->addr); 2814 goto out_release; 2815 } 2816 2817 spin_lock_init(&mdp->lock); 2818 mdp->pdev = pdev; 2819 2820 if (pdev->dev.of_node) 2821 pd = sh_eth_parse_dt(&pdev->dev); 2822 if (!pd) { 2823 dev_err(&pdev->dev, "no platform data\n"); 2824 ret = -EINVAL; 2825 goto out_release; 2826 } 2827 2828 /* get PHY ID */ 2829 mdp->phy_id = pd->phy; 2830 mdp->phy_interface = pd->phy_interface; 2831 /* EDMAC endian */ 2832 mdp->edmac_endian = pd->edmac_endian; 2833 mdp->no_ether_link = pd->no_ether_link; 2834 mdp->ether_link_active_low = pd->ether_link_active_low; 2835 2836 /* set cpu data */ 2837 if (id) { 2838 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 2839 } else { 2840 const struct of_device_id *match; 2841 2842 match = of_match_device(of_match_ptr(sh_eth_match_table), 2843 &pdev->dev); 2844 mdp->cd = (struct sh_eth_cpu_data *)match->data; 2845 } 2846 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 2847 if (!mdp->reg_offset) { 2848 dev_err(&pdev->dev, "Unknown register type (%d)\n", 2849 mdp->cd->register_type); 2850 ret = -EINVAL; 2851 goto out_release; 2852 } 2853 sh_eth_set_default_cpu_data(mdp->cd); 2854 2855 /* set function */ 2856 if (mdp->cd->tsu) 2857 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 2858 else 2859 ndev->netdev_ops = &sh_eth_netdev_ops; 2860 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); 2861 ndev->watchdog_timeo = TX_TIMEOUT; 2862 2863 /* debug message level */ 2864 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 2865 2866 /* read and set MAC address */ 2867 read_mac_address(ndev, pd->mac_addr); 2868 if (!is_valid_ether_addr(ndev->dev_addr)) { 2869 dev_warn(&pdev->dev, 2870 "no valid MAC address supplied, using a random one.\n"); 2871 eth_hw_addr_random(ndev); 2872 } 2873 2874 /* ioremap the TSU registers */ 2875 if (mdp->cd->tsu) { 2876 struct resource *rtsu; 2877 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2878 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); 2879 if (IS_ERR(mdp->tsu_addr)) { 2880 ret = PTR_ERR(mdp->tsu_addr); 2881 goto out_release; 2882 } 2883 mdp->port = devno % 2; 2884 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 2885 } 2886 2887 /* initialize first or needed device */ 2888 if (!devno || pd->needs_init) { 2889 if (mdp->cd->chip_reset) 2890 mdp->cd->chip_reset(ndev); 2891 2892 if (mdp->cd->tsu) { 2893 /* TSU init (Init only)*/ 2894 sh_eth_tsu_init(mdp); 2895 } 2896 } 2897 2898 /* MDIO bus init */ 2899 ret = sh_mdio_init(mdp, pd); 2900 if (ret) { 2901 dev_err(&ndev->dev, "failed to initialise MDIO\n"); 2902 goto out_release; 2903 } 2904 2905 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 2906 2907 /* network device register */ 2908 ret = register_netdev(ndev); 2909 if (ret) 2910 goto out_napi_del; 2911 2912 /* print device information */ 2913 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 2914 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2915 2916 pm_runtime_put(&pdev->dev); 2917 platform_set_drvdata(pdev, ndev); 2918 2919 return ret; 2920 2921out_napi_del: 2922 netif_napi_del(&mdp->napi); 2923 sh_mdio_release(mdp); 2924 2925out_release: 2926 /* net_dev free */ 2927 if (ndev) 2928 free_netdev(ndev); 2929 2930 pm_runtime_put(&pdev->dev); 2931 pm_runtime_disable(&pdev->dev); 2932 return ret; 2933} 2934 2935static int sh_eth_drv_remove(struct platform_device *pdev) 2936{ 2937 struct net_device *ndev = platform_get_drvdata(pdev); 2938 struct sh_eth_private *mdp = netdev_priv(ndev); 2939 2940 unregister_netdev(ndev); 2941 netif_napi_del(&mdp->napi); 2942 sh_mdio_release(mdp); 2943 pm_runtime_disable(&pdev->dev); 2944 free_netdev(ndev); 2945 2946 return 0; 2947} 2948 2949#ifdef CONFIG_PM 2950static int sh_eth_runtime_nop(struct device *dev) 2951{ 2952 /* Runtime PM callback shared between ->runtime_suspend() 2953 * and ->runtime_resume(). Simply returns success. 2954 * 2955 * This driver re-initializes all registers after 2956 * pm_runtime_get_sync() anyway so there is no need 2957 * to save and restore registers here. 2958 */ 2959 return 0; 2960} 2961 2962static const struct dev_pm_ops sh_eth_dev_pm_ops = { 2963 .runtime_suspend = sh_eth_runtime_nop, 2964 .runtime_resume = sh_eth_runtime_nop, 2965}; 2966#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 2967#else 2968#define SH_ETH_PM_OPS NULL 2969#endif 2970 2971static struct platform_device_id sh_eth_id_table[] = { 2972 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 2973 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 2974 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 2975 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 2976 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 2977 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 2978 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 2979 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data }, 2980 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, 2981 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data }, 2982 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data }, 2983 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data }, 2984 { } 2985}; 2986MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 2987 2988static struct platform_driver sh_eth_driver = { 2989 .probe = sh_eth_drv_probe, 2990 .remove = sh_eth_drv_remove, 2991 .id_table = sh_eth_id_table, 2992 .driver = { 2993 .name = CARDNAME, 2994 .pm = SH_ETH_PM_OPS, 2995 .of_match_table = of_match_ptr(sh_eth_match_table), 2996 }, 2997}; 2998 2999module_platform_driver(sh_eth_driver); 3000 3001MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3002MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3003MODULE_LICENSE("GPL v2"); 3004