11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * sgiseeq.h: Defines for the Seeq8003 ethernet controller. 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 479add6277396b91c638f16eb2f1338badc47760dJustin P. Mattock * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef _SGISEEQ_H 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define _SGISEEQ_H 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct sgiseeq_wregs { 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int multicase_high[2]; 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int frame_gap; 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int control; 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct sgiseeq_rregs { 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int collision_tx[2]; 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int collision_all[2]; 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int _unused0; 196aa20a2235535605db6d6d2bd850298b2fe7f31eJeff Garzik volatile unsigned int rflags; 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct sgiseeq_regs { 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds union { 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int eth_addr[6]; 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int multicast_low[6]; 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct sgiseeq_wregs wregs; 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct sgiseeq_rregs rregs; 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } rw; 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int rstat; 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile unsigned int tstat; 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Seeq8003 receive status register */ 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_OVERF 0x001 /* Overflow */ 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_CERROR 0x002 /* CRC error */ 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */ 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */ 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_FIG 0x020 /* Frame is good */ 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */ 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */ 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */ 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_ADMA 0x400 /* DMA is active */ 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RSTAT_ROVERF 0x800 /* Receive buffer overflow */ 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Seeq8003 receive command register */ 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_RDISAB 0x000 /* Disable receiver on the Seeq8003 */ 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_IOVERF 0x001 /* IRQ on buffer overflows */ 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_ICRC 0x002 /* IRQ on CRC errors */ 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_IDRIB 0x004 /* IRQ on dribble errors */ 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_ISHORT 0x008 /* IRQ on short frames */ 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_IEOF 0x010 /* IRQ on end of frame */ 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_IGOOD 0x020 /* IRQ on good frames */ 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_RANY 0x040 /* Receive any frame */ 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_RBCAST 0x080 /* Receive broadcasts */ 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_RCMD_RBMCAST 0x0c0 /* Receive broadcasts/multicasts */ 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Seeq8003 transmit status register */ 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TSTAT_UFLOW 0x001 /* Transmit buffer underflow */ 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TSTAT_CLS 0x002 /* Collision detected */ 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TSTAT_R16 0x004 /* Did 16 retries to tx a frame */ 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TSTAT_PTRANS 0x008 /* Packet was transmitted ok */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TSTAT_LCLS 0x010 /* Late collision occurred */ 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TSTAT_WHICH 0x080 /* Which status, 1=old 0=new */ 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TSTAT_TLE 0x100 /* DMA is done in little endian format */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TSTAT_SDMA 0x200 /* DMA has started */ 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TSTAT_ADMA 0x400 /* DMA is active */ 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Seeq8003 transmit command register */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TCMD_RB0 0x00 /* Register bank zero w/station addr */ 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TCMD_IUF 0x01 /* IRQ on tx underflow */ 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TCMD_IC 0x02 /* IRQ on collisions */ 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TCMD_I16 0x04 /* IRQ after 16 failed attempts to tx frame */ 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TCMD_IPT 0x08 /* IRQ when packet successfully transmitted */ 766aa20a2235535605db6d6d2bd850298b2fe7f31eJeff Garzik#define SEEQ_TCMD_RB1 0x20 /* Register bank one w/multi-cast low byte */ 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_TCMD_RB2 0x40 /* Register bank two w/multi-cast high byte */ 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Seeq8003 control register */ 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_CTRL_XCNT 0x01 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_CTRL_ACCNT 0x02 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_CTRL_SFLAG 0x04 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_CTRL_EMULTI 0x08 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_CTRL_ESHORT 0x10 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_CTRL_ENCARR 0x20 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Seeq8003 control registers on the SGI Hollywood HPC. */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HPIO_P1BITS 0x00000001 /* cycles to stay in P1 phase for PIO */ 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HPIO_P2BITS 0x00000060 /* cycles to stay in P2 phase for PIO */ 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HPIO_P3BITS 0x00000100 /* cycles to stay in P3 phase for PIO */ 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HDMA_D1BITS 0x00000006 /* cycles to stay in D1 phase for DMA */ 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HDMA_D2BITS 0x00000020 /* cycles to stay in D2 phase for DMA */ 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HDMA_D3BITS 0x00000000 /* cycles to stay in D3 phase for DMA */ 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HDMA_TIMEO 0x00030000 /* cycles for DMA timeout */ 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HCTL_NORM 0x00000000 /* Normal operation mode */ 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HCTL_RESET 0x00000001 /* Reset Seeq8003 and HPC interface */ 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HCTL_IPEND 0x00000002 /* IRQ is pending for the chip */ 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HCTL_IPG 0x00001000 /* Inter-packet gap */ 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HCTL_RFIX 0x00002000 /* At rxdc, clear end-of-packet */ 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HCTL_EFIX 0x00004000 /* fixes intr status bit settings */ 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SEEQ_HCTL_IFIX 0x00008000 /* enable startup timeouts */ 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* !(_SGISEEQ_H) */ 104