1aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO/******************************************************************************* 2aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO Copyright (C) 2007-2009 STMicroelectronics Ltd 3aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 4aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO This program is free software; you can redistribute it and/or modify it 5aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO under the terms and conditions of the GNU General Public License, 6aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO version 2, as published by the Free Software Foundation. 7aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 8aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO This program is distributed in the hope it will be useful, but WITHOUT 9aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO more details. 12aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 13aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO You should have received a copy of the GNU General Public License along with 14aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO this program; if not, write to the Free Software Foundation, Inc., 15aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 17aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO The full GNU General Public License is included in this distribution in 18aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO the file called "COPYING". 19aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 20aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 21aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO*******************************************************************************/ 22aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 23aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#include <linux/io.h> 24aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#include "common.h" 25aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#include "dwmac_dma.h" 26aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 27cffb13f4d6fb5976f907c37e7fc7f6e6acb10d5fGiuseppe CAVALLARO#define GMAC_HI_REG_AE 0x80000000 28cffb13f4d6fb5976f907c37e7fc7f6e6acb10d5fGiuseppe CAVALLARO 29aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO/* CSR1 enables the transmit DMA to check for new descriptor */ 30ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid dwmac_enable_dma_transmission(void __iomem *ioaddr) 31aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 32aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(1, ioaddr + DMA_XMT_POLL_DEMAND); 33aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 34aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 35ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid dwmac_enable_dma_irq(void __iomem *ioaddr) 36aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 37aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 38aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 39aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 40ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid dwmac_disable_dma_irq(void __iomem *ioaddr) 41aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 42aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(0, ioaddr + DMA_INTR_ENA); 43aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 44aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 45ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid dwmac_dma_start_tx(void __iomem *ioaddr) 46aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 47aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 value = readl(ioaddr + DMA_CONTROL); 48aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO value |= DMA_CONTROL_ST; 49aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(value, ioaddr + DMA_CONTROL); 50aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 51aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 52ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid dwmac_dma_stop_tx(void __iomem *ioaddr) 53aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 54aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 value = readl(ioaddr + DMA_CONTROL); 55aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO value &= ~DMA_CONTROL_ST; 56aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(value, ioaddr + DMA_CONTROL); 57aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 58aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 59ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid dwmac_dma_start_rx(void __iomem *ioaddr) 60aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 61aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 value = readl(ioaddr + DMA_CONTROL); 62aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO value |= DMA_CONTROL_SR; 63aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(value, ioaddr + DMA_CONTROL); 64aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 65aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 66ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid dwmac_dma_stop_rx(void __iomem *ioaddr) 67aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 68aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 value = readl(ioaddr + DMA_CONTROL); 69aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO value &= ~DMA_CONTROL_SR; 70aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(value, ioaddr + DMA_CONTROL); 71aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 72aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 73aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#ifdef DWMAC_DMA_DEBUG 74aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROstatic void show_tx_process_state(unsigned int status) 75aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 76aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int state; 77aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT; 78aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 79aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO switch (state) { 80aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 0: 8183d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- TX (Stopped): Reset or Stop command\n"); 82aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 83aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 1: 8483d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- TX (Running):Fetching the Tx desc\n"); 85aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 86aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 2: 8783d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- TX (Running): Waiting for end of tx\n"); 88aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 89aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 3: 9083d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- TX (Running): Reading the data " 91aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO "and queuing the data into the Tx buf\n"); 92aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 93aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 6: 9483d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- TX (Suspended): Tx Buff Underflow " 95aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO "or an unavailable Transmit descriptor\n"); 96aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 97aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 7: 9883d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- TX (Running): Closing Tx descriptor\n"); 99aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 100aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO default: 101aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 102aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 103aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 104aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 105aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROstatic void show_rx_process_state(unsigned int status) 106aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 107aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int state; 108aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT; 109aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 110aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO switch (state) { 111aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 0: 11283d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- RX (Stopped): Reset or Stop command\n"); 113aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 114aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 1: 11583d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- RX (Running): Fetching the Rx desc\n"); 116aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 117aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 2: 11883d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- RX (Running):Checking for end of pkt\n"); 119aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 120aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 3: 12183d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- RX (Running): Waiting for Rx pkt\n"); 122aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 123aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 4: 12483d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- RX (Suspended): Unavailable Rx buf\n"); 125aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 126aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 5: 12783d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- RX (Running): Closing Rx descriptor\n"); 128aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 129aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 6: 13083d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- RX(Running): Flushing the current frame" 131aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO " from the Rx buf\n"); 132aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 133aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 7: 13483d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("- RX (Running): Queuing the Rx frame" 135aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO " from the Rx buf into memory\n"); 136aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 137aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO default: 138aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 139aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 140aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 141aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#endif 142aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 143ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROint dwmac_dma_interrupt(void __iomem *ioaddr, 144aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO struct stmmac_extra_stats *x) 145aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 146aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO int ret = 0; 147aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* read the status register (CSR5) */ 148aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 intr_status = readl(ioaddr + DMA_STATUS); 149aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 150aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#ifdef DWMAC_DMA_DEBUG 15183d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO /* Enable it to monitor DMA rx/tx status in case of critical problems */ 15283d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status); 153aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO show_tx_process_state(intr_status); 154aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO show_rx_process_state(intr_status); 155aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#endif 156aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* ABNORMAL interrupts */ 157aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_AIS)) { 158aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_UNF)) { 159aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO ret = tx_hard_error_bump_tc; 160aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->tx_undeflow_irq++; 161aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 16283d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_TJT)) 163aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->tx_jabber_irq++; 16483d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO 16583d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_OVF)) 166aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->rx_overflow_irq++; 16783d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO 16883d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_RU)) 169aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->rx_buf_unav_irq++; 17083d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_RPS)) 171aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->rx_process_stopped_irq++; 17283d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_RWT)) 173aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->rx_watchdog_irq++; 17483d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_ETI)) 175aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->tx_early_irq++; 176aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_TPS)) { 177aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->tx_process_stopped_irq++; 178aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO ret = tx_hard_error; 179aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 180aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_FBI)) { 181aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->fatal_bus_error_irq++; 182aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO ret = tx_hard_error; 183aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 184aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 185aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* TX/RX NORMAL interrupts */ 18662a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO if (likely(intr_status & DMA_STATUS_NIS)) { 187aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->normal_irq_n++; 18862a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO if (likely(intr_status & DMA_STATUS_RI)) { 18962a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO u32 value = readl(ioaddr + DMA_INTR_ENA); 19062a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO /* to schedule NAPI on real RIE event. */ 19162a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO if (likely(value & DMA_INTR_ENA_RIE)) { 19262a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO x->rx_normal_irq_n++; 19362a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO ret |= handle_rx; 19462a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO } 19562a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO } 19662a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO if (likely(intr_status & DMA_STATUS_TI)) { 19762a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO x->tx_normal_irq_n++; 1989125cdd1be1199588f71c99e76e32bcda0b7d847Giuseppe CAVALLARO ret |= handle_tx; 19962a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO } 20062a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_ERI)) 20162a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO x->rx_early_irq++; 202aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 203aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* Optional hardware blocks, interrupts should be disabled */ 204aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & 205aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 20683d7af64ac9eaf4f4db7228677bc25f23c383790Giuseppe CAVALLARO pr_warn("%s: unexpected status %08x\n", __func__, intr_status); 20762a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO 208aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */ 209aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); 210aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 211aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return ret; 212aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 213aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 214ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) 215688911c2f5e5e4f33b5a1c32839184f1fdf814eeGiuseppe CAVALLARO{ 216688911c2f5e5e4f33b5a1c32839184f1fdf814eeGiuseppe CAVALLARO u32 csr6 = readl(ioaddr + DMA_CONTROL); 217688911c2f5e5e4f33b5a1c32839184f1fdf814eeGiuseppe CAVALLARO writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); 218688911c2f5e5e4f33b5a1c32839184f1fdf814eeGiuseppe CAVALLARO 219688911c2f5e5e4f33b5a1c32839184f1fdf814eeGiuseppe CAVALLARO do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); 220688911c2f5e5e4f33b5a1c32839184f1fdf814eeGiuseppe CAVALLARO} 221aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 222ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 223aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int high, unsigned int low) 224aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 225aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned long data; 226aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 227aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO data = (addr[5] << 8) | addr[4]; 228cffb13f4d6fb5976f907c37e7fc7f6e6acb10d5fGiuseppe CAVALLARO /* For MAC Addr registers se have to set the Address Enable (AE) 229cffb13f4d6fb5976f907c37e7fc7f6e6acb10d5fGiuseppe CAVALLARO * bit that has no effect on the High Reg 0 where the bit 31 (MO) 230cffb13f4d6fb5976f907c37e7fc7f6e6acb10d5fGiuseppe CAVALLARO * is RO. 231cffb13f4d6fb5976f907c37e7fc7f6e6acb10d5fGiuseppe CAVALLARO */ 232cffb13f4d6fb5976f907c37e7fc7f6e6acb10d5fGiuseppe CAVALLARO writel(data | GMAC_HI_REG_AE, ioaddr + high); 233aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 234aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(data, ioaddr + low); 235aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 236aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 237bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO/* Enable disable MAC RX/TX */ 238bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLAROvoid stmmac_set_mac(void __iomem *ioaddr, bool enable) 239bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO{ 240bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO u32 value = readl(ioaddr + MAC_CTRL_REG); 241bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO 242bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO if (enable) 243bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO value |= MAC_RNABLE_RX | MAC_ENABLE_TX; 244bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO else 245bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX); 246bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO 247bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO writel(value, ioaddr + MAC_CTRL_REG); 248bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO} 249bfab27a146ed4d722c6d399f844f955f29cd2b81Giuseppe CAVALLARO 250ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLAROvoid stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 251aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int high, unsigned int low) 252aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 253aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int hi_addr, lo_addr; 254aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 255aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* Read the MAC address from the hardware */ 256aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO hi_addr = readl(ioaddr + high); 257aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO lo_addr = readl(ioaddr + low); 258aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 259aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* Extract the MAC address from the high and low words */ 260aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[0] = lo_addr & 0xff; 261aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[1] = (lo_addr >> 8) & 0xff; 262aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[2] = (lo_addr >> 16) & 0xff; 263aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[3] = (lo_addr >> 24) & 0xff; 264aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[4] = hi_addr & 0xff; 265aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[5] = (hi_addr >> 8) & 0xff; 266aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 267aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 268