dwmac_lib.c revision aec7ff278145280c2c78377aeb98feed02c8b636
1aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO/******************************************************************************* 2aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO Copyright (C) 2007-2009 STMicroelectronics Ltd 3aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 4aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO This program is free software; you can redistribute it and/or modify it 5aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO under the terms and conditions of the GNU General Public License, 6aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO version 2, as published by the Free Software Foundation. 7aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 8aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO This program is distributed in the hope it will be useful, but WITHOUT 9aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO more details. 12aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 13aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO You should have received a copy of the GNU General Public License along with 14aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO this program; if not, write to the Free Software Foundation, Inc., 15aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 17aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO The full GNU General Public License is included in this distribution in 18aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO the file called "COPYING". 19aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 20aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 21aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO*******************************************************************************/ 22aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 23aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#include <linux/io.h> 24aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#include "common.h" 25aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#include "dwmac_dma.h" 26aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 27aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#undef DWMAC_DMA_DEBUG 28aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#ifdef DWMAC_DMA_DEBUG 29aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#define DBG(fmt, args...) printk(fmt, ## args) 30aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#else 31aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#define DBG(fmt, args...) do { } while (0) 32aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#endif 33aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 34aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO/* CSR1 enables the transmit DMA to check for new descriptor */ 35aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROvoid dwmac_enable_dma_transmission(unsigned long ioaddr) 36aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 37aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(1, ioaddr + DMA_XMT_POLL_DEMAND); 38aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 39aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 40aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROvoid dwmac_enable_dma_irq(unsigned long ioaddr) 41aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 42aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 43aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 44aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 45aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROvoid dwmac_disable_dma_irq(unsigned long ioaddr) 46aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 47aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(0, ioaddr + DMA_INTR_ENA); 48aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 49aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 50aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROvoid dwmac_dma_start_tx(unsigned long ioaddr) 51aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 52aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 value = readl(ioaddr + DMA_CONTROL); 53aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO value |= DMA_CONTROL_ST; 54aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(value, ioaddr + DMA_CONTROL); 55aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return; 56aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 57aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 58aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROvoid dwmac_dma_stop_tx(unsigned long ioaddr) 59aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 60aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 value = readl(ioaddr + DMA_CONTROL); 61aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO value &= ~DMA_CONTROL_ST; 62aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(value, ioaddr + DMA_CONTROL); 63aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return; 64aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 65aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 66aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROvoid dwmac_dma_start_rx(unsigned long ioaddr) 67aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 68aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 value = readl(ioaddr + DMA_CONTROL); 69aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO value |= DMA_CONTROL_SR; 70aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(value, ioaddr + DMA_CONTROL); 71aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 72aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return; 73aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 74aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 75aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROvoid dwmac_dma_stop_rx(unsigned long ioaddr) 76aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 77aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 value = readl(ioaddr + DMA_CONTROL); 78aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO value &= ~DMA_CONTROL_SR; 79aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(value, ioaddr + DMA_CONTROL); 80aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 81aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return; 82aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 83aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 84aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#ifdef DWMAC_DMA_DEBUG 85aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROstatic void show_tx_process_state(unsigned int status) 86aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 87aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int state; 88aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT; 89aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 90aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO switch (state) { 91aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 0: 92aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- TX (Stopped): Reset or Stop command\n"); 93aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 94aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 1: 95aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- TX (Running):Fetching the Tx desc\n"); 96aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 97aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 2: 98aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- TX (Running): Waiting for end of tx\n"); 99aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 100aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 3: 101aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- TX (Running): Reading the data " 102aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO "and queuing the data into the Tx buf\n"); 103aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 104aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 6: 105aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- TX (Suspended): Tx Buff Underflow " 106aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO "or an unavailable Transmit descriptor\n"); 107aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 108aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 7: 109aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- TX (Running): Closing Tx descriptor\n"); 110aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 111aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO default: 112aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 113aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 114aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return; 115aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 116aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 117aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROstatic void show_rx_process_state(unsigned int status) 118aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 119aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int state; 120aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT; 121aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 122aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO switch (state) { 123aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 0: 124aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- RX (Stopped): Reset or Stop command\n"); 125aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 126aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 1: 127aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- RX (Running): Fetching the Rx desc\n"); 128aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 129aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 2: 130aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- RX (Running):Checking for end of pkt\n"); 131aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 132aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 3: 133aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- RX (Running): Waiting for Rx pkt\n"); 134aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 135aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 4: 136aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- RX (Suspended): Unavailable Rx buf\n"); 137aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 138aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 5: 139aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- RX (Running): Closing Rx descriptor\n"); 140aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 141aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 6: 142aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- RX(Running): Flushing the current frame" 143aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO " from the Rx buf\n"); 144aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 145aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO case 7: 146aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("- RX (Running): Queuing the Rx frame" 147aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO " from the Rx buf into memory\n"); 148aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 149aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO default: 150aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO break; 151aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 152aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return; 153aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 154aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#endif 155aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 156aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROint dwmac_dma_interrupt(unsigned long ioaddr, 157aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO struct stmmac_extra_stats *x) 158aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 159aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO int ret = 0; 160aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* read the status register (CSR5) */ 161aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO u32 intr_status = readl(ioaddr + DMA_STATUS); 162aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 163aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status); 164aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#ifdef DWMAC_DMA_DEBUG 165aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* It displays the DMA process states (CSR5 register) */ 166aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO show_tx_process_state(intr_status); 167aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO show_rx_process_state(intr_status); 168aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO#endif 169aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* ABNORMAL interrupts */ 170aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_AIS)) { 171aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "CSR5[15] DMA ABNORMAL IRQ: "); 172aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_UNF)) { 173aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "transmit underflow\n"); 174aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO ret = tx_hard_error_bump_tc; 175aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->tx_undeflow_irq++; 176aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 177aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_TJT)) { 178aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "transmit jabber\n"); 179aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->tx_jabber_irq++; 180aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 181aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_OVF)) { 182aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "recv overflow\n"); 183aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->rx_overflow_irq++; 184aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 185aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_RU)) { 186aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "receive buffer unavailable\n"); 187aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->rx_buf_unav_irq++; 188aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 189aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_RPS)) { 190aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "receive process stopped\n"); 191aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->rx_process_stopped_irq++; 192aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 193aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_RWT)) { 194aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "receive watchdog\n"); 195aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->rx_watchdog_irq++; 196aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 197aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_ETI)) { 198aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "transmit early interrupt\n"); 199aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->tx_early_irq++; 200aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 201aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_TPS)) { 202aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "transmit process stopped\n"); 203aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->tx_process_stopped_irq++; 204aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO ret = tx_hard_error; 205aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 206aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & DMA_STATUS_FBI)) { 207aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "fatal bus error\n"); 208aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->fatal_bus_error_irq++; 209aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO ret = tx_hard_error; 210aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 211aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 212aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* TX/RX NORMAL interrupts */ 213aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (intr_status & DMA_STATUS_NIS) { 214aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO x->normal_irq_n++; 215aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (likely((intr_status & DMA_STATUS_RI) || 216aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO (intr_status & (DMA_STATUS_TI)))) 217aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO ret = handle_tx_rx; 218aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO } 219aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* Optional hardware blocks, interrupts should be disabled */ 220aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO if (unlikely(intr_status & 221aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 222aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO pr_info("%s: unexpected status %08x\n", __func__, intr_status); 223aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */ 224aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); 225aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 226aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO DBG(INFO, "\n\n"); 227aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return ret; 228aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 229aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 230aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 231aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROvoid stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], 232aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int high, unsigned int low) 233aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 234aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned long data; 235aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 236aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO data = (addr[5] << 8) | addr[4]; 237aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(data, ioaddr + high); 238aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 239aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO writel(data, ioaddr + low); 240aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 241aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return; 242aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 243aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 244aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLAROvoid stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr, 245aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int high, unsigned int low) 246aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO{ 247aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO unsigned int hi_addr, lo_addr; 248aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 249aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* Read the MAC address from the hardware */ 250aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO hi_addr = readl(ioaddr + high); 251aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO lo_addr = readl(ioaddr + low); 252aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 253aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO /* Extract the MAC address from the high and low words */ 254aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[0] = lo_addr & 0xff; 255aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[1] = (lo_addr >> 8) & 0xff; 256aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[2] = (lo_addr >> 16) & 0xff; 257aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[3] = (lo_addr >> 24) & 0xff; 258aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[4] = hi_addr & 0xff; 259aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO addr[5] = (hi_addr >> 8) & 0xff; 260aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 261aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO return; 262aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO} 263aec7ff278145280c2c78377aeb98feed02c8b636Giuseppe CAVALLARO 264