11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* $Id: sungem.h,v 1.10.2.4 2002/03/11 08:54:48 davem Exp $ 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * sungem.h: Definitions for Sun GEM ethernet driver. 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 2000 David S. Miller (davem@redhat.com) 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef _SUNGEM_H 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define _SUNGEM_H 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Global Registers */ 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_SEBSTATE 0x0000UL /* SEB State Register */ 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_CFG 0x0004UL /* Configuration Register */ 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT 0x000CUL /* Status Register */ 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_IMASK 0x0010UL /* Interrupt Mask Register */ 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_IACK 0x0014UL /* Interrupt ACK Register */ 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */ 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */ 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */ 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */ 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */ 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_SWRST 0x1010UL /* Software Reset Register */ 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Global SEB State Register */ 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_SEBSTATE_ARB 0x00000003 /* State of Arbiter */ 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */ 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Global Configuration Register */ 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */ 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */ 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */ 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_CFG_RONPAULBIT 0x00000800 /* Use mem read multiple for PCI read 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * after infinite burst (Apple) */ 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */ 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Global Interrupt Status Register. 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Reading this register automatically clears bits 0 through 6. 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This auto-clearing does not occur when the alias at GREG_STAT2 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is read instead. The rest of the interrupt bits only clear when 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the secondary interrupt status register corresponding to that 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * reading PCS_ISTAT). 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */ 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */ 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */ 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */ 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */ 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */ 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */ 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */ 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */ 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_MIF 0x00020000 /* MIF signalled interrupt */ 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_PCIERR 0x00040000 /* PCI Error interrupt */ 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */ 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_TXNR_SHIFT 19 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_ABNORMAL (GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \ 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \ 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR) 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_STAT_NAPI (GREG_STAT_TXALL | GREG_STAT_TXINTME | \ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds GREG_STAT_RXDONE | GREG_STAT_ABNORMAL) 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT. 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bits set in GREG_IMASK will prevent that interrupt type from being 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * signalled to the cpu. GREG_IACK can be used to clear specific top-level 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6. 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Setting the bit will clear that interrupt, clear bits will have no effect 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * on GREG_STAT. 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Global PCI Error Status Register */ 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_PCIESTAT_BADACK 0x00000001 /* No ACK64# during ABS64 cycle */ 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_PCIESTAT_DTRTO 0x00000002 /* Delayed transaction timeout */ 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_PCIESTAT_OTHER 0x00000004 /* Other PCI error, check cfg space */ 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT. 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bits set in GREG_PCIEMASK will prevent that interrupt type from being 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * signalled to the cpu. 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Global BIF Configuration Register */ 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_BIFCFG_SLOWCLK 0x00000001 /* Set if PCI runs < 25Mhz */ 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_BIFCFG_B64DIS 0x00000002 /* Disable 64bit wide data cycle*/ 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_BIFCFG_M66EN 0x00000004 /* Set if on 66Mhz PCI segment */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Global BIF Diagnostics Register */ 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */ 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_BIFDIAG_BIFSM 0xff000000 /* BIF state machine */ 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Global Software Reset Register. 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This register is used to perform a global reset of the RX and TX portions 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * of the GEM asic. Setting the RX or TX reset bit will start the reset. 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The driver _MUST_ poll these bits until they clear. One may not attempt 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to program any other part of GEM until the bits clear. 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */ 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */ 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */ 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_SWRST_CACHESIZE 0x00ff0000 /* RIO only: cache line size */ 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define GREG_SWRST_CACHE_SHIFT 16 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TX DMA Registers */ 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_KICK 0x2000UL /* TX Kick Register */ 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG 0x2004UL /* TX Configuration Register */ 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */ 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */ 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */ 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */ 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */ 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */ 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */ 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */ 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_DPHI 0x2034UL /* TX Data Pointer High */ 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_TXDONE 0x2100UL /* TX Completion Register */ 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_FADDR 0x2104UL /* TX FIFO Address */ 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_FTAG 0x2108UL /* TX FIFO Tag */ 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */ 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */ 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */ 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_FSZ 0x2118UL /* TX FIFO Size */ 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TX Kick Register. 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This 13-bit register is programmed by the driver to hold the descriptor 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * entry index which follows the last valid transmit descriptor. 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TX Completion Register. 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This 13-bit register is updated by GEM to hold to descriptor entry index 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * which follows the last descriptor already processed by GEM. Note that 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * this value is mirrored in GREG_STAT which eliminates the need to even 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * access this register in the driver during interrupt processing. 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TX Configuration Register. 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * that was meant to be used with jumbo packets. It should be set to the 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors. 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */ 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */ 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */ 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */ 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */ 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */ 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */ 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */ 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */ 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */ 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */ 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */ 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */ 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/ 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TX Descriptor Base Low/High. 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * These two registers store the 53 most significant bits of the base address 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * of the TX descriptor table. The 11 least significant bits are always 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * zero. As a result, the TX descriptor table must be 2K aligned. 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The rest of the TXDMA_* registers are for diagnostics and debug, I will document 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * them later. -DaveM 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* WakeOnLan Registers */ 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_MATCH0 0x3000UL 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_MATCH1 0x3004UL 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_MATCH2 0x3008UL 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_MCOUNT 0x300CUL 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_WAKECSR 0x3010UL 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* WOL Match count register 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_MCOUNT_N 0x00000010 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_MCOUNT_M 0x00000000 /* 0 << 8 */ 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_WAKECSR_ENABLE 0x00000001 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_WAKECSR_MII 0x00000002 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_WAKECSR_SEEN 0x00000004 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_WAKECSR_FILT_UCAST 0x00000008 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_WAKECSR_FILT_MCAST 0x00000010 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_WAKECSR_FILT_BCAST 0x00000020 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WOL_WAKECSR_FILT_SEEN 0x00000040 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Receive DMA Registers */ 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG 0x4000UL /* RX Configuration Register */ 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */ 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */ 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */ 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */ 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */ 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */ 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */ 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_PTHRESH 0x4020UL /* Pause Thresholds */ 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */ 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_DPHI 0x4028UL /* RX Data Pointer High */ 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_KICK 0x4100UL /* RX Kick Register */ 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_DONE 0x4104UL /* RX Completion Register */ 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_BLANK 0x4108UL /* RX Blanking Register */ 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_FADDR 0x410CUL /* RX FIFO Address */ 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_FTAG 0x4110UL /* RX FIFO Tag */ 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */ 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */ 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */ 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_FSZ 0x4120UL /* RX FIFO Size */ 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX Configuration Register. */ 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */ 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */ 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */ 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */ 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */ 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */ 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */ 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */ 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */ 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */ 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */ 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */ 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */ 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */ 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */ 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */ 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */ 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */ 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */ 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */ 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */ 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX Descriptor Base Low/High. 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * These two registers store the 53 most significant bits of the base address 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * of the RX descriptor table. The 11 least significant bits are always 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * zero. As a result, the RX descriptor table must be 2K aligned. 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX PAUSE Thresholds. 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * These values determine when XOFF and XON PAUSE frames are emitted by 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * GEM. The thresholds measure RX FIFO occupancy in units of 64 bytes. 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_PTHRESH_OFF 0x000001ff /* XOFF emitted w/FIFO > this */ 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_PTHRESH_ON 0x001ff000 /* XON emitted w/FIFO < this */ 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX Kick Register. 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This 13-bit register is written by the host CPU and holds the last 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * valid RX descriptor number plus one. This is, if 'N' is written to 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * this register, it means that all RX descriptors up to but excluding 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 'N' are valid. 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The hardware requires that RX descriptors are posted in increments 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * of 4. This means 'N' must be a multiple of four. For the best 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * performance, the first new descriptor being posted should be (PCI) 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cache line aligned. 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX Completion Register. 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This 13-bit register is updated by GEM to indicate which RX descriptors 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * have already been used for receive frames. All descriptors up to but 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * excluding the value in this register are ready to be processed. GEM 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * updates this register value after the RX FIFO empties completely into 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the RX descriptor's buffer, but before the RX_DONE bit is set in the 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * interrupt status register. 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX Blanking Register. */ 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_BLANK_IPKTS 0x000001ff /* RX_DONE asserted after this 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * many packets received since 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * previous RX_DONE. 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_BLANK_ITIME 0x000ff000 /* RX_DONE asserted after this 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * many clocks (measured in 2048 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PCI clocks) were counted since 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the previous RX_DONE. 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX FIFO Size. 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This 11-bit read-only register indicates how large, in units of 64-bytes, 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the RX FIFO is. The driver uses this to properly configure the RX PAUSE 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * thresholds. 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The rest of the RXDMA_* registers are for diagnostics and debug, I will document 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * them later. -DaveM 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MAC Registers */ 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/ 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/ 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */ 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */ 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */ 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CSTAT 0x6018UL /* MAC Control Status Register */ 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */ 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */ 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */ 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/ 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/ 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MCCFG 0x6038UL /* MAC Control Config Register */ 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_XIFCFG 0x603CUL /* XIF Configuration Register */ 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_IPG0 0x6040UL /* InterPacketGap0 Register */ 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_IPG1 0x6044UL /* InterPacketGap1 Register */ 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_IPG2 0x6048UL /* InterPacketGap2 Register */ 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_STIME 0x604CUL /* SlotTime Register */ 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MINFSZ 0x6050UL /* MinFrameSize Register */ 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */ 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_PASIZE 0x6058UL /* PA Size Register */ 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_JAMSIZE 0x605CUL /* JamSize Register */ 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ATTLIM 0x6060UL /* Attempt Limit Register */ 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */ 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */ 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */ 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */ 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */ 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */ 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */ 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */ 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */ 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */ 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */ 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */ 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */ 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */ 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */ 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH0 0x60C0UL /* Hash Table 0 Register */ 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH1 0x60C4UL /* Hash Table 1 Register */ 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH2 0x60C8UL /* Hash Table 2 Register */ 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH3 0x60CCUL /* Hash Table 3 Register */ 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH4 0x60D0UL /* Hash Table 4 Register */ 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH5 0x60D4UL /* Hash Table 5 Register */ 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH6 0x60D8UL /* Hash Table 6 Register */ 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH7 0x60DCUL /* Hash Table 7 Register */ 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH8 0x60E0UL /* Hash Table 8 Register */ 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH9 0x60E4UL /* Hash Table 9 Register */ 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH10 0x60E8UL /* Hash Table 10 Register */ 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH11 0x60ECUL /* Hash Table 11 Register */ 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH12 0x60F0UL /* Hash Table 12 Register */ 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH13 0x60F4UL /* Hash Table 13 Register */ 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */ 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */ 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_NCOLL 0x6100UL /* Normal Collision Counter */ 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */ 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_ECOLL 0x6108UL /* Excessive Collision Counter */ 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_LCOLL 0x610CUL /* Late Collision Counter */ 3571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_DTIMER 0x6110UL /* Defer Timer */ 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_PATMPS 0x6114UL /* Peak Attempts Register */ 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RFCTR 0x6118UL /* Receive Frame Counter */ 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_LERR 0x611CUL /* Length Error Counter */ 3611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_AERR 0x6120UL /* Alignment Error Counter */ 3621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_FCSERR 0x6124UL /* FCS Error Counter */ 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */ 3641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RANDSEED 0x6130UL /* Random Number Seed Register */ 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_SMACHINE 0x6134UL /* State Machine Register */ 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TX MAC Software Reset Command. */ 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */ 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX MAC Software Reset Command. */ 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */ 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Send Pause Command. */ 3741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_SNDPAUSE_TS 0x0000ffff /* The pause_time operand used in 3751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Send_Pause and flow-control 3761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * handshakes. 3771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_SNDPAUSE_SP 0x00010000 /* Setting this bit instructs the MAC 3791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to send a Pause Flow Control 3801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * frame onto the network. 3811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TX MAC Status Register. */ 3841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT_XMIT 0x00000001 /* Frame Transmitted */ 3851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */ 3861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT_MPE 0x00000004 /* Max Packet Size Error */ 3871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT_NCE 0x00000008 /* Normal Collision Cntr Expire */ 3881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT_ECE 0x00000010 /* Excess Collision Cntr Expire */ 3891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT_LCE 0x00000020 /* Late Collision Cntr Expire */ 3901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT_FCE 0x00000040 /* First Collision Cntr Expire */ 3911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT_DTE 0x00000080 /* Defer Timer Expire */ 3921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXSTAT_PCE 0x00000100 /* Peak Attempts Cntr Expire */ 3931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX MAC Status Register. */ 3951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXSTAT_RCV 0x00000001 /* Frame Received */ 3961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXSTAT_OFLW 0x00000002 /* Receive Overflow */ 3971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXSTAT_FCE 0x00000004 /* Frame Cntr Expire */ 3981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXSTAT_ACE 0x00000008 /* Align Error Cntr Expire */ 3991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXSTAT_CCE 0x00000010 /* CRC Error Cntr Expire */ 4001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXSTAT_LCE 0x00000020 /* Length Error Cntr Expire */ 4011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXSTAT_VCE 0x00000040 /* Code Violation Cntr Expire */ 4021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MAC Control Status Register. */ 4041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CSTAT_PRCV 0x00000001 /* Pause Received */ 4051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CSTAT_PS 0x00000002 /* Paused State */ 4061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CSTAT_NPS 0x00000004 /* Not Paused State */ 4071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */ 4081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The layout of the MAC_{TX,RX,C}MASK registers is identical to that 4101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent 4111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * that interrupt type from being signalled to front end of GEM. For 4121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the interrupt to actually get sent to the cpu, it is necessary to 4131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well. 4141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* TX MAC Configuration Register. 4171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * NOTE: The TX MAC Enable bit must be cleared and polled until 4191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * zero before any other bits in this register are changed. 4201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Also, enabling the Carrier Extension feature of GEM is 4221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * a 3 step process 1) Set TX Carrier Extension 2) Set 4231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * RX Carrier Extension 3) Set Slot Time to 0x200. This 4241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * mode must be enabled when in half-duplex at 1Gbps, else 4251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it must be disabled. 4261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */ 4281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_ICS 0x00000002 /* Ignore Carrier Sense */ 4291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_ICOLL 0x00000004 /* Ignore Collisions */ 4301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */ 4311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_NGU 0x00000010 /* Never Give Up */ 4321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_NGUL 0x00000020 /* Never Give Up Limit */ 4331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_NBO 0x00000040 /* No Backoff */ 4341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_SD 0x00000080 /* Slow Down */ 4351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_NFCS 0x00000100 /* No FCS */ 4361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */ 4371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* RX MAC Configuration Register. 4391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * NOTE: The RX MAC Enable bit must be cleared and polled until 4411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * zero before any other bits in this register are changed. 4421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Similar rules apply to the Hash Filter Enable bit when 4441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * programming the hash table registers, and the Address Filter 4451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Enable bit when programming the address filter registers. 4461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */ 4481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG_SPAD 0x00000002 /* Strip Pad */ 4491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */ 4501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */ 4511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */ 4521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */ 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */ 4541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG_DDE 0x00000080 /* Disable Discard on Error */ 4551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */ 4561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MAC Control Config Register. */ 4581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */ 4591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */ 4601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */ 4611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* XIF Configuration Register. 4631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * NOTE: When leaving or entering loopback mode, a global hardware 4651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * init of GEM should be performed. 4661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */ 4681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */ 4691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */ 4701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_XIFCFG_GMII 0x00000008 /* Use GMII clocks + datapath */ 4711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_XIFCFG_MBOE 0x00000010 /* Controls MII_BUF_EN pin */ 4721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_XIFCFG_LLED 0x00000020 /* Force LINKLED# active (low) */ 4731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_XIFCFG_FLED 0x00000040 /* Force FDPLXLED# active (low) */ 4741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* InterPacketGap0 Register. This 8-bit value is used as an extension 4761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to the InterPacketGap1 Register. Specifically it contributes to the 4771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * timing of the RX-to-TX IPG. This value is ignored and presumed to 4781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit 4791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is cleared in the TX MAC Configuration Register. 4801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This value in this register in terms of media byte time. 4821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x00 4841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* InterPacketGap1 Register. This 8-bit value defines the first 2/3 4871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * portion of the Inter Packet Gap. 4881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This value in this register in terms of media byte time. 4901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x08 4921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* InterPacketGap2 Register. This 8-bit value defines the second 1/3 4951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * portion of the Inter Packet Gap. 4961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This value in this register in terms of media byte time. 4981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x04 5001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Slot Time Register. This 10-bit value specifies the slot time 5031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * parameter in units of media byte time. It determines the physical 5041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * span of the network. 5051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x40 5071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Minimum Frame Size Register. This 10-bit register specifies the 5101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * smallest sized frame the TXMAC will send onto the medium, and the 5111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * RXMAC will receive from the medium. 5121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x40 5141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Maximum Frame and Burst Size Register. 5171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This register specifies two things. First it specifies the maximum 5191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * sized frame the TXMAC will send and the RXMAC will recognize as 5201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * valid. Second, it specifies the maximum run length of a burst of 5211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * packets sent in half-duplex gigabit modes. 5221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x200005ee 5241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MAXFSZ_MFS 0x00007fff /* Max Frame Size */ 5261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAC_MAXFSZ_MBS 0x7fff0000 /* Max Burst Size */ 5271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PA Size Register. This 10-bit register specifies the number of preamble 5291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * bytes which will be transmitted at the beginning of each frame. A 5301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * value of two or greater should be programmed here. 5311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x07 5331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Jam Size Register. This 4-bit register specifies the duration of 5361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the jam in units of media byte time. 5371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x04 5391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Attempts Limit Register. This 8-bit register specifies the number 5421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * of attempts that the TXMAC will make to transmit a frame, before it 5431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * resets its Attempts Counter. After reaching the Attempts Limit the 5441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * TXMAC may or may not drop the frame, as determined by the NGU 5451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC 5461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Configuration Register. 5471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x10 5491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MAX Control Type Register. This 16-bit register specifies the 5521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * "type" field of a MAC Control frame. The TXMAC uses this field to 5531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * encapsulate the MAC Control frame for transmission, and the RXMAC 5541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * uses it for decoding valid MAC Control frames received from the 5551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * network. 5561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Recommended value: 0x8808 5581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MAC Address Registers. Each of these registers specify the 5611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ethernet MAC of the interface, 16-bits at a time. Register 5621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 0 specifies bits [47:32], register 1 bits [31:16], and register 5631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2 bits [15:0]. 5641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Registers 3 through and including 5 specify an alternate 5661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MAC address for the interface. 5671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Registers 6 through and including 8 specify the MAC Control 5691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Address, which must be the reserved multicast address for MAC 5701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Control frames. 5711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Example: To program primary station address a:b:c:d:e:f into 5731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the chip. 5741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MAC_Address_2 = (a << 8) | b 5751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MAC_Address_1 = (c << 8) | d 5761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MAC_Address_0 = (e << 8) | f 5771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Address Filter Registers. Registers 0 through 2 specify bit 5801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * fields [47:32] through [15:0], respectively, of the address 5811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * filter. The Address Filter 2&1 Mask Register denotes the 8-bit 5821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * nibble mask for Address Filter Registers 2 and 1. The Address 5831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Filter 0 Mask Register denotes the 16-bit mask for the Address 5841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Filter Register 0. 5851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Hash Table Registers. Registers 0 through 15 specify bit fields 5881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * [255:240] through [15:0], respectively, of the hash table. 5891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Statistics Registers. All of these registers are 16-bits and 5921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * track occurrences of a specific event. GEM can be configured 5931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to interrupt the host cpu when any of these counters overflow. 5941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * They should all be explicitly initialized to zero when the interface 5951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is brought up. 5961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Random Number Seed Register. This 10-bit value is used as the 5991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * RNG seed inside GEM for the CSMA/CD backoff algorithm. It is 6001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * recommended to program this register to the 10 LSB of the 6011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * interfaces MAC address. 6021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Pause Timer, read-only. This 16-bit timer is used to time the pause 6051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * interval as indicated by a received pause flow control frame. 6061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * A non-zero value in this timer indicates that the MAC is currently in 6071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the paused state. 6081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MIF Registers */ 6111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */ 6121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */ 6131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */ 6141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_FRAME 0x620CUL /* MIF Frame/Output Register */ 6151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_CFG 0x6210UL /* MIF Configuration Register */ 6161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_MASK 0x6214UL /* MIF Mask Register */ 6171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_STATUS 0x6218UL /* MIF Status Register */ 6181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_SMACHINE 0x621CUL /* MIF State Machine Register */ 6191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MIF Bit-Bang Clock. This 1-bit register is used to generate the 6211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MDC clock waveform on the MII Management Interface when the MIF is 6221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into 6231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * this register will create a rising edge on the MDC, while writing 6241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * a '0' after a '1' will create a falling edge. For every bit that 6251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is transferred on the management interface, both edges have to be 6261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * generated. 6271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MIF Bit-Bang Data. This 1-bit register is used to generate the 6301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * outgoing data (MDO) on the MII Management Interface when the MIF 6311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is programmed in the "Bit-Bang" mode. The daa will be steered to the 6321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * appropriate MDIO based on the state of the PHY_Select bit in the MIF 6331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Configuration Register. 6341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MIF Big-Band Output Enable. THis 1-bit register is used to enable 6371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ('1') or disable ('0') the I-directional driver on the MII when the 6381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled 6391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * when data bits are transferred from the MIF to the transceiver, and it 6401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * should be disabled when the interface is idle or when data bits are 6411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * transferred from the transceiver to the MIF (data portion of a read 6421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * instruction). Only one MDIO will be enabled at a given time, depending 6431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * on the state of the PHY_Select bit in the MIF Configuration Register. 6441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MIF Configuration Register. This 15-bit register controls the operation 6471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * of the MIF. 6481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_CFG_PSELECT 0x00000001 /* Xcvr slct: 0=mdio0 1=mdio1 */ 6501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */ 6511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */ 6521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */ 6531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */ 6541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */ 6551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */ 6561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MIF Frame/Output Register. This 32-bit register allows the host to 6581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * communicate with a transceiver in frame mode (as opposed to big-bang 6591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * mode). Writes by the host specify an instrution. After being issued 6601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the host must poll this register for completion. Also, after 6611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * completion this register holds the data returned by the transceiver 6621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * if applicable. 6631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_FRAME_ST 0xc0000000 /* STart of frame */ 6651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_FRAME_OP 0x30000000 /* OPcode */ 6661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */ 6671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */ 6681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_FRAME_TAMSB 0x00020000 /* Turn Around MSB */ 6691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */ 6701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */ 6711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MIF Status Register. This register reports status when the MIF is 6731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * operating in the poll mode. The poll status field is auto-clearing 6741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * on read. 6751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_STATUS_DATA 0xffff0000 /* Live image of XCVR reg */ 6771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */ 6781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MIF Mask Register. This 16-bit register is used when in poll mode 6801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to say which bits of the polled register will cause an interrupt 6811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * when changed. 6821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCS/Serialink Registers */ 6851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */ 6861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */ 6871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */ 6881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */ 6891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_CFG 0x9010UL /* PCS Configuration Register */ 6901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */ 6911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */ 6921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_DMODE 0x9050UL /* Datapath Mode Register */ 6931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL 0x9054UL /* Serialink Control Register */ 6941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SOS 0x9058UL /* Shared Output Select Reg */ 6951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SSTATE 0x905CUL /* Serialink State Register */ 6961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCD MII Control Register. */ 6981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_SPD 0x00000040 /* Read as one, writes ignored */ 6991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_CT 0x00000080 /* Force COL signal active */ 7001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */ 7011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */ 7021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_ISO 0x00000400 /* Read as zero, writes ignored */ 7031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_PD 0x00000800 /* Read as zero, writes ignored */ 7041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */ 7051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_SS 0x00002000 /* Read as zero, writes ignored */ 7061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit 7071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * input side of Serialink 7081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 7091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */ 7101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCS MII Status Register. */ 7121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIISTAT_EC 0x00000001 /* Ext Capability: Read as zero */ 7131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIISTAT_JD 0x00000002 /* Jabber Detect: Read as zero */ 7141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIISTAT_LS 0x00000004 /* Link Status: 1=up 0=down */ 7151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */ 7161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIISTAT_RF 0x00000010 /* Remote Fault */ 7171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */ 7181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIISTAT_ES 0x00000100 /* Extended Status, always 1 */ 7191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCS MII Advertisement Register. */ 7211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIIADV_FD 0x00000020 /* Advertise Full Duplex */ 7221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIIADV_HD 0x00000040 /* Advertise Half Duplex */ 7231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIIADV_SP 0x00000080 /* Advertise Symmetric Pause */ 7241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIIADV_AP 0x00000100 /* Advertise Asymmetric Pause */ 7251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIIADV_RF 0x00003000 /* Remote Fault */ 7261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIIADV_ACK 0x00004000 /* Read-only */ 7271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */ 7281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCS MII Link Partner Ability Register. This register is equivalent 7301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to the Link Partnet Ability Register of the standard MII register set. 7311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * It's layout corresponds to the PCS MII Advertisement Register. 7321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 7331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCS Configuration Register. */ 7351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_CFG_ENABLE 0x00000001 /* Must be zero while changing 7361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PCS MII advertisement reg. 7371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 7381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_CFG_SDO 0x00000002 /* Signal detect override */ 7391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_CFG_SDL 0x00000004 /* Signal detect active low */ 7401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_CFG_JS 0x00000018 /* Jitter-study: 7411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 0 = normal operation 7421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1 = high-frequency test pattern 7431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2 = low-frequency test pattern 7441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3 = reserved 7451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 7461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */ 7471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCS Interrupt Status Register. This register is self-clearing 7491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * when read. 7501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 7511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_ISTAT_LSC 0x00000004 /* Link Status Change */ 7521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Datapath Mode Register. */ 7541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_DMODE_SM 0x00000001 /* 1 = use internal Serialink */ 7551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_DMODE_ESM 0x00000002 /* External SERDES mode */ 7561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */ 7571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */ 7581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Serialink Control Register. 7601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 7611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * NOTE: When in SERDES mode, the loopback bit has inverse logic. 7621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 7631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */ 7641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */ 7651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_LOCK 0x00000004 /* Lock to reference clock */ 7661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_EMP 0x00000018 /* Output driver emphasis */ 7671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_STEST 0x000001c0 /* Self test patterns */ 7681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */ 7691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_RXZ 0x00000c00 /* PLL input to Serialink */ 7701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_RXP 0x00003000 /* PLL input to Serialink */ 7711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_TXZ 0x0000c000 /* PLL input to Serialink */ 7721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SCTRL_TXP 0x00030000 /* PLL input to Serialink */ 7731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Shared Output Select Register. For test and debug, allows multiplexing 7751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * test outputs into the PROM address pins. Set to zero for normal 7761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * operation. 7771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 7781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCS_SOS_PADDR 0x00000003 /* PROM Address */ 7791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PROM Image Space */ 7811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PROM_START 0x100000UL /* Expansion ROM run time access*/ 7821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PROM_SIZE 0x0fffffUL /* Size of ROM */ 7831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PROM_END 0x200000UL /* End of ROM */ 7841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MII definitions missing from mii.h */ 7861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */ 7881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LPA_PAUSE 0x0400 7891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* More PHY registers (specific to Broadcom models) */ 7911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MII BCM5201 MULTIPHY interrupt register */ 7931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5201_INTERRUPT 0x1A 7941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5201_INTERRUPT_INTENABLE 0x4000 7951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5201_AUXMODE2 0x1B 7971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008 7981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5201_MULTIPHY 0x1E 8001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MII BCM5201 MULTIPHY register bits */ 8021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002 8031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008 8041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MII BCM5400 1000-BASET Control register */ 8061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5400_GB_CONTROL 0x09 8071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200 8081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MII BCM5400 AUXCONTROL register */ 8101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5400_AUXCONTROL 0x18 8111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004 8121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* MII BCM5400 AUXSTATUS register */ 8141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5400_AUXSTATUS 0x19 8151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700 8166aa20a2235535605db6d6d2bd850298b2fe7f31eJeff Garzik#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 8171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* When it can, GEM internally caches 4 aligned TX descriptors 8191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * at a time, so that it can use full cacheline DMA reads. 8201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 8211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note that unlike HME, there is no ownership bit in the descriptor 8221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * control word. The same functionality is obtained via the TX-Kick 8231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * and TX-Complete registers. As a result, GEM need not write back 8241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * updated values to the TX descriptor ring, it only performs reads. 8251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 8261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Since TX descriptors are never modified by GEM, the driver can 8271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * use the buffer DMA address as a place to keep track of allocated 8281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * DMA mappings for a transmitted packet. 8291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 8301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct gem_txd { 831439104b3a39b2f576daa229d783eb2cefac8b7dfAl Viro __le64 control_word; 832439104b3a39b2f576daa229d783eb2cefac8b7dfAl Viro __le64 buffer; 8331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 8341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */ 8361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */ 8371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */ 8381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */ 8391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */ 8401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */ 8411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */ 8421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDCTRL_NOCRC 0x0000000200000000ULL /* No CRC Present */ 8431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* GEM requires that RX descriptors are provided four at a time, 8451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * aligned. Also, the RX ring may not wrap around. This means that 8465a3a7658863f74f28cef53b9336bff7423659801Justin P. Mattock * there will be at least 4 unused descriptor entries in the middle 8471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * of the RX ring at all times. 8481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 8491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Similar to HME, GEM assumes that it can write garbage bytes before 8501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the beginning of the buffer and right after the end in order to DMA 8511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * whole cachelines. 8521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 8531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Unlike for TX, GEM does update the status word in the RX descriptors 8541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * when packets arrive. Therefore an ownership bit does exist in the 8551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * RX descriptors. It is advisory, GEM clears it but does not check 8561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it in any way. So when buffers are posted to the RX ring (via the 8571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * RX Kick register) by the driver it must make sure the buffers are 8581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * truly ready and that the ownership bits are set properly. 8591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 8601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Even though GEM modifies the RX descriptors, it guarantees that the 8611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * buffer DMA address field will stay the same when it performs these 8621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * updates. Therefore it can be used to keep track of DMA mappings 8631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * by the host driver just as in the TX descriptor case above. 8641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 8651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct gem_rxd { 866439104b3a39b2f576daa229d783eb2cefac8b7dfAl Viro __le64 status_word; 867439104b3a39b2f576daa229d783eb2cefac8b7dfAl Viro __le64 buffer; 8681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 8691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */ 8711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDCTRL_BUFSZ 0x000000007fff0000ULL /* Buffer Size */ 8721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDCTRL_OWN 0x0000000080000000ULL /* GEM owns this entry */ 8731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDCTRL_HASHVAL 0x0ffff00000000000ULL /* Hash Value */ 8741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */ 8751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */ 8761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDCTRL_BAD 0x4000000000000000ULL /* Frame has bad CRC */ 8771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDCTRL_FRESH(gp) \ 8791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \ 8801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds RXDCTRL_OWN) 8811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TX_RING_SIZE 128 8831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_RING_SIZE 128 8841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if TX_RING_SIZE == 32 8861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_32 8871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif TX_RING_SIZE == 64 8881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_64 8891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif TX_RING_SIZE == 128 8901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_128 8911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif TX_RING_SIZE == 256 8921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_256 8931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif TX_RING_SIZE == 512 8941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_512 8951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif TX_RING_SIZE == 1024 8961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_1K 8971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif TX_RING_SIZE == 2048 8981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_2K 8991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif TX_RING_SIZE == 4096 9001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_4K 9011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif TX_RING_SIZE == 8192 9021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_8K 9031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 9041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#error TX_RING_SIZE value is illegal... 9051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 9061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if RX_RING_SIZE == 32 9081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_32 9091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif RX_RING_SIZE == 64 9101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_64 9111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif RX_RING_SIZE == 128 9121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_128 9131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif RX_RING_SIZE == 256 9141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_256 9151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif RX_RING_SIZE == 512 9161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_512 9171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif RX_RING_SIZE == 1024 9181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_1K 9191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif RX_RING_SIZE == 2048 9201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_2K 9211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif RX_RING_SIZE == 4096 9221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_4K 9231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif RX_RING_SIZE == 8192 9241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_8K 9251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 9261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#error RX_RING_SIZE is illegal... 9271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 9281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1)) 9301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1)) 9311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TX_BUFFS_AVAIL(GP) \ 9331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (((GP)->tx_old <= (GP)->tx_new) ? \ 9341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \ 9351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (GP)->tx_old - (GP)->tx_new - 1) 9361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_OFFSET 2 9381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64) 9391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RX_COPY_THRESHOLD 256 9411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if TX_RING_SIZE < 128 9431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define INIT_BLOCK_TX_RING_SIZE 128 9441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 9451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define INIT_BLOCK_TX_RING_SIZE TX_RING_SIZE 9461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 9471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if RX_RING_SIZE < 128 9491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define INIT_BLOCK_RX_RING_SIZE 128 9501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 9511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define INIT_BLOCK_RX_RING_SIZE RX_RING_SIZE 9521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 9531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct gem_init_block { 9551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct gem_txd txd[INIT_BLOCK_TX_RING_SIZE]; 9561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct gem_rxd rxd[INIT_BLOCK_RX_RING_SIZE]; 9571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 9581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsenum gem_phy_type { 9601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds phy_mii_mdio0, 9611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds phy_mii_mdio1, 9621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds phy_serialink, 9631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds phy_serdes, 9641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 9651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsenum link_state { 9671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds link_down = 0, /* No link, will retry */ 9681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds link_aneg, /* Autoneg in progress */ 9691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds link_force_try, /* Try Forced link speed */ 9701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds link_force_ret, /* Forced mode worked, retrying autoneg */ 9711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds link_force_ok, /* Stay in forced mode */ 9721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds link_up /* Link is up */ 9731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 9741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct gem { 9761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds void __iomem *regs; 9771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int rx_new, rx_old; 9781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int tx_new, tx_old; 9791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int has_wol : 1; /* chip supports wake-on-lan */ 9811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int asleep_wol : 1; /* was asleep with WOL enabled */ 9826aa20a2235535605db6d6d2bd850298b2fe7f31eJeff Garzik 9836aa20a2235535605db6d6d2bd850298b2fe7f31eJeff Garzik int cell_enabled; 9841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 msg_enable; 9851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 status; 9861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 987bea3348eef27e6044b6161fd04c3152215f96411Stephen Hemminger struct napi_struct napi; 9881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int tx_fifo_sz; 9901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int rx_fifo_sz; 9911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int rx_pause_off; 9921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int rx_pause_on; 9931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int rx_buf_sz; 9941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u64 pause_entered; 9951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u16 pause_last_time_recvd; 9961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 mac_rx_cfg; 9971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 swrst_base; 9981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int want_autoneg; 10001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int last_forced_speed; 10011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds enum link_state lstate; 10021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct timer_list link_timer; 10031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int timer_ticks; 10041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int wake_on_lan; 10051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct work_struct reset_task; 10061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds volatile int reset_task_pending; 10071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds enum gem_phy_type phy_type; 10091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct mii_phy phy_mii; 10101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int mii_phy_addr; 10116aa20a2235535605db6d6d2bd850298b2fe7f31eJeff Garzik 10121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct gem_init_block *init_block; 10131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct sk_buff *rx_skbs[RX_RING_SIZE]; 10140014c6156f9e7d034d20742d164d7d4da289b42aGeoff Levand struct sk_buff *tx_skbs[TX_RING_SIZE]; 10151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t gblock_dvma; 10161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *pdev; 10181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct net_device *dev; 1019457e1a8afbcf5deffa501f2e9829526c18ed55b5David S. Miller#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC) 10201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct device_node *of_node; 10211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 10221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 10231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10248e95a2026f3b43f7c3d676adaccd2de9532e8dccJoe Perches#define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) && \ 10258e95a2026f3b43f7c3d676adaccd2de9532e8dccJoe Perches gp->phy_mii.def && gp->phy_mii.def->ops) 10266aa20a2235535605db6d6d2bd850298b2fe7f31eJeff Garzik 10271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* _SUNGEM_H */ 1028