cpsw.c revision 9232b16df2167c8afcb89de39ee85f5091ebacff
1/* 2 * Texas Instruments Ethernet Switch Driver 3 * 4 * Copyright (C) 2012 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#include <linux/kernel.h> 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/timer.h> 20#include <linux/module.h> 21#include <linux/platform_device.h> 22#include <linux/irqreturn.h> 23#include <linux/interrupt.h> 24#include <linux/if_ether.h> 25#include <linux/etherdevice.h> 26#include <linux/netdevice.h> 27#include <linux/net_tstamp.h> 28#include <linux/phy.h> 29#include <linux/workqueue.h> 30#include <linux/delay.h> 31#include <linux/pm_runtime.h> 32#include <linux/of.h> 33#include <linux/of_net.h> 34#include <linux/of_device.h> 35#include <linux/if_vlan.h> 36 37#include <linux/platform_data/cpsw.h> 38 39#include "cpsw_ale.h" 40#include "cpts.h" 41#include "davinci_cpdma.h" 42 43#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 44 NETIF_MSG_DRV | NETIF_MSG_LINK | \ 45 NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 46 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 47 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 48 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 49 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 50 NETIF_MSG_RX_STATUS) 51 52#define cpsw_info(priv, type, format, ...) \ 53do { \ 54 if (netif_msg_##type(priv) && net_ratelimit()) \ 55 dev_info(priv->dev, format, ## __VA_ARGS__); \ 56} while (0) 57 58#define cpsw_err(priv, type, format, ...) \ 59do { \ 60 if (netif_msg_##type(priv) && net_ratelimit()) \ 61 dev_err(priv->dev, format, ## __VA_ARGS__); \ 62} while (0) 63 64#define cpsw_dbg(priv, type, format, ...) \ 65do { \ 66 if (netif_msg_##type(priv) && net_ratelimit()) \ 67 dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 68} while (0) 69 70#define cpsw_notice(priv, type, format, ...) \ 71do { \ 72 if (netif_msg_##type(priv) && net_ratelimit()) \ 73 dev_notice(priv->dev, format, ## __VA_ARGS__); \ 74} while (0) 75 76#define ALE_ALL_PORTS 0x7 77 78#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 79#define CPSW_MINOR_VERSION(reg) (reg & 0xff) 80#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 81 82#define CPSW_VERSION_1 0x19010a 83#define CPSW_VERSION_2 0x19010c 84 85#define HOST_PORT_NUM 0 86#define SLIVER_SIZE 0x40 87 88#define CPSW1_HOST_PORT_OFFSET 0x028 89#define CPSW1_SLAVE_OFFSET 0x050 90#define CPSW1_SLAVE_SIZE 0x040 91#define CPSW1_CPDMA_OFFSET 0x100 92#define CPSW1_STATERAM_OFFSET 0x200 93#define CPSW1_CPTS_OFFSET 0x500 94#define CPSW1_ALE_OFFSET 0x600 95#define CPSW1_SLIVER_OFFSET 0x700 96 97#define CPSW2_HOST_PORT_OFFSET 0x108 98#define CPSW2_SLAVE_OFFSET 0x200 99#define CPSW2_SLAVE_SIZE 0x100 100#define CPSW2_CPDMA_OFFSET 0x800 101#define CPSW2_STATERAM_OFFSET 0xa00 102#define CPSW2_CPTS_OFFSET 0xc00 103#define CPSW2_ALE_OFFSET 0xd00 104#define CPSW2_SLIVER_OFFSET 0xd80 105#define CPSW2_BD_OFFSET 0x2000 106 107#define CPDMA_RXTHRESH 0x0c0 108#define CPDMA_RXFREE 0x0e0 109#define CPDMA_TXHDP 0x00 110#define CPDMA_RXHDP 0x20 111#define CPDMA_TXCP 0x40 112#define CPDMA_RXCP 0x60 113 114#define CPSW_POLL_WEIGHT 64 115#define CPSW_MIN_PACKET_SIZE 60 116#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 117 118#define RX_PRIORITY_MAPPING 0x76543210 119#define TX_PRIORITY_MAPPING 0x33221100 120#define CPDMA_TX_PRIORITY_MAP 0x76543210 121 122#define CPSW_VLAN_AWARE BIT(1) 123#define CPSW_ALE_VLAN_AWARE 1 124 125#define cpsw_enable_irq(priv) \ 126 do { \ 127 u32 i; \ 128 for (i = 0; i < priv->num_irqs; i++) \ 129 enable_irq(priv->irqs_table[i]); \ 130 } while (0); 131#define cpsw_disable_irq(priv) \ 132 do { \ 133 u32 i; \ 134 for (i = 0; i < priv->num_irqs; i++) \ 135 disable_irq_nosync(priv->irqs_table[i]); \ 136 } while (0); 137 138static int debug_level; 139module_param(debug_level, int, 0); 140MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 141 142static int ale_ageout = 10; 143module_param(ale_ageout, int, 0); 144MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 145 146static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 147module_param(rx_packet_max, int, 0); 148MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 149 150struct cpsw_wr_regs { 151 u32 id_ver; 152 u32 soft_reset; 153 u32 control; 154 u32 int_control; 155 u32 rx_thresh_en; 156 u32 rx_en; 157 u32 tx_en; 158 u32 misc_en; 159}; 160 161struct cpsw_ss_regs { 162 u32 id_ver; 163 u32 control; 164 u32 soft_reset; 165 u32 stat_port_en; 166 u32 ptype; 167 u32 soft_idle; 168 u32 thru_rate; 169 u32 gap_thresh; 170 u32 tx_start_wds; 171 u32 flow_control; 172 u32 vlan_ltype; 173 u32 ts_ltype; 174 u32 dlr_ltype; 175}; 176 177/* CPSW_PORT_V1 */ 178#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 179#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 180#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 181#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 182#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 183#define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 184#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 185#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 186 187/* CPSW_PORT_V2 */ 188#define CPSW2_CONTROL 0x00 /* Control Register */ 189#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 190#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 191#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 192#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 193#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 194#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 195 196/* CPSW_PORT_V1 and V2 */ 197#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 198#define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 199#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 200 201/* CPSW_PORT_V2 only */ 202#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 203#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 204#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 205#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 206#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 207#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 208#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 209#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 210 211/* Bit definitions for the CPSW2_CONTROL register */ 212#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 213#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 214#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 215#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 216#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 217#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 218#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 219#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 220#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 221#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 222#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 223#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 224#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 225#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 226#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 227#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 228 229#define CTRL_TS_BITS \ 230 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 231 TS_ANNEX_D_EN | TS_LTYPE1_EN) 232 233#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 234#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 235#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 236 237/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 238#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 239#define TS_SEQ_ID_OFFSET_MASK (0x3f) 240#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 241#define TS_MSG_TYPE_EN_MASK (0xffff) 242 243/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 244#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 245 246/* Bit definitions for the CPSW1_TS_CTL register */ 247#define CPSW_V1_TS_RX_EN BIT(0) 248#define CPSW_V1_TS_TX_EN BIT(4) 249#define CPSW_V1_MSG_TYPE_OFS 16 250 251/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 252#define CPSW_V1_SEQ_ID_OFS_SHIFT 16 253 254struct cpsw_host_regs { 255 u32 max_blks; 256 u32 blk_cnt; 257 u32 flow_thresh; 258 u32 port_vlan; 259 u32 tx_pri_map; 260 u32 cpdma_tx_pri_map; 261 u32 cpdma_rx_chan_map; 262}; 263 264struct cpsw_sliver_regs { 265 u32 id_ver; 266 u32 mac_control; 267 u32 mac_status; 268 u32 soft_reset; 269 u32 rx_maxlen; 270 u32 __reserved_0; 271 u32 rx_pause; 272 u32 tx_pause; 273 u32 __reserved_1; 274 u32 rx_pri_map; 275}; 276 277struct cpsw_slave { 278 void __iomem *regs; 279 struct cpsw_sliver_regs __iomem *sliver; 280 int slave_num; 281 u32 mac_control; 282 struct cpsw_slave_data *data; 283 struct phy_device *phy; 284}; 285 286static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 287{ 288 return __raw_readl(slave->regs + offset); 289} 290 291static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 292{ 293 __raw_writel(val, slave->regs + offset); 294} 295 296struct cpsw_priv { 297 spinlock_t lock; 298 struct platform_device *pdev; 299 struct net_device *ndev; 300 struct resource *cpsw_res; 301 struct resource *cpsw_wr_res; 302 struct napi_struct napi; 303 struct device *dev; 304 struct cpsw_platform_data data; 305 struct cpsw_ss_regs __iomem *regs; 306 struct cpsw_wr_regs __iomem *wr_regs; 307 struct cpsw_host_regs __iomem *host_port_regs; 308 u32 msg_enable; 309 u32 version; 310 struct net_device_stats stats; 311 int rx_packet_max; 312 int host_port; 313 struct clk *clk; 314 u8 mac_addr[ETH_ALEN]; 315 struct cpsw_slave *slaves; 316 struct cpdma_ctlr *dma; 317 struct cpdma_chan *txch, *rxch; 318 struct cpsw_ale *ale; 319 /* snapshot of IRQ numbers */ 320 u32 irqs_table[4]; 321 u32 num_irqs; 322 struct cpts *cpts; 323}; 324 325#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 326#define for_each_slave(priv, func, arg...) \ 327 do { \ 328 int idx; \ 329 for (idx = 0; idx < (priv)->data.slaves; idx++) \ 330 (func)((priv)->slaves + idx, ##arg); \ 331 } while (0) 332 333static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 334{ 335 struct cpsw_priv *priv = netdev_priv(ndev); 336 337 if (ndev->flags & IFF_PROMISC) { 338 /* Enable promiscuous mode */ 339 dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 340 return; 341 } 342 343 /* Clear all mcast from ALE */ 344 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 345 346 if (!netdev_mc_empty(ndev)) { 347 struct netdev_hw_addr *ha; 348 349 /* program multicast address list into ALE register */ 350 netdev_for_each_mc_addr(ha, ndev) { 351 cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr, 352 ALE_ALL_PORTS << priv->host_port, 0, 0, 0); 353 } 354 } 355} 356 357static void cpsw_intr_enable(struct cpsw_priv *priv) 358{ 359 __raw_writel(0xFF, &priv->wr_regs->tx_en); 360 __raw_writel(0xFF, &priv->wr_regs->rx_en); 361 362 cpdma_ctlr_int_ctrl(priv->dma, true); 363 return; 364} 365 366static void cpsw_intr_disable(struct cpsw_priv *priv) 367{ 368 __raw_writel(0, &priv->wr_regs->tx_en); 369 __raw_writel(0, &priv->wr_regs->rx_en); 370 371 cpdma_ctlr_int_ctrl(priv->dma, false); 372 return; 373} 374 375void cpsw_tx_handler(void *token, int len, int status) 376{ 377 struct sk_buff *skb = token; 378 struct net_device *ndev = skb->dev; 379 struct cpsw_priv *priv = netdev_priv(ndev); 380 381 /* Check whether the queue is stopped due to stalled tx dma, if the 382 * queue is stopped then start the queue as we have free desc for tx 383 */ 384 if (unlikely(netif_queue_stopped(ndev))) 385 netif_start_queue(ndev); 386 cpts_tx_timestamp(priv->cpts, skb); 387 priv->stats.tx_packets++; 388 priv->stats.tx_bytes += len; 389 dev_kfree_skb_any(skb); 390} 391 392void cpsw_rx_handler(void *token, int len, int status) 393{ 394 struct sk_buff *skb = token; 395 struct net_device *ndev = skb->dev; 396 struct cpsw_priv *priv = netdev_priv(ndev); 397 int ret = 0; 398 399 /* free and bail if we are shutting down */ 400 if (unlikely(!netif_running(ndev)) || 401 unlikely(!netif_carrier_ok(ndev))) { 402 dev_kfree_skb_any(skb); 403 return; 404 } 405 if (likely(status >= 0)) { 406 skb_put(skb, len); 407 cpts_rx_timestamp(priv->cpts, skb); 408 skb->protocol = eth_type_trans(skb, ndev); 409 netif_receive_skb(skb); 410 priv->stats.rx_bytes += len; 411 priv->stats.rx_packets++; 412 skb = NULL; 413 } 414 415 if (unlikely(!netif_running(ndev))) { 416 if (skb) 417 dev_kfree_skb_any(skb); 418 return; 419 } 420 421 if (likely(!skb)) { 422 skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 423 if (WARN_ON(!skb)) 424 return; 425 426 ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 427 skb_tailroom(skb), 0, GFP_KERNEL); 428 } 429 WARN_ON(ret < 0); 430} 431 432static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 433{ 434 struct cpsw_priv *priv = dev_id; 435 436 if (likely(netif_running(priv->ndev))) { 437 cpsw_intr_disable(priv); 438 cpsw_disable_irq(priv); 439 napi_schedule(&priv->napi); 440 } 441 return IRQ_HANDLED; 442} 443 444static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 445{ 446 if (priv->host_port == 0) 447 return slave_num + 1; 448 else 449 return slave_num; 450} 451 452static int cpsw_poll(struct napi_struct *napi, int budget) 453{ 454 struct cpsw_priv *priv = napi_to_priv(napi); 455 int num_tx, num_rx; 456 457 num_tx = cpdma_chan_process(priv->txch, 128); 458 num_rx = cpdma_chan_process(priv->rxch, budget); 459 460 if (num_rx || num_tx) 461 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 462 num_rx, num_tx); 463 464 if (num_rx < budget) { 465 napi_complete(napi); 466 cpsw_intr_enable(priv); 467 cpdma_ctlr_eoi(priv->dma); 468 cpsw_enable_irq(priv); 469 } 470 471 return num_rx; 472} 473 474static inline void soft_reset(const char *module, void __iomem *reg) 475{ 476 unsigned long timeout = jiffies + HZ; 477 478 __raw_writel(1, reg); 479 do { 480 cpu_relax(); 481 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 482 483 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 484} 485 486#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 487 ((mac)[2] << 16) | ((mac)[3] << 24)) 488#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 489 490static void cpsw_set_slave_mac(struct cpsw_slave *slave, 491 struct cpsw_priv *priv) 492{ 493 slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 494 slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 495} 496 497static void _cpsw_adjust_link(struct cpsw_slave *slave, 498 struct cpsw_priv *priv, bool *link) 499{ 500 struct phy_device *phy = slave->phy; 501 u32 mac_control = 0; 502 u32 slave_port; 503 504 if (!phy) 505 return; 506 507 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 508 509 if (phy->link) { 510 mac_control = priv->data.mac_control; 511 512 /* enable forwarding */ 513 cpsw_ale_control_set(priv->ale, slave_port, 514 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 515 516 if (phy->speed == 1000) 517 mac_control |= BIT(7); /* GIGABITEN */ 518 if (phy->duplex) 519 mac_control |= BIT(0); /* FULLDUPLEXEN */ 520 521 /* set speed_in input in case RMII mode is used in 100Mbps */ 522 if (phy->speed == 100) 523 mac_control |= BIT(15); 524 525 *link = true; 526 } else { 527 mac_control = 0; 528 /* disable forwarding */ 529 cpsw_ale_control_set(priv->ale, slave_port, 530 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 531 } 532 533 if (mac_control != slave->mac_control) { 534 phy_print_status(phy); 535 __raw_writel(mac_control, &slave->sliver->mac_control); 536 } 537 538 slave->mac_control = mac_control; 539} 540 541static void cpsw_adjust_link(struct net_device *ndev) 542{ 543 struct cpsw_priv *priv = netdev_priv(ndev); 544 bool link = false; 545 546 for_each_slave(priv, _cpsw_adjust_link, priv, &link); 547 548 if (link) { 549 netif_carrier_on(ndev); 550 if (netif_running(ndev)) 551 netif_wake_queue(ndev); 552 } else { 553 netif_carrier_off(ndev); 554 netif_stop_queue(ndev); 555 } 556} 557 558static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 559{ 560 static char *leader = "........................................"; 561 562 if (!val) 563 return 0; 564 else 565 return snprintf(buf, maxlen, "%s %s %10d\n", name, 566 leader + strlen(name), val); 567} 568 569static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 570{ 571 char name[32]; 572 u32 slave_port; 573 574 sprintf(name, "slave-%d", slave->slave_num); 575 576 soft_reset(name, &slave->sliver->soft_reset); 577 578 /* setup priority mapping */ 579 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 580 581 switch (priv->version) { 582 case CPSW_VERSION_1: 583 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 584 break; 585 case CPSW_VERSION_2: 586 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 587 break; 588 } 589 590 /* setup max packet size, and mac address */ 591 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 592 cpsw_set_slave_mac(slave, priv); 593 594 slave->mac_control = 0; /* no link yet */ 595 596 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 597 598 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 599 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 600 601 slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 602 &cpsw_adjust_link, slave->data->phy_if); 603 if (IS_ERR(slave->phy)) { 604 dev_err(priv->dev, "phy %s not found on slave %d\n", 605 slave->data->phy_id, slave->slave_num); 606 slave->phy = NULL; 607 } else { 608 dev_info(priv->dev, "phy found : id is : 0x%x\n", 609 slave->phy->phy_id); 610 phy_start(slave->phy); 611 } 612} 613 614static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 615{ 616 const int vlan = priv->data.default_vlan; 617 const int port = priv->host_port; 618 u32 reg; 619 int i; 620 621 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 622 CPSW2_PORT_VLAN; 623 624 writel(vlan, &priv->host_port_regs->port_vlan); 625 626 for (i = 0; i < 2; i++) 627 slave_write(priv->slaves + i, vlan, reg); 628 629 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 630 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 631 (ALE_PORT_1 | ALE_PORT_2) << port); 632} 633 634static void cpsw_init_host_port(struct cpsw_priv *priv) 635{ 636 u32 control_reg; 637 638 /* soft reset the controller and initialize ale */ 639 soft_reset("cpsw", &priv->regs->soft_reset); 640 cpsw_ale_start(priv->ale); 641 642 /* switch to vlan unaware mode */ 643 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 644 CPSW_ALE_VLAN_AWARE); 645 control_reg = readl(&priv->regs->control); 646 control_reg |= CPSW_VLAN_AWARE; 647 writel(control_reg, &priv->regs->control); 648 649 /* setup host port priority mapping */ 650 __raw_writel(CPDMA_TX_PRIORITY_MAP, 651 &priv->host_port_regs->cpdma_tx_pri_map); 652 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 653 654 cpsw_ale_control_set(priv->ale, priv->host_port, 655 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 656 657 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0, 0); 658 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 659 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 660} 661 662static int cpsw_ndo_open(struct net_device *ndev) 663{ 664 struct cpsw_priv *priv = netdev_priv(ndev); 665 int i, ret; 666 u32 reg; 667 668 cpsw_intr_disable(priv); 669 netif_carrier_off(ndev); 670 671 pm_runtime_get_sync(&priv->pdev->dev); 672 673 reg = priv->version; 674 675 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 676 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 677 CPSW_RTL_VERSION(reg)); 678 679 /* initialize host and slave ports */ 680 cpsw_init_host_port(priv); 681 for_each_slave(priv, cpsw_slave_open, priv); 682 683 /* Add default VLAN */ 684 cpsw_add_default_vlan(priv); 685 686 /* setup tx dma to fixed prio and zero offset */ 687 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 688 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 689 690 /* disable priority elevation and enable statistics on all ports */ 691 __raw_writel(0, &priv->regs->ptype); 692 693 /* enable statistics collection only on the host port */ 694 __raw_writel(0x7, &priv->regs->stat_port_en); 695 696 if (WARN_ON(!priv->data.rx_descs)) 697 priv->data.rx_descs = 128; 698 699 for (i = 0; i < priv->data.rx_descs; i++) { 700 struct sk_buff *skb; 701 702 ret = -ENOMEM; 703 skb = netdev_alloc_skb_ip_align(priv->ndev, 704 priv->rx_packet_max); 705 if (!skb) 706 break; 707 ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 708 skb_tailroom(skb), 0, GFP_KERNEL); 709 if (WARN_ON(ret < 0)) 710 break; 711 } 712 /* continue even if we didn't manage to submit all receive descs */ 713 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 714 715 cpdma_ctlr_start(priv->dma); 716 cpsw_intr_enable(priv); 717 napi_enable(&priv->napi); 718 cpdma_ctlr_eoi(priv->dma); 719 720 return 0; 721} 722 723static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 724{ 725 if (!slave->phy) 726 return; 727 phy_stop(slave->phy); 728 phy_disconnect(slave->phy); 729 slave->phy = NULL; 730} 731 732static int cpsw_ndo_stop(struct net_device *ndev) 733{ 734 struct cpsw_priv *priv = netdev_priv(ndev); 735 736 cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 737 netif_stop_queue(priv->ndev); 738 napi_disable(&priv->napi); 739 netif_carrier_off(priv->ndev); 740 cpsw_intr_disable(priv); 741 cpdma_ctlr_int_ctrl(priv->dma, false); 742 cpdma_ctlr_stop(priv->dma); 743 cpsw_ale_stop(priv->ale); 744 for_each_slave(priv, cpsw_slave_stop, priv); 745 pm_runtime_put_sync(&priv->pdev->dev); 746 return 0; 747} 748 749static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 750 struct net_device *ndev) 751{ 752 struct cpsw_priv *priv = netdev_priv(ndev); 753 int ret; 754 755 ndev->trans_start = jiffies; 756 757 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 758 cpsw_err(priv, tx_err, "packet pad failed\n"); 759 priv->stats.tx_dropped++; 760 return NETDEV_TX_OK; 761 } 762 763 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 764 priv->cpts->tx_enable) 765 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 766 767 skb_tx_timestamp(skb); 768 769 ret = cpdma_chan_submit(priv->txch, skb, skb->data, 770 skb->len, 0, GFP_KERNEL); 771 if (unlikely(ret != 0)) { 772 cpsw_err(priv, tx_err, "desc submit failed\n"); 773 goto fail; 774 } 775 776 /* If there is no more tx desc left free then we need to 777 * tell the kernel to stop sending us tx frames. 778 */ 779 if (unlikely(cpdma_check_free_tx_desc(priv->txch))) 780 netif_stop_queue(ndev); 781 782 return NETDEV_TX_OK; 783fail: 784 priv->stats.tx_dropped++; 785 netif_stop_queue(ndev); 786 return NETDEV_TX_BUSY; 787} 788 789static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 790{ 791 /* 792 * The switch cannot operate in promiscuous mode without substantial 793 * headache. For promiscuous mode to work, we would need to put the 794 * ALE in bypass mode and route all traffic to the host port. 795 * Subsequently, the host will need to operate as a "bridge", learn, 796 * and flood as needed. For now, we simply complain here and 797 * do nothing about it :-) 798 */ 799 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 800 dev_err(&ndev->dev, "promiscuity ignored!\n"); 801 802 /* 803 * The switch cannot filter multicast traffic unless it is configured 804 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 805 * whole bunch of additional logic that this driver does not implement 806 * at present. 807 */ 808 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 809 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 810} 811 812#ifdef CONFIG_TI_CPTS 813 814static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 815{ 816 struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; 817 u32 ts_en, seq_id; 818 819 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 820 slave_write(slave, 0, CPSW1_TS_CTL); 821 return; 822 } 823 824 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 825 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 826 827 if (priv->cpts->tx_enable) 828 ts_en |= CPSW_V1_TS_TX_EN; 829 830 if (priv->cpts->rx_enable) 831 ts_en |= CPSW_V1_TS_RX_EN; 832 833 slave_write(slave, ts_en, CPSW1_TS_CTL); 834 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 835} 836 837static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 838{ 839 struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; 840 u32 ctrl, mtype; 841 842 ctrl = slave_read(slave, CPSW2_CONTROL); 843 ctrl &= ~CTRL_ALL_TS_MASK; 844 845 if (priv->cpts->tx_enable) 846 ctrl |= CTRL_TX_TS_BITS; 847 848 if (priv->cpts->rx_enable) 849 ctrl |= CTRL_RX_TS_BITS; 850 851 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 852 853 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 854 slave_write(slave, ctrl, CPSW2_CONTROL); 855 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 856} 857 858static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 859{ 860 struct cpsw_priv *priv = netdev_priv(dev); 861 struct cpts *cpts = priv->cpts; 862 struct hwtstamp_config cfg; 863 864 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 865 return -EFAULT; 866 867 /* reserved for future extensions */ 868 if (cfg.flags) 869 return -EINVAL; 870 871 switch (cfg.tx_type) { 872 case HWTSTAMP_TX_OFF: 873 cpts->tx_enable = 0; 874 break; 875 case HWTSTAMP_TX_ON: 876 cpts->tx_enable = 1; 877 break; 878 default: 879 return -ERANGE; 880 } 881 882 switch (cfg.rx_filter) { 883 case HWTSTAMP_FILTER_NONE: 884 cpts->rx_enable = 0; 885 break; 886 case HWTSTAMP_FILTER_ALL: 887 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 888 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 889 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 890 return -ERANGE; 891 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 892 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 893 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 894 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 895 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 896 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 897 case HWTSTAMP_FILTER_PTP_V2_EVENT: 898 case HWTSTAMP_FILTER_PTP_V2_SYNC: 899 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 900 cpts->rx_enable = 1; 901 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 902 break; 903 default: 904 return -ERANGE; 905 } 906 907 switch (priv->version) { 908 case CPSW_VERSION_1: 909 cpsw_hwtstamp_v1(priv); 910 break; 911 case CPSW_VERSION_2: 912 cpsw_hwtstamp_v2(priv); 913 break; 914 default: 915 return -ENOTSUPP; 916 } 917 918 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 919} 920 921#endif /*CONFIG_TI_CPTS*/ 922 923static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 924{ 925 if (!netif_running(dev)) 926 return -EINVAL; 927 928#ifdef CONFIG_TI_CPTS 929 if (cmd == SIOCSHWTSTAMP) 930 return cpsw_hwtstamp_ioctl(dev, req); 931#endif 932 return -ENOTSUPP; 933} 934 935static void cpsw_ndo_tx_timeout(struct net_device *ndev) 936{ 937 struct cpsw_priv *priv = netdev_priv(ndev); 938 939 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 940 priv->stats.tx_errors++; 941 cpsw_intr_disable(priv); 942 cpdma_ctlr_int_ctrl(priv->dma, false); 943 cpdma_chan_stop(priv->txch); 944 cpdma_chan_start(priv->txch); 945 cpdma_ctlr_int_ctrl(priv->dma, true); 946 cpsw_intr_enable(priv); 947 cpdma_ctlr_eoi(priv->dma); 948} 949 950static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 951{ 952 struct cpsw_priv *priv = netdev_priv(ndev); 953 return &priv->stats; 954} 955 956#ifdef CONFIG_NET_POLL_CONTROLLER 957static void cpsw_ndo_poll_controller(struct net_device *ndev) 958{ 959 struct cpsw_priv *priv = netdev_priv(ndev); 960 961 cpsw_intr_disable(priv); 962 cpdma_ctlr_int_ctrl(priv->dma, false); 963 cpsw_interrupt(ndev->irq, priv); 964 cpdma_ctlr_int_ctrl(priv->dma, true); 965 cpsw_intr_enable(priv); 966 cpdma_ctlr_eoi(priv->dma); 967} 968#endif 969 970static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 971 unsigned short vid) 972{ 973 int ret; 974 975 ret = cpsw_ale_add_vlan(priv->ale, vid, 976 ALE_ALL_PORTS << priv->host_port, 977 0, ALE_ALL_PORTS << priv->host_port, 978 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 979 if (ret != 0) 980 return ret; 981 982 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 983 priv->host_port, ALE_VLAN, vid); 984 if (ret != 0) 985 goto clean_vid; 986 987 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 988 ALE_ALL_PORTS << priv->host_port, 989 ALE_VLAN, vid, 0); 990 if (ret != 0) 991 goto clean_vlan_ucast; 992 return 0; 993 994clean_vlan_ucast: 995 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 996 priv->host_port, ALE_VLAN, vid); 997clean_vid: 998 cpsw_ale_del_vlan(priv->ale, vid, 0); 999 return ret; 1000} 1001 1002static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 1003 unsigned short vid) 1004{ 1005 struct cpsw_priv *priv = netdev_priv(ndev); 1006 1007 if (vid == priv->data.default_vlan) 1008 return 0; 1009 1010 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1011 return cpsw_add_vlan_ale_entry(priv, vid); 1012} 1013 1014static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 1015 unsigned short vid) 1016{ 1017 struct cpsw_priv *priv = netdev_priv(ndev); 1018 int ret; 1019 1020 if (vid == priv->data.default_vlan) 1021 return 0; 1022 1023 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 1024 ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 1025 if (ret != 0) 1026 return ret; 1027 1028 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 1029 priv->host_port, ALE_VLAN, vid); 1030 if (ret != 0) 1031 return ret; 1032 1033 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 1034 0, ALE_VLAN, vid); 1035} 1036 1037static const struct net_device_ops cpsw_netdev_ops = { 1038 .ndo_open = cpsw_ndo_open, 1039 .ndo_stop = cpsw_ndo_stop, 1040 .ndo_start_xmit = cpsw_ndo_start_xmit, 1041 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 1042 .ndo_do_ioctl = cpsw_ndo_ioctl, 1043 .ndo_validate_addr = eth_validate_addr, 1044 .ndo_change_mtu = eth_change_mtu, 1045 .ndo_tx_timeout = cpsw_ndo_tx_timeout, 1046 .ndo_get_stats = cpsw_ndo_get_stats, 1047 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1048#ifdef CONFIG_NET_POLL_CONTROLLER 1049 .ndo_poll_controller = cpsw_ndo_poll_controller, 1050#endif 1051 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 1052 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1053}; 1054 1055static void cpsw_get_drvinfo(struct net_device *ndev, 1056 struct ethtool_drvinfo *info) 1057{ 1058 struct cpsw_priv *priv = netdev_priv(ndev); 1059 1060 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 1061 strlcpy(info->version, "1.0", sizeof(info->version)); 1062 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1063} 1064 1065static u32 cpsw_get_msglevel(struct net_device *ndev) 1066{ 1067 struct cpsw_priv *priv = netdev_priv(ndev); 1068 return priv->msg_enable; 1069} 1070 1071static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1072{ 1073 struct cpsw_priv *priv = netdev_priv(ndev); 1074 priv->msg_enable = value; 1075} 1076 1077static int cpsw_get_ts_info(struct net_device *ndev, 1078 struct ethtool_ts_info *info) 1079{ 1080#ifdef CONFIG_TI_CPTS 1081 struct cpsw_priv *priv = netdev_priv(ndev); 1082 1083 info->so_timestamping = 1084 SOF_TIMESTAMPING_TX_HARDWARE | 1085 SOF_TIMESTAMPING_TX_SOFTWARE | 1086 SOF_TIMESTAMPING_RX_HARDWARE | 1087 SOF_TIMESTAMPING_RX_SOFTWARE | 1088 SOF_TIMESTAMPING_SOFTWARE | 1089 SOF_TIMESTAMPING_RAW_HARDWARE; 1090 info->phc_index = priv->cpts->phc_index; 1091 info->tx_types = 1092 (1 << HWTSTAMP_TX_OFF) | 1093 (1 << HWTSTAMP_TX_ON); 1094 info->rx_filters = 1095 (1 << HWTSTAMP_FILTER_NONE) | 1096 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1097#else 1098 info->so_timestamping = 1099 SOF_TIMESTAMPING_TX_SOFTWARE | 1100 SOF_TIMESTAMPING_RX_SOFTWARE | 1101 SOF_TIMESTAMPING_SOFTWARE; 1102 info->phc_index = -1; 1103 info->tx_types = 0; 1104 info->rx_filters = 0; 1105#endif 1106 return 0; 1107} 1108 1109static const struct ethtool_ops cpsw_ethtool_ops = { 1110 .get_drvinfo = cpsw_get_drvinfo, 1111 .get_msglevel = cpsw_get_msglevel, 1112 .set_msglevel = cpsw_set_msglevel, 1113 .get_link = ethtool_op_get_link, 1114 .get_ts_info = cpsw_get_ts_info, 1115}; 1116 1117static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1118 u32 slave_reg_ofs, u32 sliver_reg_ofs) 1119{ 1120 void __iomem *regs = priv->regs; 1121 int slave_num = slave->slave_num; 1122 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1123 1124 slave->data = data; 1125 slave->regs = regs + slave_reg_ofs; 1126 slave->sliver = regs + sliver_reg_ofs; 1127} 1128 1129static int cpsw_probe_dt(struct cpsw_platform_data *data, 1130 struct platform_device *pdev) 1131{ 1132 struct device_node *node = pdev->dev.of_node; 1133 struct device_node *slave_node; 1134 int i = 0, ret; 1135 u32 prop; 1136 1137 if (!node) 1138 return -EINVAL; 1139 1140 if (of_property_read_u32(node, "slaves", &prop)) { 1141 pr_err("Missing slaves property in the DT.\n"); 1142 return -EINVAL; 1143 } 1144 data->slaves = prop; 1145 1146 if (of_property_read_u32(node, "cpts_active_slave", &prop)) { 1147 pr_err("Missing cpts_active_slave property in the DT.\n"); 1148 ret = -EINVAL; 1149 goto error_ret; 1150 } 1151 data->cpts_active_slave = prop; 1152 1153 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 1154 pr_err("Missing cpts_clock_mult property in the DT.\n"); 1155 ret = -EINVAL; 1156 goto error_ret; 1157 } 1158 data->cpts_clock_mult = prop; 1159 1160 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 1161 pr_err("Missing cpts_clock_shift property in the DT.\n"); 1162 ret = -EINVAL; 1163 goto error_ret; 1164 } 1165 data->cpts_clock_shift = prop; 1166 1167 data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data), 1168 GFP_KERNEL); 1169 if (!data->slave_data) 1170 return -EINVAL; 1171 1172 if (of_property_read_u32(node, "cpdma_channels", &prop)) { 1173 pr_err("Missing cpdma_channels property in the DT.\n"); 1174 ret = -EINVAL; 1175 goto error_ret; 1176 } 1177 data->channels = prop; 1178 1179 if (of_property_read_u32(node, "ale_entries", &prop)) { 1180 pr_err("Missing ale_entries property in the DT.\n"); 1181 ret = -EINVAL; 1182 goto error_ret; 1183 } 1184 data->ale_entries = prop; 1185 1186 if (of_property_read_u32(node, "bd_ram_size", &prop)) { 1187 pr_err("Missing bd_ram_size property in the DT.\n"); 1188 ret = -EINVAL; 1189 goto error_ret; 1190 } 1191 data->bd_ram_size = prop; 1192 1193 if (of_property_read_u32(node, "rx_descs", &prop)) { 1194 pr_err("Missing rx_descs property in the DT.\n"); 1195 ret = -EINVAL; 1196 goto error_ret; 1197 } 1198 data->rx_descs = prop; 1199 1200 if (of_property_read_u32(node, "mac_control", &prop)) { 1201 pr_err("Missing mac_control property in the DT.\n"); 1202 ret = -EINVAL; 1203 goto error_ret; 1204 } 1205 data->mac_control = prop; 1206 1207 /* 1208 * Populate all the child nodes here... 1209 */ 1210 ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 1211 /* We do not want to force this, as in some cases may not have child */ 1212 if (ret) 1213 pr_warn("Doesn't have any child node\n"); 1214 1215 for_each_node_by_name(slave_node, "slave") { 1216 struct cpsw_slave_data *slave_data = data->slave_data + i; 1217 const void *mac_addr = NULL; 1218 u32 phyid; 1219 int lenp; 1220 const __be32 *parp; 1221 struct device_node *mdio_node; 1222 struct platform_device *mdio; 1223 1224 parp = of_get_property(slave_node, "phy_id", &lenp); 1225 if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) { 1226 pr_err("Missing slave[%d] phy_id property\n", i); 1227 ret = -EINVAL; 1228 goto error_ret; 1229 } 1230 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1231 phyid = be32_to_cpup(parp+1); 1232 mdio = of_find_device_by_node(mdio_node); 1233 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1234 PHY_ID_FMT, mdio->name, phyid); 1235 1236 mac_addr = of_get_mac_address(slave_node); 1237 if (mac_addr) 1238 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1239 1240 i++; 1241 } 1242 1243 return 0; 1244 1245error_ret: 1246 kfree(data->slave_data); 1247 return ret; 1248} 1249 1250static int cpsw_probe(struct platform_device *pdev) 1251{ 1252 struct cpsw_platform_data *data = pdev->dev.platform_data; 1253 struct net_device *ndev; 1254 struct cpsw_priv *priv; 1255 struct cpdma_params dma_params; 1256 struct cpsw_ale_params ale_params; 1257 void __iomem *ss_regs, *wr_regs; 1258 struct resource *res; 1259 u32 slave_offset, sliver_offset, slave_size; 1260 int ret = 0, i, k = 0; 1261 1262 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1263 if (!ndev) { 1264 pr_err("error allocating net_device\n"); 1265 return -ENOMEM; 1266 } 1267 1268 platform_set_drvdata(pdev, ndev); 1269 priv = netdev_priv(ndev); 1270 spin_lock_init(&priv->lock); 1271 priv->pdev = pdev; 1272 priv->ndev = ndev; 1273 priv->dev = &ndev->dev; 1274 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1275 priv->rx_packet_max = max(rx_packet_max, 128); 1276 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 1277 if (!ndev) { 1278 pr_err("error allocating cpts\n"); 1279 goto clean_ndev_ret; 1280 } 1281 1282 /* 1283 * This may be required here for child devices. 1284 */ 1285 pm_runtime_enable(&pdev->dev); 1286 1287 if (cpsw_probe_dt(&priv->data, pdev)) { 1288 pr_err("cpsw: platform data missing\n"); 1289 ret = -ENODEV; 1290 goto clean_ndev_ret; 1291 } 1292 data = &priv->data; 1293 1294 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1295 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1296 pr_info("Detected MACID = %pM", priv->mac_addr); 1297 } else { 1298 eth_random_addr(priv->mac_addr); 1299 pr_info("Random MACID = %pM", priv->mac_addr); 1300 } 1301 1302 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1303 1304 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, 1305 GFP_KERNEL); 1306 if (!priv->slaves) { 1307 ret = -EBUSY; 1308 goto clean_ndev_ret; 1309 } 1310 for (i = 0; i < data->slaves; i++) 1311 priv->slaves[i].slave_num = i; 1312 1313 priv->clk = clk_get(&pdev->dev, "fck"); 1314 if (IS_ERR(priv->clk)) { 1315 dev_err(&pdev->dev, "fck is not found\n"); 1316 ret = -ENODEV; 1317 goto clean_slave_ret; 1318 } 1319 1320 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1321 if (!priv->cpsw_res) { 1322 dev_err(priv->dev, "error getting i/o resource\n"); 1323 ret = -ENOENT; 1324 goto clean_clk_ret; 1325 } 1326 if (!request_mem_region(priv->cpsw_res->start, 1327 resource_size(priv->cpsw_res), ndev->name)) { 1328 dev_err(priv->dev, "failed request i/o region\n"); 1329 ret = -ENXIO; 1330 goto clean_clk_ret; 1331 } 1332 ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); 1333 if (!ss_regs) { 1334 dev_err(priv->dev, "unable to map i/o region\n"); 1335 goto clean_cpsw_iores_ret; 1336 } 1337 priv->regs = ss_regs; 1338 priv->version = __raw_readl(&priv->regs->id_ver); 1339 priv->host_port = HOST_PORT_NUM; 1340 1341 priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1342 if (!priv->cpsw_wr_res) { 1343 dev_err(priv->dev, "error getting i/o resource\n"); 1344 ret = -ENOENT; 1345 goto clean_iomap_ret; 1346 } 1347 if (!request_mem_region(priv->cpsw_wr_res->start, 1348 resource_size(priv->cpsw_wr_res), ndev->name)) { 1349 dev_err(priv->dev, "failed request i/o region\n"); 1350 ret = -ENXIO; 1351 goto clean_iomap_ret; 1352 } 1353 wr_regs = ioremap(priv->cpsw_wr_res->start, 1354 resource_size(priv->cpsw_wr_res)); 1355 if (!wr_regs) { 1356 dev_err(priv->dev, "unable to map i/o region\n"); 1357 goto clean_cpsw_wr_iores_ret; 1358 } 1359 priv->wr_regs = wr_regs; 1360 1361 memset(&dma_params, 0, sizeof(dma_params)); 1362 memset(&ale_params, 0, sizeof(ale_params)); 1363 1364 switch (priv->version) { 1365 case CPSW_VERSION_1: 1366 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 1367 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 1368 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 1369 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 1370 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 1371 slave_offset = CPSW1_SLAVE_OFFSET; 1372 slave_size = CPSW1_SLAVE_SIZE; 1373 sliver_offset = CPSW1_SLIVER_OFFSET; 1374 dma_params.desc_mem_phys = 0; 1375 break; 1376 case CPSW_VERSION_2: 1377 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 1378 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 1379 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 1380 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 1381 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 1382 slave_offset = CPSW2_SLAVE_OFFSET; 1383 slave_size = CPSW2_SLAVE_SIZE; 1384 sliver_offset = CPSW2_SLIVER_OFFSET; 1385 dma_params.desc_mem_phys = 1386 (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; 1387 break; 1388 default: 1389 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 1390 ret = -ENODEV; 1391 goto clean_cpsw_wr_iores_ret; 1392 } 1393 for (i = 0; i < priv->data.slaves; i++) { 1394 struct cpsw_slave *slave = &priv->slaves[i]; 1395 cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 1396 slave_offset += slave_size; 1397 sliver_offset += SLIVER_SIZE; 1398 } 1399 1400 dma_params.dev = &pdev->dev; 1401 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 1402 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 1403 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 1404 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 1405 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 1406 1407 dma_params.num_chan = data->channels; 1408 dma_params.has_soft_reset = true; 1409 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 1410 dma_params.desc_mem_size = data->bd_ram_size; 1411 dma_params.desc_align = 16; 1412 dma_params.has_ext_regs = true; 1413 dma_params.desc_hw_addr = dma_params.desc_mem_phys; 1414 1415 priv->dma = cpdma_ctlr_create(&dma_params); 1416 if (!priv->dma) { 1417 dev_err(priv->dev, "error initializing dma\n"); 1418 ret = -ENOMEM; 1419 goto clean_wr_iomap_ret; 1420 } 1421 1422 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 1423 cpsw_tx_handler); 1424 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 1425 cpsw_rx_handler); 1426 1427 if (WARN_ON(!priv->txch || !priv->rxch)) { 1428 dev_err(priv->dev, "error initializing dma channels\n"); 1429 ret = -ENOMEM; 1430 goto clean_dma_ret; 1431 } 1432 1433 ale_params.dev = &ndev->dev; 1434 ale_params.ale_ageout = ale_ageout; 1435 ale_params.ale_entries = data->ale_entries; 1436 ale_params.ale_ports = data->slaves; 1437 1438 priv->ale = cpsw_ale_create(&ale_params); 1439 if (!priv->ale) { 1440 dev_err(priv->dev, "error initializing ale engine\n"); 1441 ret = -ENODEV; 1442 goto clean_dma_ret; 1443 } 1444 1445 ndev->irq = platform_get_irq(pdev, 0); 1446 if (ndev->irq < 0) { 1447 dev_err(priv->dev, "error getting irq resource\n"); 1448 ret = -ENOENT; 1449 goto clean_ale_ret; 1450 } 1451 1452 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 1453 for (i = res->start; i <= res->end; i++) { 1454 if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, 1455 dev_name(&pdev->dev), priv)) { 1456 dev_err(priv->dev, "error attaching irq\n"); 1457 goto clean_ale_ret; 1458 } 1459 priv->irqs_table[k] = i; 1460 priv->num_irqs = k; 1461 } 1462 k++; 1463 } 1464 1465 ndev->features |= NETIF_F_HW_VLAN_FILTER; 1466 1467 ndev->netdev_ops = &cpsw_netdev_ops; 1468 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1469 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1470 1471 /* register the network device */ 1472 SET_NETDEV_DEV(ndev, &pdev->dev); 1473 ret = register_netdev(ndev); 1474 if (ret) { 1475 dev_err(priv->dev, "error registering net device\n"); 1476 ret = -ENODEV; 1477 goto clean_irq_ret; 1478 } 1479 1480 if (cpts_register(&pdev->dev, priv->cpts, 1481 data->cpts_clock_mult, data->cpts_clock_shift)) 1482 dev_err(priv->dev, "error registering cpts device\n"); 1483 1484 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 1485 priv->cpsw_res->start, ndev->irq); 1486 1487 return 0; 1488 1489clean_irq_ret: 1490 free_irq(ndev->irq, priv); 1491clean_ale_ret: 1492 cpsw_ale_destroy(priv->ale); 1493clean_dma_ret: 1494 cpdma_chan_destroy(priv->txch); 1495 cpdma_chan_destroy(priv->rxch); 1496 cpdma_ctlr_destroy(priv->dma); 1497clean_wr_iomap_ret: 1498 iounmap(priv->wr_regs); 1499clean_cpsw_wr_iores_ret: 1500 release_mem_region(priv->cpsw_wr_res->start, 1501 resource_size(priv->cpsw_wr_res)); 1502clean_iomap_ret: 1503 iounmap(priv->regs); 1504clean_cpsw_iores_ret: 1505 release_mem_region(priv->cpsw_res->start, 1506 resource_size(priv->cpsw_res)); 1507clean_clk_ret: 1508 clk_put(priv->clk); 1509clean_slave_ret: 1510 pm_runtime_disable(&pdev->dev); 1511 kfree(priv->slaves); 1512clean_ndev_ret: 1513 free_netdev(ndev); 1514 return ret; 1515} 1516 1517static int cpsw_remove(struct platform_device *pdev) 1518{ 1519 struct net_device *ndev = platform_get_drvdata(pdev); 1520 struct cpsw_priv *priv = netdev_priv(ndev); 1521 1522 pr_info("removing device"); 1523 platform_set_drvdata(pdev, NULL); 1524 1525 cpts_unregister(priv->cpts); 1526 free_irq(ndev->irq, priv); 1527 cpsw_ale_destroy(priv->ale); 1528 cpdma_chan_destroy(priv->txch); 1529 cpdma_chan_destroy(priv->rxch); 1530 cpdma_ctlr_destroy(priv->dma); 1531 iounmap(priv->regs); 1532 release_mem_region(priv->cpsw_res->start, 1533 resource_size(priv->cpsw_res)); 1534 iounmap(priv->wr_regs); 1535 release_mem_region(priv->cpsw_wr_res->start, 1536 resource_size(priv->cpsw_wr_res)); 1537 pm_runtime_disable(&pdev->dev); 1538 clk_put(priv->clk); 1539 kfree(priv->slaves); 1540 free_netdev(ndev); 1541 1542 return 0; 1543} 1544 1545static int cpsw_suspend(struct device *dev) 1546{ 1547 struct platform_device *pdev = to_platform_device(dev); 1548 struct net_device *ndev = platform_get_drvdata(pdev); 1549 1550 if (netif_running(ndev)) 1551 cpsw_ndo_stop(ndev); 1552 pm_runtime_put_sync(&pdev->dev); 1553 1554 return 0; 1555} 1556 1557static int cpsw_resume(struct device *dev) 1558{ 1559 struct platform_device *pdev = to_platform_device(dev); 1560 struct net_device *ndev = platform_get_drvdata(pdev); 1561 1562 pm_runtime_get_sync(&pdev->dev); 1563 if (netif_running(ndev)) 1564 cpsw_ndo_open(ndev); 1565 return 0; 1566} 1567 1568static const struct dev_pm_ops cpsw_pm_ops = { 1569 .suspend = cpsw_suspend, 1570 .resume = cpsw_resume, 1571}; 1572 1573static const struct of_device_id cpsw_of_mtable[] = { 1574 { .compatible = "ti,cpsw", }, 1575 { /* sentinel */ }, 1576}; 1577 1578static struct platform_driver cpsw_driver = { 1579 .driver = { 1580 .name = "cpsw", 1581 .owner = THIS_MODULE, 1582 .pm = &cpsw_pm_ops, 1583 .of_match_table = of_match_ptr(cpsw_of_mtable), 1584 }, 1585 .probe = cpsw_probe, 1586 .remove = cpsw_remove, 1587}; 1588 1589static int __init cpsw_init(void) 1590{ 1591 return platform_driver_register(&cpsw_driver); 1592} 1593late_initcall(cpsw_init); 1594 1595static void __exit cpsw_exit(void) 1596{ 1597 platform_driver_unregister(&cpsw_driver); 1598} 1599module_exit(cpsw_exit); 1600 1601MODULE_LICENSE("GPL"); 1602MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 1603MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 1604MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 1605