cpsw.c revision fae50823d0ee579e006a7ba2b20880e354388b25
1/* 2 * Texas Instruments Ethernet Switch Driver 3 * 4 * Copyright (C) 2012 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#include <linux/kernel.h> 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/timer.h> 20#include <linux/module.h> 21#include <linux/platform_device.h> 22#include <linux/irqreturn.h> 23#include <linux/interrupt.h> 24#include <linux/if_ether.h> 25#include <linux/etherdevice.h> 26#include <linux/netdevice.h> 27#include <linux/net_tstamp.h> 28#include <linux/phy.h> 29#include <linux/workqueue.h> 30#include <linux/delay.h> 31#include <linux/pm_runtime.h> 32#include <linux/of.h> 33#include <linux/of_net.h> 34#include <linux/of_device.h> 35 36#include <linux/platform_data/cpsw.h> 37 38#include "cpsw_ale.h" 39#include "cpts.h" 40#include "davinci_cpdma.h" 41 42#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 43 NETIF_MSG_DRV | NETIF_MSG_LINK | \ 44 NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 45 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 46 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 47 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 48 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 49 NETIF_MSG_RX_STATUS) 50 51#define cpsw_info(priv, type, format, ...) \ 52do { \ 53 if (netif_msg_##type(priv) && net_ratelimit()) \ 54 dev_info(priv->dev, format, ## __VA_ARGS__); \ 55} while (0) 56 57#define cpsw_err(priv, type, format, ...) \ 58do { \ 59 if (netif_msg_##type(priv) && net_ratelimit()) \ 60 dev_err(priv->dev, format, ## __VA_ARGS__); \ 61} while (0) 62 63#define cpsw_dbg(priv, type, format, ...) \ 64do { \ 65 if (netif_msg_##type(priv) && net_ratelimit()) \ 66 dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 67} while (0) 68 69#define cpsw_notice(priv, type, format, ...) \ 70do { \ 71 if (netif_msg_##type(priv) && net_ratelimit()) \ 72 dev_notice(priv->dev, format, ## __VA_ARGS__); \ 73} while (0) 74 75#define ALE_ALL_PORTS 0x7 76 77#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 78#define CPSW_MINOR_VERSION(reg) (reg & 0xff) 79#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 80 81#define CPSW_VERSION_1 0x19010a 82#define CPSW_VERSION_2 0x19010c 83 84#define HOST_PORT_NUM 0 85#define SLIVER_SIZE 0x40 86 87#define CPSW1_HOST_PORT_OFFSET 0x028 88#define CPSW1_SLAVE_OFFSET 0x050 89#define CPSW1_SLAVE_SIZE 0x040 90#define CPSW1_CPDMA_OFFSET 0x100 91#define CPSW1_STATERAM_OFFSET 0x200 92#define CPSW1_CPTS_OFFSET 0x500 93#define CPSW1_ALE_OFFSET 0x600 94#define CPSW1_SLIVER_OFFSET 0x700 95 96#define CPSW2_HOST_PORT_OFFSET 0x108 97#define CPSW2_SLAVE_OFFSET 0x200 98#define CPSW2_SLAVE_SIZE 0x100 99#define CPSW2_CPDMA_OFFSET 0x800 100#define CPSW2_STATERAM_OFFSET 0xa00 101#define CPSW2_CPTS_OFFSET 0xc00 102#define CPSW2_ALE_OFFSET 0xd00 103#define CPSW2_SLIVER_OFFSET 0xd80 104#define CPSW2_BD_OFFSET 0x2000 105 106#define CPDMA_RXTHRESH 0x0c0 107#define CPDMA_RXFREE 0x0e0 108#define CPDMA_TXHDP 0x00 109#define CPDMA_RXHDP 0x20 110#define CPDMA_TXCP 0x40 111#define CPDMA_RXCP 0x60 112 113#define CPSW_POLL_WEIGHT 64 114#define CPSW_MIN_PACKET_SIZE 60 115#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 116 117#define RX_PRIORITY_MAPPING 0x76543210 118#define TX_PRIORITY_MAPPING 0x33221100 119#define CPDMA_TX_PRIORITY_MAP 0x76543210 120 121#define cpsw_enable_irq(priv) \ 122 do { \ 123 u32 i; \ 124 for (i = 0; i < priv->num_irqs; i++) \ 125 enable_irq(priv->irqs_table[i]); \ 126 } while (0); 127#define cpsw_disable_irq(priv) \ 128 do { \ 129 u32 i; \ 130 for (i = 0; i < priv->num_irqs; i++) \ 131 disable_irq_nosync(priv->irqs_table[i]); \ 132 } while (0); 133 134static int debug_level; 135module_param(debug_level, int, 0); 136MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 137 138static int ale_ageout = 10; 139module_param(ale_ageout, int, 0); 140MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 141 142static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 143module_param(rx_packet_max, int, 0); 144MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 145 146struct cpsw_wr_regs { 147 u32 id_ver; 148 u32 soft_reset; 149 u32 control; 150 u32 int_control; 151 u32 rx_thresh_en; 152 u32 rx_en; 153 u32 tx_en; 154 u32 misc_en; 155}; 156 157struct cpsw_ss_regs { 158 u32 id_ver; 159 u32 control; 160 u32 soft_reset; 161 u32 stat_port_en; 162 u32 ptype; 163 u32 soft_idle; 164 u32 thru_rate; 165 u32 gap_thresh; 166 u32 tx_start_wds; 167 u32 flow_control; 168 u32 vlan_ltype; 169 u32 ts_ltype; 170 u32 dlr_ltype; 171}; 172 173/* CPSW_PORT_V1 */ 174#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 175#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 176#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 177#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 178#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 179#define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 180#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 181#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 182 183/* CPSW_PORT_V2 */ 184#define CPSW2_CONTROL 0x00 /* Control Register */ 185#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 186#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 187#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 188#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 189#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 190#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 191 192/* CPSW_PORT_V1 and V2 */ 193#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 194#define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 195#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 196 197/* CPSW_PORT_V2 only */ 198#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 199#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 200#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 201#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 202#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 203#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 204#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 205#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 206 207/* Bit definitions for the CPSW2_CONTROL register */ 208#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 209#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 210#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 211#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 212#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 213#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 214#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 215#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 216#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 217#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 218#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 219#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 220#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 221#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 222#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 223#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 224 225#define CTRL_TS_BITS \ 226 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 227 TS_ANNEX_D_EN | TS_LTYPE1_EN) 228 229#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 230#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 231#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 232 233/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 234#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 235#define TS_SEQ_ID_OFFSET_MASK (0x3f) 236#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 237#define TS_MSG_TYPE_EN_MASK (0xffff) 238 239/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 240#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 241 242/* Bit definitions for the CPSW1_TS_CTL register */ 243#define CPSW_V1_TS_RX_EN BIT(0) 244#define CPSW_V1_TS_TX_EN BIT(4) 245#define CPSW_V1_MSG_TYPE_OFS 16 246 247/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 248#define CPSW_V1_SEQ_ID_OFS_SHIFT 16 249 250struct cpsw_host_regs { 251 u32 max_blks; 252 u32 blk_cnt; 253 u32 flow_thresh; 254 u32 port_vlan; 255 u32 tx_pri_map; 256 u32 cpdma_tx_pri_map; 257 u32 cpdma_rx_chan_map; 258}; 259 260struct cpsw_sliver_regs { 261 u32 id_ver; 262 u32 mac_control; 263 u32 mac_status; 264 u32 soft_reset; 265 u32 rx_maxlen; 266 u32 __reserved_0; 267 u32 rx_pause; 268 u32 tx_pause; 269 u32 __reserved_1; 270 u32 rx_pri_map; 271}; 272 273struct cpsw_slave { 274 void __iomem *regs; 275 struct cpsw_sliver_regs __iomem *sliver; 276 int slave_num; 277 u32 mac_control; 278 struct cpsw_slave_data *data; 279 struct phy_device *phy; 280}; 281 282static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 283{ 284 return __raw_readl(slave->regs + offset); 285} 286 287static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 288{ 289 __raw_writel(val, slave->regs + offset); 290} 291 292struct cpsw_priv { 293 spinlock_t lock; 294 struct platform_device *pdev; 295 struct net_device *ndev; 296 struct resource *cpsw_res; 297 struct resource *cpsw_wr_res; 298 struct napi_struct napi; 299 struct device *dev; 300 struct cpsw_platform_data data; 301 struct cpsw_ss_regs __iomem *regs; 302 struct cpsw_wr_regs __iomem *wr_regs; 303 struct cpsw_host_regs __iomem *host_port_regs; 304 u32 msg_enable; 305 u32 version; 306 struct net_device_stats stats; 307 int rx_packet_max; 308 int host_port; 309 struct clk *clk; 310 u8 mac_addr[ETH_ALEN]; 311 struct cpsw_slave *slaves; 312 struct cpdma_ctlr *dma; 313 struct cpdma_chan *txch, *rxch; 314 struct cpsw_ale *ale; 315 /* snapshot of IRQ numbers */ 316 u32 irqs_table[4]; 317 u32 num_irqs; 318 struct cpts cpts; 319}; 320 321#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 322#define for_each_slave(priv, func, arg...) \ 323 do { \ 324 int idx; \ 325 for (idx = 0; idx < (priv)->data.slaves; idx++) \ 326 (func)((priv)->slaves + idx, ##arg); \ 327 } while (0) 328 329static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 330{ 331 struct cpsw_priv *priv = netdev_priv(ndev); 332 333 if (ndev->flags & IFF_PROMISC) { 334 /* Enable promiscuous mode */ 335 dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 336 return; 337 } 338 339 /* Clear all mcast from ALE */ 340 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 341 342 if (!netdev_mc_empty(ndev)) { 343 struct netdev_hw_addr *ha; 344 345 /* program multicast address list into ALE register */ 346 netdev_for_each_mc_addr(ha, ndev) { 347 cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr, 348 ALE_ALL_PORTS << priv->host_port, 0, 0); 349 } 350 } 351} 352 353static void cpsw_intr_enable(struct cpsw_priv *priv) 354{ 355 __raw_writel(0xFF, &priv->wr_regs->tx_en); 356 __raw_writel(0xFF, &priv->wr_regs->rx_en); 357 358 cpdma_ctlr_int_ctrl(priv->dma, true); 359 return; 360} 361 362static void cpsw_intr_disable(struct cpsw_priv *priv) 363{ 364 __raw_writel(0, &priv->wr_regs->tx_en); 365 __raw_writel(0, &priv->wr_regs->rx_en); 366 367 cpdma_ctlr_int_ctrl(priv->dma, false); 368 return; 369} 370 371void cpsw_tx_handler(void *token, int len, int status) 372{ 373 struct sk_buff *skb = token; 374 struct net_device *ndev = skb->dev; 375 struct cpsw_priv *priv = netdev_priv(ndev); 376 377 /* Check whether the queue is stopped due to stalled tx dma, if the 378 * queue is stopped then start the queue as we have free desc for tx 379 */ 380 if (unlikely(netif_queue_stopped(ndev))) 381 netif_start_queue(ndev); 382 cpts_tx_timestamp(&priv->cpts, skb); 383 priv->stats.tx_packets++; 384 priv->stats.tx_bytes += len; 385 dev_kfree_skb_any(skb); 386} 387 388void cpsw_rx_handler(void *token, int len, int status) 389{ 390 struct sk_buff *skb = token; 391 struct net_device *ndev = skb->dev; 392 struct cpsw_priv *priv = netdev_priv(ndev); 393 int ret = 0; 394 395 /* free and bail if we are shutting down */ 396 if (unlikely(!netif_running(ndev)) || 397 unlikely(!netif_carrier_ok(ndev))) { 398 dev_kfree_skb_any(skb); 399 return; 400 } 401 if (likely(status >= 0)) { 402 skb_put(skb, len); 403 cpts_rx_timestamp(&priv->cpts, skb); 404 skb->protocol = eth_type_trans(skb, ndev); 405 netif_receive_skb(skb); 406 priv->stats.rx_bytes += len; 407 priv->stats.rx_packets++; 408 skb = NULL; 409 } 410 411 if (unlikely(!netif_running(ndev))) { 412 if (skb) 413 dev_kfree_skb_any(skb); 414 return; 415 } 416 417 if (likely(!skb)) { 418 skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 419 if (WARN_ON(!skb)) 420 return; 421 422 ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 423 skb_tailroom(skb), GFP_KERNEL); 424 } 425 WARN_ON(ret < 0); 426} 427 428static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 429{ 430 struct cpsw_priv *priv = dev_id; 431 432 if (likely(netif_running(priv->ndev))) { 433 cpsw_intr_disable(priv); 434 cpsw_disable_irq(priv); 435 napi_schedule(&priv->napi); 436 } 437 return IRQ_HANDLED; 438} 439 440static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 441{ 442 if (priv->host_port == 0) 443 return slave_num + 1; 444 else 445 return slave_num; 446} 447 448static int cpsw_poll(struct napi_struct *napi, int budget) 449{ 450 struct cpsw_priv *priv = napi_to_priv(napi); 451 int num_tx, num_rx; 452 453 num_tx = cpdma_chan_process(priv->txch, 128); 454 num_rx = cpdma_chan_process(priv->rxch, budget); 455 456 if (num_rx || num_tx) 457 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 458 num_rx, num_tx); 459 460 if (num_rx < budget) { 461 napi_complete(napi); 462 cpsw_intr_enable(priv); 463 cpdma_ctlr_eoi(priv->dma); 464 cpsw_enable_irq(priv); 465 } 466 467 return num_rx; 468} 469 470static inline void soft_reset(const char *module, void __iomem *reg) 471{ 472 unsigned long timeout = jiffies + HZ; 473 474 __raw_writel(1, reg); 475 do { 476 cpu_relax(); 477 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 478 479 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 480} 481 482#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 483 ((mac)[2] << 16) | ((mac)[3] << 24)) 484#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 485 486static void cpsw_set_slave_mac(struct cpsw_slave *slave, 487 struct cpsw_priv *priv) 488{ 489 slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 490 slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 491} 492 493static void _cpsw_adjust_link(struct cpsw_slave *slave, 494 struct cpsw_priv *priv, bool *link) 495{ 496 struct phy_device *phy = slave->phy; 497 u32 mac_control = 0; 498 u32 slave_port; 499 500 if (!phy) 501 return; 502 503 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 504 505 if (phy->link) { 506 mac_control = priv->data.mac_control; 507 508 /* enable forwarding */ 509 cpsw_ale_control_set(priv->ale, slave_port, 510 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 511 512 if (phy->speed == 1000) 513 mac_control |= BIT(7); /* GIGABITEN */ 514 if (phy->duplex) 515 mac_control |= BIT(0); /* FULLDUPLEXEN */ 516 517 /* set speed_in input in case RMII mode is used in 100Mbps */ 518 if (phy->speed == 100) 519 mac_control |= BIT(15); 520 521 *link = true; 522 } else { 523 mac_control = 0; 524 /* disable forwarding */ 525 cpsw_ale_control_set(priv->ale, slave_port, 526 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 527 } 528 529 if (mac_control != slave->mac_control) { 530 phy_print_status(phy); 531 __raw_writel(mac_control, &slave->sliver->mac_control); 532 } 533 534 slave->mac_control = mac_control; 535} 536 537static void cpsw_adjust_link(struct net_device *ndev) 538{ 539 struct cpsw_priv *priv = netdev_priv(ndev); 540 bool link = false; 541 542 for_each_slave(priv, _cpsw_adjust_link, priv, &link); 543 544 if (link) { 545 netif_carrier_on(ndev); 546 if (netif_running(ndev)) 547 netif_wake_queue(ndev); 548 } else { 549 netif_carrier_off(ndev); 550 netif_stop_queue(ndev); 551 } 552} 553 554static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 555{ 556 static char *leader = "........................................"; 557 558 if (!val) 559 return 0; 560 else 561 return snprintf(buf, maxlen, "%s %s %10d\n", name, 562 leader + strlen(name), val); 563} 564 565static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 566{ 567 char name[32]; 568 u32 slave_port; 569 570 sprintf(name, "slave-%d", slave->slave_num); 571 572 soft_reset(name, &slave->sliver->soft_reset); 573 574 /* setup priority mapping */ 575 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 576 577 switch (priv->version) { 578 case CPSW_VERSION_1: 579 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 580 break; 581 case CPSW_VERSION_2: 582 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 583 break; 584 } 585 586 /* setup max packet size, and mac address */ 587 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 588 cpsw_set_slave_mac(slave, priv); 589 590 slave->mac_control = 0; /* no link yet */ 591 592 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 593 594 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 595 1 << slave_port, 0, ALE_MCAST_FWD_2); 596 597 slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 598 &cpsw_adjust_link, slave->data->phy_if); 599 if (IS_ERR(slave->phy)) { 600 dev_err(priv->dev, "phy %s not found on slave %d\n", 601 slave->data->phy_id, slave->slave_num); 602 slave->phy = NULL; 603 } else { 604 dev_info(priv->dev, "phy found : id is : 0x%x\n", 605 slave->phy->phy_id); 606 phy_start(slave->phy); 607 } 608} 609 610static void cpsw_init_host_port(struct cpsw_priv *priv) 611{ 612 /* soft reset the controller and initialize ale */ 613 soft_reset("cpsw", &priv->regs->soft_reset); 614 cpsw_ale_start(priv->ale); 615 616 /* switch to vlan unaware mode */ 617 cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0); 618 619 /* setup host port priority mapping */ 620 __raw_writel(CPDMA_TX_PRIORITY_MAP, 621 &priv->host_port_regs->cpdma_tx_pri_map); 622 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 623 624 cpsw_ale_control_set(priv->ale, priv->host_port, 625 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 626 627 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0); 628 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 629 1 << priv->host_port, 0, ALE_MCAST_FWD_2); 630} 631 632static int cpsw_ndo_open(struct net_device *ndev) 633{ 634 struct cpsw_priv *priv = netdev_priv(ndev); 635 int i, ret; 636 u32 reg; 637 638 cpsw_intr_disable(priv); 639 netif_carrier_off(ndev); 640 641 pm_runtime_get_sync(&priv->pdev->dev); 642 643 reg = priv->version; 644 645 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 646 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 647 CPSW_RTL_VERSION(reg)); 648 649 /* initialize host and slave ports */ 650 cpsw_init_host_port(priv); 651 for_each_slave(priv, cpsw_slave_open, priv); 652 653 /* setup tx dma to fixed prio and zero offset */ 654 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 655 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 656 657 /* disable priority elevation and enable statistics on all ports */ 658 __raw_writel(0, &priv->regs->ptype); 659 660 /* enable statistics collection only on the host port */ 661 __raw_writel(0x7, &priv->regs->stat_port_en); 662 663 if (WARN_ON(!priv->data.rx_descs)) 664 priv->data.rx_descs = 128; 665 666 for (i = 0; i < priv->data.rx_descs; i++) { 667 struct sk_buff *skb; 668 669 ret = -ENOMEM; 670 skb = netdev_alloc_skb_ip_align(priv->ndev, 671 priv->rx_packet_max); 672 if (!skb) 673 break; 674 ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 675 skb_tailroom(skb), GFP_KERNEL); 676 if (WARN_ON(ret < 0)) 677 break; 678 } 679 /* continue even if we didn't manage to submit all receive descs */ 680 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 681 682 cpdma_ctlr_start(priv->dma); 683 cpsw_intr_enable(priv); 684 napi_enable(&priv->napi); 685 cpdma_ctlr_eoi(priv->dma); 686 687 return 0; 688} 689 690static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 691{ 692 if (!slave->phy) 693 return; 694 phy_stop(slave->phy); 695 phy_disconnect(slave->phy); 696 slave->phy = NULL; 697} 698 699static int cpsw_ndo_stop(struct net_device *ndev) 700{ 701 struct cpsw_priv *priv = netdev_priv(ndev); 702 703 cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 704 netif_stop_queue(priv->ndev); 705 napi_disable(&priv->napi); 706 netif_carrier_off(priv->ndev); 707 cpsw_intr_disable(priv); 708 cpdma_ctlr_int_ctrl(priv->dma, false); 709 cpdma_ctlr_stop(priv->dma); 710 cpsw_ale_stop(priv->ale); 711 for_each_slave(priv, cpsw_slave_stop, priv); 712 pm_runtime_put_sync(&priv->pdev->dev); 713 return 0; 714} 715 716static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 717 struct net_device *ndev) 718{ 719 struct cpsw_priv *priv = netdev_priv(ndev); 720 int ret; 721 722 ndev->trans_start = jiffies; 723 724 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 725 cpsw_err(priv, tx_err, "packet pad failed\n"); 726 priv->stats.tx_dropped++; 727 return NETDEV_TX_OK; 728 } 729 730 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && priv->cpts.tx_enable) 731 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 732 733 skb_tx_timestamp(skb); 734 735 ret = cpdma_chan_submit(priv->txch, skb, skb->data, 736 skb->len, GFP_KERNEL); 737 if (unlikely(ret != 0)) { 738 cpsw_err(priv, tx_err, "desc submit failed\n"); 739 goto fail; 740 } 741 742 /* If there is no more tx desc left free then we need to 743 * tell the kernel to stop sending us tx frames. 744 */ 745 if (unlikely(cpdma_check_free_tx_desc(priv->txch))) 746 netif_stop_queue(ndev); 747 748 return NETDEV_TX_OK; 749fail: 750 priv->stats.tx_dropped++; 751 netif_stop_queue(ndev); 752 return NETDEV_TX_BUSY; 753} 754 755static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 756{ 757 /* 758 * The switch cannot operate in promiscuous mode without substantial 759 * headache. For promiscuous mode to work, we would need to put the 760 * ALE in bypass mode and route all traffic to the host port. 761 * Subsequently, the host will need to operate as a "bridge", learn, 762 * and flood as needed. For now, we simply complain here and 763 * do nothing about it :-) 764 */ 765 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 766 dev_err(&ndev->dev, "promiscuity ignored!\n"); 767 768 /* 769 * The switch cannot filter multicast traffic unless it is configured 770 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 771 * whole bunch of additional logic that this driver does not implement 772 * at present. 773 */ 774 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 775 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 776} 777 778#ifdef CONFIG_TI_CPTS 779 780static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 781{ 782 struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; 783 u32 ts_en, seq_id; 784 785 if (!priv->cpts.tx_enable && !priv->cpts.rx_enable) { 786 slave_write(slave, 0, CPSW1_TS_CTL); 787 return; 788 } 789 790 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 791 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 792 793 if (priv->cpts.tx_enable) 794 ts_en |= CPSW_V1_TS_TX_EN; 795 796 if (priv->cpts.rx_enable) 797 ts_en |= CPSW_V1_TS_RX_EN; 798 799 slave_write(slave, ts_en, CPSW1_TS_CTL); 800 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 801} 802 803static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 804{ 805 struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; 806 u32 ctrl, mtype; 807 808 ctrl = slave_read(slave, CPSW2_CONTROL); 809 ctrl &= ~CTRL_ALL_TS_MASK; 810 811 if (priv->cpts.tx_enable) 812 ctrl |= CTRL_TX_TS_BITS; 813 814 if (priv->cpts.rx_enable) 815 ctrl |= CTRL_RX_TS_BITS; 816 817 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 818 819 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 820 slave_write(slave, ctrl, CPSW2_CONTROL); 821 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 822} 823 824static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 825{ 826 struct cpsw_priv *priv = netdev_priv(dev); 827 struct cpts *cpts = &priv->cpts; 828 struct hwtstamp_config cfg; 829 830 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 831 return -EFAULT; 832 833 /* reserved for future extensions */ 834 if (cfg.flags) 835 return -EINVAL; 836 837 switch (cfg.tx_type) { 838 case HWTSTAMP_TX_OFF: 839 cpts->tx_enable = 0; 840 break; 841 case HWTSTAMP_TX_ON: 842 cpts->tx_enable = 1; 843 break; 844 default: 845 return -ERANGE; 846 } 847 848 switch (cfg.rx_filter) { 849 case HWTSTAMP_FILTER_NONE: 850 cpts->rx_enable = 0; 851 break; 852 case HWTSTAMP_FILTER_ALL: 853 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 854 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 855 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 856 return -ERANGE; 857 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 858 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 859 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 860 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 861 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 862 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 863 case HWTSTAMP_FILTER_PTP_V2_EVENT: 864 case HWTSTAMP_FILTER_PTP_V2_SYNC: 865 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 866 cpts->rx_enable = 1; 867 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 868 break; 869 default: 870 return -ERANGE; 871 } 872 873 switch (priv->version) { 874 case CPSW_VERSION_1: 875 cpsw_hwtstamp_v1(priv); 876 break; 877 case CPSW_VERSION_2: 878 cpsw_hwtstamp_v2(priv); 879 break; 880 default: 881 return -ENOTSUPP; 882 } 883 884 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 885} 886 887#endif /*CONFIG_TI_CPTS*/ 888 889static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 890{ 891 if (!netif_running(dev)) 892 return -EINVAL; 893 894#ifdef CONFIG_TI_CPTS 895 if (cmd == SIOCSHWTSTAMP) 896 return cpsw_hwtstamp_ioctl(dev, req); 897#endif 898 return -ENOTSUPP; 899} 900 901static void cpsw_ndo_tx_timeout(struct net_device *ndev) 902{ 903 struct cpsw_priv *priv = netdev_priv(ndev); 904 905 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 906 priv->stats.tx_errors++; 907 cpsw_intr_disable(priv); 908 cpdma_ctlr_int_ctrl(priv->dma, false); 909 cpdma_chan_stop(priv->txch); 910 cpdma_chan_start(priv->txch); 911 cpdma_ctlr_int_ctrl(priv->dma, true); 912 cpsw_intr_enable(priv); 913 cpdma_ctlr_eoi(priv->dma); 914} 915 916static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 917{ 918 struct cpsw_priv *priv = netdev_priv(ndev); 919 return &priv->stats; 920} 921 922#ifdef CONFIG_NET_POLL_CONTROLLER 923static void cpsw_ndo_poll_controller(struct net_device *ndev) 924{ 925 struct cpsw_priv *priv = netdev_priv(ndev); 926 927 cpsw_intr_disable(priv); 928 cpdma_ctlr_int_ctrl(priv->dma, false); 929 cpsw_interrupt(ndev->irq, priv); 930 cpdma_ctlr_int_ctrl(priv->dma, true); 931 cpsw_intr_enable(priv); 932 cpdma_ctlr_eoi(priv->dma); 933} 934#endif 935 936static const struct net_device_ops cpsw_netdev_ops = { 937 .ndo_open = cpsw_ndo_open, 938 .ndo_stop = cpsw_ndo_stop, 939 .ndo_start_xmit = cpsw_ndo_start_xmit, 940 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 941 .ndo_do_ioctl = cpsw_ndo_ioctl, 942 .ndo_validate_addr = eth_validate_addr, 943 .ndo_change_mtu = eth_change_mtu, 944 .ndo_tx_timeout = cpsw_ndo_tx_timeout, 945 .ndo_get_stats = cpsw_ndo_get_stats, 946 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 947#ifdef CONFIG_NET_POLL_CONTROLLER 948 .ndo_poll_controller = cpsw_ndo_poll_controller, 949#endif 950}; 951 952static void cpsw_get_drvinfo(struct net_device *ndev, 953 struct ethtool_drvinfo *info) 954{ 955 struct cpsw_priv *priv = netdev_priv(ndev); 956 957 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 958 strlcpy(info->version, "1.0", sizeof(info->version)); 959 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 960} 961 962static u32 cpsw_get_msglevel(struct net_device *ndev) 963{ 964 struct cpsw_priv *priv = netdev_priv(ndev); 965 return priv->msg_enable; 966} 967 968static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 969{ 970 struct cpsw_priv *priv = netdev_priv(ndev); 971 priv->msg_enable = value; 972} 973 974static int cpsw_get_ts_info(struct net_device *ndev, 975 struct ethtool_ts_info *info) 976{ 977#ifdef CONFIG_TI_CPTS 978 struct cpsw_priv *priv = netdev_priv(ndev); 979 980 info->so_timestamping = 981 SOF_TIMESTAMPING_TX_HARDWARE | 982 SOF_TIMESTAMPING_TX_SOFTWARE | 983 SOF_TIMESTAMPING_RX_HARDWARE | 984 SOF_TIMESTAMPING_RX_SOFTWARE | 985 SOF_TIMESTAMPING_SOFTWARE | 986 SOF_TIMESTAMPING_RAW_HARDWARE; 987 info->phc_index = priv->cpts.phc_index; 988 info->tx_types = 989 (1 << HWTSTAMP_TX_OFF) | 990 (1 << HWTSTAMP_TX_ON); 991 info->rx_filters = 992 (1 << HWTSTAMP_FILTER_NONE) | 993 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 994#else 995 info->so_timestamping = 996 SOF_TIMESTAMPING_TX_SOFTWARE | 997 SOF_TIMESTAMPING_RX_SOFTWARE | 998 SOF_TIMESTAMPING_SOFTWARE; 999 info->phc_index = -1; 1000 info->tx_types = 0; 1001 info->rx_filters = 0; 1002#endif 1003 return 0; 1004} 1005 1006static const struct ethtool_ops cpsw_ethtool_ops = { 1007 .get_drvinfo = cpsw_get_drvinfo, 1008 .get_msglevel = cpsw_get_msglevel, 1009 .set_msglevel = cpsw_set_msglevel, 1010 .get_link = ethtool_op_get_link, 1011 .get_ts_info = cpsw_get_ts_info, 1012}; 1013 1014static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1015 u32 slave_reg_ofs, u32 sliver_reg_ofs) 1016{ 1017 void __iomem *regs = priv->regs; 1018 int slave_num = slave->slave_num; 1019 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1020 1021 slave->data = data; 1022 slave->regs = regs + slave_reg_ofs; 1023 slave->sliver = regs + sliver_reg_ofs; 1024} 1025 1026static int cpsw_probe_dt(struct cpsw_platform_data *data, 1027 struct platform_device *pdev) 1028{ 1029 struct device_node *node = pdev->dev.of_node; 1030 struct device_node *slave_node; 1031 int i = 0, ret; 1032 u32 prop; 1033 1034 if (!node) 1035 return -EINVAL; 1036 1037 if (of_property_read_u32(node, "slaves", &prop)) { 1038 pr_err("Missing slaves property in the DT.\n"); 1039 return -EINVAL; 1040 } 1041 data->slaves = prop; 1042 1043 if (of_property_read_u32(node, "cpts_active_slave", &prop)) { 1044 pr_err("Missing cpts_active_slave property in the DT.\n"); 1045 ret = -EINVAL; 1046 goto error_ret; 1047 } 1048 data->cpts_active_slave = prop; 1049 1050 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 1051 pr_err("Missing cpts_clock_mult property in the DT.\n"); 1052 ret = -EINVAL; 1053 goto error_ret; 1054 } 1055 data->cpts_clock_mult = prop; 1056 1057 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 1058 pr_err("Missing cpts_clock_shift property in the DT.\n"); 1059 ret = -EINVAL; 1060 goto error_ret; 1061 } 1062 data->cpts_clock_shift = prop; 1063 1064 data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) * 1065 data->slaves, GFP_KERNEL); 1066 if (!data->slave_data) { 1067 pr_err("Could not allocate slave memory.\n"); 1068 return -EINVAL; 1069 } 1070 1071 if (of_property_read_u32(node, "cpdma_channels", &prop)) { 1072 pr_err("Missing cpdma_channels property in the DT.\n"); 1073 ret = -EINVAL; 1074 goto error_ret; 1075 } 1076 data->channels = prop; 1077 1078 if (of_property_read_u32(node, "ale_entries", &prop)) { 1079 pr_err("Missing ale_entries property in the DT.\n"); 1080 ret = -EINVAL; 1081 goto error_ret; 1082 } 1083 data->ale_entries = prop; 1084 1085 if (of_property_read_u32(node, "bd_ram_size", &prop)) { 1086 pr_err("Missing bd_ram_size property in the DT.\n"); 1087 ret = -EINVAL; 1088 goto error_ret; 1089 } 1090 data->bd_ram_size = prop; 1091 1092 if (of_property_read_u32(node, "rx_descs", &prop)) { 1093 pr_err("Missing rx_descs property in the DT.\n"); 1094 ret = -EINVAL; 1095 goto error_ret; 1096 } 1097 data->rx_descs = prop; 1098 1099 if (of_property_read_u32(node, "mac_control", &prop)) { 1100 pr_err("Missing mac_control property in the DT.\n"); 1101 ret = -EINVAL; 1102 goto error_ret; 1103 } 1104 data->mac_control = prop; 1105 1106 /* 1107 * Populate all the child nodes here... 1108 */ 1109 ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 1110 /* We do not want to force this, as in some cases may not have child */ 1111 if (ret) 1112 pr_warn("Doesn't have any child node\n"); 1113 1114 for_each_node_by_name(slave_node, "slave") { 1115 struct cpsw_slave_data *slave_data = data->slave_data + i; 1116 const void *mac_addr = NULL; 1117 u32 phyid; 1118 int lenp; 1119 const __be32 *parp; 1120 struct device_node *mdio_node; 1121 struct platform_device *mdio; 1122 1123 parp = of_get_property(slave_node, "phy_id", &lenp); 1124 if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) { 1125 pr_err("Missing slave[%d] phy_id property\n", i); 1126 ret = -EINVAL; 1127 goto error_ret; 1128 } 1129 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1130 phyid = be32_to_cpup(parp+1); 1131 mdio = of_find_device_by_node(mdio_node); 1132 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1133 PHY_ID_FMT, mdio->name, phyid); 1134 1135 mac_addr = of_get_mac_address(slave_node); 1136 if (mac_addr) 1137 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1138 1139 i++; 1140 } 1141 1142 return 0; 1143 1144error_ret: 1145 kfree(data->slave_data); 1146 return ret; 1147} 1148 1149static int cpsw_probe(struct platform_device *pdev) 1150{ 1151 struct cpsw_platform_data *data = pdev->dev.platform_data; 1152 struct net_device *ndev; 1153 struct cpsw_priv *priv; 1154 struct cpdma_params dma_params; 1155 struct cpsw_ale_params ale_params; 1156 void __iomem *ss_regs, *wr_regs; 1157 struct resource *res; 1158 u32 slave_offset, sliver_offset, slave_size; 1159 int ret = 0, i, k = 0; 1160 1161 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1162 if (!ndev) { 1163 pr_err("error allocating net_device\n"); 1164 return -ENOMEM; 1165 } 1166 1167 platform_set_drvdata(pdev, ndev); 1168 priv = netdev_priv(ndev); 1169 spin_lock_init(&priv->lock); 1170 priv->pdev = pdev; 1171 priv->ndev = ndev; 1172 priv->dev = &ndev->dev; 1173 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1174 priv->rx_packet_max = max(rx_packet_max, 128); 1175 1176 /* 1177 * This may be required here for child devices. 1178 */ 1179 pm_runtime_enable(&pdev->dev); 1180 1181 if (cpsw_probe_dt(&priv->data, pdev)) { 1182 pr_err("cpsw: platform data missing\n"); 1183 ret = -ENODEV; 1184 goto clean_ndev_ret; 1185 } 1186 data = &priv->data; 1187 1188 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1189 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1190 pr_info("Detected MACID = %pM", priv->mac_addr); 1191 } else { 1192 eth_random_addr(priv->mac_addr); 1193 pr_info("Random MACID = %pM", priv->mac_addr); 1194 } 1195 1196 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1197 1198 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, 1199 GFP_KERNEL); 1200 if (!priv->slaves) { 1201 ret = -EBUSY; 1202 goto clean_ndev_ret; 1203 } 1204 for (i = 0; i < data->slaves; i++) 1205 priv->slaves[i].slave_num = i; 1206 1207 priv->clk = clk_get(&pdev->dev, "fck"); 1208 if (IS_ERR(priv->clk)) { 1209 dev_err(&pdev->dev, "fck is not found\n"); 1210 ret = -ENODEV; 1211 goto clean_slave_ret; 1212 } 1213 1214 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1215 if (!priv->cpsw_res) { 1216 dev_err(priv->dev, "error getting i/o resource\n"); 1217 ret = -ENOENT; 1218 goto clean_clk_ret; 1219 } 1220 if (!request_mem_region(priv->cpsw_res->start, 1221 resource_size(priv->cpsw_res), ndev->name)) { 1222 dev_err(priv->dev, "failed request i/o region\n"); 1223 ret = -ENXIO; 1224 goto clean_clk_ret; 1225 } 1226 ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); 1227 if (!ss_regs) { 1228 dev_err(priv->dev, "unable to map i/o region\n"); 1229 goto clean_cpsw_iores_ret; 1230 } 1231 priv->regs = ss_regs; 1232 priv->version = __raw_readl(&priv->regs->id_ver); 1233 priv->host_port = HOST_PORT_NUM; 1234 1235 priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1236 if (!priv->cpsw_wr_res) { 1237 dev_err(priv->dev, "error getting i/o resource\n"); 1238 ret = -ENOENT; 1239 goto clean_iomap_ret; 1240 } 1241 if (!request_mem_region(priv->cpsw_wr_res->start, 1242 resource_size(priv->cpsw_wr_res), ndev->name)) { 1243 dev_err(priv->dev, "failed request i/o region\n"); 1244 ret = -ENXIO; 1245 goto clean_iomap_ret; 1246 } 1247 wr_regs = ioremap(priv->cpsw_wr_res->start, 1248 resource_size(priv->cpsw_wr_res)); 1249 if (!wr_regs) { 1250 dev_err(priv->dev, "unable to map i/o region\n"); 1251 goto clean_cpsw_wr_iores_ret; 1252 } 1253 priv->wr_regs = wr_regs; 1254 1255 memset(&dma_params, 0, sizeof(dma_params)); 1256 memset(&ale_params, 0, sizeof(ale_params)); 1257 1258 switch (priv->version) { 1259 case CPSW_VERSION_1: 1260 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 1261 priv->cpts.reg = ss_regs + CPSW1_CPTS_OFFSET; 1262 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 1263 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 1264 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 1265 slave_offset = CPSW1_SLAVE_OFFSET; 1266 slave_size = CPSW1_SLAVE_SIZE; 1267 sliver_offset = CPSW1_SLIVER_OFFSET; 1268 dma_params.desc_mem_phys = 0; 1269 break; 1270 case CPSW_VERSION_2: 1271 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 1272 priv->cpts.reg = ss_regs + CPSW2_CPTS_OFFSET; 1273 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 1274 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 1275 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 1276 slave_offset = CPSW2_SLAVE_OFFSET; 1277 slave_size = CPSW2_SLAVE_SIZE; 1278 sliver_offset = CPSW2_SLIVER_OFFSET; 1279 dma_params.desc_mem_phys = 1280 (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; 1281 break; 1282 default: 1283 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 1284 ret = -ENODEV; 1285 goto clean_cpsw_wr_iores_ret; 1286 } 1287 for (i = 0; i < priv->data.slaves; i++) { 1288 struct cpsw_slave *slave = &priv->slaves[i]; 1289 cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 1290 slave_offset += slave_size; 1291 sliver_offset += SLIVER_SIZE; 1292 } 1293 1294 dma_params.dev = &pdev->dev; 1295 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 1296 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 1297 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 1298 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 1299 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 1300 1301 dma_params.num_chan = data->channels; 1302 dma_params.has_soft_reset = true; 1303 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 1304 dma_params.desc_mem_size = data->bd_ram_size; 1305 dma_params.desc_align = 16; 1306 dma_params.has_ext_regs = true; 1307 dma_params.desc_hw_addr = dma_params.desc_mem_phys; 1308 1309 priv->dma = cpdma_ctlr_create(&dma_params); 1310 if (!priv->dma) { 1311 dev_err(priv->dev, "error initializing dma\n"); 1312 ret = -ENOMEM; 1313 goto clean_wr_iomap_ret; 1314 } 1315 1316 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 1317 cpsw_tx_handler); 1318 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 1319 cpsw_rx_handler); 1320 1321 if (WARN_ON(!priv->txch || !priv->rxch)) { 1322 dev_err(priv->dev, "error initializing dma channels\n"); 1323 ret = -ENOMEM; 1324 goto clean_dma_ret; 1325 } 1326 1327 ale_params.dev = &ndev->dev; 1328 ale_params.ale_ageout = ale_ageout; 1329 ale_params.ale_entries = data->ale_entries; 1330 ale_params.ale_ports = data->slaves; 1331 1332 priv->ale = cpsw_ale_create(&ale_params); 1333 if (!priv->ale) { 1334 dev_err(priv->dev, "error initializing ale engine\n"); 1335 ret = -ENODEV; 1336 goto clean_dma_ret; 1337 } 1338 1339 ndev->irq = platform_get_irq(pdev, 0); 1340 if (ndev->irq < 0) { 1341 dev_err(priv->dev, "error getting irq resource\n"); 1342 ret = -ENOENT; 1343 goto clean_ale_ret; 1344 } 1345 1346 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 1347 for (i = res->start; i <= res->end; i++) { 1348 if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, 1349 dev_name(&pdev->dev), priv)) { 1350 dev_err(priv->dev, "error attaching irq\n"); 1351 goto clean_ale_ret; 1352 } 1353 priv->irqs_table[k] = i; 1354 priv->num_irqs = k; 1355 } 1356 k++; 1357 } 1358 1359 ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */ 1360 1361 ndev->netdev_ops = &cpsw_netdev_ops; 1362 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1363 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1364 1365 /* register the network device */ 1366 SET_NETDEV_DEV(ndev, &pdev->dev); 1367 ret = register_netdev(ndev); 1368 if (ret) { 1369 dev_err(priv->dev, "error registering net device\n"); 1370 ret = -ENODEV; 1371 goto clean_irq_ret; 1372 } 1373 1374 if (cpts_register(&pdev->dev, &priv->cpts, 1375 data->cpts_clock_mult, data->cpts_clock_shift)) 1376 dev_err(priv->dev, "error registering cpts device\n"); 1377 1378 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 1379 priv->cpsw_res->start, ndev->irq); 1380 1381 return 0; 1382 1383clean_irq_ret: 1384 free_irq(ndev->irq, priv); 1385clean_ale_ret: 1386 cpsw_ale_destroy(priv->ale); 1387clean_dma_ret: 1388 cpdma_chan_destroy(priv->txch); 1389 cpdma_chan_destroy(priv->rxch); 1390 cpdma_ctlr_destroy(priv->dma); 1391clean_wr_iomap_ret: 1392 iounmap(priv->wr_regs); 1393clean_cpsw_wr_iores_ret: 1394 release_mem_region(priv->cpsw_wr_res->start, 1395 resource_size(priv->cpsw_wr_res)); 1396clean_iomap_ret: 1397 iounmap(priv->regs); 1398clean_cpsw_iores_ret: 1399 release_mem_region(priv->cpsw_res->start, 1400 resource_size(priv->cpsw_res)); 1401clean_clk_ret: 1402 clk_put(priv->clk); 1403clean_slave_ret: 1404 pm_runtime_disable(&pdev->dev); 1405 kfree(priv->slaves); 1406clean_ndev_ret: 1407 free_netdev(ndev); 1408 return ret; 1409} 1410 1411static int cpsw_remove(struct platform_device *pdev) 1412{ 1413 struct net_device *ndev = platform_get_drvdata(pdev); 1414 struct cpsw_priv *priv = netdev_priv(ndev); 1415 1416 pr_info("removing device"); 1417 platform_set_drvdata(pdev, NULL); 1418 1419 cpts_unregister(&priv->cpts); 1420 free_irq(ndev->irq, priv); 1421 cpsw_ale_destroy(priv->ale); 1422 cpdma_chan_destroy(priv->txch); 1423 cpdma_chan_destroy(priv->rxch); 1424 cpdma_ctlr_destroy(priv->dma); 1425 iounmap(priv->regs); 1426 release_mem_region(priv->cpsw_res->start, 1427 resource_size(priv->cpsw_res)); 1428 iounmap(priv->wr_regs); 1429 release_mem_region(priv->cpsw_wr_res->start, 1430 resource_size(priv->cpsw_wr_res)); 1431 pm_runtime_disable(&pdev->dev); 1432 clk_put(priv->clk); 1433 kfree(priv->slaves); 1434 free_netdev(ndev); 1435 1436 return 0; 1437} 1438 1439static int cpsw_suspend(struct device *dev) 1440{ 1441 struct platform_device *pdev = to_platform_device(dev); 1442 struct net_device *ndev = platform_get_drvdata(pdev); 1443 1444 if (netif_running(ndev)) 1445 cpsw_ndo_stop(ndev); 1446 pm_runtime_put_sync(&pdev->dev); 1447 1448 return 0; 1449} 1450 1451static int cpsw_resume(struct device *dev) 1452{ 1453 struct platform_device *pdev = to_platform_device(dev); 1454 struct net_device *ndev = platform_get_drvdata(pdev); 1455 1456 pm_runtime_get_sync(&pdev->dev); 1457 if (netif_running(ndev)) 1458 cpsw_ndo_open(ndev); 1459 return 0; 1460} 1461 1462static const struct dev_pm_ops cpsw_pm_ops = { 1463 .suspend = cpsw_suspend, 1464 .resume = cpsw_resume, 1465}; 1466 1467static const struct of_device_id cpsw_of_mtable[] = { 1468 { .compatible = "ti,cpsw", }, 1469 { /* sentinel */ }, 1470}; 1471 1472static struct platform_driver cpsw_driver = { 1473 .driver = { 1474 .name = "cpsw", 1475 .owner = THIS_MODULE, 1476 .pm = &cpsw_pm_ops, 1477 .of_match_table = of_match_ptr(cpsw_of_mtable), 1478 }, 1479 .probe = cpsw_probe, 1480 .remove = cpsw_remove, 1481}; 1482 1483static int __init cpsw_init(void) 1484{ 1485 return platform_driver_register(&cpsw_driver); 1486} 1487late_initcall(cpsw_init); 1488 1489static void __exit cpsw_exit(void) 1490{ 1491 platform_driver_unregister(&cpsw_driver); 1492} 1493module_exit(cpsw_exit); 1494 1495MODULE_LICENSE("GPL"); 1496MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 1497MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 1498MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 1499