ll_temac_main.c revision 720a43efd30f04a0a492c85fb997361c44fbae05
1/* 2 * Driver for Xilinx TEMAC Ethernet device 3 * 4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi 5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net> 6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd. 7 * 8 * This is a driver for the Xilinx ll_temac ipcore which is often used 9 * in the Virtex and Spartan series of chips. 10 * 11 * Notes: 12 * - The ll_temac hardware uses indirect access for many of the TEMAC 13 * registers, include the MDIO bus. However, indirect access to MDIO 14 * registers take considerably more clock cycles than to TEMAC registers. 15 * MDIO accesses are long, so threads doing them should probably sleep 16 * rather than busywait. However, since only one indirect access can be 17 * in progress at any given time, that means that *all* indirect accesses 18 * could end up sleeping (to wait for an MDIO access to complete). 19 * Fortunately none of the indirect accesses are on the 'hot' path for tx 20 * or rx, so this should be okay. 21 * 22 * TODO: 23 * - Factor out locallink DMA code into separate driver 24 * - Fix multicast assignment. 25 * - Fix support for hardware checksumming. 26 * - Testing. Lots and lots of testing. 27 * 28 */ 29 30#include <linux/delay.h> 31#include <linux/etherdevice.h> 32#include <linux/init.h> 33#include <linux/mii.h> 34#include <linux/module.h> 35#include <linux/mutex.h> 36#include <linux/netdevice.h> 37#include <linux/of.h> 38#include <linux/of_device.h> 39#include <linux/of_mdio.h> 40#include <linux/of_platform.h> 41#include <linux/of_address.h> 42#include <linux/skbuff.h> 43#include <linux/spinlock.h> 44#include <linux/tcp.h> /* needed for sizeof(tcphdr) */ 45#include <linux/udp.h> /* needed for sizeof(udphdr) */ 46#include <linux/phy.h> 47#include <linux/in.h> 48#include <linux/io.h> 49#include <linux/ip.h> 50#include <linux/slab.h> 51#include <linux/interrupt.h> 52#include <linux/dma-mapping.h> 53 54#include "ll_temac.h" 55 56#define TX_BD_NUM 64 57#define RX_BD_NUM 128 58 59/* --------------------------------------------------------------------- 60 * Low level register access functions 61 */ 62 63u32 temac_ior(struct temac_local *lp, int offset) 64{ 65 return in_be32((u32 *)(lp->regs + offset)); 66} 67 68void temac_iow(struct temac_local *lp, int offset, u32 value) 69{ 70 out_be32((u32 *) (lp->regs + offset), value); 71} 72 73int temac_indirect_busywait(struct temac_local *lp) 74{ 75 long end = jiffies + 2; 76 77 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) { 78 if (end - jiffies <= 0) { 79 WARN_ON(1); 80 return -ETIMEDOUT; 81 } 82 msleep(1); 83 } 84 return 0; 85} 86 87/** 88 * temac_indirect_in32 89 * 90 * lp->indirect_mutex must be held when calling this function 91 */ 92u32 temac_indirect_in32(struct temac_local *lp, int reg) 93{ 94 u32 val; 95 96 if (temac_indirect_busywait(lp)) 97 return -ETIMEDOUT; 98 temac_iow(lp, XTE_CTL0_OFFSET, reg); 99 if (temac_indirect_busywait(lp)) 100 return -ETIMEDOUT; 101 val = temac_ior(lp, XTE_LSW0_OFFSET); 102 103 return val; 104} 105 106/** 107 * temac_indirect_out32 108 * 109 * lp->indirect_mutex must be held when calling this function 110 */ 111void temac_indirect_out32(struct temac_local *lp, int reg, u32 value) 112{ 113 if (temac_indirect_busywait(lp)) 114 return; 115 temac_iow(lp, XTE_LSW0_OFFSET, value); 116 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg); 117 temac_indirect_busywait(lp); 118} 119 120/** 121 * temac_dma_in32 - Memory mapped DMA read, this function expects a 122 * register input that is based on DCR word addresses which 123 * are then converted to memory mapped byte addresses 124 */ 125static u32 temac_dma_in32(struct temac_local *lp, int reg) 126{ 127 return in_be32((u32 *)(lp->sdma_regs + (reg << 2))); 128} 129 130/** 131 * temac_dma_out32 - Memory mapped DMA read, this function expects a 132 * register input that is based on DCR word addresses which 133 * are then converted to memory mapped byte addresses 134 */ 135static void temac_dma_out32(struct temac_local *lp, int reg, u32 value) 136{ 137 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value); 138} 139 140/* DMA register access functions can be DCR based or memory mapped. 141 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both 142 * memory mapped. 143 */ 144#ifdef CONFIG_PPC_DCR 145 146/** 147 * temac_dma_dcr_in32 - DCR based DMA read 148 */ 149static u32 temac_dma_dcr_in(struct temac_local *lp, int reg) 150{ 151 return dcr_read(lp->sdma_dcrs, reg); 152} 153 154/** 155 * temac_dma_dcr_out32 - DCR based DMA write 156 */ 157static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value) 158{ 159 dcr_write(lp->sdma_dcrs, reg, value); 160} 161 162/** 163 * temac_dcr_setup - If the DMA is DCR based, then setup the address and 164 * I/O functions 165 */ 166static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op, 167 struct device_node *np) 168{ 169 unsigned int dcrs; 170 171 /* setup the dcr address mapping if it's in the device tree */ 172 173 dcrs = dcr_resource_start(np, 0); 174 if (dcrs != 0) { 175 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); 176 lp->dma_in = temac_dma_dcr_in; 177 lp->dma_out = temac_dma_dcr_out; 178 dev_dbg(&op->dev, "DCR base: %x\n", dcrs); 179 return 0; 180 } 181 /* no DCR in the device tree, indicate a failure */ 182 return -1; 183} 184 185#else 186 187/* 188 * temac_dcr_setup - This is a stub for when DCR is not supported, 189 * such as with MicroBlaze 190 */ 191static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op, 192 struct device_node *np) 193{ 194 return -1; 195} 196 197#endif 198 199/** 200 * temac_dma_bd_release - Release buffer descriptor rings 201 */ 202static void temac_dma_bd_release(struct net_device *ndev) 203{ 204 struct temac_local *lp = netdev_priv(ndev); 205 int i; 206 207 /* Reset Local Link (DMA) */ 208 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); 209 210 for (i = 0; i < RX_BD_NUM; i++) { 211 if (!lp->rx_skb[i]) 212 break; 213 else { 214 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys, 215 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE); 216 dev_kfree_skb(lp->rx_skb[i]); 217 } 218 } 219 if (lp->rx_bd_v) 220 dma_free_coherent(ndev->dev.parent, 221 sizeof(*lp->rx_bd_v) * RX_BD_NUM, 222 lp->rx_bd_v, lp->rx_bd_p); 223 if (lp->tx_bd_v) 224 dma_free_coherent(ndev->dev.parent, 225 sizeof(*lp->tx_bd_v) * TX_BD_NUM, 226 lp->tx_bd_v, lp->tx_bd_p); 227 if (lp->rx_skb) 228 kfree(lp->rx_skb); 229} 230 231/** 232 * temac_dma_bd_init - Setup buffer descriptor rings 233 */ 234static int temac_dma_bd_init(struct net_device *ndev) 235{ 236 struct temac_local *lp = netdev_priv(ndev); 237 struct sk_buff *skb; 238 int i; 239 240 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL); 241 if (!lp->rx_skb) 242 goto out; 243 244 /* allocate the tx and rx ring buffer descriptors. */ 245 /* returns a virtual address and a physical address. */ 246 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent, 247 sizeof(*lp->tx_bd_v) * TX_BD_NUM, 248 &lp->tx_bd_p, GFP_KERNEL); 249 if (!lp->tx_bd_v) { 250 dev_err(&ndev->dev, 251 "unable to allocate DMA TX buffer descriptors"); 252 goto out; 253 } 254 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent, 255 sizeof(*lp->rx_bd_v) * RX_BD_NUM, 256 &lp->rx_bd_p, GFP_KERNEL); 257 if (!lp->rx_bd_v) { 258 dev_err(&ndev->dev, 259 "unable to allocate DMA RX buffer descriptors"); 260 goto out; 261 } 262 263 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM); 264 for (i = 0; i < TX_BD_NUM; i++) { 265 lp->tx_bd_v[i].next = lp->tx_bd_p + 266 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM); 267 } 268 269 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM); 270 for (i = 0; i < RX_BD_NUM; i++) { 271 lp->rx_bd_v[i].next = lp->rx_bd_p + 272 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM); 273 274 skb = netdev_alloc_skb_ip_align(ndev, 275 XTE_MAX_JUMBO_FRAME_SIZE); 276 if (!skb) 277 goto out; 278 279 lp->rx_skb[i] = skb; 280 /* returns physical address of skb->data */ 281 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent, 282 skb->data, 283 XTE_MAX_JUMBO_FRAME_SIZE, 284 DMA_FROM_DEVICE); 285 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE; 286 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND; 287 } 288 289 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 | 290 CHNL_CTRL_IRQ_EN | 291 CHNL_CTRL_IRQ_DLY_EN | 292 CHNL_CTRL_IRQ_COAL_EN); 293 /* 0x10220483 */ 294 /* 0x00100483 */ 295 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 | 296 CHNL_CTRL_IRQ_EN | 297 CHNL_CTRL_IRQ_DLY_EN | 298 CHNL_CTRL_IRQ_COAL_EN | 299 CHNL_CTRL_IRQ_IOE); 300 /* 0xff010283 */ 301 302 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p); 303 lp->dma_out(lp, RX_TAILDESC_PTR, 304 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1))); 305 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p); 306 307 return 0; 308 309out: 310 temac_dma_bd_release(ndev); 311 return -ENOMEM; 312} 313 314/* --------------------------------------------------------------------- 315 * net_device_ops 316 */ 317 318static void temac_do_set_mac_address(struct net_device *ndev) 319{ 320 struct temac_local *lp = netdev_priv(ndev); 321 322 /* set up unicast MAC address filter set its mac address */ 323 mutex_lock(&lp->indirect_mutex); 324 temac_indirect_out32(lp, XTE_UAW0_OFFSET, 325 (ndev->dev_addr[0]) | 326 (ndev->dev_addr[1] << 8) | 327 (ndev->dev_addr[2] << 16) | 328 (ndev->dev_addr[3] << 24)); 329 /* There are reserved bits in EUAW1 330 * so don't affect them Set MAC bits [47:32] in EUAW1 */ 331 temac_indirect_out32(lp, XTE_UAW1_OFFSET, 332 (ndev->dev_addr[4] & 0x000000ff) | 333 (ndev->dev_addr[5] << 8)); 334 mutex_unlock(&lp->indirect_mutex); 335} 336 337static int temac_init_mac_address(struct net_device *ndev, void *address) 338{ 339 memcpy(ndev->dev_addr, address, ETH_ALEN); 340 if (!is_valid_ether_addr(ndev->dev_addr)) 341 eth_hw_addr_random(ndev); 342 temac_do_set_mac_address(ndev); 343 return 0; 344} 345 346static int temac_set_mac_address(struct net_device *ndev, void *p) 347{ 348 struct sockaddr *addr = p; 349 350 if (!is_valid_ether_addr(addr->sa_data)) 351 return -EADDRNOTAVAIL; 352 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN); 353 temac_do_set_mac_address(ndev); 354 return 0; 355} 356 357static void temac_set_multicast_list(struct net_device *ndev) 358{ 359 struct temac_local *lp = netdev_priv(ndev); 360 u32 multi_addr_msw, multi_addr_lsw, val; 361 int i; 362 363 mutex_lock(&lp->indirect_mutex); 364 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) || 365 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) { 366 /* 367 * We must make the kernel realise we had to move 368 * into promisc mode or we start all out war on 369 * the cable. If it was a promisc request the 370 * flag is already set. If not we assert it. 371 */ 372 ndev->flags |= IFF_PROMISC; 373 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK); 374 dev_info(&ndev->dev, "Promiscuous mode enabled.\n"); 375 } else if (!netdev_mc_empty(ndev)) { 376 struct netdev_hw_addr *ha; 377 378 i = 0; 379 netdev_for_each_mc_addr(ha, ndev) { 380 if (i >= MULTICAST_CAM_TABLE_NUM) 381 break; 382 multi_addr_msw = ((ha->addr[3] << 24) | 383 (ha->addr[2] << 16) | 384 (ha->addr[1] << 8) | 385 (ha->addr[0])); 386 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 387 multi_addr_msw); 388 multi_addr_lsw = ((ha->addr[5] << 8) | 389 (ha->addr[4]) | (i << 16)); 390 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 391 multi_addr_lsw); 392 i++; 393 } 394 } else { 395 val = temac_indirect_in32(lp, XTE_AFM_OFFSET); 396 temac_indirect_out32(lp, XTE_AFM_OFFSET, 397 val & ~XTE_AFM_EPPRM_MASK); 398 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0); 399 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0); 400 dev_info(&ndev->dev, "Promiscuous mode disabled.\n"); 401 } 402 mutex_unlock(&lp->indirect_mutex); 403} 404 405struct temac_option { 406 int flg; 407 u32 opt; 408 u32 reg; 409 u32 m_or; 410 u32 m_and; 411} temac_options[] = { 412 /* Turn on jumbo packet support for both Rx and Tx */ 413 { 414 .opt = XTE_OPTION_JUMBO, 415 .reg = XTE_TXC_OFFSET, 416 .m_or = XTE_TXC_TXJMBO_MASK, 417 }, 418 { 419 .opt = XTE_OPTION_JUMBO, 420 .reg = XTE_RXC1_OFFSET, 421 .m_or =XTE_RXC1_RXJMBO_MASK, 422 }, 423 /* Turn on VLAN packet support for both Rx and Tx */ 424 { 425 .opt = XTE_OPTION_VLAN, 426 .reg = XTE_TXC_OFFSET, 427 .m_or =XTE_TXC_TXVLAN_MASK, 428 }, 429 { 430 .opt = XTE_OPTION_VLAN, 431 .reg = XTE_RXC1_OFFSET, 432 .m_or =XTE_RXC1_RXVLAN_MASK, 433 }, 434 /* Turn on FCS stripping on receive packets */ 435 { 436 .opt = XTE_OPTION_FCS_STRIP, 437 .reg = XTE_RXC1_OFFSET, 438 .m_or =XTE_RXC1_RXFCS_MASK, 439 }, 440 /* Turn on FCS insertion on transmit packets */ 441 { 442 .opt = XTE_OPTION_FCS_INSERT, 443 .reg = XTE_TXC_OFFSET, 444 .m_or =XTE_TXC_TXFCS_MASK, 445 }, 446 /* Turn on length/type field checking on receive packets */ 447 { 448 .opt = XTE_OPTION_LENTYPE_ERR, 449 .reg = XTE_RXC1_OFFSET, 450 .m_or =XTE_RXC1_RXLT_MASK, 451 }, 452 /* Turn on flow control */ 453 { 454 .opt = XTE_OPTION_FLOW_CONTROL, 455 .reg = XTE_FCC_OFFSET, 456 .m_or =XTE_FCC_RXFLO_MASK, 457 }, 458 /* Turn on flow control */ 459 { 460 .opt = XTE_OPTION_FLOW_CONTROL, 461 .reg = XTE_FCC_OFFSET, 462 .m_or =XTE_FCC_TXFLO_MASK, 463 }, 464 /* Turn on promiscuous frame filtering (all frames are received ) */ 465 { 466 .opt = XTE_OPTION_PROMISC, 467 .reg = XTE_AFM_OFFSET, 468 .m_or =XTE_AFM_EPPRM_MASK, 469 }, 470 /* Enable transmitter if not already enabled */ 471 { 472 .opt = XTE_OPTION_TXEN, 473 .reg = XTE_TXC_OFFSET, 474 .m_or =XTE_TXC_TXEN_MASK, 475 }, 476 /* Enable receiver? */ 477 { 478 .opt = XTE_OPTION_RXEN, 479 .reg = XTE_RXC1_OFFSET, 480 .m_or =XTE_RXC1_RXEN_MASK, 481 }, 482 {} 483}; 484 485/** 486 * temac_setoptions 487 */ 488static u32 temac_setoptions(struct net_device *ndev, u32 options) 489{ 490 struct temac_local *lp = netdev_priv(ndev); 491 struct temac_option *tp = &temac_options[0]; 492 int reg; 493 494 mutex_lock(&lp->indirect_mutex); 495 while (tp->opt) { 496 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or; 497 if (options & tp->opt) 498 reg |= tp->m_or; 499 temac_indirect_out32(lp, tp->reg, reg); 500 tp++; 501 } 502 lp->options |= options; 503 mutex_unlock(&lp->indirect_mutex); 504 505 return 0; 506} 507 508/* Initialize temac */ 509static void temac_device_reset(struct net_device *ndev) 510{ 511 struct temac_local *lp = netdev_priv(ndev); 512 u32 timeout; 513 u32 val; 514 515 /* Perform a software reset */ 516 517 /* 0x300 host enable bit ? */ 518 /* reset PHY through control register ?:1 */ 519 520 dev_dbg(&ndev->dev, "%s()\n", __func__); 521 522 mutex_lock(&lp->indirect_mutex); 523 /* Reset the receiver and wait for it to finish reset */ 524 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK); 525 timeout = 1000; 526 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) { 527 udelay(1); 528 if (--timeout == 0) { 529 dev_err(&ndev->dev, 530 "temac_device_reset RX reset timeout!!\n"); 531 break; 532 } 533 } 534 535 /* Reset the transmitter and wait for it to finish reset */ 536 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK); 537 timeout = 1000; 538 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) { 539 udelay(1); 540 if (--timeout == 0) { 541 dev_err(&ndev->dev, 542 "temac_device_reset TX reset timeout!!\n"); 543 break; 544 } 545 } 546 547 /* Disable the receiver */ 548 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET); 549 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK); 550 551 /* Reset Local Link (DMA) */ 552 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); 553 timeout = 1000; 554 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) { 555 udelay(1); 556 if (--timeout == 0) { 557 dev_err(&ndev->dev, 558 "temac_device_reset DMA reset timeout!!\n"); 559 break; 560 } 561 } 562 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE); 563 564 if (temac_dma_bd_init(ndev)) { 565 dev_err(&ndev->dev, 566 "temac_device_reset descriptor allocation failed\n"); 567 } 568 569 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0); 570 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0); 571 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0); 572 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK); 573 574 mutex_unlock(&lp->indirect_mutex); 575 576 /* Sync default options with HW 577 * but leave receiver and transmitter disabled. */ 578 temac_setoptions(ndev, 579 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN)); 580 581 temac_do_set_mac_address(ndev); 582 583 /* Set address filter table */ 584 temac_set_multicast_list(ndev); 585 if (temac_setoptions(ndev, lp->options)) 586 dev_err(&ndev->dev, "Error setting TEMAC options\n"); 587 588 /* Init Driver variable */ 589 ndev->trans_start = jiffies; /* prevent tx timeout */ 590} 591 592void temac_adjust_link(struct net_device *ndev) 593{ 594 struct temac_local *lp = netdev_priv(ndev); 595 struct phy_device *phy = lp->phy_dev; 596 u32 mii_speed; 597 int link_state; 598 599 /* hash together the state values to decide if something has changed */ 600 link_state = phy->speed | (phy->duplex << 1) | phy->link; 601 602 mutex_lock(&lp->indirect_mutex); 603 if (lp->last_link != link_state) { 604 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET); 605 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK; 606 607 switch (phy->speed) { 608 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break; 609 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break; 610 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break; 611 } 612 613 /* Write new speed setting out to TEMAC */ 614 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed); 615 lp->last_link = link_state; 616 phy_print_status(phy); 617 } 618 mutex_unlock(&lp->indirect_mutex); 619} 620 621static void temac_start_xmit_done(struct net_device *ndev) 622{ 623 struct temac_local *lp = netdev_priv(ndev); 624 struct cdmac_bd *cur_p; 625 unsigned int stat = 0; 626 627 cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; 628 stat = cur_p->app0; 629 630 while (stat & STS_CTRL_APP0_CMPLT) { 631 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len, 632 DMA_TO_DEVICE); 633 if (cur_p->app4) 634 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4); 635 cur_p->app0 = 0; 636 cur_p->app1 = 0; 637 cur_p->app2 = 0; 638 cur_p->app3 = 0; 639 cur_p->app4 = 0; 640 641 ndev->stats.tx_packets++; 642 ndev->stats.tx_bytes += cur_p->len; 643 644 lp->tx_bd_ci++; 645 if (lp->tx_bd_ci >= TX_BD_NUM) 646 lp->tx_bd_ci = 0; 647 648 cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; 649 stat = cur_p->app0; 650 } 651 652 netif_wake_queue(ndev); 653} 654 655static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag) 656{ 657 struct cdmac_bd *cur_p; 658 int tail; 659 660 tail = lp->tx_bd_tail; 661 cur_p = &lp->tx_bd_v[tail]; 662 663 do { 664 if (cur_p->app0) 665 return NETDEV_TX_BUSY; 666 667 tail++; 668 if (tail >= TX_BD_NUM) 669 tail = 0; 670 671 cur_p = &lp->tx_bd_v[tail]; 672 num_frag--; 673 } while (num_frag >= 0); 674 675 return 0; 676} 677 678static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 679{ 680 struct temac_local *lp = netdev_priv(ndev); 681 struct cdmac_bd *cur_p; 682 dma_addr_t start_p, tail_p; 683 int ii; 684 unsigned long num_frag; 685 skb_frag_t *frag; 686 687 num_frag = skb_shinfo(skb)->nr_frags; 688 frag = &skb_shinfo(skb)->frags[0]; 689 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; 690 cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; 691 692 if (temac_check_tx_bd_space(lp, num_frag)) { 693 if (!netif_queue_stopped(ndev)) { 694 netif_stop_queue(ndev); 695 return NETDEV_TX_BUSY; 696 } 697 return NETDEV_TX_BUSY; 698 } 699 700 cur_p->app0 = 0; 701 if (skb->ip_summed == CHECKSUM_PARTIAL) { 702 unsigned int csum_start_off = skb_checksum_start_offset(skb); 703 unsigned int csum_index_off = csum_start_off + skb->csum_offset; 704 705 cur_p->app0 |= 1; /* TX Checksum Enabled */ 706 cur_p->app1 = (csum_start_off << 16) | csum_index_off; 707 cur_p->app2 = 0; /* initial checksum seed */ 708 } 709 710 cur_p->app0 |= STS_CTRL_APP0_SOP; 711 cur_p->len = skb_headlen(skb); 712 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len, 713 DMA_TO_DEVICE); 714 cur_p->app4 = (unsigned long)skb; 715 716 for (ii = 0; ii < num_frag; ii++) { 717 lp->tx_bd_tail++; 718 if (lp->tx_bd_tail >= TX_BD_NUM) 719 lp->tx_bd_tail = 0; 720 721 cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; 722 cur_p->phys = dma_map_single(ndev->dev.parent, 723 skb_frag_address(frag), 724 skb_frag_size(frag), DMA_TO_DEVICE); 725 cur_p->len = skb_frag_size(frag); 726 cur_p->app0 = 0; 727 frag++; 728 } 729 cur_p->app0 |= STS_CTRL_APP0_EOP; 730 731 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; 732 lp->tx_bd_tail++; 733 if (lp->tx_bd_tail >= TX_BD_NUM) 734 lp->tx_bd_tail = 0; 735 736 skb_tx_timestamp(skb); 737 738 /* Kick off the transfer */ 739 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */ 740 741 return NETDEV_TX_OK; 742} 743 744 745static void ll_temac_recv(struct net_device *ndev) 746{ 747 struct temac_local *lp = netdev_priv(ndev); 748 struct sk_buff *skb, *new_skb; 749 unsigned int bdstat; 750 struct cdmac_bd *cur_p; 751 dma_addr_t tail_p; 752 int length; 753 unsigned long flags; 754 755 spin_lock_irqsave(&lp->rx_lock, flags); 756 757 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci; 758 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 759 760 bdstat = cur_p->app0; 761 while ((bdstat & STS_CTRL_APP0_CMPLT)) { 762 763 skb = lp->rx_skb[lp->rx_bd_ci]; 764 length = cur_p->app4 & 0x3FFF; 765 766 dma_unmap_single(ndev->dev.parent, cur_p->phys, length, 767 DMA_FROM_DEVICE); 768 769 skb_put(skb, length); 770 skb->protocol = eth_type_trans(skb, ndev); 771 skb_checksum_none_assert(skb); 772 773 /* if we're doing rx csum offload, set it up */ 774 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) && 775 (skb->protocol == __constant_htons(ETH_P_IP)) && 776 (skb->len > 64)) { 777 778 skb->csum = cur_p->app3 & 0xFFFF; 779 skb->ip_summed = CHECKSUM_COMPLETE; 780 } 781 782 if (!skb_defer_rx_timestamp(skb)) 783 netif_rx(skb); 784 785 ndev->stats.rx_packets++; 786 ndev->stats.rx_bytes += length; 787 788 new_skb = netdev_alloc_skb_ip_align(ndev, 789 XTE_MAX_JUMBO_FRAME_SIZE); 790 if (!new_skb) { 791 spin_unlock_irqrestore(&lp->rx_lock, flags); 792 return; 793 } 794 795 cur_p->app0 = STS_CTRL_APP0_IRQONEND; 796 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data, 797 XTE_MAX_JUMBO_FRAME_SIZE, 798 DMA_FROM_DEVICE); 799 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE; 800 lp->rx_skb[lp->rx_bd_ci] = new_skb; 801 802 lp->rx_bd_ci++; 803 if (lp->rx_bd_ci >= RX_BD_NUM) 804 lp->rx_bd_ci = 0; 805 806 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 807 bdstat = cur_p->app0; 808 } 809 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p); 810 811 spin_unlock_irqrestore(&lp->rx_lock, flags); 812} 813 814static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev) 815{ 816 struct net_device *ndev = _ndev; 817 struct temac_local *lp = netdev_priv(ndev); 818 unsigned int status; 819 820 status = lp->dma_in(lp, TX_IRQ_REG); 821 lp->dma_out(lp, TX_IRQ_REG, status); 822 823 if (status & (IRQ_COAL | IRQ_DLY)) 824 temac_start_xmit_done(lp->ndev); 825 if (status & 0x080) 826 dev_err(&ndev->dev, "DMA error 0x%x\n", status); 827 828 return IRQ_HANDLED; 829} 830 831static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev) 832{ 833 struct net_device *ndev = _ndev; 834 struct temac_local *lp = netdev_priv(ndev); 835 unsigned int status; 836 837 /* Read and clear the status registers */ 838 status = lp->dma_in(lp, RX_IRQ_REG); 839 lp->dma_out(lp, RX_IRQ_REG, status); 840 841 if (status & (IRQ_COAL | IRQ_DLY)) 842 ll_temac_recv(lp->ndev); 843 844 return IRQ_HANDLED; 845} 846 847static int temac_open(struct net_device *ndev) 848{ 849 struct temac_local *lp = netdev_priv(ndev); 850 int rc; 851 852 dev_dbg(&ndev->dev, "temac_open()\n"); 853 854 if (lp->phy_node) { 855 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 856 temac_adjust_link, 0, 0); 857 if (!lp->phy_dev) { 858 dev_err(lp->dev, "of_phy_connect() failed\n"); 859 return -ENODEV; 860 } 861 862 phy_start(lp->phy_dev); 863 } 864 865 temac_device_reset(ndev); 866 867 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev); 868 if (rc) 869 goto err_tx_irq; 870 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev); 871 if (rc) 872 goto err_rx_irq; 873 874 return 0; 875 876 err_rx_irq: 877 free_irq(lp->tx_irq, ndev); 878 err_tx_irq: 879 if (lp->phy_dev) 880 phy_disconnect(lp->phy_dev); 881 lp->phy_dev = NULL; 882 dev_err(lp->dev, "request_irq() failed\n"); 883 return rc; 884} 885 886static int temac_stop(struct net_device *ndev) 887{ 888 struct temac_local *lp = netdev_priv(ndev); 889 890 dev_dbg(&ndev->dev, "temac_close()\n"); 891 892 free_irq(lp->tx_irq, ndev); 893 free_irq(lp->rx_irq, ndev); 894 895 if (lp->phy_dev) 896 phy_disconnect(lp->phy_dev); 897 lp->phy_dev = NULL; 898 899 temac_dma_bd_release(ndev); 900 901 return 0; 902} 903 904#ifdef CONFIG_NET_POLL_CONTROLLER 905static void 906temac_poll_controller(struct net_device *ndev) 907{ 908 struct temac_local *lp = netdev_priv(ndev); 909 910 disable_irq(lp->tx_irq); 911 disable_irq(lp->rx_irq); 912 913 ll_temac_rx_irq(lp->tx_irq, ndev); 914 ll_temac_tx_irq(lp->rx_irq, ndev); 915 916 enable_irq(lp->tx_irq); 917 enable_irq(lp->rx_irq); 918} 919#endif 920 921static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 922{ 923 struct temac_local *lp = netdev_priv(ndev); 924 925 if (!netif_running(ndev)) 926 return -EINVAL; 927 928 if (!lp->phy_dev) 929 return -EINVAL; 930 931 return phy_mii_ioctl(lp->phy_dev, rq, cmd); 932} 933 934static const struct net_device_ops temac_netdev_ops = { 935 .ndo_open = temac_open, 936 .ndo_stop = temac_stop, 937 .ndo_start_xmit = temac_start_xmit, 938 .ndo_set_mac_address = temac_set_mac_address, 939 .ndo_validate_addr = eth_validate_addr, 940 .ndo_do_ioctl = temac_ioctl, 941#ifdef CONFIG_NET_POLL_CONTROLLER 942 .ndo_poll_controller = temac_poll_controller, 943#endif 944}; 945 946/* --------------------------------------------------------------------- 947 * SYSFS device attributes 948 */ 949static ssize_t temac_show_llink_regs(struct device *dev, 950 struct device_attribute *attr, char *buf) 951{ 952 struct net_device *ndev = dev_get_drvdata(dev); 953 struct temac_local *lp = netdev_priv(ndev); 954 int i, len = 0; 955 956 for (i = 0; i < 0x11; i++) 957 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i), 958 (i % 8) == 7 ? "\n" : " "); 959 len += sprintf(buf + len, "\n"); 960 961 return len; 962} 963 964static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL); 965 966static struct attribute *temac_device_attrs[] = { 967 &dev_attr_llink_regs.attr, 968 NULL, 969}; 970 971static const struct attribute_group temac_attr_group = { 972 .attrs = temac_device_attrs, 973}; 974 975/* ethtool support */ 976static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd) 977{ 978 struct temac_local *lp = netdev_priv(ndev); 979 return phy_ethtool_gset(lp->phy_dev, cmd); 980} 981 982static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd) 983{ 984 struct temac_local *lp = netdev_priv(ndev); 985 return phy_ethtool_sset(lp->phy_dev, cmd); 986} 987 988static int temac_nway_reset(struct net_device *ndev) 989{ 990 struct temac_local *lp = netdev_priv(ndev); 991 return phy_start_aneg(lp->phy_dev); 992} 993 994static const struct ethtool_ops temac_ethtool_ops = { 995 .get_settings = temac_get_settings, 996 .set_settings = temac_set_settings, 997 .nway_reset = temac_nway_reset, 998 .get_link = ethtool_op_get_link, 999 .get_ts_info = ethtool_op_get_ts_info, 1000}; 1001 1002static int temac_of_probe(struct platform_device *op) 1003{ 1004 struct device_node *np; 1005 struct temac_local *lp; 1006 struct net_device *ndev; 1007 const void *addr; 1008 __be32 *p; 1009 int size, rc = 0; 1010 1011 /* Init network device structure */ 1012 ndev = alloc_etherdev(sizeof(*lp)); 1013 if (!ndev) 1014 return -ENOMEM; 1015 1016 ether_setup(ndev); 1017 dev_set_drvdata(&op->dev, ndev); 1018 SET_NETDEV_DEV(ndev, &op->dev); 1019 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ 1020 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST; 1021 ndev->netdev_ops = &temac_netdev_ops; 1022 ndev->ethtool_ops = &temac_ethtool_ops; 1023#if 0 1024 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */ 1025 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */ 1026 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */ 1027 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */ 1028 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */ 1029 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */ 1030 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */ 1031 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */ 1032 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */ 1033 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */ 1034 ndev->features |= NETIF_F_LRO; /* large receive offload */ 1035#endif 1036 1037 /* setup temac private info structure */ 1038 lp = netdev_priv(ndev); 1039 lp->ndev = ndev; 1040 lp->dev = &op->dev; 1041 lp->options = XTE_OPTION_DEFAULTS; 1042 spin_lock_init(&lp->rx_lock); 1043 mutex_init(&lp->indirect_mutex); 1044 1045 /* map device registers */ 1046 lp->regs = of_iomap(op->dev.of_node, 0); 1047 if (!lp->regs) { 1048 dev_err(&op->dev, "could not map temac regs.\n"); 1049 goto nodev; 1050 } 1051 1052 /* Setup checksum offload, but default to off if not specified */ 1053 lp->temac_features = 0; 1054 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL); 1055 if (p && be32_to_cpu(*p)) { 1056 lp->temac_features |= TEMAC_FEATURE_TX_CSUM; 1057 /* Can checksum TCP/UDP over IPv4. */ 1058 ndev->features |= NETIF_F_IP_CSUM; 1059 } 1060 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL); 1061 if (p && be32_to_cpu(*p)) 1062 lp->temac_features |= TEMAC_FEATURE_RX_CSUM; 1063 1064 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ 1065 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0); 1066 if (!np) { 1067 dev_err(&op->dev, "could not find DMA node\n"); 1068 goto err_iounmap; 1069 } 1070 1071 /* Setup the DMA register accesses, could be DCR or memory mapped */ 1072 if (temac_dcr_setup(lp, op, np)) { 1073 1074 /* no DCR in the device tree, try non-DCR */ 1075 lp->sdma_regs = of_iomap(np, 0); 1076 if (lp->sdma_regs) { 1077 lp->dma_in = temac_dma_in32; 1078 lp->dma_out = temac_dma_out32; 1079 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs); 1080 } else { 1081 dev_err(&op->dev, "unable to map DMA registers\n"); 1082 of_node_put(np); 1083 goto err_iounmap; 1084 } 1085 } 1086 1087 lp->rx_irq = irq_of_parse_and_map(np, 0); 1088 lp->tx_irq = irq_of_parse_and_map(np, 1); 1089 1090 of_node_put(np); /* Finished with the DMA node; drop the reference */ 1091 1092 if (!lp->rx_irq || !lp->tx_irq) { 1093 dev_err(&op->dev, "could not determine irqs\n"); 1094 rc = -ENOMEM; 1095 goto err_iounmap_2; 1096 } 1097 1098 1099 /* Retrieve the MAC address */ 1100 addr = of_get_property(op->dev.of_node, "local-mac-address", &size); 1101 if ((!addr) || (size != 6)) { 1102 dev_err(&op->dev, "could not find MAC address\n"); 1103 rc = -ENODEV; 1104 goto err_iounmap_2; 1105 } 1106 temac_init_mac_address(ndev, (void *)addr); 1107 1108 rc = temac_mdio_setup(lp, op->dev.of_node); 1109 if (rc) 1110 dev_warn(&op->dev, "error registering MDIO bus\n"); 1111 1112 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0); 1113 if (lp->phy_node) 1114 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np); 1115 1116 /* Add the device attributes */ 1117 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group); 1118 if (rc) { 1119 dev_err(lp->dev, "Error creating sysfs files\n"); 1120 goto err_iounmap_2; 1121 } 1122 1123 rc = register_netdev(lp->ndev); 1124 if (rc) { 1125 dev_err(lp->dev, "register_netdev() error (%i)\n", rc); 1126 goto err_register_ndev; 1127 } 1128 1129 return 0; 1130 1131 err_register_ndev: 1132 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); 1133 err_iounmap_2: 1134 if (lp->sdma_regs) 1135 iounmap(lp->sdma_regs); 1136 err_iounmap: 1137 iounmap(lp->regs); 1138 nodev: 1139 free_netdev(ndev); 1140 ndev = NULL; 1141 return rc; 1142} 1143 1144static int temac_of_remove(struct platform_device *op) 1145{ 1146 struct net_device *ndev = dev_get_drvdata(&op->dev); 1147 struct temac_local *lp = netdev_priv(ndev); 1148 1149 temac_mdio_teardown(lp); 1150 unregister_netdev(ndev); 1151 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group); 1152 if (lp->phy_node) 1153 of_node_put(lp->phy_node); 1154 lp->phy_node = NULL; 1155 dev_set_drvdata(&op->dev, NULL); 1156 iounmap(lp->regs); 1157 if (lp->sdma_regs) 1158 iounmap(lp->sdma_regs); 1159 free_netdev(ndev); 1160 return 0; 1161} 1162 1163static struct of_device_id temac_of_match[] = { 1164 { .compatible = "xlnx,xps-ll-temac-1.01.b", }, 1165 { .compatible = "xlnx,xps-ll-temac-2.00.a", }, 1166 { .compatible = "xlnx,xps-ll-temac-2.02.a", }, 1167 { .compatible = "xlnx,xps-ll-temac-2.03.a", }, 1168 {}, 1169}; 1170MODULE_DEVICE_TABLE(of, temac_of_match); 1171 1172static struct platform_driver temac_of_driver = { 1173 .probe = temac_of_probe, 1174 .remove = temac_of_remove, 1175 .driver = { 1176 .owner = THIS_MODULE, 1177 .name = "xilinx_temac", 1178 .of_match_table = temac_of_match, 1179 }, 1180}; 1181 1182module_platform_driver(temac_of_driver); 1183 1184MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver"); 1185MODULE_AUTHOR("Yoshio Kashiwagi"); 1186MODULE_LICENSE("GPL"); 1187