pxaficp_ir.c revision 5a0e3ad6af8660be21ca98a971cd00f331318c05
16f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* 26f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * linux/drivers/net/irda/pxaficp_ir.c 36f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * 46f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Based on sa1100_ir.c by Russell King 56f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * 66f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Changes copyright (C) 2003-2005 MontaVista Software, Inc. 76f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * 86f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * This program is free software; you can redistribute it and/or modify 96f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * it under the terms of the GNU General Public License version 2 as 106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * published by the Free Software Foundation. 116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * 126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Infra-red driver (SIR/FIR) for the PXA2xx embedded microprocessor 136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * 146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/module.h> 166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/netdevice.h> 17f6a2629353718e588820b731af43a445b6f35648Alexander Beregalov#include <linux/etherdevice.h> 18d052d1beff706920e82c5d55006b08e256b5df09Russell King#include <linux/platform_device.h> 1982d553c67deef92c6c84ecb70afc56e99863060cRussell King#include <linux/clk.h> 20c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut#include <linux/gpio.h> 215a0e3ad6af8660be21ca98a971cd00f331318c05Tejun Heo#include <linux/slab.h> 226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <net/irda/irda.h> 246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <net/irda/irmod.h> 256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <net/irda/wrapper.h> 266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <net/irda/irda_device.h> 276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 28dcea83adc666061864b82c96e059dffe7268b512Russell King#include <mach/dma.h> 29a09e64fbc0094e3073dbb09c3b4bfe4ab669244bRussell King#include <mach/irda.h> 3002f652626a8f23e513877cb751c8ea533739c28fEric Miao#include <mach/regs-uart.h> 315bf3df3f00f507119a26ba0780aa8799e741615cEric Miao#include <mach/regs-ost.h> 326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 33b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define FICP __REG(0x40800000) /* Start of FICP area */ 34b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ 35b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ 36b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ 37b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICDR __REG(0x4080000c) /* ICP Data Register */ 38b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ 39b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ 40b40ddf575883ceca303906556bcd0cff5c284fefEric Miao 41b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR0_AME (1 << 7) /* Address match enable */ 42b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ 43b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ 44b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR0_RXE (1 << 4) /* Receive enable */ 45b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR0_TXE (1 << 3) /* Transmit enable */ 46b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ 47b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR0_LBM (1 << 1) /* Loopback mode */ 48b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR0_ITR (1 << 0) /* IrDA transmission */ 49b40ddf575883ceca303906556bcd0cff5c284fefEric Miao 50b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ 51b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ 52b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ 53b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ 54b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ 55b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ 56b40ddf575883ceca303906556bcd0cff5c284fefEric Miao 57b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#ifdef CONFIG_PXA27x 58b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ 59b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#endif 60b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR0_FRE (1 << 5) /* Framing error */ 61b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ 62b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ 63b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR0_RAB (1 << 2) /* Receiver abort */ 64b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ 65b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ 66b40ddf575883ceca303906556bcd0cff5c284fefEric Miao 67b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ 68b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR1_CRE (1 << 5) /* CRC error */ 69b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR1_EOF (1 << 4) /* End of frame */ 70b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ 71b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ 72b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ 73b40ddf575883ceca303906556bcd0cff5c284fefEric Miao#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ 746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_RXPL_NEG_IS_ZERO (1<<4) 766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_RXPL_POS_IS_ZERO 0x0 776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_TXPL_NEG_IS_ZERO (1<<3) 786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_TXPL_POS_IS_ZERO 0x0 796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_XMODE_PULSE_1_6 (1<<2) 806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_XMODE_PULSE_3_16 0x0 816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_RCVEIR_IR_MODE (1<<1) 826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_RCVEIR_UART_MODE 0x0 836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_XMITIR_IR_MODE (1<<0) 846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_XMITIR_UART_MODE 0x0 856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_IR_RECEIVE_ON (\ 876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_RXPL_NEG_IS_ZERO | \ 886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_TXPL_POS_IS_ZERO | \ 896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_XMODE_PULSE_3_16 | \ 906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_RCVEIR_IR_MODE | \ 916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_XMITIR_UART_MODE) 926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_IR_TRANSMIT_ON (\ 946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_RXPL_NEG_IS_ZERO | \ 956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_TXPL_POS_IS_ZERO | \ 966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_XMODE_PULSE_3_16 | \ 976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_RCVEIR_UART_MODE | \ 986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre IrSR_XMITIR_IR_MODE) 996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestruct pxa_irda { 1016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int speed; 1026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int newspeed; 1036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned long last_oscr; 1046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned char *dma_rx_buff; 1066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned char *dma_tx_buff; 1076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dma_addr_t dma_rx_buff_phy; 1086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dma_addr_t dma_tx_buff_phy; 1096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned int dma_tx_buff_len; 1106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int txdma; 1116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int rxdma; 1126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct irlap_cb *irlap; 1146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct qos_info qos; 1156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre iobuff_t tx_buff; 1176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre iobuff_t rx_buff; 1186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct device *dev; 1206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxaficp_platform_data *pdata; 12182d553c67deef92c6c84ecb70afc56e99863060cRussell King struct clk *fir_clk; 12282d553c67deef92c6c84ecb70afc56e99863060cRussell King struct clk *sir_clk; 12382d553c67deef92c6c84ecb70afc56e99863060cRussell King struct clk *cur_clk; 1246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}; 1256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 12682d553c67deef92c6c84ecb70afc56e99863060cRussell Kingstatic inline void pxa_irda_disable_clk(struct pxa_irda *si) 12782d553c67deef92c6c84ecb70afc56e99863060cRussell King{ 12882d553c67deef92c6c84ecb70afc56e99863060cRussell King if (si->cur_clk) 12982d553c67deef92c6c84ecb70afc56e99863060cRussell King clk_disable(si->cur_clk); 13082d553c67deef92c6c84ecb70afc56e99863060cRussell King si->cur_clk = NULL; 13182d553c67deef92c6c84ecb70afc56e99863060cRussell King} 13282d553c67deef92c6c84ecb70afc56e99863060cRussell King 13382d553c67deef92c6c84ecb70afc56e99863060cRussell Kingstatic inline void pxa_irda_enable_firclk(struct pxa_irda *si) 13482d553c67deef92c6c84ecb70afc56e99863060cRussell King{ 13582d553c67deef92c6c84ecb70afc56e99863060cRussell King si->cur_clk = si->fir_clk; 13682d553c67deef92c6c84ecb70afc56e99863060cRussell King clk_enable(si->fir_clk); 13782d553c67deef92c6c84ecb70afc56e99863060cRussell King} 13882d553c67deef92c6c84ecb70afc56e99863060cRussell King 13982d553c67deef92c6c84ecb70afc56e99863060cRussell Kingstatic inline void pxa_irda_enable_sirclk(struct pxa_irda *si) 14082d553c67deef92c6c84ecb70afc56e99863060cRussell King{ 14182d553c67deef92c6c84ecb70afc56e99863060cRussell King si->cur_clk = si->sir_clk; 14282d553c67deef92c6c84ecb70afc56e99863060cRussell King clk_enable(si->sir_clk); 14382d553c67deef92c6c84ecb70afc56e99863060cRussell King} 14482d553c67deef92c6c84ecb70afc56e99863060cRussell King 1456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IS_FIR(si) ((si)->speed >= 4000000) 1476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IRDA_FRAME_SIZE_LIMIT 2047 1486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreinline static void pxa_irda_fir_dma_rx_start(struct pxa_irda *si) 1506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 1516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(si->rxdma) = DCSR_NODESC; 1526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DSADR(si->rxdma) = __PREG(ICDR); 1536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DTADR(si->rxdma) = si->dma_rx_buff_phy; 1546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCMD(si->rxdma) = DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_WIDTH1 | DCMD_BURST32 | IRDA_FRAME_SIZE_LIMIT; 1556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(si->rxdma) |= DCSR_RUN; 1566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 1576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreinline static void pxa_irda_fir_dma_tx_start(struct pxa_irda *si) 1596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 1606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(si->txdma) = DCSR_NODESC; 1616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DSADR(si->txdma) = si->dma_tx_buff_phy; 1626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DTADR(si->txdma) = __PREG(ICDR); 1636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCMD(si->txdma) = DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_ENDIRQEN | DCMD_WIDTH1 | DCMD_BURST32 | si->dma_tx_buff_len; 1646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(si->txdma) |= DCSR_RUN; 1656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 1666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* 168c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut * Set the IrDA communications mode. 169c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut */ 170c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasutstatic void pxa_irda_set_mode(struct pxa_irda *si, int mode) 171c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut{ 172c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut if (si->pdata->transceiver_mode) 173c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut si->pdata->transceiver_mode(si->dev, mode); 174c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut else { 175c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut if (gpio_is_valid(si->pdata->gpio_pwdown)) 176c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut gpio_set_value(si->pdata->gpio_pwdown, 177c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut !(mode & IR_OFF) ^ 178c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut !si->pdata->gpio_pwdown_inverted); 179c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut pxa2xx_transceiver_mode(si->dev, mode); 180c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut } 181c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut} 182c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut 183c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut/* 1846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Set the IrDA communications speed. 1856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 1866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_set_speed(struct pxa_irda *si, int speed) 1876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 1886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned long flags; 1896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned int divisor; 1906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre switch (speed) { 1926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case 9600: case 19200: case 38400: 1936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case 57600: case 115200: 1946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* refer to PXA250/210 Developer's Manual 10-7 */ 1966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* BaudRate = 14.7456 MHz / (16*Divisor) */ 1976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre divisor = 14745600 / (16 * speed); 1986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 1996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre local_irq_save(flags); 2006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (IS_FIR(si)) { 2026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* stop RX DMA */ 2036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(si->rxdma) &= ~DCSR_RUN; 2046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* disable FICP */ 2056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = 0; 20682d553c67deef92c6c84ecb70afc56e99863060cRussell King pxa_irda_disable_clk(si); 2076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* set board transceiver to SIR mode */ 209c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut pxa_irda_set_mode(si, IR_SIRMODE); 2106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* enable the STUART clock */ 21282d553c67deef92c6c84ecb70afc56e99863060cRussell King pxa_irda_enable_sirclk(si); 2136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 2146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* disable STUART first */ 2166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STIER = 0; 2176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* access DLL & DLH */ 2196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STLCR |= LCR_DLAB; 2206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STDLL = divisor & 0xff; 2216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STDLH = divisor >> 8; 2226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STLCR &= ~LCR_DLAB; 2236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->speed = speed; 2256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6; 2266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE; 2276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre local_irq_restore(flags); 2296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 2306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case 4000000: 2326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre local_irq_save(flags); 2336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* disable STUART */ 2356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STIER = 0; 2366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STISR = 0; 23782d553c67deef92c6c84ecb70afc56e99863060cRussell King pxa_irda_disable_clk(si); 2386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* disable FICP first */ 2406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = 0; 2416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* set board transceiver to FIR mode */ 243c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut pxa_irda_set_mode(si, IR_FIRMODE); 2446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* enable the FICP clock */ 24682d553c67deef92c6c84ecb70afc56e99863060cRussell King pxa_irda_enable_firclk(si); 2476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->speed = speed; 2496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_fir_dma_rx_start(si); 2506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = ICCR0_ITR | ICCR0_RXE; 2516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre local_irq_restore(flags); 2536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 2546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre default: 2566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return -EINVAL; 2576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 2586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return 0; 2606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 2616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* SIR interrupt service routine. */ 2637d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id) 2646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 2656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct net_device *dev = dev_id; 2666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si = netdev_priv(dev); 2676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int iir, lsr, data; 2686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre iir = STIIR; 2706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre switch (iir & 0x0F) { 2726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case 0x06: /* Receiver Line Status */ 2736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre lsr = STLSR; 2746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre while (lsr & LSR_FIFOE) { 2756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre data = STRBR; 2766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (lsr & (LSR_OE | LSR_PE | LSR_FE | LSR_BI)) { 2776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: sir receiving error\n"); 278af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_errors++; 2796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (lsr & LSR_FE) 280af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_frame_errors++; 2816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (lsr & LSR_OE) 282af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_fifo_errors++; 2836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } else { 284af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_bytes++; 285af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger async_unwrap_char(dev, &dev->stats, 286af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger &si->rx_buff, data); 2876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 2886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre lsr = STLSR; 2896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 2906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->last_oscr = OSCR; 2916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 2926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case 0x04: /* Received Data Available */ 2946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* forth through */ 2956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 2966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case 0x0C: /* Character Timeout Indication */ 2976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre do { 298af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_bytes++; 299af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger async_unwrap_char(dev, &dev->stats, &si->rx_buff, STRBR); 3006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } while (STLSR & LSR_DR); 3016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->last_oscr = OSCR; 3026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 3036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case 0x02: /* Transmit FIFO Data Request */ 3056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre while ((si->tx_buff.len) && (STLSR & LSR_TDRQ)) { 3066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STTHR = *si->tx_buff.data++; 3076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->tx_buff.len -= 1; 3086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 3096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->tx_buff.len == 0) { 311af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.tx_packets++; 312af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head; 3136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* We need to ensure that the transmitter has finished. */ 3156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre while ((STLSR & LSR_TEMT) == 0) 3166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre cpu_relax(); 3176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->last_oscr = OSCR; 3186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* 3206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Ok, we've finished transmitting. Now enable 3216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * the receiver. Sometimes we get a receive IRQ 3226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * immediately after a transmit... 3236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 3246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->newspeed) { 3256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_set_speed(si, si->newspeed); 3266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->newspeed = 0; 3276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } else { 3286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* enable IR Receiver, disable IR Transmitter */ 3296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6; 3306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* enable STUART and receive interrupts */ 3316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE; 3326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 3336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* I'm hungry! */ 3346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre netif_wake_queue(dev); 3356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 3366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 3376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 3386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return IRQ_HANDLED; 3406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 3416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* FIR Receive DMA interrupt handler */ 3437d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic void pxa_irda_fir_dma_rx_irq(int channel, void *data) 3446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 3456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int dcsr = DCSR(channel); 3466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(channel) = dcsr & ~DCSR_RUN; 3486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: fir rx dma bus error %#x\n", dcsr); 3506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 3516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* FIR Transmit DMA interrupt handler */ 3537d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic void pxa_irda_fir_dma_tx_irq(int channel, void *data) 3546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 3556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct net_device *dev = data; 3566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si = netdev_priv(dev); 3576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int dcsr; 3586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dcsr = DCSR(channel); 3606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(channel) = dcsr & ~DCSR_RUN; 3616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (dcsr & DCSR_ENDINTR) { 363af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.tx_packets++; 364af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.tx_bytes += si->dma_tx_buff_len; 3656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } else { 366af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.tx_errors++; 3676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 3686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre while (ICSR1 & ICSR1_TBY) 3706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre cpu_relax(); 3716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->last_oscr = OSCR; 3726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* 3746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * HACK: It looks like the TBY bit is dropped too soon. 3756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Without this delay things break. 3766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 3776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre udelay(120); 3786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->newspeed) { 3806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_set_speed(si, si->newspeed); 3816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->newspeed = 0; 3826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } else { 3839a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski int i = 64; 3849a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski 3856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = 0; 3866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_fir_dma_rx_start(si); 3879a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski while ((ICSR1 & ICSR1_RNE) && i--) 3889a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski (void)ICDR; 3896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = ICCR0_ITR | ICCR0_RXE; 3909a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski 3919a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski if (i < 0) 3929a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n"); 3936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 3946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre netif_wake_queue(dev); 3956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 3966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 3976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* EIF(Error in FIFO/End in Frame) handler for FIR */ 3989a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetskistatic void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev, int icsr0) 3996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 4006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned int len, stat, data; 4016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* Get the current data position. */ 4036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre len = DTADR(si->rxdma) - si->dma_rx_buff_phy; 4046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre do { 4066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* Read Status, and then Data. */ 4076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre stat = ICSR1; 4086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre rmb(); 4096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre data = ICDR; 4106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (stat & (ICSR1_CRE | ICSR1_ROR)) { 412af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_errors++; 4136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (stat & ICSR1_CRE) { 4146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: fir receive CRC error\n"); 415af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_crc_errors++; 4166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 4176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (stat & ICSR1_ROR) { 4186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: fir receive overrun\n"); 419af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_over_errors++; 4206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 4216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } else { 4226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->dma_rx_buff[len++] = data; 4236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 4246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* If we hit the end of frame, there's no point in continuing. */ 4256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (stat & ICSR1_EOF) 4266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 4276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } while (ICSR0 & ICSR0_EIF); 4286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (stat & ICSR1_EOF) { 4306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* end of frame. */ 4319a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski struct sk_buff *skb; 4329a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski 4339a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski if (icsr0 & ICSR0_FRE) { 4349a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski printk(KERN_ERR "pxa_ir: dropping erroneous frame\n"); 435af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_dropped++; 4369a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski return; 4379a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski } 4389a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski 4399a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski skb = alloc_skb(len+1,GFP_ATOMIC); 4406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (!skb) { 4416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_ERR "pxa_ir: fir out of memory for receive skb\n"); 442af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_dropped++; 4436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return; 4446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 4456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* Align IP header to 20 bytes */ 4476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre skb_reserve(skb, 1); 44827d7ff46a3498d3debc6ba68fb8014c702b81170Arnaldo Carvalho de Melo skb_copy_to_linear_data(skb, si->dma_rx_buff, len); 4496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre skb_put(skb, len); 4506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* Feed it to IrLAP */ 4526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre skb->dev = dev; 453459a98ed881802dee55897441bc7f77af614368eArnaldo Carvalho de Melo skb_reset_mac_header(skb); 4546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre skb->protocol = htons(ETH_P_IRDA); 4556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre netif_rx(skb); 4566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 457af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_packets++; 458af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_bytes += len; 4596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 4606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 4616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* FIR interrupt handler */ 4637d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id) 4646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 4656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct net_device *dev = dev_id; 4666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si = netdev_priv(dev); 4679a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski int icsr0, i = 64; 4686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* stop RX DMA */ 4706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(si->rxdma) &= ~DCSR_RUN; 4716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->last_oscr = OSCR; 4726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre icsr0 = ICSR0; 4736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (icsr0 & (ICSR0_FRE | ICSR0_RAB)) { 4756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (icsr0 & ICSR0_FRE) { 4766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: fir receive frame error\n"); 477af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_frame_errors++; 4786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } else { 4796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: fir receive abort\n"); 480af0490810cfa159b4894ddecfc5eb2e4432fb976Stephen Hemminger dev->stats.rx_errors++; 4816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 4826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICSR0 = icsr0 & (ICSR0_FRE | ICSR0_RAB); 4836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 4846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (icsr0 & ICSR0_EIF) { 4866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* An error in FIFO occured, or there is a end of frame */ 4879a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski pxa_irda_fir_irq_eif(si, dev, icsr0); 4886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 4896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = 0; 4916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_fir_dma_rx_start(si); 4929a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski while ((ICSR1 & ICSR1_RNE) && i--) 4939a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski (void)ICDR; 4946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = ICCR0_ITR | ICCR0_RXE; 4956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 4969a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski if (i < 0) 4979a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n"); 4989a4d93d49d140c196020a1bae339efcf211cac03Guennadi Liakhovetski 4996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return IRQ_HANDLED; 5006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 5016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* hard_xmit interface of irda device */ 5036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) 5046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 5056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si = netdev_priv(dev); 5066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int speed = irda_get_next_speed(skb); 5076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* 5096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Does this packet contain a request to change the interface 5106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * speed? If so, remember it until we complete the transmission 5116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * of this frame. 5126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 5136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (speed != si->speed && speed != -1) 5146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->newspeed = speed; 5156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* 5176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * If this is an empty frame, we can bypass a lot. 5186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 5196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (skb->len == 0) { 5206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->newspeed) { 5216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->newspeed = 0; 5226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_set_speed(si, speed); 5236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 5246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dev_kfree_skb(skb); 5256ed106549d17474ca17a16057f4c0ed4eba5a7caPatrick McHardy return NETDEV_TX_OK; 5266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 5276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre netif_stop_queue(dev); 5296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (!IS_FIR(si)) { 5316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->tx_buff.data = si->tx_buff.head; 5326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, si->tx_buff.truesize); 5336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* Disable STUART interrupts and switch to transmit mode. */ 5356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STIER = 0; 5366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STISR = IrSR_IR_TRANSMIT_ON | IrSR_XMODE_PULSE_1_6; 5376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* enable STUART and transmit interrupts */ 5396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STIER = IER_UUE | IER_TIE; 5406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } else { 5416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned long mtt = irda_get_mtt(skb); 5426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->dma_tx_buff_len = skb->len; 544d626f62b11e00c16e81e4308ab93d3f13551812aArnaldo Carvalho de Melo skb_copy_from_linear_data(skb, si->dma_tx_buff, skb->len); 5456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (mtt) 5476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre while ((unsigned)(OSCR - si->last_oscr)/4 < mtt) 5486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre cpu_relax(); 5496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* stop RX DMA, disable FICP */ 5516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(si->rxdma) &= ~DCSR_RUN; 5526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = 0; 5536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_fir_dma_tx_start(si); 5556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = ICCR0_ITR | ICCR0_TXE; 5566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 5576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dev_kfree_skb(skb); 5596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dev->trans_start = jiffies; 5606ed106549d17474ca17a16057f4c0ed4eba5a7caPatrick McHardy return NETDEV_TX_OK; 5616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 5626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) 5646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 5656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct if_irda_req *rq = (struct if_irda_req *)ifreq; 5666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si = netdev_priv(dev); 5676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int ret; 5686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre switch (cmd) { 5706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case SIOCSBANDWIDTH: 5716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ret = -EPERM; 5726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (capable(CAP_NET_ADMIN)) { 5736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* 5746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * We are unable to set the speed if the 5756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * device is not running. 5766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 5776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (netif_running(dev)) { 5786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ret = pxa_irda_set_speed(si, 5796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre rq->ifr_baudrate); 5806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } else { 5816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_INFO "pxa_ir: SIOCSBANDWIDTH: !netif_running\n"); 5826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ret = 0; 5836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 5846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 5856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 5866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case SIOCSMEDIABUSY: 5886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ret = -EPERM; 5896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (capable(CAP_NET_ADMIN)) { 5906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre irda_device_set_media_busy(dev, TRUE); 5916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ret = 0; 5926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 5936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 5946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 5956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre case SIOCGRECEIVING: 5966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ret = 0; 5976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre rq->ifr_receiving = IS_FIR(si) ? 0 5986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre : si->rx_buff.state != OUTSIDE_FRAME; 5996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 6006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre default: 6026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ret = -EOPNOTSUPP; 6036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre break; 6046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 6056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return ret; 6076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 6086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic void pxa_irda_startup(struct pxa_irda *si) 6106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 6116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* Disable STUART interrupts */ 6126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STIER = 0; 6136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* enable STUART interrupt to the processor */ 6146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STMCR = MCR_OUT2; 6156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* configure SIR frame format: StartBit - Data 7 ... Data 0 - Stop Bit */ 6166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STLCR = LCR_WLS0 | LCR_WLS1; 6176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* enable FIFO, we use FIFO to improve performance */ 6186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STFCR = FCR_TRFIFOE | FCR_ITL_32; 6196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* disable FICP */ 6216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = 0; 6226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* configure FICP ICCR2 */ 6236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR2 = ICCR2_TXP | ICCR2_TRIG_32; 6246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* configure DMAC */ 62687f3dd77974cba1ba0798abd741ede50f56b3eb3Eric Miao DRCMR(17) = si->rxdma | DRCMR_MAPVLD; 62787f3dd77974cba1ba0798abd741ede50f56b3eb3Eric Miao DRCMR(18) = si->txdma | DRCMR_MAPVLD; 6286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* force SIR reinitialization */ 6306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->speed = 4000000; 6316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_set_speed(si, 9600); 6326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: irda startup\n"); 6346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 6356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic void pxa_irda_shutdown(struct pxa_irda *si) 6376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 6386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned long flags; 6396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre local_irq_save(flags); 6416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* disable STUART and interrupt */ 6436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STIER = 0; 6446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* disable STUART SIR mode */ 6456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre STISR = 0; 6466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* disable DMA */ 6486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(si->txdma) &= ~DCSR_RUN; 6496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre DCSR(si->rxdma) &= ~DCSR_RUN; 6506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* disable FICP */ 6516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre ICCR0 = 0; 65282d553c67deef92c6c84ecb70afc56e99863060cRussell King 65382d553c67deef92c6c84ecb70afc56e99863060cRussell King /* disable the STUART or FICP clocks */ 65482d553c67deef92c6c84ecb70afc56e99863060cRussell King pxa_irda_disable_clk(si); 6556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 65687f3dd77974cba1ba0798abd741ede50f56b3eb3Eric Miao DRCMR(17) = 0; 65787f3dd77974cba1ba0798abd741ede50f56b3eb3Eric Miao DRCMR(18) = 0; 6586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre local_irq_restore(flags); 6606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* power off board transceiver */ 662c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut pxa_irda_set_mode(si, IR_OFF); 6636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: irda shutdown\n"); 6656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 6666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_start(struct net_device *dev) 6686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 6696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si = netdev_priv(dev); 6706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int err; 6716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->speed = 9600; 6736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = request_irq(IRQ_STUART, pxa_irda_sir_irq, 0, dev->name, dev); 6756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (err) 6766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_irq1; 6776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = request_irq(IRQ_ICP, pxa_irda_fir_irq, 0, dev->name, dev); 6796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (err) 6806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_irq2; 6816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* 6836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * The interrupt must remain disabled for now. 6846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 6856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre disable_irq(IRQ_STUART); 6866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre disable_irq(IRQ_ICP); 6876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = -EBUSY; 6896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->rxdma = pxa_request_dma("FICP_RX",DMA_PRIO_LOW, pxa_irda_fir_dma_rx_irq, dev); 6906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->rxdma < 0) 6916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_rx_dma; 6926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->txdma = pxa_request_dma("FICP_TX",DMA_PRIO_LOW, pxa_irda_fir_dma_tx_irq, dev); 6946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->txdma < 0) 6956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_tx_dma; 6966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 6976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = -ENOMEM; 6986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->dma_rx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, 6996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre &si->dma_rx_buff_phy, GFP_KERNEL ); 7006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (!si->dma_rx_buff) 7016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_dma_rx_buff; 7026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->dma_tx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, 7046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre &si->dma_tx_buff_phy, GFP_KERNEL ); 7056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (!si->dma_tx_buff) 7066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_dma_tx_buff; 7076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* Setup the serial port for the initial speed. */ 7096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_startup(si); 7106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* 7126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Open a new IrLAP layer instance. 7136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 7146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->irlap = irlap_open(dev, &si->qos, "pxa"); 7156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = -ENOMEM; 7166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (!si->irlap) 7176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_irlap; 7186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* 7206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Now enable the interrupt and start the queue 7216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 7226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre enable_irq(IRQ_STUART); 7236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre enable_irq(IRQ_ICP); 7246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre netif_start_queue(dev); 7256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: irda driver opened\n"); 7276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return 0; 7296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_irlap: 7316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_shutdown(si); 7326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy); 7336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_dma_tx_buff: 7346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy); 7356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_dma_rx_buff: 7366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_free_dma(si->txdma); 7376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_tx_dma: 7386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_free_dma(si->rxdma); 7396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_rx_dma: 7406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre free_irq(IRQ_ICP, dev); 7416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_irq2: 7426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre free_irq(IRQ_STUART, dev); 7436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_irq1: 7446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return err; 7466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 7476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_stop(struct net_device *dev) 7496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 7506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si = netdev_priv(dev); 7516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre netif_stop_queue(dev); 7536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_shutdown(si); 7556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* Stop IrLAP */ 7576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->irlap) { 7586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre irlap_close(si->irlap); 7596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->irlap = NULL; 7606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 7616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre free_irq(IRQ_STUART, dev); 7636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre free_irq(IRQ_ICP, dev); 7646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_free_dma(si->rxdma); 7666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_free_dma(si->txdma); 7676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->dma_rx_buff) 7696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy); 7706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->dma_tx_buff) 7716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy); 7726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre printk(KERN_DEBUG "pxa_ir: irda driver closed\n"); 7746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return 0; 7756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 7766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 777b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovskystatic int pxa_irda_suspend(struct platform_device *_dev, pm_message_t state) 7786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 779b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovsky struct net_device *dev = platform_get_drvdata(_dev); 7806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si; 7816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 78291e1a512291f258746611c18ec4970a81c9f311bRichard Purdie if (dev && netif_running(dev)) { 7836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si = netdev_priv(dev); 7846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre netif_device_detach(dev); 7856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_shutdown(si); 7866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 7876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 7886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return 0; 7896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 7906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 791b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovskystatic int pxa_irda_resume(struct platform_device *_dev) 7926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 793b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovsky struct net_device *dev = platform_get_drvdata(_dev); 7946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si; 7956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 79691e1a512291f258746611c18ec4970a81c9f311bRichard Purdie if (dev && netif_running(dev)) { 7976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si = netdev_priv(dev); 7986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre pxa_irda_startup(si); 7996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre netif_device_attach(dev); 8006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre netif_wake_queue(dev); 8016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 8026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 8036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return 0; 8046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 8056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 8066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 8076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_init_iobuf(iobuff_t *io, int size) 8086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 8096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre io->head = kmalloc(size, GFP_KERNEL | GFP_DMA); 8106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (io->head != NULL) { 8116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre io->truesize = size; 8126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre io->in_frame = FALSE; 8136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre io->state = OUTSIDE_FRAME; 8146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre io->data = io->head; 8156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 8166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return io->head ? 0 : -ENOMEM; 8176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 8186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 819c76ccd6a256004cca1127c9afb5474638fc78b74Alexander Beregalovstatic const struct net_device_ops pxa_irda_netdev_ops = { 820c76ccd6a256004cca1127c9afb5474638fc78b74Alexander Beregalov .ndo_open = pxa_irda_start, 821c76ccd6a256004cca1127c9afb5474638fc78b74Alexander Beregalov .ndo_stop = pxa_irda_stop, 822c76ccd6a256004cca1127c9afb5474638fc78b74Alexander Beregalov .ndo_start_xmit = pxa_irda_hard_xmit, 823c76ccd6a256004cca1127c9afb5474638fc78b74Alexander Beregalov .ndo_do_ioctl = pxa_irda_ioctl, 824c76ccd6a256004cca1127c9afb5474638fc78b74Alexander Beregalov}; 825c76ccd6a256004cca1127c9afb5474638fc78b74Alexander Beregalov 826b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovskystatic int pxa_irda_probe(struct platform_device *pdev) 8276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 8286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct net_device *dev; 8296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si; 8306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unsigned int baudrate_mask; 8316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre int err; 8326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 8336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (!pdev->dev.platform_data) 8346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return -ENODEV; 8356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 8366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = request_mem_region(__PREG(STUART), 0x24, "IrDA") ? 0 : -EBUSY; 8376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (err) 8386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_mem_1; 8396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 8406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = request_mem_region(__PREG(FICP), 0x1c, "IrDA") ? 0 : -EBUSY; 8416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (err) 8426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_mem_2; 8436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 8446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dev = alloc_irdadev(sizeof(struct pxa_irda)); 8456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (!dev) 8466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_mem_3; 8476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 848d2f3ad4cedc00c8ee848e7abe9b2bbc93b9a8c2dMarek Vasut SET_NETDEV_DEV(dev, &pdev->dev); 8496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si = netdev_priv(dev); 8506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->dev = &pdev->dev; 8516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->pdata = pdev->dev.platform_data; 8526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 85382d553c67deef92c6c84ecb70afc56e99863060cRussell King si->sir_clk = clk_get(&pdev->dev, "UARTCLK"); 85482d553c67deef92c6c84ecb70afc56e99863060cRussell King si->fir_clk = clk_get(&pdev->dev, "FICPCLK"); 85582d553c67deef92c6c84ecb70afc56e99863060cRussell King if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) { 85682d553c67deef92c6c84ecb70afc56e99863060cRussell King err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk); 85782d553c67deef92c6c84ecb70afc56e99863060cRussell King goto err_mem_4; 85882d553c67deef92c6c84ecb70afc56e99863060cRussell King } 85982d553c67deef92c6c84ecb70afc56e99863060cRussell King 8606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre /* 8616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Initialise the SIR buffers 8626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */ 8636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = pxa_irda_init_iobuf(&si->rx_buff, 14384); 8646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (err) 8656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_mem_4; 8666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = pxa_irda_init_iobuf(&si->tx_buff, 4000); 8676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (err) 8686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre goto err_mem_5; 8696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 870c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut if (gpio_is_valid(si->pdata->gpio_pwdown)) { 871c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut err = gpio_request(si->pdata->gpio_pwdown, "IrDA switch"); 872c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut if (err) 873c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut goto err_startup; 874c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut err = gpio_direction_output(si->pdata->gpio_pwdown, 875c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut !si->pdata->gpio_pwdown_inverted); 876c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut if (err) { 877c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut gpio_free(si->pdata->gpio_pwdown); 878c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut goto err_startup; 879c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut } 880c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut } 881c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut 882c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut if (si->pdata->startup) { 883baf1c5d2a08c828d6333e0a37bcdf5afb3d5d003Dmitry Eremin-Solenikov err = si->pdata->startup(si->dev); 884c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut if (err) 885c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut goto err_startup; 886c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut } 887c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut 888c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut if (gpio_is_valid(si->pdata->gpio_pwdown) && si->pdata->startup) 889c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut dev_warn(si->dev, "gpio_pwdown and startup() both defined!\n"); 890baf1c5d2a08c828d6333e0a37bcdf5afb3d5d003Dmitry Eremin-Solenikov 891c76ccd6a256004cca1127c9afb5474638fc78b74Alexander Beregalov dev->netdev_ops = &pxa_irda_netdev_ops; 8926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 8936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre irda_init_max_qos_capabilies(&si->qos); 8946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 8956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre baudrate_mask = 0; 8966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->pdata->transceiver_cap & IR_SIRMODE) 8976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre baudrate_mask |= IR_9600|IR_19200|IR_38400|IR_57600|IR_115200; 8986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (si->pdata->transceiver_cap & IR_FIRMODE) 8996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre baudrate_mask |= IR_4000000 << 8; 9006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->qos.baud_rate.bits &= baudrate_mask; 9026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre si->qos.min_turn_time.bits = 7; /* 1ms or more */ 9036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre irda_qos_bits_to_value(&si->qos); 9056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre err = register_netdev(dev); 9076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (err == 0) 9096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre dev_set_drvdata(&pdev->dev, dev); 9106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (err) { 912baf1c5d2a08c828d6333e0a37bcdf5afb3d5d003Dmitry Eremin-Solenikov if (si->pdata->shutdown) 913baf1c5d2a08c828d6333e0a37bcdf5afb3d5d003Dmitry Eremin-Solenikov si->pdata->shutdown(si->dev); 914baf1c5d2a08c828d6333e0a37bcdf5afb3d5d003Dmitry Eremin-Solenikoverr_startup: 9156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre kfree(si->tx_buff.head); 9166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_5: 9176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre kfree(si->rx_buff.head); 9186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_4: 91982d553c67deef92c6c84ecb70afc56e99863060cRussell King if (si->sir_clk && !IS_ERR(si->sir_clk)) 92082d553c67deef92c6c84ecb70afc56e99863060cRussell King clk_put(si->sir_clk); 92182d553c67deef92c6c84ecb70afc56e99863060cRussell King if (si->fir_clk && !IS_ERR(si->fir_clk)) 92282d553c67deef92c6c84ecb70afc56e99863060cRussell King clk_put(si->fir_clk); 9236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre free_netdev(dev); 9246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_3: 9256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre release_mem_region(__PREG(FICP), 0x1c); 9266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_2: 9276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre release_mem_region(__PREG(STUART), 0x24); 9286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 9296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_1: 9306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return err; 9316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 9326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 933b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovskystatic int pxa_irda_remove(struct platform_device *_dev) 9346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 935b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovsky struct net_device *dev = platform_get_drvdata(_dev); 9366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre if (dev) { 9386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre struct pxa_irda *si = netdev_priv(dev); 9396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre unregister_netdev(dev); 940c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut if (gpio_is_valid(si->pdata->gpio_pwdown)) 941c4bd01727380ce666aba987b3d7c0e838cb99bbeMarek Vasut gpio_free(si->pdata->gpio_pwdown); 942baf1c5d2a08c828d6333e0a37bcdf5afb3d5d003Dmitry Eremin-Solenikov if (si->pdata->shutdown) 943baf1c5d2a08c828d6333e0a37bcdf5afb3d5d003Dmitry Eremin-Solenikov si->pdata->shutdown(si->dev); 9446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre kfree(si->tx_buff.head); 9456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre kfree(si->rx_buff.head); 94682d553c67deef92c6c84ecb70afc56e99863060cRussell King clk_put(si->fir_clk); 94782d553c67deef92c6c84ecb70afc56e99863060cRussell King clk_put(si->sir_clk); 9486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre free_netdev(dev); 9496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre } 9506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre release_mem_region(__PREG(STUART), 0x24); 9526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre release_mem_region(__PREG(FICP), 0x1c); 9536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre return 0; 9556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 9566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 957b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovskystatic struct platform_driver pxa_ir_driver = { 958b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovsky .driver = { 959b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovsky .name = "pxa2xx-ir", 96072abb46101fb5c47a9592914adb221b430ff26bdKay Sievers .owner = THIS_MODULE, 961b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovsky }, 9626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre .probe = pxa_irda_probe, 9636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre .remove = pxa_irda_remove, 9646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre .suspend = pxa_irda_suspend, 9656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre .resume = pxa_irda_resume, 9666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}; 9676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int __init pxa_irda_init(void) 9696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 970b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovsky return platform_driver_register(&pxa_ir_driver); 9716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 9726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic void __exit pxa_irda_exit(void) 9746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{ 975b259e7d250e15d45b3c8362917931aaff1c88d73Paul Sokolovsky platform_driver_unregister(&pxa_ir_driver); 9766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre} 9776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitremodule_init(pxa_irda_init); 9796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitremodule_exit(pxa_irda_exit); 9806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre 9816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas PitreMODULE_LICENSE("GPL"); 98272abb46101fb5c47a9592914adb221b430ff26bdKay SieversMODULE_ALIAS("platform:pxa2xx-ir"); 983