pxaficp_ir.c revision 6f475c0133eb91c7df3b056843dc33d2824368a2
16f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/*
26f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * linux/drivers/net/irda/pxaficp_ir.c
36f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre *
46f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Based on sa1100_ir.c by Russell King
56f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre *
66f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Changes copyright (C) 2003-2005 MontaVista Software, Inc.
76f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre *
86f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * This program is free software; you can redistribute it and/or modify
96f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * it under the terms of the GNU General Public License version 2 as
106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * published by the Free Software Foundation.
116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre *
126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Infra-red driver (SIR/FIR) for the PXA2xx embedded microprocessor
136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre *
146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */
156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/config.h>
166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/module.h>
176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/types.h>
186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/init.h>
196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/errno.h>
206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/netdevice.h>
216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/slab.h>
226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/rtnetlink.h>
236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/interrupt.h>
246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/dma-mapping.h>
256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <linux/pm.h>
266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <net/irda/irda.h>
286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <net/irda/irmod.h>
296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <net/irda/wrapper.h>
306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <net/irda/irda_device.h>
316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <asm/irq.h>
336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <asm/dma.h>
346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <asm/delay.h>
356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <asm/hardware.h>
366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <asm/arch/irda.h>
376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <asm/arch/pxa-regs.h>
386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#ifdef CONFIG_MACH_MAINSTONE
406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#include <asm/arch/mainstone.h>
416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#endif
426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_RXPL_POS_IS_ZERO 0x0
456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_TXPL_POS_IS_ZERO 0x0
476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_XMODE_PULSE_1_6  (1<<2)
486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_XMODE_PULSE_3_16 0x0
496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_RCVEIR_IR_MODE   (1<<1)
506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_RCVEIR_UART_MODE 0x0
516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_XMITIR_IR_MODE   (1<<0)
526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_XMITIR_UART_MODE 0x0
536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_IR_RECEIVE_ON (\
556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_RXPL_NEG_IS_ZERO | \
566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_TXPL_POS_IS_ZERO | \
576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_XMODE_PULSE_3_16 | \
586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_RCVEIR_IR_MODE   | \
596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_XMITIR_UART_MODE)
606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IrSR_IR_TRANSMIT_ON (\
626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_RXPL_NEG_IS_ZERO | \
636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_TXPL_POS_IS_ZERO | \
646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_XMODE_PULSE_3_16 | \
656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_RCVEIR_UART_MODE | \
666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                IrSR_XMITIR_IR_MODE)
676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestruct pxa_irda {
696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int			speed;
706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int			newspeed;
716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	unsigned long		last_oscr;
726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	unsigned char		*dma_rx_buff;
746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	unsigned char		*dma_tx_buff;
756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dma_addr_t		dma_rx_buff_phy;
766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dma_addr_t		dma_tx_buff_phy;
776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	unsigned int		dma_tx_buff_len;
786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int			txdma;
796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int			rxdma;
806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct net_device_stats	stats;
826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct irlap_cb		*irlap;
836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct qos_info		qos;
846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	iobuff_t		tx_buff;
866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	iobuff_t		rx_buff;
876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct device		*dev;
896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxaficp_platform_data *pdata;
906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre};
916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IS_FIR(si)		((si)->speed >= 4000000)
946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre#define IRDA_FRAME_SIZE_LIMIT	2047
956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreinline static void pxa_irda_fir_dma_rx_start(struct pxa_irda *si)
976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCSR(si->rxdma)  = DCSR_NODESC;
996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DSADR(si->rxdma) = __PREG(ICDR);
1006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DTADR(si->rxdma) = si->dma_rx_buff_phy;
1016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCMD(si->rxdma) = DCMD_INCTRGADDR | DCMD_FLOWSRC |  DCMD_WIDTH1 | DCMD_BURST32 | IRDA_FRAME_SIZE_LIMIT;
1026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCSR(si->rxdma) |= DCSR_RUN;
1036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
1046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreinline static void pxa_irda_fir_dma_tx_start(struct pxa_irda *si)
1066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
1076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCSR(si->txdma)  = DCSR_NODESC;
1086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DSADR(si->txdma) = si->dma_tx_buff_phy;
1096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DTADR(si->txdma) = __PREG(ICDR);
1106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCMD(si->txdma) = DCMD_INCSRCADDR | DCMD_FLOWTRG |  DCMD_ENDIRQEN | DCMD_WIDTH1 | DCMD_BURST32 | si->dma_tx_buff_len;
1116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCSR(si->txdma) |= DCSR_RUN;
1126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
1136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/*
1156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre * Set the IrDA communications speed.
1166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre */
1176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_set_speed(struct pxa_irda *si, int speed)
1186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
1196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	unsigned long flags;
1206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	unsigned int divisor;
1216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	switch (speed) {
1236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case 9600:	case 19200:	case 38400:
1246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case 57600:	case 115200:
1256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* refer to PXA250/210 Developer's Manual 10-7 */
1276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/*  BaudRate = 14.7456 MHz / (16*Divisor) */
1286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		divisor = 14745600 / (16 * speed);
1296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		local_irq_save(flags);
1316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (IS_FIR(si)) {
1336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			/* stop RX DMA */
1346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			DCSR(si->rxdma) &= ~DCSR_RUN;
1356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			/* disable FICP */
1366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			ICCR0 = 0;
1376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			pxa_set_cken(CKEN13_FICP, 0);
1386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			/* set board transceiver to SIR mode */
1406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->pdata->transceiver_mode(si->dev, IR_SIRMODE);
1416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			/* configure GPIO46/47 */
1436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			pxa_gpio_mode(GPIO46_STRXD_MD);
1446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			pxa_gpio_mode(GPIO47_STTXD_MD);
1456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			/* enable the STUART clock */
1476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			pxa_set_cken(CKEN5_STUART, 1);
1486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		}
1496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* disable STUART first */
1516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STIER = 0;
1526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* access DLL & DLH */
1546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STLCR |= LCR_DLAB;
1556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STDLL = divisor & 0xff;
1566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STDLH = divisor >> 8;
1576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STLCR &= ~LCR_DLAB;
1586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->speed = speed;
1606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6;
1616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE;
1626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		local_irq_restore(flags);
1646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		break;
1656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case 4000000:
1676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		local_irq_save(flags);
1686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* disable STUART */
1706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STIER = 0;
1716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STISR = 0;
1726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_set_cken(CKEN5_STUART, 0);
1736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* disable FICP first */
1756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ICCR0 = 0;
1766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* set board transceiver to FIR mode */
1786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->pdata->transceiver_mode(si->dev, IR_FIRMODE);
1796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* configure GPIO46/47 */
1816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_gpio_mode(GPIO46_ICPRXD_MD);
1826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_gpio_mode(GPIO47_ICPTXD_MD);
1836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* enable the FICP clock */
1856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_set_cken(CKEN13_FICP, 1);
1866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->speed = speed;
1886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_irda_fir_dma_rx_start(si);
1896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ICCR0 = ICCR0_ITR | ICCR0_RXE;
1906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		local_irq_restore(flags);
1926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		break;
1936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	default:
1956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		return -EINVAL;
1966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
1976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
1986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return 0;
1996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
2006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* SIR interrupt service routine. */
2026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id, struct pt_regs *regs)
2036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
2046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct net_device *dev = dev_id;
2056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si = netdev_priv(dev);
2066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int iir, lsr, data;
2076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	iir = STIIR;
2096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	switch  (iir & 0x0F) {
2116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case 0x06: /* Receiver Line Status */
2126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	  	lsr = STLSR;
2136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		while (lsr & LSR_FIFOE) {
2146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			data = STRBR;
2156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			if (lsr & (LSR_OE | LSR_PE | LSR_FE | LSR_BI)) {
2166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				printk(KERN_DEBUG "pxa_ir: sir receiving error\n");
2176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				si->stats.rx_errors++;
2186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				if (lsr & LSR_FE)
2196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre					si->stats.rx_frame_errors++;
2206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				if (lsr & LSR_OE)
2216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre					si->stats.rx_fifo_errors++;
2226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			} else {
2236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				si->stats.rx_bytes++;
2246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				async_unwrap_char(dev, &si->stats, &si->rx_buff, data);
2256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			}
2266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			lsr = STLSR;
2276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		}
2286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		dev->last_rx = jiffies;
2296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->last_oscr = OSCR;
2306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		break;
2316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case 0x04: /* Received Data Available */
2336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	  	   /* forth through */
2346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case 0x0C: /* Character Timeout Indication */
2366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	  	do  {
2376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		    si->stats.rx_bytes++;
2386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	            async_unwrap_char(dev, &si->stats, &si->rx_buff, STRBR);
2396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	  	} while (STLSR & LSR_DR);
2406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	  	dev->last_rx = jiffies;
2416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->last_oscr = OSCR;
2426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	  	break;
2436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case 0x02: /* Transmit FIFO Data Request */
2456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	    	while ((si->tx_buff.len) && (STLSR & LSR_TDRQ)) {
2466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	    		STTHR = *si->tx_buff.data++;
2476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->tx_buff.len -= 1;
2486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	    	}
2496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (si->tx_buff.len == 0) {
2516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->stats.tx_packets++;
2526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->stats.tx_bytes += si->tx_buff.data -
2536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre					      si->tx_buff.head;
2546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre                        /* We need to ensure that the transmitter has finished. */
2566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			while ((STLSR & LSR_TEMT) == 0)
2576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				cpu_relax();
2586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->last_oscr = OSCR;
2596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			/*
2616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		 	* Ok, we've finished transmitting.  Now enable
2626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		 	* the receiver.  Sometimes we get a receive IRQ
2636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		 	* immediately after a transmit...
2646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		 	*/
2656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			if (si->newspeed) {
2666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				pxa_irda_set_speed(si, si->newspeed);
2676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				si->newspeed = 0;
2686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			} else {
2696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				/* enable IR Receiver, disable IR Transmitter */
2706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6;
2716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				/* enable STUART and receive interrupts */
2726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE;
2736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			}
2746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			/* I'm hungry! */
2756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			netif_wake_queue(dev);
2766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		}
2776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		break;
2786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
2796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return IRQ_HANDLED;
2816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
2826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* FIR Receive DMA interrupt handler */
2846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic void pxa_irda_fir_dma_rx_irq(int channel, void *data, struct pt_regs *regs)
2856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
2866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int dcsr = DCSR(channel);
2876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCSR(channel) = dcsr & ~DCSR_RUN;
2896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	printk(KERN_DEBUG "pxa_ir: fir rx dma bus error %#x\n", dcsr);
2916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
2926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
2936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* FIR Transmit DMA interrupt handler */
2946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic void pxa_irda_fir_dma_tx_irq(int channel, void *data, struct pt_regs *regs)
2956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
2966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct net_device *dev = data;
2976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si = netdev_priv(dev);
2986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int dcsr;
2996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dcsr = DCSR(channel);
3016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCSR(channel) = dcsr & ~DCSR_RUN;
3026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (dcsr & DCSR_ENDINTR)  {
3046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->stats.tx_packets++;
3056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->stats.tx_bytes += si->dma_tx_buff_len;
3066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	} else {
3076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->stats.tx_errors++;
3086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
3096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	while (ICSR1 & ICSR1_TBY)
3116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		cpu_relax();
3126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->last_oscr = OSCR;
3136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/*
3156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * HACK: It looks like the TBY bit is dropped too soon.
3166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * Without this delay things break.
3176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 */
3186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	udelay(120);
3196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (si->newspeed) {
3216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_irda_set_speed(si, si->newspeed);
3226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->newspeed = 0;
3236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	} else {
3246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ICCR0 = 0;
3256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_irda_fir_dma_rx_start(si);
3266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ICCR0 = ICCR0_ITR | ICCR0_RXE;
3276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
3286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	netif_wake_queue(dev);
3296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
3306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* EIF(Error in FIFO/End in Frame) handler for FIR */
3326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev)
3336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
3346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	unsigned int len, stat, data;
3356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* Get the current data position. */
3376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	len = DTADR(si->rxdma) - si->dma_rx_buff_phy;
3386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	do {
3406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* Read Status, and then Data. 	 */
3416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		stat = ICSR1;
3426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		rmb();
3436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		data = ICDR;
3446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (stat & (ICSR1_CRE | ICSR1_ROR)) {
3466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->stats.rx_errors++;
3476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			if (stat & ICSR1_CRE) {
3486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				printk(KERN_DEBUG "pxa_ir: fir receive CRC error\n");
3496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				si->stats.rx_crc_errors++;
3506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			}
3516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			if (stat & ICSR1_ROR) {
3526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				printk(KERN_DEBUG "pxa_ir: fir receive overrun\n");
3536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				si->stats.rx_frame_errors++;
3546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			}
3556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		} else	{
3566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->dma_rx_buff[len++] = data;
3576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		}
3586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* If we hit the end of frame, there's no point in continuing. */
3596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (stat & ICSR1_EOF)
3606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			break;
3616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	} while (ICSR0 & ICSR0_EIF);
3626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (stat & ICSR1_EOF) {
3646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* end of frame. */
3656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		struct sk_buff *skb = alloc_skb(len+1,GFP_ATOMIC);
3666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (!skb)  {
3676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			printk(KERN_ERR "pxa_ir: fir out of memory for receive skb\n");
3686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->stats.rx_dropped++;
3696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			return;
3706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		}
3716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* Align IP header to 20 bytes  */
3736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		skb_reserve(skb, 1);
3746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		memcpy(skb->data, si->dma_rx_buff, len);
3756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		skb_put(skb, len);
3766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* Feed it to IrLAP  */
3786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		skb->dev = dev;
3796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		skb->mac.raw  = skb->data;
3806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		skb->protocol = htons(ETH_P_IRDA);
3816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		netif_rx(skb);
3826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->stats.rx_packets++;
3846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->stats.rx_bytes += len;
3856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		dev->last_rx = jiffies;
3876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
3886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
3896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* FIR interrupt handler */
3916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id, struct pt_regs *regs)
3926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
3936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct net_device *dev = dev_id;
3946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si = netdev_priv(dev);
3956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int icsr0;
3966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
3976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* stop RX DMA */
3986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCSR(si->rxdma) &= ~DCSR_RUN;
3996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->last_oscr = OSCR;
4006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	icsr0 = ICSR0;
4016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (icsr0 & (ICSR0_FRE | ICSR0_RAB)) {
4036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (icsr0 & ICSR0_FRE) {
4046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		        printk(KERN_DEBUG "pxa_ir: fir receive frame error\n");
4056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->stats.rx_frame_errors++;
4066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		} else {
4076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			printk(KERN_DEBUG "pxa_ir: fir receive abort\n");
4086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->stats.rx_errors++;
4096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		}
4106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ICSR0 = icsr0 & (ICSR0_FRE | ICSR0_RAB);
4116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
4126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (icsr0 & ICSR0_EIF) {
4146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* An error in FIFO occured, or there is a end of frame */
4156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_irda_fir_irq_eif(si, dev);
4166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
4176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	ICCR0 = 0;
4196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_irda_fir_dma_rx_start(si);
4206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	ICCR0 = ICCR0_ITR | ICCR0_RXE;
4216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return IRQ_HANDLED;
4236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
4246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre/* hard_xmit interface of irda device */
4266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
4276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
4286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si = netdev_priv(dev);
4296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int speed = irda_get_next_speed(skb);
4306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/*
4326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * Does this packet contain a request to change the interface
4336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * speed?  If so, remember it until we complete the transmission
4346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * of this frame.
4356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 */
4366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (speed != si->speed && speed != -1)
4376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->newspeed = speed;
4386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/*
4406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * If this is an empty frame, we can bypass a lot.
4416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 */
4426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (skb->len == 0) {
4436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (si->newspeed) {
4446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			si->newspeed = 0;
4456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			pxa_irda_set_speed(si, speed);
4466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		}
4476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		dev_kfree_skb(skb);
4486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		return 0;
4496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
4506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	netif_stop_queue(dev);
4526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (!IS_FIR(si)) {
4546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->tx_buff.data = si->tx_buff.head;
4556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->tx_buff.len  = async_wrap_skb(skb, si->tx_buff.data, si->tx_buff.truesize);
4566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* Disable STUART interrupts and switch to transmit mode. */
4586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STIER = 0;
4596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STISR = IrSR_IR_TRANSMIT_ON | IrSR_XMODE_PULSE_1_6;
4606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* enable STUART and transmit interrupts */
4626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		STIER = IER_UUE | IER_TIE;
4636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	} else {
4646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		unsigned long mtt = irda_get_mtt(skb);
4656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->dma_tx_buff_len = skb->len;
4676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		memcpy(si->dma_tx_buff, skb->data, skb->len);
4686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (mtt)
4706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			while ((unsigned)(OSCR - si->last_oscr)/4 < mtt)
4716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				cpu_relax();
4726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		/* stop RX DMA,  disable FICP */
4746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		DCSR(si->rxdma) &= ~DCSR_RUN;
4756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ICCR0 = 0;
4766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_irda_fir_dma_tx_start(si);
4786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ICCR0 = ICCR0_ITR | ICCR0_TXE;
4796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
4806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dev_kfree_skb(skb);
4826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dev->trans_start = jiffies;
4836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return 0;
4846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
4856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
4876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
4886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct if_irda_req *rq = (struct if_irda_req *)ifreq;
4896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si = netdev_priv(dev);
4906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int ret;
4916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
4926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	switch (cmd) {
4936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case SIOCSBANDWIDTH:
4946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ret = -EPERM;
4956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (capable(CAP_NET_ADMIN)) {
4966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			/*
4976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			 * We are unable to set the speed if the
4986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			 * device is not running.
4996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			 */
5006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			if (netif_running(dev)) {
5016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				ret = pxa_irda_set_speed(si,
5026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre						rq->ifr_baudrate);
5036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			} else {
5046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				printk(KERN_INFO "pxa_ir: SIOCSBANDWIDTH: !netif_running\n");
5056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre				ret = 0;
5066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			}
5076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		}
5086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		break;
5096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case SIOCSMEDIABUSY:
5116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ret = -EPERM;
5126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		if (capable(CAP_NET_ADMIN)) {
5136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			irda_device_set_media_busy(dev, TRUE);
5146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre			ret = 0;
5156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		}
5166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		break;
5176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	case SIOCGRECEIVING:
5196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ret = 0;
5206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		rq->ifr_receiving = IS_FIR(si) ? 0
5216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre					: si->rx_buff.state != OUTSIDE_FRAME;
5226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		break;
5236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	default:
5256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		ret = -EOPNOTSUPP;
5266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		break;
5276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
5286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return ret;
5306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
5316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic struct net_device_stats *pxa_irda_stats(struct net_device *dev)
5336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
5346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si = netdev_priv(dev);
5356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return &si->stats;
5366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
5376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic void pxa_irda_startup(struct pxa_irda *si)
5396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
5406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* Disable STUART interrupts */
5416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	STIER = 0;
5426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* enable STUART interrupt to the processor */
5436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	STMCR = MCR_OUT2;
5446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* configure SIR frame format: StartBit - Data 7 ... Data 0 - Stop Bit */
5456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	STLCR = LCR_WLS0 | LCR_WLS1;
5466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* enable FIFO, we use FIFO to improve performance */
5476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	STFCR = FCR_TRFIFOE | FCR_ITL_32;
5486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* disable FICP */
5506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	ICCR0 = 0;
5516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* configure FICP ICCR2 */
5526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	ICCR2 = ICCR2_TXP | ICCR2_TRIG_32;
5536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* configure DMAC */
5556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DRCMR17 = si->rxdma | DRCMR_MAPVLD;
5566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DRCMR18 = si->txdma | DRCMR_MAPVLD;
5576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* force SIR reinitialization */
5596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->speed = 4000000;
5606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_irda_set_speed(si, 9600);
5616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	printk(KERN_DEBUG "pxa_ir: irda startup\n");
5636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
5646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic void pxa_irda_shutdown(struct pxa_irda *si)
5666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
5676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	unsigned long flags;
5686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	local_irq_save(flags);
5706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* disable STUART and interrupt */
5726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	STIER = 0;
5736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* disable STUART SIR mode */
5746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	STISR = 0;
5756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* disable the STUART clock */
5766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_set_cken(CKEN5_STUART, 0);
5776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* disable DMA */
5796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCSR(si->txdma) &= ~DCSR_RUN;
5806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DCSR(si->rxdma) &= ~DCSR_RUN;
5816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* disable FICP */
5826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	ICCR0 = 0;
5836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* disable the FICP clock */
5846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_set_cken(CKEN13_FICP, 0);
5856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DRCMR17 = 0;
5876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	DRCMR18 = 0;
5886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	local_irq_restore(flags);
5906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* power off board transceiver */
5926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->pdata->transceiver_mode(si->dev, IR_OFF);
5936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	printk(KERN_DEBUG "pxa_ir: irda shutdown\n");
5956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
5966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
5976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_start(struct net_device *dev)
5986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
5996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si = netdev_priv(dev);
6006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int err;
6016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->speed = 9600;
6036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = request_irq(IRQ_STUART, pxa_irda_sir_irq, 0, dev->name, dev);
6056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (err)
6066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_irq1;
6076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = request_irq(IRQ_ICP, pxa_irda_fir_irq, 0, dev->name, dev);
6096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (err)
6106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_irq2;
6116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/*
6136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * The interrupt must remain disabled for now.
6146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 */
6156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	disable_irq(IRQ_STUART);
6166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	disable_irq(IRQ_ICP);
6176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = -EBUSY;
6196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->rxdma = pxa_request_dma("FICP_RX",DMA_PRIO_LOW, pxa_irda_fir_dma_rx_irq, dev);
6206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (si->rxdma < 0)
6216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_rx_dma;
6226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->txdma = pxa_request_dma("FICP_TX",DMA_PRIO_LOW, pxa_irda_fir_dma_tx_irq, dev);
6246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (si->txdma < 0)
6256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_tx_dma;
6266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = -ENOMEM;
6286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->dma_rx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT,
6296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre					     &si->dma_rx_buff_phy, GFP_KERNEL );
6306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (!si->dma_rx_buff)
6316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_dma_rx_buff;
6326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->dma_tx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT,
6346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre					     &si->dma_tx_buff_phy, GFP_KERNEL );
6356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (!si->dma_tx_buff)
6366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_dma_tx_buff;
6376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* Setup the serial port for the initial speed. */
6396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_irda_startup(si);
6406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/*
6426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * Open a new IrLAP layer instance.
6436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 */
6446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->irlap = irlap_open(dev, &si->qos, "pxa");
6456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = -ENOMEM;
6466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (!si->irlap)
6476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_irlap;
6486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/*
6506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * Now enable the interrupt and start the queue
6516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 */
6526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	enable_irq(IRQ_STUART);
6536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	enable_irq(IRQ_ICP);
6546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	netif_start_queue(dev);
6556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	printk(KERN_DEBUG "pxa_ir: irda driver opened\n");
6576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return 0;
6596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_irlap:
6616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_irda_shutdown(si);
6626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy);
6636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_dma_tx_buff:
6646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy);
6656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_dma_rx_buff:
6666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_free_dma(si->txdma);
6676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_tx_dma:
6686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_free_dma(si->rxdma);
6696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_rx_dma:
6706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	free_irq(IRQ_ICP, dev);
6716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_irq2:
6726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	free_irq(IRQ_STUART, dev);
6736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_irq1:
6746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return err;
6766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
6776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_stop(struct net_device *dev)
6796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
6806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si = netdev_priv(dev);
6816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	netif_stop_queue(dev);
6836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_irda_shutdown(si);
6856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/* Stop IrLAP */
6876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (si->irlap) {
6886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		irlap_close(si->irlap);
6896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si->irlap = NULL;
6906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
6916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	free_irq(IRQ_STUART, dev);
6936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	free_irq(IRQ_ICP, dev);
6946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_free_dma(si->rxdma);
6966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	pxa_free_dma(si->txdma);
6976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
6986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (si->dma_rx_buff)
6996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy);
7006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (si->dma_tx_buff)
7016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy);
7026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	printk(KERN_DEBUG "pxa_ir: irda driver closed\n");
7046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return 0;
7056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
7066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_suspend(struct device *_dev, pm_message_t state, u32 level)
7086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
7096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct net_device *dev = dev_get_drvdata(_dev);
7106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si;
7116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (!dev || level != SUSPEND_DISABLE)
7136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		return 0;
7146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (netif_running(dev)) {
7166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si = netdev_priv(dev);
7176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		netif_device_detach(dev);
7186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_irda_shutdown(si);
7196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
7206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return 0;
7226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
7236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_resume(struct device *_dev, u32 level)
7256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
7266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct net_device *dev = dev_get_drvdata(_dev);
7276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si;
7286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (!dev || level != RESUME_ENABLE)
7306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		return 0;
7316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (netif_running(dev)) {
7336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		si = netdev_priv(dev);
7346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		pxa_irda_startup(si);
7356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		netif_device_attach(dev);
7366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		netif_wake_queue(dev);
7376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
7386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return 0;
7406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
7416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_init_iobuf(iobuff_t *io, int size)
7446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
7456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	io->head = kmalloc(size, GFP_KERNEL | GFP_DMA);
7466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (io->head != NULL) {
7476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		io->truesize = size;
7486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		io->in_frame = FALSE;
7496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		io->state    = OUTSIDE_FRAME;
7506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		io->data     = io->head;
7516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
7526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return io->head ? 0 : -ENOMEM;
7536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
7546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_probe(struct device *_dev)
7566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
7576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct platform_device *pdev = to_platform_device(_dev);
7586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct net_device *dev;
7596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct pxa_irda *si;
7606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	unsigned int baudrate_mask;
7616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	int err;
7626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (!pdev->dev.platform_data)
7646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		return -ENODEV;
7656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = request_mem_region(__PREG(STUART), 0x24, "IrDA") ? 0 : -EBUSY;
7676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (err)
7686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_mem_1;
7696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = request_mem_region(__PREG(FICP), 0x1c, "IrDA") ? 0 : -EBUSY;
7716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (err)
7726f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_mem_2;
7736f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7746f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dev = alloc_irdadev(sizeof(struct pxa_irda));
7756f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (!dev)
7766f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_mem_3;
7776f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7786f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si = netdev_priv(dev);
7796f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->dev = &pdev->dev;
7806f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->pdata = pdev->dev.platform_data;
7816f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7826f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	/*
7836f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 * Initialise the SIR buffers
7846f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	 */
7856f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = pxa_irda_init_iobuf(&si->rx_buff, 14384);
7866f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (err)
7876f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_mem_4;
7886f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = pxa_irda_init_iobuf(&si->tx_buff, 4000);
7896f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (err)
7906f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		goto err_mem_5;
7916f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7926f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dev->hard_start_xmit	= pxa_irda_hard_xmit;
7936f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dev->open		= pxa_irda_start;
7946f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dev->stop		= pxa_irda_stop;
7956f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dev->do_ioctl		= pxa_irda_ioctl;
7966f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	dev->get_stats		= pxa_irda_stats;
7976f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
7986f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	irda_init_max_qos_capabilies(&si->qos);
7996f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8006f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	baudrate_mask = 0;
8016f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (si->pdata->transceiver_cap & IR_SIRMODE)
8026f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		baudrate_mask |= IR_9600|IR_19200|IR_38400|IR_57600|IR_115200;
8036f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (si->pdata->transceiver_cap & IR_FIRMODE)
8046f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		baudrate_mask |= IR_4000000 << 8;
8056f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8066f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->qos.baud_rate.bits &= baudrate_mask;
8076f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	si->qos.min_turn_time.bits = 7;  /* 1ms or more */
8086f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8096f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	irda_qos_bits_to_value(&si->qos);
8106f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8116f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	err = register_netdev(dev);
8126f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8136f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (err == 0)
8146f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		dev_set_drvdata(&pdev->dev, dev);
8156f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8166f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (err) {
8176f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		kfree(si->tx_buff.head);
8186f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_5:
8196f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		kfree(si->rx_buff.head);
8206f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_4:
8216f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		free_netdev(dev);
8226f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_3:
8236f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		release_mem_region(__PREG(FICP), 0x1c);
8246f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_2:
8256f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		release_mem_region(__PREG(STUART), 0x24);
8266f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
8276f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitreerr_mem_1:
8286f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return err;
8296f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
8306f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8316f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int pxa_irda_remove(struct device *_dev)
8326f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
8336f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	struct net_device *dev = dev_get_drvdata(_dev);
8346f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8356f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	if (dev) {
8366f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		struct pxa_irda *si = netdev_priv(dev);
8376f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		unregister_netdev(dev);
8386f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		kfree(si->tx_buff.head);
8396f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		kfree(si->rx_buff.head);
8406f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre		free_netdev(dev);
8416f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	}
8426f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8436f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	release_mem_region(__PREG(STUART), 0x24);
8446f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	release_mem_region(__PREG(FICP), 0x1c);
8456f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8466f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return 0;
8476f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
8486f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8496f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic struct device_driver pxa_ir_driver = {
8506f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	.name		= "pxa2xx-ir",
8516f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	.bus		= &platform_bus_type,
8526f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	.probe		= pxa_irda_probe,
8536f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	.remove		= pxa_irda_remove,
8546f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	.suspend	= pxa_irda_suspend,
8556f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	.resume		= pxa_irda_resume,
8566f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre};
8576f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8586f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic int __init pxa_irda_init(void)
8596f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
8606f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	return driver_register(&pxa_ir_driver);
8616f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
8626f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8636f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitrestatic void __exit pxa_irda_exit(void)
8646f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre{
8656f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre	driver_unregister(&pxa_ir_driver);
8666f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre}
8676f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8686f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitremodule_init(pxa_irda_init);
8696f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitremodule_exit(pxa_irda_exit);
8706f475c0133eb91c7df3b056843dc33d2824368a2Nicolas Pitre
8716f475c0133eb91c7df3b056843dc33d2824368a2Nicolas PitreMODULE_LICENSE("GPL");
872