smsc95xx.c revision 9ebca5071c8679bba96981af6bc29370f1c2f0aa
1 /*************************************************************************** 2 * 3 * Copyright (C) 2007-2008 SMSC 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 * 19 *****************************************************************************/ 20 21#include <linux/module.h> 22#include <linux/kmod.h> 23#include <linux/init.h> 24#include <linux/netdevice.h> 25#include <linux/etherdevice.h> 26#include <linux/ethtool.h> 27#include <linux/mii.h> 28#include <linux/usb.h> 29#include <linux/bitrev.h> 30#include <linux/crc16.h> 31#include <linux/crc32.h> 32#include <linux/usb/usbnet.h> 33#include <linux/slab.h> 34#include "smsc95xx.h" 35 36#define SMSC_CHIPNAME "smsc95xx" 37#define SMSC_DRIVER_VERSION "1.0.4" 38#define HS_USB_PKT_SIZE (512) 39#define FS_USB_PKT_SIZE (64) 40#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 41#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 42#define DEFAULT_BULK_IN_DELAY (0x00002000) 43#define MAX_SINGLE_PACKET_SIZE (2048) 44#define LAN95XX_EEPROM_MAGIC (0x9500) 45#define EEPROM_MAC_OFFSET (0x01) 46#define DEFAULT_TX_CSUM_ENABLE (true) 47#define DEFAULT_RX_CSUM_ENABLE (true) 48#define SMSC95XX_INTERNAL_PHY_ID (1) 49#define SMSC95XX_TX_OVERHEAD (8) 50#define SMSC95XX_TX_OVERHEAD_CSUM (12) 51#define SUPPORTED_WAKE (WAKE_UCAST | WAKE_BCAST | \ 52 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC) 53 54#define FEATURE_8_WAKEUP_FILTERS (0x01) 55#define FEATURE_PHY_NLP_CROSSOVER (0x02) 56#define FEATURE_AUTOSUSPEND (0x04) 57 58#define check_warn(ret, fmt, args...) \ 59 ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); }) 60 61#define check_warn_return(ret, fmt, args...) \ 62 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } }) 63 64#define check_warn_goto_done(ret, fmt, args...) \ 65 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } }) 66 67struct smsc95xx_priv { 68 u32 mac_cr; 69 u32 hash_hi; 70 u32 hash_lo; 71 u32 wolopts; 72 spinlock_t mac_cr_lock; 73 u8 features; 74}; 75 76static bool turbo_mode = true; 77module_param(turbo_mode, bool, 0644); 78MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); 79 80static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index, 81 u32 *data, int in_pm) 82{ 83 u32 buf; 84 int ret; 85 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16); 86 87 BUG_ON(!dev); 88 89 if (!in_pm) 90 fn = usbnet_read_cmd; 91 else 92 fn = usbnet_read_cmd_nopm; 93 94 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN 95 | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 96 0, index, &buf, 4); 97 if (unlikely(ret < 0)) 98 netdev_warn(dev->net, 99 "Failed to read reg index 0x%08x: %d", index, ret); 100 101 le32_to_cpus(&buf); 102 *data = buf; 103 104 return ret; 105} 106 107static int __must_check __smsc95xx_write_reg(struct usbnet *dev, u32 index, 108 u32 data, int in_pm) 109{ 110 u32 buf; 111 int ret; 112 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16); 113 114 BUG_ON(!dev); 115 116 if (!in_pm) 117 fn = usbnet_write_cmd; 118 else 119 fn = usbnet_write_cmd_nopm; 120 121 buf = data; 122 cpu_to_le32s(&buf); 123 124 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT 125 | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 126 0, index, &buf, 4); 127 if (unlikely(ret < 0)) 128 netdev_warn(dev->net, 129 "Failed to write reg index 0x%08x: %d", index, ret); 130 131 return ret; 132} 133 134static int __must_check smsc95xx_read_reg_nopm(struct usbnet *dev, u32 index, 135 u32 *data) 136{ 137 return __smsc95xx_read_reg(dev, index, data, 1); 138} 139 140static int __must_check smsc95xx_write_reg_nopm(struct usbnet *dev, u32 index, 141 u32 data) 142{ 143 return __smsc95xx_write_reg(dev, index, data, 1); 144} 145 146static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index, 147 u32 *data) 148{ 149 return __smsc95xx_read_reg(dev, index, data, 0); 150} 151 152static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index, 153 u32 data) 154{ 155 return __smsc95xx_write_reg(dev, index, data, 0); 156} 157static int smsc95xx_set_feature(struct usbnet *dev, u32 feature) 158{ 159 if (WARN_ON_ONCE(!dev)) 160 return -EINVAL; 161 162 return usbnet_write_cmd_nopm(dev, USB_REQ_SET_FEATURE, 163 USB_RECIP_DEVICE, feature, 0, 164 NULL, 0); 165} 166 167static int smsc95xx_clear_feature(struct usbnet *dev, u32 feature) 168{ 169 if (WARN_ON_ONCE(!dev)) 170 return -EINVAL; 171 172 return usbnet_write_cmd_nopm(dev, USB_REQ_CLEAR_FEATURE, 173 USB_RECIP_DEVICE, feature, 174 0, NULL, 0); 175} 176 177/* Loop until the read is completed with timeout 178 * called with phy_mutex held */ 179static int __must_check smsc95xx_phy_wait_not_busy(struct usbnet *dev) 180{ 181 unsigned long start_time = jiffies; 182 u32 val; 183 int ret; 184 185 do { 186 ret = smsc95xx_read_reg(dev, MII_ADDR, &val); 187 check_warn_return(ret, "Error reading MII_ACCESS"); 188 if (!(val & MII_BUSY_)) 189 return 0; 190 } while (!time_after(jiffies, start_time + HZ)); 191 192 return -EIO; 193} 194 195static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx) 196{ 197 struct usbnet *dev = netdev_priv(netdev); 198 u32 val, addr; 199 int ret; 200 201 mutex_lock(&dev->phy_mutex); 202 203 /* confirm MII not busy */ 204 ret = smsc95xx_phy_wait_not_busy(dev); 205 check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_read"); 206 207 /* set the address, index & direction (read from PHY) */ 208 phy_id &= dev->mii.phy_id_mask; 209 idx &= dev->mii.reg_num_mask; 210 addr = (phy_id << 11) | (idx << 6) | MII_READ_ | MII_BUSY_; 211 ret = smsc95xx_write_reg(dev, MII_ADDR, addr); 212 check_warn_goto_done(ret, "Error writing MII_ADDR"); 213 214 ret = smsc95xx_phy_wait_not_busy(dev); 215 check_warn_goto_done(ret, "Timed out reading MII reg %02X", idx); 216 217 ret = smsc95xx_read_reg(dev, MII_DATA, &val); 218 check_warn_goto_done(ret, "Error reading MII_DATA"); 219 220 ret = (u16)(val & 0xFFFF); 221 222done: 223 mutex_unlock(&dev->phy_mutex); 224 return ret; 225} 226 227static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx, 228 int regval) 229{ 230 struct usbnet *dev = netdev_priv(netdev); 231 u32 val, addr; 232 int ret; 233 234 mutex_lock(&dev->phy_mutex); 235 236 /* confirm MII not busy */ 237 ret = smsc95xx_phy_wait_not_busy(dev); 238 check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_write"); 239 240 val = regval; 241 ret = smsc95xx_write_reg(dev, MII_DATA, val); 242 check_warn_goto_done(ret, "Error writing MII_DATA"); 243 244 /* set the address, index & direction (write to PHY) */ 245 phy_id &= dev->mii.phy_id_mask; 246 idx &= dev->mii.reg_num_mask; 247 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_ | MII_BUSY_; 248 ret = smsc95xx_write_reg(dev, MII_ADDR, addr); 249 check_warn_goto_done(ret, "Error writing MII_ADDR"); 250 251 ret = smsc95xx_phy_wait_not_busy(dev); 252 check_warn_goto_done(ret, "Timed out writing MII reg %02X", idx); 253 254done: 255 mutex_unlock(&dev->phy_mutex); 256} 257 258static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev) 259{ 260 unsigned long start_time = jiffies; 261 u32 val; 262 int ret; 263 264 do { 265 ret = smsc95xx_read_reg(dev, E2P_CMD, &val); 266 check_warn_return(ret, "Error reading E2P_CMD"); 267 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 268 break; 269 udelay(40); 270 } while (!time_after(jiffies, start_time + HZ)); 271 272 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 273 netdev_warn(dev->net, "EEPROM read operation timeout\n"); 274 return -EIO; 275 } 276 277 return 0; 278} 279 280static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev) 281{ 282 unsigned long start_time = jiffies; 283 u32 val; 284 int ret; 285 286 do { 287 ret = smsc95xx_read_reg(dev, E2P_CMD, &val); 288 check_warn_return(ret, "Error reading E2P_CMD"); 289 290 if (!(val & E2P_CMD_BUSY_)) 291 return 0; 292 293 udelay(40); 294 } while (!time_after(jiffies, start_time + HZ)); 295 296 netdev_warn(dev->net, "EEPROM is busy\n"); 297 return -EIO; 298} 299 300static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length, 301 u8 *data) 302{ 303 u32 val; 304 int i, ret; 305 306 BUG_ON(!dev); 307 BUG_ON(!data); 308 309 ret = smsc95xx_eeprom_confirm_not_busy(dev); 310 if (ret) 311 return ret; 312 313 for (i = 0; i < length; i++) { 314 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 315 ret = smsc95xx_write_reg(dev, E2P_CMD, val); 316 check_warn_return(ret, "Error writing E2P_CMD"); 317 318 ret = smsc95xx_wait_eeprom(dev); 319 if (ret < 0) 320 return ret; 321 322 ret = smsc95xx_read_reg(dev, E2P_DATA, &val); 323 check_warn_return(ret, "Error reading E2P_DATA"); 324 325 data[i] = val & 0xFF; 326 offset++; 327 } 328 329 return 0; 330} 331 332static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length, 333 u8 *data) 334{ 335 u32 val; 336 int i, ret; 337 338 BUG_ON(!dev); 339 BUG_ON(!data); 340 341 ret = smsc95xx_eeprom_confirm_not_busy(dev); 342 if (ret) 343 return ret; 344 345 /* Issue write/erase enable command */ 346 val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_; 347 ret = smsc95xx_write_reg(dev, E2P_CMD, val); 348 check_warn_return(ret, "Error writing E2P_DATA"); 349 350 ret = smsc95xx_wait_eeprom(dev); 351 if (ret < 0) 352 return ret; 353 354 for (i = 0; i < length; i++) { 355 356 /* Fill data register */ 357 val = data[i]; 358 ret = smsc95xx_write_reg(dev, E2P_DATA, val); 359 check_warn_return(ret, "Error writing E2P_DATA"); 360 361 /* Send "write" command */ 362 val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_); 363 ret = smsc95xx_write_reg(dev, E2P_CMD, val); 364 check_warn_return(ret, "Error writing E2P_CMD"); 365 366 ret = smsc95xx_wait_eeprom(dev); 367 if (ret < 0) 368 return ret; 369 370 offset++; 371 } 372 373 return 0; 374} 375 376static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index, 377 u32 *data) 378{ 379 const u16 size = 4; 380 int ret; 381 382 ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, 383 USB_DIR_OUT | USB_TYPE_VENDOR | 384 USB_RECIP_DEVICE, 385 0, index, data, size); 386 if (ret < 0) 387 netdev_warn(dev->net, "Error write async cmd, sts=%d\n", 388 ret); 389 return ret; 390} 391 392/* returns hash bit number for given MAC address 393 * example: 394 * 01 00 5E 00 00 01 -> returns bit number 31 */ 395static unsigned int smsc95xx_hash(char addr[ETH_ALEN]) 396{ 397 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; 398} 399 400static void smsc95xx_set_multicast(struct net_device *netdev) 401{ 402 struct usbnet *dev = netdev_priv(netdev); 403 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 404 unsigned long flags; 405 int ret; 406 407 pdata->hash_hi = 0; 408 pdata->hash_lo = 0; 409 410 spin_lock_irqsave(&pdata->mac_cr_lock, flags); 411 412 if (dev->net->flags & IFF_PROMISC) { 413 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n"); 414 pdata->mac_cr |= MAC_CR_PRMS_; 415 pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 416 } else if (dev->net->flags & IFF_ALLMULTI) { 417 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n"); 418 pdata->mac_cr |= MAC_CR_MCPAS_; 419 pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_); 420 } else if (!netdev_mc_empty(dev->net)) { 421 struct netdev_hw_addr *ha; 422 423 pdata->mac_cr |= MAC_CR_HPFILT_; 424 pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_); 425 426 netdev_for_each_mc_addr(ha, netdev) { 427 u32 bitnum = smsc95xx_hash(ha->addr); 428 u32 mask = 0x01 << (bitnum & 0x1F); 429 if (bitnum & 0x20) 430 pdata->hash_hi |= mask; 431 else 432 pdata->hash_lo |= mask; 433 } 434 435 netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n", 436 pdata->hash_hi, pdata->hash_lo); 437 } else { 438 netif_dbg(dev, drv, dev->net, "receive own packets only\n"); 439 pdata->mac_cr &= 440 ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 441 } 442 443 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); 444 445 /* Initiate async writes, as we can't wait for completion here */ 446 ret = smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi); 447 check_warn(ret, "failed to initiate async write to HASHH"); 448 449 ret = smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo); 450 check_warn(ret, "failed to initiate async write to HASHL"); 451 452 ret = smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr); 453 check_warn(ret, "failed to initiate async write to MAC_CR"); 454} 455 456static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex, 457 u16 lcladv, u16 rmtadv) 458{ 459 u32 flow, afc_cfg = 0; 460 461 int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg); 462 check_warn_return(ret, "Error reading AFC_CFG"); 463 464 if (duplex == DUPLEX_FULL) { 465 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); 466 467 if (cap & FLOW_CTRL_RX) 468 flow = 0xFFFF0002; 469 else 470 flow = 0; 471 472 if (cap & FLOW_CTRL_TX) 473 afc_cfg |= 0xF; 474 else 475 afc_cfg &= ~0xF; 476 477 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n", 478 cap & FLOW_CTRL_RX ? "enabled" : "disabled", 479 cap & FLOW_CTRL_TX ? "enabled" : "disabled"); 480 } else { 481 netif_dbg(dev, link, dev->net, "half duplex\n"); 482 flow = 0; 483 afc_cfg |= 0xF; 484 } 485 486 ret = smsc95xx_write_reg(dev, FLOW, flow); 487 check_warn_return(ret, "Error writing FLOW"); 488 489 ret = smsc95xx_write_reg(dev, AFC_CFG, afc_cfg); 490 check_warn_return(ret, "Error writing AFC_CFG"); 491 492 return 0; 493} 494 495static int smsc95xx_link_reset(struct usbnet *dev) 496{ 497 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 498 struct mii_if_info *mii = &dev->mii; 499 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 500 unsigned long flags; 501 u16 lcladv, rmtadv; 502 int ret; 503 504 /* clear interrupt status */ 505 ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC); 506 check_warn_return(ret, "Error reading PHY_INT_SRC"); 507 508 ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); 509 check_warn_return(ret, "Error writing INT_STS"); 510 511 mii_check_media(mii, 1, 1); 512 mii_ethtool_gset(&dev->mii, &ecmd); 513 lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE); 514 rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA); 515 516 netif_dbg(dev, link, dev->net, 517 "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n", 518 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv); 519 520 spin_lock_irqsave(&pdata->mac_cr_lock, flags); 521 if (ecmd.duplex != DUPLEX_FULL) { 522 pdata->mac_cr &= ~MAC_CR_FDPX_; 523 pdata->mac_cr |= MAC_CR_RCVOWN_; 524 } else { 525 pdata->mac_cr &= ~MAC_CR_RCVOWN_; 526 pdata->mac_cr |= MAC_CR_FDPX_; 527 } 528 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); 529 530 ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); 531 check_warn_return(ret, "Error writing MAC_CR"); 532 533 ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv); 534 check_warn_return(ret, "Error updating PHY flow control"); 535 536 return 0; 537} 538 539static void smsc95xx_status(struct usbnet *dev, struct urb *urb) 540{ 541 u32 intdata; 542 543 if (urb->actual_length != 4) { 544 netdev_warn(dev->net, "unexpected urb length %d\n", 545 urb->actual_length); 546 return; 547 } 548 549 memcpy(&intdata, urb->transfer_buffer, 4); 550 le32_to_cpus(&intdata); 551 552 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata); 553 554 if (intdata & INT_ENP_PHY_INT_) 555 usbnet_defer_kevent(dev, EVENT_LINK_RESET); 556 else 557 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n", 558 intdata); 559} 560 561/* Enable or disable Tx & Rx checksum offload engines */ 562static int smsc95xx_set_features(struct net_device *netdev, 563 netdev_features_t features) 564{ 565 struct usbnet *dev = netdev_priv(netdev); 566 u32 read_buf; 567 int ret; 568 569 ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); 570 check_warn_return(ret, "Failed to read COE_CR: %d\n", ret); 571 572 if (features & NETIF_F_HW_CSUM) 573 read_buf |= Tx_COE_EN_; 574 else 575 read_buf &= ~Tx_COE_EN_; 576 577 if (features & NETIF_F_RXCSUM) 578 read_buf |= Rx_COE_EN_; 579 else 580 read_buf &= ~Rx_COE_EN_; 581 582 ret = smsc95xx_write_reg(dev, COE_CR, read_buf); 583 check_warn_return(ret, "Failed to write COE_CR: %d\n", ret); 584 585 netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf); 586 return 0; 587} 588 589static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net) 590{ 591 return MAX_EEPROM_SIZE; 592} 593 594static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev, 595 struct ethtool_eeprom *ee, u8 *data) 596{ 597 struct usbnet *dev = netdev_priv(netdev); 598 599 ee->magic = LAN95XX_EEPROM_MAGIC; 600 601 return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data); 602} 603 604static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev, 605 struct ethtool_eeprom *ee, u8 *data) 606{ 607 struct usbnet *dev = netdev_priv(netdev); 608 609 if (ee->magic != LAN95XX_EEPROM_MAGIC) { 610 netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n", 611 ee->magic); 612 return -EINVAL; 613 } 614 615 return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data); 616} 617 618static int smsc95xx_ethtool_getregslen(struct net_device *netdev) 619{ 620 /* all smsc95xx registers */ 621 return COE_CR - ID_REV + 1; 622} 623 624static void 625smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs, 626 void *buf) 627{ 628 struct usbnet *dev = netdev_priv(netdev); 629 unsigned int i, j; 630 int retval; 631 u32 *data = buf; 632 633 retval = smsc95xx_read_reg(dev, ID_REV, ®s->version); 634 if (retval < 0) { 635 netdev_warn(netdev, "REGS: cannot read ID_REV\n"); 636 return; 637 } 638 639 for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) { 640 retval = smsc95xx_read_reg(dev, i, &data[j]); 641 if (retval < 0) { 642 netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i); 643 return; 644 } 645 } 646} 647 648static void smsc95xx_ethtool_get_wol(struct net_device *net, 649 struct ethtool_wolinfo *wolinfo) 650{ 651 struct usbnet *dev = netdev_priv(net); 652 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 653 654 wolinfo->supported = SUPPORTED_WAKE; 655 wolinfo->wolopts = pdata->wolopts; 656} 657 658static int smsc95xx_ethtool_set_wol(struct net_device *net, 659 struct ethtool_wolinfo *wolinfo) 660{ 661 struct usbnet *dev = netdev_priv(net); 662 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 663 664 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE; 665 return 0; 666} 667 668static const struct ethtool_ops smsc95xx_ethtool_ops = { 669 .get_link = usbnet_get_link, 670 .nway_reset = usbnet_nway_reset, 671 .get_drvinfo = usbnet_get_drvinfo, 672 .get_msglevel = usbnet_get_msglevel, 673 .set_msglevel = usbnet_set_msglevel, 674 .get_settings = usbnet_get_settings, 675 .set_settings = usbnet_set_settings, 676 .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len, 677 .get_eeprom = smsc95xx_ethtool_get_eeprom, 678 .set_eeprom = smsc95xx_ethtool_set_eeprom, 679 .get_regs_len = smsc95xx_ethtool_getregslen, 680 .get_regs = smsc95xx_ethtool_getregs, 681 .get_wol = smsc95xx_ethtool_get_wol, 682 .set_wol = smsc95xx_ethtool_set_wol, 683}; 684 685static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 686{ 687 struct usbnet *dev = netdev_priv(netdev); 688 689 if (!netif_running(netdev)) 690 return -EINVAL; 691 692 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 693} 694 695static void smsc95xx_init_mac_address(struct usbnet *dev) 696{ 697 /* try reading mac address from EEPROM */ 698 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, 699 dev->net->dev_addr) == 0) { 700 if (is_valid_ether_addr(dev->net->dev_addr)) { 701 /* eeprom values are valid so use them */ 702 netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n"); 703 return; 704 } 705 } 706 707 /* no eeprom, or eeprom values are invalid. generate random MAC */ 708 eth_hw_addr_random(dev->net); 709 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n"); 710} 711 712static int smsc95xx_set_mac_address(struct usbnet *dev) 713{ 714 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 | 715 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24; 716 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8; 717 int ret; 718 719 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); 720 check_warn_return(ret, "Failed to write ADDRL: %d\n", ret); 721 722 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); 723 check_warn_return(ret, "Failed to write ADDRH: %d\n", ret); 724 725 return 0; 726} 727 728/* starts the TX path */ 729static int smsc95xx_start_tx_path(struct usbnet *dev) 730{ 731 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 732 unsigned long flags; 733 int ret; 734 735 /* Enable Tx at MAC */ 736 spin_lock_irqsave(&pdata->mac_cr_lock, flags); 737 pdata->mac_cr |= MAC_CR_TXEN_; 738 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); 739 740 ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); 741 check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); 742 743 /* Enable Tx at SCSRs */ 744 ret = smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_); 745 check_warn_return(ret, "Failed to write TX_CFG: %d\n", ret); 746 747 return 0; 748} 749 750/* Starts the Receive path */ 751static int smsc95xx_start_rx_path(struct usbnet *dev, int in_pm) 752{ 753 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 754 unsigned long flags; 755 int ret; 756 757 spin_lock_irqsave(&pdata->mac_cr_lock, flags); 758 pdata->mac_cr |= MAC_CR_RXEN_; 759 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); 760 761 ret = __smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr, in_pm); 762 check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); 763 764 return 0; 765} 766 767static int smsc95xx_phy_initialize(struct usbnet *dev) 768{ 769 int bmcr, ret, timeout = 0; 770 771 /* Initialize MII structure */ 772 dev->mii.dev = dev->net; 773 dev->mii.mdio_read = smsc95xx_mdio_read; 774 dev->mii.mdio_write = smsc95xx_mdio_write; 775 dev->mii.phy_id_mask = 0x1f; 776 dev->mii.reg_num_mask = 0x1f; 777 dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID; 778 779 /* reset phy and wait for reset to complete */ 780 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); 781 782 do { 783 msleep(10); 784 bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR); 785 timeout++; 786 } while ((bmcr & BMCR_RESET) && (timeout < 100)); 787 788 if (timeout >= 100) { 789 netdev_warn(dev->net, "timeout on PHY Reset"); 790 return -EIO; 791 } 792 793 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 794 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | 795 ADVERTISE_PAUSE_ASYM); 796 797 /* read to clear */ 798 ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC); 799 check_warn_return(ret, "Failed to read PHY_INT_SRC during init"); 800 801 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK, 802 PHY_INT_MASK_DEFAULT_); 803 mii_nway_restart(&dev->mii); 804 805 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n"); 806 return 0; 807} 808 809static int smsc95xx_reset(struct usbnet *dev) 810{ 811 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 812 u32 read_buf, write_buf, burst_cap; 813 int ret = 0, timeout; 814 815 netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n"); 816 817 ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_); 818 check_warn_return(ret, "Failed to write HW_CFG_LRST_ bit in HW_CFG\n"); 819 820 timeout = 0; 821 do { 822 msleep(10); 823 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 824 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); 825 timeout++; 826 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 827 828 if (timeout >= 100) { 829 netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n"); 830 return ret; 831 } 832 833 ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_); 834 check_warn_return(ret, "Failed to write PM_CTRL: %d\n", ret); 835 836 timeout = 0; 837 do { 838 msleep(10); 839 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); 840 check_warn_return(ret, "Failed to read PM_CTRL: %d\n", ret); 841 timeout++; 842 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 843 844 if (timeout >= 100) { 845 netdev_warn(dev->net, "timeout waiting for PHY Reset\n"); 846 return ret; 847 } 848 849 ret = smsc95xx_set_mac_address(dev); 850 if (ret < 0) 851 return ret; 852 853 netif_dbg(dev, ifup, dev->net, 854 "MAC Address: %pM\n", dev->net->dev_addr); 855 856 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 857 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); 858 859 netif_dbg(dev, ifup, dev->net, 860 "Read Value from HW_CFG : 0x%08x\n", read_buf); 861 862 read_buf |= HW_CFG_BIR_; 863 864 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 865 check_warn_return(ret, "Failed to write HW_CFG_BIR_ bit in HW_CFG\n"); 866 867 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 868 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); 869 netif_dbg(dev, ifup, dev->net, 870 "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n", 871 read_buf); 872 873 if (!turbo_mode) { 874 burst_cap = 0; 875 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 876 } else if (dev->udev->speed == USB_SPEED_HIGH) { 877 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 878 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 879 } else { 880 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 881 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 882 } 883 884 netif_dbg(dev, ifup, dev->net, 885 "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size); 886 887 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); 888 check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret); 889 890 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); 891 check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret); 892 893 netif_dbg(dev, ifup, dev->net, 894 "Read Value from BURST_CAP after writing: 0x%08x\n", 895 read_buf); 896 897 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); 898 check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret); 899 900 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); 901 check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret); 902 903 netif_dbg(dev, ifup, dev->net, 904 "Read Value from BULK_IN_DLY after writing: 0x%08x\n", 905 read_buf); 906 907 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 908 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); 909 910 netif_dbg(dev, ifup, dev->net, 911 "Read Value from HW_CFG: 0x%08x\n", read_buf); 912 913 if (turbo_mode) 914 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 915 916 read_buf &= ~HW_CFG_RXDOFF_; 917 918 /* set Rx data offset=2, Make IP header aligns on word boundary. */ 919 read_buf |= NET_IP_ALIGN << 9; 920 921 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); 922 check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret); 923 924 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); 925 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); 926 927 netif_dbg(dev, ifup, dev->net, 928 "Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 929 930 ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); 931 check_warn_return(ret, "Failed to write INT_STS: %d\n", ret); 932 933 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); 934 check_warn_return(ret, "Failed to read ID_REV: %d\n", ret); 935 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf); 936 937 /* Configure GPIO pins as LED outputs */ 938 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | 939 LED_GPIO_CFG_FDX_LED; 940 ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf); 941 check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n", ret); 942 943 /* Init Tx */ 944 ret = smsc95xx_write_reg(dev, FLOW, 0); 945 check_warn_return(ret, "Failed to write FLOW: %d\n", ret); 946 947 ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT); 948 check_warn_return(ret, "Failed to write AFC_CFG: %d\n", ret); 949 950 /* Don't need mac_cr_lock during initialisation */ 951 ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr); 952 check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret); 953 954 /* Init Rx */ 955 /* Set Vlan */ 956 ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q); 957 check_warn_return(ret, "Failed to write VLAN1: %d\n", ret); 958 959 /* Enable or disable checksum offload engines */ 960 ret = smsc95xx_set_features(dev->net, dev->net->features); 961 check_warn_return(ret, "Failed to set checksum offload features"); 962 963 smsc95xx_set_multicast(dev->net); 964 965 ret = smsc95xx_phy_initialize(dev); 966 check_warn_return(ret, "Failed to init PHY"); 967 968 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); 969 check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret); 970 971 /* enable PHY interrupts */ 972 read_buf |= INT_EP_CTL_PHY_INT_; 973 974 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); 975 check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret); 976 977 ret = smsc95xx_start_tx_path(dev); 978 check_warn_return(ret, "Failed to start TX path"); 979 980 ret = smsc95xx_start_rx_path(dev, 0); 981 check_warn_return(ret, "Failed to start RX path"); 982 983 netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n"); 984 return 0; 985} 986 987static const struct net_device_ops smsc95xx_netdev_ops = { 988 .ndo_open = usbnet_open, 989 .ndo_stop = usbnet_stop, 990 .ndo_start_xmit = usbnet_start_xmit, 991 .ndo_tx_timeout = usbnet_tx_timeout, 992 .ndo_change_mtu = usbnet_change_mtu, 993 .ndo_set_mac_address = eth_mac_addr, 994 .ndo_validate_addr = eth_validate_addr, 995 .ndo_do_ioctl = smsc95xx_ioctl, 996 .ndo_set_rx_mode = smsc95xx_set_multicast, 997 .ndo_set_features = smsc95xx_set_features, 998}; 999 1000static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf) 1001{ 1002 struct smsc95xx_priv *pdata = NULL; 1003 u32 val; 1004 int ret; 1005 1006 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n"); 1007 1008 ret = usbnet_get_endpoints(dev, intf); 1009 check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret); 1010 1011 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv), 1012 GFP_KERNEL); 1013 1014 pdata = (struct smsc95xx_priv *)(dev->data[0]); 1015 if (!pdata) { 1016 netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n"); 1017 return -ENOMEM; 1018 } 1019 1020 spin_lock_init(&pdata->mac_cr_lock); 1021 1022 if (DEFAULT_TX_CSUM_ENABLE) 1023 dev->net->features |= NETIF_F_HW_CSUM; 1024 if (DEFAULT_RX_CSUM_ENABLE) 1025 dev->net->features |= NETIF_F_RXCSUM; 1026 1027 dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM; 1028 1029 smsc95xx_init_mac_address(dev); 1030 1031 /* Init all registers */ 1032 ret = smsc95xx_reset(dev); 1033 1034 /* detect device revision as different features may be available */ 1035 ret = smsc95xx_read_reg(dev, ID_REV, &val); 1036 check_warn_return(ret, "Failed to read ID_REV: %d\n", ret); 1037 val >>= 16; 1038 1039 if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9530_) || 1040 (val == ID_REV_CHIP_ID_89530_) || (val == ID_REV_CHIP_ID_9730_)) 1041 pdata->features = (FEATURE_8_WAKEUP_FILTERS | 1042 FEATURE_PHY_NLP_CROSSOVER | 1043 FEATURE_AUTOSUSPEND); 1044 else if (val == ID_REV_CHIP_ID_9512_) 1045 pdata->features = FEATURE_8_WAKEUP_FILTERS; 1046 1047 dev->net->netdev_ops = &smsc95xx_netdev_ops; 1048 dev->net->ethtool_ops = &smsc95xx_ethtool_ops; 1049 dev->net->flags |= IFF_MULTICAST; 1050 dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM; 1051 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; 1052 return 0; 1053} 1054 1055static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf) 1056{ 1057 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 1058 if (pdata) { 1059 netif_dbg(dev, ifdown, dev->net, "free pdata\n"); 1060 kfree(pdata); 1061 pdata = NULL; 1062 dev->data[0] = 0; 1063 } 1064} 1065 1066static u16 smsc_crc(const u8 *buffer, size_t len, int filter) 1067{ 1068 return bitrev16(crc16(0xFFFF, buffer, len)) << ((filter % 2) * 16); 1069} 1070 1071static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message) 1072{ 1073 struct usbnet *dev = usb_get_intfdata(intf); 1074 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 1075 int ret; 1076 u32 val; 1077 1078 ret = usbnet_suspend(intf, message); 1079 check_warn_return(ret, "usbnet_suspend error"); 1080 1081 /* if no wol options set, enter lowest power SUSPEND2 mode */ 1082 if (!(pdata->wolopts & SUPPORTED_WAKE)) { 1083 netdev_info(dev->net, "entering SUSPEND2 mode"); 1084 1085 /* disable energy detect (link up) & wake up events */ 1086 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); 1087 check_warn_return(ret, "Error reading WUCSR"); 1088 1089 val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_); 1090 1091 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); 1092 check_warn_return(ret, "Error writing WUCSR"); 1093 1094 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); 1095 check_warn_return(ret, "Error reading PM_CTRL"); 1096 1097 val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_); 1098 1099 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); 1100 check_warn_return(ret, "Error writing PM_CTRL"); 1101 1102 /* enter suspend2 mode */ 1103 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); 1104 check_warn_return(ret, "Error reading PM_CTRL"); 1105 1106 val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); 1107 val |= PM_CTL_SUS_MODE_2; 1108 1109 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); 1110 check_warn_return(ret, "Error writing PM_CTRL"); 1111 1112 return 0; 1113 } 1114 1115 if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) { 1116 u32 *filter_mask = kzalloc(32, GFP_KERNEL); 1117 u32 command[2]; 1118 u32 offset[2]; 1119 u32 crc[4]; 1120 int wuff_filter_count = 1121 (pdata->features & FEATURE_8_WAKEUP_FILTERS) ? 1122 LAN9500A_WUFF_NUM : LAN9500_WUFF_NUM; 1123 int i, filter = 0; 1124 1125 memset(command, 0, sizeof(command)); 1126 memset(offset, 0, sizeof(offset)); 1127 memset(crc, 0, sizeof(crc)); 1128 1129 if (pdata->wolopts & WAKE_BCAST) { 1130 const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; 1131 netdev_info(dev->net, "enabling broadcast detection"); 1132 filter_mask[filter * 4] = 0x003F; 1133 filter_mask[filter * 4 + 1] = 0x00; 1134 filter_mask[filter * 4 + 2] = 0x00; 1135 filter_mask[filter * 4 + 3] = 0x00; 1136 command[filter/4] |= 0x05UL << ((filter % 4) * 8); 1137 offset[filter/4] |= 0x00 << ((filter % 4) * 8); 1138 crc[filter/2] |= smsc_crc(bcast, 6, filter); 1139 filter++; 1140 } 1141 1142 if (pdata->wolopts & WAKE_MCAST) { 1143 const u8 mcast[] = {0x01, 0x00, 0x5E}; 1144 netdev_info(dev->net, "enabling multicast detection"); 1145 filter_mask[filter * 4] = 0x0007; 1146 filter_mask[filter * 4 + 1] = 0x00; 1147 filter_mask[filter * 4 + 2] = 0x00; 1148 filter_mask[filter * 4 + 3] = 0x00; 1149 command[filter/4] |= 0x09UL << ((filter % 4) * 8); 1150 offset[filter/4] |= 0x00 << ((filter % 4) * 8); 1151 crc[filter/2] |= smsc_crc(mcast, 3, filter); 1152 filter++; 1153 } 1154 1155 if (pdata->wolopts & WAKE_ARP) { 1156 const u8 arp[] = {0x08, 0x06}; 1157 netdev_info(dev->net, "enabling ARP detection"); 1158 filter_mask[filter * 4] = 0x0003; 1159 filter_mask[filter * 4 + 1] = 0x00; 1160 filter_mask[filter * 4 + 2] = 0x00; 1161 filter_mask[filter * 4 + 3] = 0x00; 1162 command[filter/4] |= 0x05UL << ((filter % 4) * 8); 1163 offset[filter/4] |= 0x0C << ((filter % 4) * 8); 1164 crc[filter/2] |= smsc_crc(arp, 2, filter); 1165 filter++; 1166 } 1167 1168 if (pdata->wolopts & WAKE_UCAST) { 1169 netdev_info(dev->net, "enabling unicast detection"); 1170 filter_mask[filter * 4] = 0x003F; 1171 filter_mask[filter * 4 + 1] = 0x00; 1172 filter_mask[filter * 4 + 2] = 0x00; 1173 filter_mask[filter * 4 + 3] = 0x00; 1174 command[filter/4] |= 0x01UL << ((filter % 4) * 8); 1175 offset[filter/4] |= 0x00 << ((filter % 4) * 8); 1176 crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter); 1177 filter++; 1178 } 1179 1180 for (i = 0; i < (wuff_filter_count * 4); i++) { 1181 ret = smsc95xx_write_reg_nopm(dev, WUFF, filter_mask[i]); 1182 if (ret < 0) 1183 kfree(filter_mask); 1184 check_warn_return(ret, "Error writing WUFF"); 1185 } 1186 kfree(filter_mask); 1187 1188 for (i = 0; i < (wuff_filter_count / 4); i++) { 1189 ret = smsc95xx_write_reg_nopm(dev, WUFF, command[i]); 1190 check_warn_return(ret, "Error writing WUFF"); 1191 } 1192 1193 for (i = 0; i < (wuff_filter_count / 4); i++) { 1194 ret = smsc95xx_write_reg_nopm(dev, WUFF, offset[i]); 1195 check_warn_return(ret, "Error writing WUFF"); 1196 } 1197 1198 for (i = 0; i < (wuff_filter_count / 2); i++) { 1199 ret = smsc95xx_write_reg_nopm(dev, WUFF, crc[i]); 1200 check_warn_return(ret, "Error writing WUFF"); 1201 } 1202 1203 /* clear any pending pattern match packet status */ 1204 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); 1205 check_warn_return(ret, "Error reading WUCSR"); 1206 1207 val |= WUCSR_WUFR_; 1208 1209 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); 1210 check_warn_return(ret, "Error writing WUCSR"); 1211 } 1212 1213 if (pdata->wolopts & WAKE_MAGIC) { 1214 /* clear any pending magic packet status */ 1215 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); 1216 check_warn_return(ret, "Error reading WUCSR"); 1217 1218 val |= WUCSR_MPR_; 1219 1220 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); 1221 check_warn_return(ret, "Error writing WUCSR"); 1222 } 1223 1224 /* enable/disable wakeup sources */ 1225 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); 1226 check_warn_return(ret, "Error reading WUCSR"); 1227 1228 if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) { 1229 netdev_info(dev->net, "enabling pattern match wakeup"); 1230 val |= WUCSR_WAKE_EN_; 1231 } else { 1232 netdev_info(dev->net, "disabling pattern match wakeup"); 1233 val &= ~WUCSR_WAKE_EN_; 1234 } 1235 1236 if (pdata->wolopts & WAKE_MAGIC) { 1237 netdev_info(dev->net, "enabling magic packet wakeup"); 1238 val |= WUCSR_MPEN_; 1239 } else { 1240 netdev_info(dev->net, "disabling magic packet wakeup"); 1241 val &= ~WUCSR_MPEN_; 1242 } 1243 1244 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); 1245 check_warn_return(ret, "Error writing WUCSR"); 1246 1247 /* enable wol wakeup source */ 1248 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); 1249 check_warn_return(ret, "Error reading PM_CTRL"); 1250 1251 val |= PM_CTL_WOL_EN_; 1252 1253 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); 1254 check_warn_return(ret, "Error writing PM_CTRL"); 1255 1256 /* enable receiver to enable frame reception */ 1257 smsc95xx_start_rx_path(dev, 1); 1258 1259 /* some wol options are enabled, so enter SUSPEND0 */ 1260 netdev_info(dev->net, "entering SUSPEND0 mode"); 1261 1262 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); 1263 check_warn_return(ret, "Error reading PM_CTRL"); 1264 1265 val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_)); 1266 val |= PM_CTL_SUS_MODE_0; 1267 1268 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); 1269 check_warn_return(ret, "Error writing PM_CTRL"); 1270 1271 /* clear wol status */ 1272 val &= ~PM_CTL_WUPS_; 1273 val |= PM_CTL_WUPS_WOL_; 1274 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); 1275 check_warn_return(ret, "Error writing PM_CTRL"); 1276 1277 /* read back PM_CTRL */ 1278 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); 1279 check_warn_return(ret, "Error reading PM_CTRL"); 1280 1281 smsc95xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP); 1282 1283 return 0; 1284} 1285 1286static int smsc95xx_resume(struct usb_interface *intf) 1287{ 1288 struct usbnet *dev = usb_get_intfdata(intf); 1289 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); 1290 int ret; 1291 u32 val; 1292 1293 BUG_ON(!dev); 1294 1295 if (pdata->wolopts) { 1296 smsc95xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP); 1297 1298 /* clear wake-up sources */ 1299 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val); 1300 check_warn_return(ret, "Error reading WUCSR"); 1301 1302 val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_); 1303 1304 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val); 1305 check_warn_return(ret, "Error writing WUCSR"); 1306 1307 /* clear wake-up status */ 1308 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val); 1309 check_warn_return(ret, "Error reading PM_CTRL"); 1310 1311 val &= ~PM_CTL_WOL_EN_; 1312 val |= PM_CTL_WUPS_; 1313 1314 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val); 1315 check_warn_return(ret, "Error writing PM_CTRL"); 1316 } 1317 1318 ret = usbnet_resume(intf); 1319 check_warn_return(ret, "usbnet_resume error"); 1320 1321 return 0; 1322} 1323 1324static void smsc95xx_rx_csum_offload(struct sk_buff *skb) 1325{ 1326 skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2); 1327 skb->ip_summed = CHECKSUM_COMPLETE; 1328 skb_trim(skb, skb->len - 2); 1329} 1330 1331static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) 1332{ 1333 while (skb->len > 0) { 1334 u32 header, align_count; 1335 struct sk_buff *ax_skb; 1336 unsigned char *packet; 1337 u16 size; 1338 1339 memcpy(&header, skb->data, sizeof(header)); 1340 le32_to_cpus(&header); 1341 skb_pull(skb, 4 + NET_IP_ALIGN); 1342 packet = skb->data; 1343 1344 /* get the packet length */ 1345 size = (u16)((header & RX_STS_FL_) >> 16); 1346 align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4; 1347 1348 if (unlikely(header & RX_STS_ES_)) { 1349 netif_dbg(dev, rx_err, dev->net, 1350 "Error header=0x%08x\n", header); 1351 dev->net->stats.rx_errors++; 1352 dev->net->stats.rx_dropped++; 1353 1354 if (header & RX_STS_CRC_) { 1355 dev->net->stats.rx_crc_errors++; 1356 } else { 1357 if (header & (RX_STS_TL_ | RX_STS_RF_)) 1358 dev->net->stats.rx_frame_errors++; 1359 1360 if ((header & RX_STS_LE_) && 1361 (!(header & RX_STS_FT_))) 1362 dev->net->stats.rx_length_errors++; 1363 } 1364 } else { 1365 /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */ 1366 if (unlikely(size > (ETH_FRAME_LEN + 12))) { 1367 netif_dbg(dev, rx_err, dev->net, 1368 "size err header=0x%08x\n", header); 1369 return 0; 1370 } 1371 1372 /* last frame in this batch */ 1373 if (skb->len == size) { 1374 if (dev->net->features & NETIF_F_RXCSUM) 1375 smsc95xx_rx_csum_offload(skb); 1376 skb_trim(skb, skb->len - 4); /* remove fcs */ 1377 skb->truesize = size + sizeof(struct sk_buff); 1378 1379 return 1; 1380 } 1381 1382 ax_skb = skb_clone(skb, GFP_ATOMIC); 1383 if (unlikely(!ax_skb)) { 1384 netdev_warn(dev->net, "Error allocating skb\n"); 1385 return 0; 1386 } 1387 1388 ax_skb->len = size; 1389 ax_skb->data = packet; 1390 skb_set_tail_pointer(ax_skb, size); 1391 1392 if (dev->net->features & NETIF_F_RXCSUM) 1393 smsc95xx_rx_csum_offload(ax_skb); 1394 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ 1395 ax_skb->truesize = size + sizeof(struct sk_buff); 1396 1397 usbnet_skb_return(dev, ax_skb); 1398 } 1399 1400 skb_pull(skb, size); 1401 1402 /* padding bytes before the next frame starts */ 1403 if (skb->len) 1404 skb_pull(skb, align_count); 1405 } 1406 1407 if (unlikely(skb->len < 0)) { 1408 netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len); 1409 return 0; 1410 } 1411 1412 return 1; 1413} 1414 1415static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb) 1416{ 1417 u16 low_16 = (u16)skb_checksum_start_offset(skb); 1418 u16 high_16 = low_16 + skb->csum_offset; 1419 return (high_16 << 16) | low_16; 1420} 1421 1422static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev, 1423 struct sk_buff *skb, gfp_t flags) 1424{ 1425 bool csum = skb->ip_summed == CHECKSUM_PARTIAL; 1426 int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD; 1427 u32 tx_cmd_a, tx_cmd_b; 1428 1429 /* We do not advertise SG, so skbs should be already linearized */ 1430 BUG_ON(skb_shinfo(skb)->nr_frags); 1431 1432 if (skb_headroom(skb) < overhead) { 1433 struct sk_buff *skb2 = skb_copy_expand(skb, 1434 overhead, 0, flags); 1435 dev_kfree_skb_any(skb); 1436 skb = skb2; 1437 if (!skb) 1438 return NULL; 1439 } 1440 1441 if (csum) { 1442 if (skb->len <= 45) { 1443 /* workaround - hardware tx checksum does not work 1444 * properly with extremely small packets */ 1445 long csstart = skb_checksum_start_offset(skb); 1446 __wsum calc = csum_partial(skb->data + csstart, 1447 skb->len - csstart, 0); 1448 *((__sum16 *)(skb->data + csstart 1449 + skb->csum_offset)) = csum_fold(calc); 1450 1451 csum = false; 1452 } else { 1453 u32 csum_preamble = smsc95xx_calc_csum_preamble(skb); 1454 skb_push(skb, 4); 1455 cpu_to_le32s(&csum_preamble); 1456 memcpy(skb->data, &csum_preamble, 4); 1457 } 1458 } 1459 1460 skb_push(skb, 4); 1461 tx_cmd_b = (u32)(skb->len - 4); 1462 if (csum) 1463 tx_cmd_b |= TX_CMD_B_CSUM_ENABLE; 1464 cpu_to_le32s(&tx_cmd_b); 1465 memcpy(skb->data, &tx_cmd_b, 4); 1466 1467 skb_push(skb, 4); 1468 tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ | 1469 TX_CMD_A_LAST_SEG_; 1470 cpu_to_le32s(&tx_cmd_a); 1471 memcpy(skb->data, &tx_cmd_a, 4); 1472 1473 return skb; 1474} 1475 1476static const struct driver_info smsc95xx_info = { 1477 .description = "smsc95xx USB 2.0 Ethernet", 1478 .bind = smsc95xx_bind, 1479 .unbind = smsc95xx_unbind, 1480 .link_reset = smsc95xx_link_reset, 1481 .reset = smsc95xx_reset, 1482 .rx_fixup = smsc95xx_rx_fixup, 1483 .tx_fixup = smsc95xx_tx_fixup, 1484 .status = smsc95xx_status, 1485 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR, 1486}; 1487 1488static const struct usb_device_id products[] = { 1489 { 1490 /* SMSC9500 USB Ethernet Device */ 1491 USB_DEVICE(0x0424, 0x9500), 1492 .driver_info = (unsigned long) &smsc95xx_info, 1493 }, 1494 { 1495 /* SMSC9505 USB Ethernet Device */ 1496 USB_DEVICE(0x0424, 0x9505), 1497 .driver_info = (unsigned long) &smsc95xx_info, 1498 }, 1499 { 1500 /* SMSC9500A USB Ethernet Device */ 1501 USB_DEVICE(0x0424, 0x9E00), 1502 .driver_info = (unsigned long) &smsc95xx_info, 1503 }, 1504 { 1505 /* SMSC9505A USB Ethernet Device */ 1506 USB_DEVICE(0x0424, 0x9E01), 1507 .driver_info = (unsigned long) &smsc95xx_info, 1508 }, 1509 { 1510 /* SMSC9512/9514 USB Hub & Ethernet Device */ 1511 USB_DEVICE(0x0424, 0xec00), 1512 .driver_info = (unsigned long) &smsc95xx_info, 1513 }, 1514 { 1515 /* SMSC9500 USB Ethernet Device (SAL10) */ 1516 USB_DEVICE(0x0424, 0x9900), 1517 .driver_info = (unsigned long) &smsc95xx_info, 1518 }, 1519 { 1520 /* SMSC9505 USB Ethernet Device (SAL10) */ 1521 USB_DEVICE(0x0424, 0x9901), 1522 .driver_info = (unsigned long) &smsc95xx_info, 1523 }, 1524 { 1525 /* SMSC9500A USB Ethernet Device (SAL10) */ 1526 USB_DEVICE(0x0424, 0x9902), 1527 .driver_info = (unsigned long) &smsc95xx_info, 1528 }, 1529 { 1530 /* SMSC9505A USB Ethernet Device (SAL10) */ 1531 USB_DEVICE(0x0424, 0x9903), 1532 .driver_info = (unsigned long) &smsc95xx_info, 1533 }, 1534 { 1535 /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */ 1536 USB_DEVICE(0x0424, 0x9904), 1537 .driver_info = (unsigned long) &smsc95xx_info, 1538 }, 1539 { 1540 /* SMSC9500A USB Ethernet Device (HAL) */ 1541 USB_DEVICE(0x0424, 0x9905), 1542 .driver_info = (unsigned long) &smsc95xx_info, 1543 }, 1544 { 1545 /* SMSC9505A USB Ethernet Device (HAL) */ 1546 USB_DEVICE(0x0424, 0x9906), 1547 .driver_info = (unsigned long) &smsc95xx_info, 1548 }, 1549 { 1550 /* SMSC9500 USB Ethernet Device (Alternate ID) */ 1551 USB_DEVICE(0x0424, 0x9907), 1552 .driver_info = (unsigned long) &smsc95xx_info, 1553 }, 1554 { 1555 /* SMSC9500A USB Ethernet Device (Alternate ID) */ 1556 USB_DEVICE(0x0424, 0x9908), 1557 .driver_info = (unsigned long) &smsc95xx_info, 1558 }, 1559 { 1560 /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */ 1561 USB_DEVICE(0x0424, 0x9909), 1562 .driver_info = (unsigned long) &smsc95xx_info, 1563 }, 1564 { 1565 /* SMSC LAN9530 USB Ethernet Device */ 1566 USB_DEVICE(0x0424, 0x9530), 1567 .driver_info = (unsigned long) &smsc95xx_info, 1568 }, 1569 { 1570 /* SMSC LAN9730 USB Ethernet Device */ 1571 USB_DEVICE(0x0424, 0x9730), 1572 .driver_info = (unsigned long) &smsc95xx_info, 1573 }, 1574 { 1575 /* SMSC LAN89530 USB Ethernet Device */ 1576 USB_DEVICE(0x0424, 0x9E08), 1577 .driver_info = (unsigned long) &smsc95xx_info, 1578 }, 1579 { }, /* END */ 1580}; 1581MODULE_DEVICE_TABLE(usb, products); 1582 1583static struct usb_driver smsc95xx_driver = { 1584 .name = "smsc95xx", 1585 .id_table = products, 1586 .probe = usbnet_probe, 1587 .suspend = smsc95xx_suspend, 1588 .resume = smsc95xx_resume, 1589 .reset_resume = smsc95xx_resume, 1590 .disconnect = usbnet_disconnect, 1591 .disable_hub_initiated_lpm = 1, 1592}; 1593 1594module_usb_driver(smsc95xx_driver); 1595 1596MODULE_AUTHOR("Nancy Lin"); 1597MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); 1598MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices"); 1599MODULE_LICENSE("GPL"); 1600