vmxnet3_drv.c revision 1ae5dc342ac78d7a42965fd1f323815f6f5ef2c1
1/* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com> 24 * 25 */ 26 27#include <net/ip6_checksum.h> 28 29#include "vmxnet3_int.h" 30 31char vmxnet3_driver_name[] = "vmxnet3"; 32#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver" 33 34/* 35 * PCI Device ID Table 36 * Last entry must be all 0s 37 */ 38static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = { 39 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)}, 40 {0} 41}; 42 43MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table); 44 45static atomic_t devices_found; 46 47 48/* 49 * Enable/Disable the given intr 50 */ 51static void 52vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 53{ 54 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0); 55} 56 57 58static void 59vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 60{ 61 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1); 62} 63 64 65/* 66 * Enable/Disable all intrs used by the device 67 */ 68static void 69vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter) 70{ 71 int i; 72 73 for (i = 0; i < adapter->intr.num_intrs; i++) 74 vmxnet3_enable_intr(adapter, i); 75} 76 77 78static void 79vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter) 80{ 81 int i; 82 83 for (i = 0; i < adapter->intr.num_intrs; i++) 84 vmxnet3_disable_intr(adapter, i); 85} 86 87 88static void 89vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events) 90{ 91 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events); 92} 93 94 95static bool 96vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 97{ 98 return netif_queue_stopped(adapter->netdev); 99} 100 101 102static void 103vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 104{ 105 tq->stopped = false; 106 netif_start_queue(adapter->netdev); 107} 108 109 110static void 111vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 112{ 113 tq->stopped = false; 114 netif_wake_queue(adapter->netdev); 115} 116 117 118static void 119vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 120{ 121 tq->stopped = true; 122 tq->num_stop++; 123 netif_stop_queue(adapter->netdev); 124} 125 126 127/* 128 * Check the link state. This may start or stop the tx queue. 129 */ 130static void 131vmxnet3_check_link(struct vmxnet3_adapter *adapter) 132{ 133 u32 ret; 134 135 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 136 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 137 adapter->link_speed = ret >> 16; 138 if (ret & 1) { /* Link is up. */ 139 printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n", 140 adapter->netdev->name, adapter->link_speed); 141 if (!netif_carrier_ok(adapter->netdev)) 142 netif_carrier_on(adapter->netdev); 143 144 vmxnet3_tq_start(&adapter->tx_queue, adapter); 145 } else { 146 printk(KERN_INFO "%s: NIC Link is Down\n", 147 adapter->netdev->name); 148 if (netif_carrier_ok(adapter->netdev)) 149 netif_carrier_off(adapter->netdev); 150 151 vmxnet3_tq_stop(&adapter->tx_queue, adapter); 152 } 153} 154 155static void 156vmxnet3_process_events(struct vmxnet3_adapter *adapter) 157{ 158 u32 events = le32_to_cpu(adapter->shared->ecr); 159 if (!events) 160 return; 161 162 vmxnet3_ack_events(adapter, events); 163 164 /* Check if link state has changed */ 165 if (events & VMXNET3_ECR_LINK) 166 vmxnet3_check_link(adapter); 167 168 /* Check if there is an error on xmit/recv queues */ 169 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 170 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 171 VMXNET3_CMD_GET_QUEUE_STATUS); 172 173 if (adapter->tqd_start->status.stopped) { 174 printk(KERN_ERR "%s: tq error 0x%x\n", 175 adapter->netdev->name, 176 le32_to_cpu(adapter->tqd_start->status.error)); 177 } 178 if (adapter->rqd_start->status.stopped) { 179 printk(KERN_ERR "%s: rq error 0x%x\n", 180 adapter->netdev->name, 181 adapter->rqd_start->status.error); 182 } 183 184 schedule_work(&adapter->work); 185 } 186} 187 188#ifdef __BIG_ENDIAN_BITFIELD 189/* 190 * The device expects the bitfields in shared structures to be written in 191 * little endian. When CPU is big endian, the following routines are used to 192 * correctly read and write into ABI. 193 * The general technique used here is : double word bitfields are defined in 194 * opposite order for big endian architecture. Then before reading them in 195 * driver the complete double word is translated using le32_to_cpu. Similarly 196 * After the driver writes into bitfields, cpu_to_le32 is used to translate the 197 * double words into required format. 198 * In order to avoid touching bits in shared structure more than once, temporary 199 * descriptors are used. These are passed as srcDesc to following functions. 200 */ 201static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc, 202 struct Vmxnet3_RxDesc *dstDesc) 203{ 204 u32 *src = (u32 *)srcDesc + 2; 205 u32 *dst = (u32 *)dstDesc + 2; 206 dstDesc->addr = le64_to_cpu(srcDesc->addr); 207 *dst = le32_to_cpu(*src); 208 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1); 209} 210 211static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc, 212 struct Vmxnet3_TxDesc *dstDesc) 213{ 214 int i; 215 u32 *src = (u32 *)(srcDesc + 1); 216 u32 *dst = (u32 *)(dstDesc + 1); 217 218 /* Working backwards so that the gen bit is set at the end. */ 219 for (i = 2; i > 0; i--) { 220 src--; 221 dst--; 222 *dst = cpu_to_le32(*src); 223 } 224} 225 226 227static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc, 228 struct Vmxnet3_RxCompDesc *dstDesc) 229{ 230 int i = 0; 231 u32 *src = (u32 *)srcDesc; 232 u32 *dst = (u32 *)dstDesc; 233 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) { 234 *dst = le32_to_cpu(*src); 235 src++; 236 dst++; 237 } 238} 239 240 241/* Used to read bitfield values from double words. */ 242static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size) 243{ 244 u32 temp = le32_to_cpu(*bitfield); 245 u32 mask = ((1 << size) - 1) << pos; 246 temp &= mask; 247 temp >>= pos; 248 return temp; 249} 250 251 252 253#endif /* __BIG_ENDIAN_BITFIELD */ 254 255#ifdef __BIG_ENDIAN_BITFIELD 256 257# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \ 258 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \ 259 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE) 260# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \ 261 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \ 262 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE) 263# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \ 264 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \ 265 VMXNET3_TCD_GEN_SIZE) 266# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \ 267 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE) 268# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \ 269 (dstrcd) = (tmp); \ 270 vmxnet3_RxCompToCPU((rcd), (tmp)); \ 271 } while (0) 272# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \ 273 (dstrxd) = (tmp); \ 274 vmxnet3_RxDescToCPU((rxd), (tmp)); \ 275 } while (0) 276 277#else 278 279# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen) 280# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop) 281# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen) 282# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx) 283# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd) 284# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd) 285 286#endif /* __BIG_ENDIAN_BITFIELD */ 287 288 289static void 290vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi, 291 struct pci_dev *pdev) 292{ 293 if (tbi->map_type == VMXNET3_MAP_SINGLE) 294 pci_unmap_single(pdev, tbi->dma_addr, tbi->len, 295 PCI_DMA_TODEVICE); 296 else if (tbi->map_type == VMXNET3_MAP_PAGE) 297 pci_unmap_page(pdev, tbi->dma_addr, tbi->len, 298 PCI_DMA_TODEVICE); 299 else 300 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE); 301 302 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */ 303} 304 305 306static int 307vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq, 308 struct pci_dev *pdev, struct vmxnet3_adapter *adapter) 309{ 310 struct sk_buff *skb; 311 int entries = 0; 312 313 /* no out of order completion */ 314 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp); 315 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); 316 317 skb = tq->buf_info[eop_idx].skb; 318 BUG_ON(skb == NULL); 319 tq->buf_info[eop_idx].skb = NULL; 320 321 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size); 322 323 while (tq->tx_ring.next2comp != eop_idx) { 324 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp, 325 pdev); 326 327 /* update next2comp w/o tx_lock. Since we are marking more, 328 * instead of less, tx ring entries avail, the worst case is 329 * that the tx routine incorrectly re-queues a pkt due to 330 * insufficient tx ring entries. 331 */ 332 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 333 entries++; 334 } 335 336 dev_kfree_skb_any(skb); 337 return entries; 338} 339 340 341static int 342vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq, 343 struct vmxnet3_adapter *adapter) 344{ 345 int completed = 0; 346 union Vmxnet3_GenericDesc *gdesc; 347 348 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 349 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) { 350 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX( 351 &gdesc->tcd), tq, adapter->pdev, 352 adapter); 353 354 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring); 355 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 356 } 357 358 if (completed) { 359 spin_lock(&tq->tx_lock); 360 if (unlikely(vmxnet3_tq_stopped(tq, adapter) && 361 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) > 362 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) && 363 netif_carrier_ok(adapter->netdev))) { 364 vmxnet3_tq_wake(tq, adapter); 365 } 366 spin_unlock(&tq->tx_lock); 367 } 368 return completed; 369} 370 371 372static void 373vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq, 374 struct vmxnet3_adapter *adapter) 375{ 376 int i; 377 378 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) { 379 struct vmxnet3_tx_buf_info *tbi; 380 union Vmxnet3_GenericDesc *gdesc; 381 382 tbi = tq->buf_info + tq->tx_ring.next2comp; 383 gdesc = tq->tx_ring.base + tq->tx_ring.next2comp; 384 385 vmxnet3_unmap_tx_buf(tbi, adapter->pdev); 386 if (tbi->skb) { 387 dev_kfree_skb_any(tbi->skb); 388 tbi->skb = NULL; 389 } 390 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 391 } 392 393 /* sanity check, verify all buffers are indeed unmapped and freed */ 394 for (i = 0; i < tq->tx_ring.size; i++) { 395 BUG_ON(tq->buf_info[i].skb != NULL || 396 tq->buf_info[i].map_type != VMXNET3_MAP_NONE); 397 } 398 399 tq->tx_ring.gen = VMXNET3_INIT_GEN; 400 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 401 402 tq->comp_ring.gen = VMXNET3_INIT_GEN; 403 tq->comp_ring.next2proc = 0; 404} 405 406 407void 408vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq, 409 struct vmxnet3_adapter *adapter) 410{ 411 if (tq->tx_ring.base) { 412 pci_free_consistent(adapter->pdev, tq->tx_ring.size * 413 sizeof(struct Vmxnet3_TxDesc), 414 tq->tx_ring.base, tq->tx_ring.basePA); 415 tq->tx_ring.base = NULL; 416 } 417 if (tq->data_ring.base) { 418 pci_free_consistent(adapter->pdev, tq->data_ring.size * 419 sizeof(struct Vmxnet3_TxDataDesc), 420 tq->data_ring.base, tq->data_ring.basePA); 421 tq->data_ring.base = NULL; 422 } 423 if (tq->comp_ring.base) { 424 pci_free_consistent(adapter->pdev, tq->comp_ring.size * 425 sizeof(struct Vmxnet3_TxCompDesc), 426 tq->comp_ring.base, tq->comp_ring.basePA); 427 tq->comp_ring.base = NULL; 428 } 429 kfree(tq->buf_info); 430 tq->buf_info = NULL; 431} 432 433 434static void 435vmxnet3_tq_init(struct vmxnet3_tx_queue *tq, 436 struct vmxnet3_adapter *adapter) 437{ 438 int i; 439 440 /* reset the tx ring contents to 0 and reset the tx ring states */ 441 memset(tq->tx_ring.base, 0, tq->tx_ring.size * 442 sizeof(struct Vmxnet3_TxDesc)); 443 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 444 tq->tx_ring.gen = VMXNET3_INIT_GEN; 445 446 memset(tq->data_ring.base, 0, tq->data_ring.size * 447 sizeof(struct Vmxnet3_TxDataDesc)); 448 449 /* reset the tx comp ring contents to 0 and reset comp ring states */ 450 memset(tq->comp_ring.base, 0, tq->comp_ring.size * 451 sizeof(struct Vmxnet3_TxCompDesc)); 452 tq->comp_ring.next2proc = 0; 453 tq->comp_ring.gen = VMXNET3_INIT_GEN; 454 455 /* reset the bookkeeping data */ 456 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size); 457 for (i = 0; i < tq->tx_ring.size; i++) 458 tq->buf_info[i].map_type = VMXNET3_MAP_NONE; 459 460 /* stats are not reset */ 461} 462 463 464static int 465vmxnet3_tq_create(struct vmxnet3_tx_queue *tq, 466 struct vmxnet3_adapter *adapter) 467{ 468 BUG_ON(tq->tx_ring.base || tq->data_ring.base || 469 tq->comp_ring.base || tq->buf_info); 470 471 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size 472 * sizeof(struct Vmxnet3_TxDesc), 473 &tq->tx_ring.basePA); 474 if (!tq->tx_ring.base) { 475 printk(KERN_ERR "%s: failed to allocate tx ring\n", 476 adapter->netdev->name); 477 goto err; 478 } 479 480 tq->data_ring.base = pci_alloc_consistent(adapter->pdev, 481 tq->data_ring.size * 482 sizeof(struct Vmxnet3_TxDataDesc), 483 &tq->data_ring.basePA); 484 if (!tq->data_ring.base) { 485 printk(KERN_ERR "%s: failed to allocate data ring\n", 486 adapter->netdev->name); 487 goto err; 488 } 489 490 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev, 491 tq->comp_ring.size * 492 sizeof(struct Vmxnet3_TxCompDesc), 493 &tq->comp_ring.basePA); 494 if (!tq->comp_ring.base) { 495 printk(KERN_ERR "%s: failed to allocate tx comp ring\n", 496 adapter->netdev->name); 497 goto err; 498 } 499 500 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]), 501 GFP_KERNEL); 502 if (!tq->buf_info) { 503 printk(KERN_ERR "%s: failed to allocate tx bufinfo\n", 504 adapter->netdev->name); 505 goto err; 506 } 507 508 return 0; 509 510err: 511 vmxnet3_tq_destroy(tq, adapter); 512 return -ENOMEM; 513} 514 515 516/* 517 * starting from ring->next2fill, allocate rx buffers for the given ring 518 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers 519 * are allocated or allocation fails 520 */ 521 522static int 523vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx, 524 int num_to_alloc, struct vmxnet3_adapter *adapter) 525{ 526 int num_allocated = 0; 527 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx]; 528 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx]; 529 u32 val; 530 531 while (num_allocated < num_to_alloc) { 532 struct vmxnet3_rx_buf_info *rbi; 533 union Vmxnet3_GenericDesc *gd; 534 535 rbi = rbi_base + ring->next2fill; 536 gd = ring->base + ring->next2fill; 537 538 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) { 539 if (rbi->skb == NULL) { 540 rbi->skb = dev_alloc_skb(rbi->len + 541 NET_IP_ALIGN); 542 if (unlikely(rbi->skb == NULL)) { 543 rq->stats.rx_buf_alloc_failure++; 544 break; 545 } 546 rbi->skb->dev = adapter->netdev; 547 548 skb_reserve(rbi->skb, NET_IP_ALIGN); 549 rbi->dma_addr = pci_map_single(adapter->pdev, 550 rbi->skb->data, rbi->len, 551 PCI_DMA_FROMDEVICE); 552 } else { 553 /* rx buffer skipped by the device */ 554 } 555 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; 556 } else { 557 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE || 558 rbi->len != PAGE_SIZE); 559 560 if (rbi->page == NULL) { 561 rbi->page = alloc_page(GFP_ATOMIC); 562 if (unlikely(rbi->page == NULL)) { 563 rq->stats.rx_buf_alloc_failure++; 564 break; 565 } 566 rbi->dma_addr = pci_map_page(adapter->pdev, 567 rbi->page, 0, PAGE_SIZE, 568 PCI_DMA_FROMDEVICE); 569 } else { 570 /* rx buffers skipped by the device */ 571 } 572 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; 573 } 574 575 BUG_ON(rbi->dma_addr == 0); 576 gd->rxd.addr = cpu_to_le64(rbi->dma_addr); 577 gd->dword[2] = cpu_to_le32((ring->gen << VMXNET3_RXD_GEN_SHIFT) 578 | val | rbi->len); 579 580 num_allocated++; 581 vmxnet3_cmd_ring_adv_next2fill(ring); 582 } 583 rq->uncommitted[ring_idx] += num_allocated; 584 585 dev_dbg(&adapter->netdev->dev, 586 "alloc_rx_buf: %d allocated, next2fill %u, next2comp " 587 "%u, uncommited %u\n", num_allocated, ring->next2fill, 588 ring->next2comp, rq->uncommitted[ring_idx]); 589 590 /* so that the device can distinguish a full ring and an empty ring */ 591 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp); 592 593 return num_allocated; 594} 595 596 597static void 598vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd, 599 struct vmxnet3_rx_buf_info *rbi) 600{ 601 struct skb_frag_struct *frag = skb_shinfo(skb)->frags + 602 skb_shinfo(skb)->nr_frags; 603 604 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS); 605 606 frag->page = rbi->page; 607 frag->page_offset = 0; 608 frag->size = rcd->len; 609 skb->data_len += frag->size; 610 skb_shinfo(skb)->nr_frags++; 611} 612 613 614static void 615vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, 616 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev, 617 struct vmxnet3_adapter *adapter) 618{ 619 u32 dw2, len; 620 unsigned long buf_offset; 621 int i; 622 union Vmxnet3_GenericDesc *gdesc; 623 struct vmxnet3_tx_buf_info *tbi = NULL; 624 625 BUG_ON(ctx->copy_size > skb_headlen(skb)); 626 627 /* use the previous gen bit for the SOP desc */ 628 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT; 629 630 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; 631 gdesc = ctx->sop_txd; /* both loops below can be skipped */ 632 633 /* no need to map the buffer if headers are copied */ 634 if (ctx->copy_size) { 635 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA + 636 tq->tx_ring.next2fill * 637 sizeof(struct Vmxnet3_TxDataDesc)); 638 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size); 639 ctx->sop_txd->dword[3] = 0; 640 641 tbi = tq->buf_info + tq->tx_ring.next2fill; 642 tbi->map_type = VMXNET3_MAP_NONE; 643 644 dev_dbg(&adapter->netdev->dev, 645 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 646 tq->tx_ring.next2fill, 647 le64_to_cpu(ctx->sop_txd->txd.addr), 648 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]); 649 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 650 651 /* use the right gen for non-SOP desc */ 652 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 653 } 654 655 /* linear part can use multiple tx desc if it's big */ 656 len = skb_headlen(skb) - ctx->copy_size; 657 buf_offset = ctx->copy_size; 658 while (len) { 659 u32 buf_size; 660 661 buf_size = len > VMXNET3_MAX_TX_BUF_SIZE ? 662 VMXNET3_MAX_TX_BUF_SIZE : len; 663 664 tbi = tq->buf_info + tq->tx_ring.next2fill; 665 tbi->map_type = VMXNET3_MAP_SINGLE; 666 tbi->dma_addr = pci_map_single(adapter->pdev, 667 skb->data + buf_offset, buf_size, 668 PCI_DMA_TODEVICE); 669 670 tbi->len = buf_size; /* this automatically convert 2^14 to 0 */ 671 672 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 673 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 674 675 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 676 gdesc->dword[2] = cpu_to_le32(dw2 | buf_size); 677 gdesc->dword[3] = 0; 678 679 dev_dbg(&adapter->netdev->dev, 680 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 681 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 682 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 683 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 684 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 685 686 len -= buf_size; 687 buf_offset += buf_size; 688 } 689 690 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 691 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 692 693 tbi = tq->buf_info + tq->tx_ring.next2fill; 694 tbi->map_type = VMXNET3_MAP_PAGE; 695 tbi->dma_addr = pci_map_page(adapter->pdev, frag->page, 696 frag->page_offset, frag->size, 697 PCI_DMA_TODEVICE); 698 699 tbi->len = frag->size; 700 701 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 702 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 703 704 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 705 gdesc->dword[2] = cpu_to_le32(dw2 | frag->size); 706 gdesc->dword[3] = 0; 707 708 dev_dbg(&adapter->netdev->dev, 709 "txd[%u]: 0x%llu %u %u\n", 710 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 711 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 712 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 713 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 714 } 715 716 ctx->eop_txd = gdesc; 717 718 /* set the last buf_info for the pkt */ 719 tbi->skb = skb; 720 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; 721} 722 723 724/* 725 * parse and copy relevant protocol headers: 726 * For a tso pkt, relevant headers are L2/3/4 including options 727 * For a pkt requesting csum offloading, they are L2/3 and may include L4 728 * if it's a TCP/UDP pkt 729 * 730 * Returns: 731 * -1: error happens during parsing 732 * 0: protocol headers parsed, but too big to be copied 733 * 1: protocol headers parsed and copied 734 * 735 * Other effects: 736 * 1. related *ctx fields are updated. 737 * 2. ctx->copy_size is # of bytes copied 738 * 3. the portion copied is guaranteed to be in the linear part 739 * 740 */ 741static int 742vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 743 struct vmxnet3_tx_ctx *ctx, 744 struct vmxnet3_adapter *adapter) 745{ 746 struct Vmxnet3_TxDataDesc *tdd; 747 748 if (ctx->mss) { 749 ctx->eth_ip_hdr_size = skb_transport_offset(skb); 750 ctx->l4_hdr_size = ((struct tcphdr *) 751 skb_transport_header(skb))->doff * 4; 752 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size; 753 } else { 754 unsigned int pull_size; 755 756 if (skb->ip_summed == CHECKSUM_PARTIAL) { 757 ctx->eth_ip_hdr_size = skb_transport_offset(skb); 758 759 if (ctx->ipv4) { 760 struct iphdr *iph = (struct iphdr *) 761 skb_network_header(skb); 762 if (iph->protocol == IPPROTO_TCP) { 763 pull_size = ctx->eth_ip_hdr_size + 764 sizeof(struct tcphdr); 765 766 if (unlikely(!pskb_may_pull(skb, 767 pull_size))) { 768 goto err; 769 } 770 ctx->l4_hdr_size = ((struct tcphdr *) 771 skb_transport_header(skb))->doff * 4; 772 } else if (iph->protocol == IPPROTO_UDP) { 773 ctx->l4_hdr_size = 774 sizeof(struct udphdr); 775 } else { 776 ctx->l4_hdr_size = 0; 777 } 778 } else { 779 /* for simplicity, don't copy L4 headers */ 780 ctx->l4_hdr_size = 0; 781 } 782 ctx->copy_size = ctx->eth_ip_hdr_size + 783 ctx->l4_hdr_size; 784 } else { 785 ctx->eth_ip_hdr_size = 0; 786 ctx->l4_hdr_size = 0; 787 /* copy as much as allowed */ 788 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE 789 , skb_headlen(skb)); 790 } 791 792 /* make sure headers are accessible directly */ 793 if (unlikely(!pskb_may_pull(skb, ctx->copy_size))) 794 goto err; 795 } 796 797 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) { 798 tq->stats.oversized_hdr++; 799 ctx->copy_size = 0; 800 return 0; 801 } 802 803 tdd = tq->data_ring.base + tq->tx_ring.next2fill; 804 805 memcpy(tdd->data, skb->data, ctx->copy_size); 806 dev_dbg(&adapter->netdev->dev, 807 "copy %u bytes to dataRing[%u]\n", 808 ctx->copy_size, tq->tx_ring.next2fill); 809 return 1; 810 811err: 812 return -1; 813} 814 815 816static void 817vmxnet3_prepare_tso(struct sk_buff *skb, 818 struct vmxnet3_tx_ctx *ctx) 819{ 820 struct tcphdr *tcph = (struct tcphdr *)skb_transport_header(skb); 821 if (ctx->ipv4) { 822 struct iphdr *iph = (struct iphdr *)skb_network_header(skb); 823 iph->check = 0; 824 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 825 IPPROTO_TCP, 0); 826 } else { 827 struct ipv6hdr *iph = (struct ipv6hdr *)skb_network_header(skb); 828 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0, 829 IPPROTO_TCP, 0); 830 } 831} 832 833 834/* 835 * Transmits a pkt thru a given tq 836 * Returns: 837 * NETDEV_TX_OK: descriptors are setup successfully 838 * NETDEV_TX_OK: error occured, the pkt is dropped 839 * NETDEV_TX_BUSY: tx ring is full, queue is stopped 840 * 841 * Side-effects: 842 * 1. tx ring may be changed 843 * 2. tq stats may be updated accordingly 844 * 3. shared->txNumDeferred may be updated 845 */ 846 847static int 848vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 849 struct vmxnet3_adapter *adapter, struct net_device *netdev) 850{ 851 int ret; 852 u32 count; 853 unsigned long flags; 854 struct vmxnet3_tx_ctx ctx; 855 union Vmxnet3_GenericDesc *gdesc; 856#ifdef __BIG_ENDIAN_BITFIELD 857 /* Use temporary descriptor to avoid touching bits multiple times */ 858 union Vmxnet3_GenericDesc tempTxDesc; 859#endif 860 861 /* conservatively estimate # of descriptors to use */ 862 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 863 skb_shinfo(skb)->nr_frags + 1; 864 865 ctx.ipv4 = (skb->protocol == __constant_ntohs(ETH_P_IP)); 866 867 ctx.mss = skb_shinfo(skb)->gso_size; 868 if (ctx.mss) { 869 if (skb_header_cloned(skb)) { 870 if (unlikely(pskb_expand_head(skb, 0, 0, 871 GFP_ATOMIC) != 0)) { 872 tq->stats.drop_tso++; 873 goto drop_pkt; 874 } 875 tq->stats.copy_skb_header++; 876 } 877 vmxnet3_prepare_tso(skb, &ctx); 878 } else { 879 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) { 880 881 /* non-tso pkts must not use more than 882 * VMXNET3_MAX_TXD_PER_PKT entries 883 */ 884 if (skb_linearize(skb) != 0) { 885 tq->stats.drop_too_many_frags++; 886 goto drop_pkt; 887 } 888 tq->stats.linearized++; 889 890 /* recalculate the # of descriptors to use */ 891 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 892 } 893 } 894 895 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter); 896 if (ret >= 0) { 897 BUG_ON(ret <= 0 && ctx.copy_size != 0); 898 /* hdrs parsed, check against other limits */ 899 if (ctx.mss) { 900 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size > 901 VMXNET3_MAX_TX_BUF_SIZE)) { 902 goto hdr_too_big; 903 } 904 } else { 905 if (skb->ip_summed == CHECKSUM_PARTIAL) { 906 if (unlikely(ctx.eth_ip_hdr_size + 907 skb->csum_offset > 908 VMXNET3_MAX_CSUM_OFFSET)) { 909 goto hdr_too_big; 910 } 911 } 912 } 913 } else { 914 tq->stats.drop_hdr_inspect_err++; 915 goto drop_pkt; 916 } 917 918 spin_lock_irqsave(&tq->tx_lock, flags); 919 920 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) { 921 tq->stats.tx_ring_full++; 922 dev_dbg(&adapter->netdev->dev, 923 "tx queue stopped on %s, next2comp %u" 924 " next2fill %u\n", adapter->netdev->name, 925 tq->tx_ring.next2comp, tq->tx_ring.next2fill); 926 927 vmxnet3_tq_stop(tq, adapter); 928 spin_unlock_irqrestore(&tq->tx_lock, flags); 929 return NETDEV_TX_BUSY; 930 } 931 932 /* fill tx descs related to addr & len */ 933 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter); 934 935 /* setup the EOP desc */ 936 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP); 937 938 /* setup the SOP desc */ 939#ifdef __BIG_ENDIAN_BITFIELD 940 gdesc = &tempTxDesc; 941 gdesc->dword[2] = ctx.sop_txd->dword[2]; 942 gdesc->dword[3] = ctx.sop_txd->dword[3]; 943#else 944 gdesc = ctx.sop_txd; 945#endif 946 if (ctx.mss) { 947 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size; 948 gdesc->txd.om = VMXNET3_OM_TSO; 949 gdesc->txd.msscof = ctx.mss; 950 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len - 951 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss); 952 } else { 953 if (skb->ip_summed == CHECKSUM_PARTIAL) { 954 gdesc->txd.hlen = ctx.eth_ip_hdr_size; 955 gdesc->txd.om = VMXNET3_OM_CSUM; 956 gdesc->txd.msscof = ctx.eth_ip_hdr_size + 957 skb->csum_offset; 958 } else { 959 gdesc->txd.om = 0; 960 gdesc->txd.msscof = 0; 961 } 962 le32_add_cpu(&tq->shared->txNumDeferred, 1); 963 } 964 965 if (vlan_tx_tag_present(skb)) { 966 gdesc->txd.ti = 1; 967 gdesc->txd.tci = vlan_tx_tag_get(skb); 968 } 969 970 /* finally flips the GEN bit of the SOP desc. */ 971 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^ 972 VMXNET3_TXD_GEN); 973#ifdef __BIG_ENDIAN_BITFIELD 974 /* Finished updating in bitfields of Tx Desc, so write them in original 975 * place. 976 */ 977 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc, 978 (struct Vmxnet3_TxDesc *)ctx.sop_txd); 979 gdesc = ctx.sop_txd; 980#endif 981 dev_dbg(&adapter->netdev->dev, 982 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n", 983 (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd - 984 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), 985 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3])); 986 987 spin_unlock_irqrestore(&tq->tx_lock, flags); 988 989 if (le32_to_cpu(tq->shared->txNumDeferred) >= 990 le32_to_cpu(tq->shared->txThreshold)) { 991 tq->shared->txNumDeferred = 0; 992 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_TXPROD, 993 tq->tx_ring.next2fill); 994 } 995 996 return NETDEV_TX_OK; 997 998hdr_too_big: 999 tq->stats.drop_oversized_hdr++; 1000drop_pkt: 1001 tq->stats.drop_total++; 1002 dev_kfree_skb(skb); 1003 return NETDEV_TX_OK; 1004} 1005 1006 1007static netdev_tx_t 1008vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1009{ 1010 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1011 1012 return vmxnet3_tq_xmit(skb, &adapter->tx_queue, adapter, netdev); 1013} 1014 1015 1016static void 1017vmxnet3_rx_csum(struct vmxnet3_adapter *adapter, 1018 struct sk_buff *skb, 1019 union Vmxnet3_GenericDesc *gdesc) 1020{ 1021 if (!gdesc->rcd.cnc && adapter->rxcsum) { 1022 /* typical case: TCP/UDP over IP and both csums are correct */ 1023 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) == 1024 VMXNET3_RCD_CSUM_OK) { 1025 skb->ip_summed = CHECKSUM_UNNECESSARY; 1026 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1027 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6)); 1028 BUG_ON(gdesc->rcd.frg); 1029 } else { 1030 if (gdesc->rcd.csum) { 1031 skb->csum = htons(gdesc->rcd.csum); 1032 skb->ip_summed = CHECKSUM_PARTIAL; 1033 } else { 1034 skb->ip_summed = CHECKSUM_NONE; 1035 } 1036 } 1037 } else { 1038 skb->ip_summed = CHECKSUM_NONE; 1039 } 1040} 1041 1042 1043static void 1044vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd, 1045 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter) 1046{ 1047 rq->stats.drop_err++; 1048 if (!rcd->fcs) 1049 rq->stats.drop_fcs++; 1050 1051 rq->stats.drop_total++; 1052 1053 /* 1054 * We do not unmap and chain the rx buffer to the skb. 1055 * We basically pretend this buffer is not used and will be recycled 1056 * by vmxnet3_rq_alloc_rx_buf() 1057 */ 1058 1059 /* 1060 * ctx->skb may be NULL if this is the first and the only one 1061 * desc for the pkt 1062 */ 1063 if (ctx->skb) 1064 dev_kfree_skb_irq(ctx->skb); 1065 1066 ctx->skb = NULL; 1067} 1068 1069 1070static int 1071vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq, 1072 struct vmxnet3_adapter *adapter, int quota) 1073{ 1074 static u32 rxprod_reg[2] = {VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2}; 1075 u32 num_rxd = 0; 1076 struct Vmxnet3_RxCompDesc *rcd; 1077 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx; 1078#ifdef __BIG_ENDIAN_BITFIELD 1079 struct Vmxnet3_RxDesc rxCmdDesc; 1080 struct Vmxnet3_RxCompDesc rxComp; 1081#endif 1082 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, 1083 &rxComp); 1084 while (rcd->gen == rq->comp_ring.gen) { 1085 struct vmxnet3_rx_buf_info *rbi; 1086 struct sk_buff *skb; 1087 int num_to_alloc; 1088 struct Vmxnet3_RxDesc *rxd; 1089 u32 idx, ring_idx; 1090 1091 if (num_rxd >= quota) { 1092 /* we may stop even before we see the EOP desc of 1093 * the current pkt 1094 */ 1095 break; 1096 } 1097 num_rxd++; 1098 1099 idx = rcd->rxdIdx; 1100 ring_idx = rcd->rqID == rq->qid ? 0 : 1; 1101 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, 1102 &rxCmdDesc); 1103 rbi = rq->buf_info[ring_idx] + idx; 1104 1105 BUG_ON(rxd->addr != rbi->dma_addr || 1106 rxd->len != rbi->len); 1107 1108 if (unlikely(rcd->eop && rcd->err)) { 1109 vmxnet3_rx_error(rq, rcd, ctx, adapter); 1110 goto rcd_done; 1111 } 1112 1113 if (rcd->sop) { /* first buf of the pkt */ 1114 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD || 1115 rcd->rqID != rq->qid); 1116 1117 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB); 1118 BUG_ON(ctx->skb != NULL || rbi->skb == NULL); 1119 1120 if (unlikely(rcd->len == 0)) { 1121 /* Pretend the rx buffer is skipped. */ 1122 BUG_ON(!(rcd->sop && rcd->eop)); 1123 dev_dbg(&adapter->netdev->dev, 1124 "rxRing[%u][%u] 0 length\n", 1125 ring_idx, idx); 1126 goto rcd_done; 1127 } 1128 1129 ctx->skb = rbi->skb; 1130 rbi->skb = NULL; 1131 1132 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len, 1133 PCI_DMA_FROMDEVICE); 1134 1135 skb_put(ctx->skb, rcd->len); 1136 } else { 1137 BUG_ON(ctx->skb == NULL); 1138 /* non SOP buffer must be type 1 in most cases */ 1139 if (rbi->buf_type == VMXNET3_RX_BUF_PAGE) { 1140 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY); 1141 1142 if (rcd->len) { 1143 pci_unmap_page(adapter->pdev, 1144 rbi->dma_addr, rbi->len, 1145 PCI_DMA_FROMDEVICE); 1146 1147 vmxnet3_append_frag(ctx->skb, rcd, rbi); 1148 rbi->page = NULL; 1149 } 1150 } else { 1151 /* 1152 * The only time a non-SOP buffer is type 0 is 1153 * when it's EOP and error flag is raised, which 1154 * has already been handled. 1155 */ 1156 BUG_ON(true); 1157 } 1158 } 1159 1160 skb = ctx->skb; 1161 if (rcd->eop) { 1162 skb->len += skb->data_len; 1163 skb->truesize += skb->data_len; 1164 1165 vmxnet3_rx_csum(adapter, skb, 1166 (union Vmxnet3_GenericDesc *)rcd); 1167 skb->protocol = eth_type_trans(skb, adapter->netdev); 1168 1169 if (unlikely(adapter->vlan_grp && rcd->ts)) { 1170 vlan_hwaccel_receive_skb(skb, 1171 adapter->vlan_grp, rcd->tci); 1172 } else { 1173 netif_receive_skb(skb); 1174 } 1175 1176 ctx->skb = NULL; 1177 } 1178 1179rcd_done: 1180 /* device may skip some rx descs */ 1181 rq->rx_ring[ring_idx].next2comp = idx; 1182 VMXNET3_INC_RING_IDX_ONLY(rq->rx_ring[ring_idx].next2comp, 1183 rq->rx_ring[ring_idx].size); 1184 1185 /* refill rx buffers frequently to avoid starving the h/w */ 1186 num_to_alloc = vmxnet3_cmd_ring_desc_avail(rq->rx_ring + 1187 ring_idx); 1188 if (unlikely(num_to_alloc > VMXNET3_RX_ALLOC_THRESHOLD(rq, 1189 ring_idx, adapter))) { 1190 vmxnet3_rq_alloc_rx_buf(rq, ring_idx, num_to_alloc, 1191 adapter); 1192 1193 /* if needed, update the register */ 1194 if (unlikely(rq->shared->updateRxProd)) { 1195 VMXNET3_WRITE_BAR0_REG(adapter, 1196 rxprod_reg[ring_idx] + rq->qid * 8, 1197 rq->rx_ring[ring_idx].next2fill); 1198 rq->uncommitted[ring_idx] = 0; 1199 } 1200 } 1201 1202 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring); 1203 vmxnet3_getRxComp(rcd, 1204 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); 1205 } 1206 1207 return num_rxd; 1208} 1209 1210 1211static void 1212vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq, 1213 struct vmxnet3_adapter *adapter) 1214{ 1215 u32 i, ring_idx; 1216 struct Vmxnet3_RxDesc *rxd; 1217 1218 for (ring_idx = 0; ring_idx < 2; ring_idx++) { 1219 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) { 1220#ifdef __BIG_ENDIAN_BITFIELD 1221 struct Vmxnet3_RxDesc rxDesc; 1222#endif 1223 vmxnet3_getRxDesc(rxd, 1224 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); 1225 1226 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD && 1227 rq->buf_info[ring_idx][i].skb) { 1228 pci_unmap_single(adapter->pdev, rxd->addr, 1229 rxd->len, PCI_DMA_FROMDEVICE); 1230 dev_kfree_skb(rq->buf_info[ring_idx][i].skb); 1231 rq->buf_info[ring_idx][i].skb = NULL; 1232 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY && 1233 rq->buf_info[ring_idx][i].page) { 1234 pci_unmap_page(adapter->pdev, rxd->addr, 1235 rxd->len, PCI_DMA_FROMDEVICE); 1236 put_page(rq->buf_info[ring_idx][i].page); 1237 rq->buf_info[ring_idx][i].page = NULL; 1238 } 1239 } 1240 1241 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN; 1242 rq->rx_ring[ring_idx].next2fill = 1243 rq->rx_ring[ring_idx].next2comp = 0; 1244 rq->uncommitted[ring_idx] = 0; 1245 } 1246 1247 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1248 rq->comp_ring.next2proc = 0; 1249} 1250 1251 1252void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq, 1253 struct vmxnet3_adapter *adapter) 1254{ 1255 int i; 1256 int j; 1257 1258 /* all rx buffers must have already been freed */ 1259 for (i = 0; i < 2; i++) { 1260 if (rq->buf_info[i]) { 1261 for (j = 0; j < rq->rx_ring[i].size; j++) 1262 BUG_ON(rq->buf_info[i][j].page != NULL); 1263 } 1264 } 1265 1266 1267 kfree(rq->buf_info[0]); 1268 1269 for (i = 0; i < 2; i++) { 1270 if (rq->rx_ring[i].base) { 1271 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size 1272 * sizeof(struct Vmxnet3_RxDesc), 1273 rq->rx_ring[i].base, 1274 rq->rx_ring[i].basePA); 1275 rq->rx_ring[i].base = NULL; 1276 } 1277 rq->buf_info[i] = NULL; 1278 } 1279 1280 if (rq->comp_ring.base) { 1281 pci_free_consistent(adapter->pdev, rq->comp_ring.size * 1282 sizeof(struct Vmxnet3_RxCompDesc), 1283 rq->comp_ring.base, rq->comp_ring.basePA); 1284 rq->comp_ring.base = NULL; 1285 } 1286} 1287 1288 1289static int 1290vmxnet3_rq_init(struct vmxnet3_rx_queue *rq, 1291 struct vmxnet3_adapter *adapter) 1292{ 1293 int i; 1294 1295 /* initialize buf_info */ 1296 for (i = 0; i < rq->rx_ring[0].size; i++) { 1297 1298 /* 1st buf for a pkt is skbuff */ 1299 if (i % adapter->rx_buf_per_pkt == 0) { 1300 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB; 1301 rq->buf_info[0][i].len = adapter->skb_buf_size; 1302 } else { /* subsequent bufs for a pkt is frag */ 1303 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE; 1304 rq->buf_info[0][i].len = PAGE_SIZE; 1305 } 1306 } 1307 for (i = 0; i < rq->rx_ring[1].size; i++) { 1308 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE; 1309 rq->buf_info[1][i].len = PAGE_SIZE; 1310 } 1311 1312 /* reset internal state and allocate buffers for both rings */ 1313 for (i = 0; i < 2; i++) { 1314 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0; 1315 rq->uncommitted[i] = 0; 1316 1317 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * 1318 sizeof(struct Vmxnet3_RxDesc)); 1319 rq->rx_ring[i].gen = VMXNET3_INIT_GEN; 1320 } 1321 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1, 1322 adapter) == 0) { 1323 /* at least has 1 rx buffer for the 1st ring */ 1324 return -ENOMEM; 1325 } 1326 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter); 1327 1328 /* reset the comp ring */ 1329 rq->comp_ring.next2proc = 0; 1330 memset(rq->comp_ring.base, 0, rq->comp_ring.size * 1331 sizeof(struct Vmxnet3_RxCompDesc)); 1332 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1333 1334 /* reset rxctx */ 1335 rq->rx_ctx.skb = NULL; 1336 1337 /* stats are not reset */ 1338 return 0; 1339} 1340 1341 1342static int 1343vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter) 1344{ 1345 int i; 1346 size_t sz; 1347 struct vmxnet3_rx_buf_info *bi; 1348 1349 for (i = 0; i < 2; i++) { 1350 1351 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc); 1352 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz, 1353 &rq->rx_ring[i].basePA); 1354 if (!rq->rx_ring[i].base) { 1355 printk(KERN_ERR "%s: failed to allocate rx ring %d\n", 1356 adapter->netdev->name, i); 1357 goto err; 1358 } 1359 } 1360 1361 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc); 1362 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz, 1363 &rq->comp_ring.basePA); 1364 if (!rq->comp_ring.base) { 1365 printk(KERN_ERR "%s: failed to allocate rx comp ring\n", 1366 adapter->netdev->name); 1367 goto err; 1368 } 1369 1370 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size + 1371 rq->rx_ring[1].size); 1372 bi = kmalloc(sz, GFP_KERNEL); 1373 if (!bi) { 1374 printk(KERN_ERR "%s: failed to allocate rx bufinfo\n", 1375 adapter->netdev->name); 1376 goto err; 1377 } 1378 memset(bi, 0, sz); 1379 rq->buf_info[0] = bi; 1380 rq->buf_info[1] = bi + rq->rx_ring[0].size; 1381 1382 return 0; 1383 1384err: 1385 vmxnet3_rq_destroy(rq, adapter); 1386 return -ENOMEM; 1387} 1388 1389 1390static int 1391vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget) 1392{ 1393 if (unlikely(adapter->shared->ecr)) 1394 vmxnet3_process_events(adapter); 1395 1396 vmxnet3_tq_tx_complete(&adapter->tx_queue, adapter); 1397 return vmxnet3_rq_rx_complete(&adapter->rx_queue, adapter, budget); 1398} 1399 1400 1401static int 1402vmxnet3_poll(struct napi_struct *napi, int budget) 1403{ 1404 struct vmxnet3_adapter *adapter = container_of(napi, 1405 struct vmxnet3_adapter, napi); 1406 int rxd_done; 1407 1408 rxd_done = vmxnet3_do_poll(adapter, budget); 1409 1410 if (rxd_done < budget) { 1411 napi_complete(napi); 1412 vmxnet3_enable_intr(adapter, 0); 1413 } 1414 return rxd_done; 1415} 1416 1417 1418/* Interrupt handler for vmxnet3 */ 1419static irqreturn_t 1420vmxnet3_intr(int irq, void *dev_id) 1421{ 1422 struct net_device *dev = dev_id; 1423 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1424 1425 if (unlikely(adapter->intr.type == VMXNET3_IT_INTX)) { 1426 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR); 1427 if (unlikely(icr == 0)) 1428 /* not ours */ 1429 return IRQ_NONE; 1430 } 1431 1432 1433 /* disable intr if needed */ 1434 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1435 vmxnet3_disable_intr(adapter, 0); 1436 1437 napi_schedule(&adapter->napi); 1438 1439 return IRQ_HANDLED; 1440} 1441 1442#ifdef CONFIG_NET_POLL_CONTROLLER 1443 1444 1445/* netpoll callback. */ 1446static void 1447vmxnet3_netpoll(struct net_device *netdev) 1448{ 1449 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1450 int irq; 1451 1452#ifdef CONFIG_PCI_MSI 1453 if (adapter->intr.type == VMXNET3_IT_MSIX) 1454 irq = adapter->intr.msix_entries[0].vector; 1455 else 1456#endif 1457 irq = adapter->pdev->irq; 1458 1459 disable_irq(irq); 1460 vmxnet3_intr(irq, netdev); 1461 enable_irq(irq); 1462} 1463#endif 1464 1465static int 1466vmxnet3_request_irqs(struct vmxnet3_adapter *adapter) 1467{ 1468 int err; 1469 1470#ifdef CONFIG_PCI_MSI 1471 if (adapter->intr.type == VMXNET3_IT_MSIX) { 1472 /* we only use 1 MSI-X vector */ 1473 err = request_irq(adapter->intr.msix_entries[0].vector, 1474 vmxnet3_intr, 0, adapter->netdev->name, 1475 adapter->netdev); 1476 } else if (adapter->intr.type == VMXNET3_IT_MSI) { 1477 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0, 1478 adapter->netdev->name, adapter->netdev); 1479 } else 1480#endif 1481 { 1482 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 1483 IRQF_SHARED, adapter->netdev->name, 1484 adapter->netdev); 1485 } 1486 1487 if (err) 1488 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error" 1489 ":%d\n", adapter->netdev->name, adapter->intr.type, err); 1490 1491 1492 if (!err) { 1493 int i; 1494 /* init our intr settings */ 1495 for (i = 0; i < adapter->intr.num_intrs; i++) 1496 adapter->intr.mod_levels[i] = UPT1_IML_ADAPTIVE; 1497 1498 /* next setup intr index for all intr sources */ 1499 adapter->tx_queue.comp_ring.intr_idx = 0; 1500 adapter->rx_queue.comp_ring.intr_idx = 0; 1501 adapter->intr.event_intr_idx = 0; 1502 1503 printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors " 1504 "allocated\n", adapter->netdev->name, adapter->intr.type, 1505 adapter->intr.mask_mode, adapter->intr.num_intrs); 1506 } 1507 1508 return err; 1509} 1510 1511 1512static void 1513vmxnet3_free_irqs(struct vmxnet3_adapter *adapter) 1514{ 1515 BUG_ON(adapter->intr.type == VMXNET3_IT_AUTO || 1516 adapter->intr.num_intrs <= 0); 1517 1518 switch (adapter->intr.type) { 1519#ifdef CONFIG_PCI_MSI 1520 case VMXNET3_IT_MSIX: 1521 { 1522 int i; 1523 1524 for (i = 0; i < adapter->intr.num_intrs; i++) 1525 free_irq(adapter->intr.msix_entries[i].vector, 1526 adapter->netdev); 1527 break; 1528 } 1529#endif 1530 case VMXNET3_IT_MSI: 1531 free_irq(adapter->pdev->irq, adapter->netdev); 1532 break; 1533 case VMXNET3_IT_INTX: 1534 free_irq(adapter->pdev->irq, adapter->netdev); 1535 break; 1536 default: 1537 BUG_ON(true); 1538 } 1539} 1540 1541 1542inline void set_flag_le16(__le16 *data, u16 flag) 1543{ 1544 *data = cpu_to_le16(le16_to_cpu(*data) | flag); 1545} 1546 1547inline void set_flag_le64(__le64 *data, u64 flag) 1548{ 1549 *data = cpu_to_le64(le64_to_cpu(*data) | flag); 1550} 1551 1552inline void reset_flag_le64(__le64 *data, u64 flag) 1553{ 1554 *data = cpu_to_le64(le64_to_cpu(*data) & ~flag); 1555} 1556 1557 1558static void 1559vmxnet3_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) 1560{ 1561 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1562 struct Vmxnet3_DriverShared *shared = adapter->shared; 1563 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1564 1565 if (grp) { 1566 /* add vlan rx stripping. */ 1567 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) { 1568 int i; 1569 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 1570 adapter->vlan_grp = grp; 1571 1572 /* update FEATURES to device */ 1573 set_flag_le64(&devRead->misc.uptFeatures, 1574 UPT1_F_RXVLAN); 1575 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1576 VMXNET3_CMD_UPDATE_FEATURE); 1577 /* 1578 * Clear entire vfTable; then enable untagged pkts. 1579 * Note: setting one entry in vfTable to non-zero turns 1580 * on VLAN rx filtering. 1581 */ 1582 for (i = 0; i < VMXNET3_VFT_SIZE; i++) 1583 vfTable[i] = 0; 1584 1585 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 1586 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1587 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1588 } else { 1589 printk(KERN_ERR "%s: vlan_rx_register when device has " 1590 "no NETIF_F_HW_VLAN_RX\n", netdev->name); 1591 } 1592 } else { 1593 /* remove vlan rx stripping. */ 1594 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 1595 adapter->vlan_grp = NULL; 1596 1597 if (le64_to_cpu(devRead->misc.uptFeatures) & UPT1_F_RXVLAN) { 1598 int i; 1599 1600 for (i = 0; i < VMXNET3_VFT_SIZE; i++) { 1601 /* clear entire vfTable; this also disables 1602 * VLAN rx filtering 1603 */ 1604 vfTable[i] = 0; 1605 } 1606 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1607 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1608 1609 /* update FEATURES to device */ 1610 reset_flag_le64(&devRead->misc.uptFeatures, 1611 UPT1_F_RXVLAN); 1612 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1613 VMXNET3_CMD_UPDATE_FEATURE); 1614 } 1615 } 1616} 1617 1618 1619static void 1620vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter) 1621{ 1622 if (adapter->vlan_grp) { 1623 u16 vid; 1624 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1625 bool activeVlan = false; 1626 1627 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { 1628 if (vlan_group_get_device(adapter->vlan_grp, vid)) { 1629 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 1630 activeVlan = true; 1631 } 1632 } 1633 if (activeVlan) { 1634 /* continue to allow untagged pkts */ 1635 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 1636 } 1637 } 1638} 1639 1640 1641static void 1642vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 1643{ 1644 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1645 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1646 1647 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 1648 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1649 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1650} 1651 1652 1653static void 1654vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 1655{ 1656 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1657 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1658 1659 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid); 1660 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1661 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1662} 1663 1664 1665static u8 * 1666vmxnet3_copy_mc(struct net_device *netdev) 1667{ 1668 u8 *buf = NULL; 1669 u32 sz = netdev_mc_count(netdev) * ETH_ALEN; 1670 1671 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */ 1672 if (sz <= 0xffff) { 1673 /* We may be called with BH disabled */ 1674 buf = kmalloc(sz, GFP_ATOMIC); 1675 if (buf) { 1676 struct netdev_hw_addr *ha; 1677 int i = 0; 1678 1679 netdev_for_each_mc_addr(ha, netdev) 1680 memcpy(buf + i++ * ETH_ALEN, ha->addr, 1681 ETH_ALEN); 1682 } 1683 } 1684 return buf; 1685} 1686 1687 1688static void 1689vmxnet3_set_mc(struct net_device *netdev) 1690{ 1691 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1692 struct Vmxnet3_RxFilterConf *rxConf = 1693 &adapter->shared->devRead.rxFilterConf; 1694 u8 *new_table = NULL; 1695 u32 new_mode = VMXNET3_RXM_UCAST; 1696 1697 if (netdev->flags & IFF_PROMISC) 1698 new_mode |= VMXNET3_RXM_PROMISC; 1699 1700 if (netdev->flags & IFF_BROADCAST) 1701 new_mode |= VMXNET3_RXM_BCAST; 1702 1703 if (netdev->flags & IFF_ALLMULTI) 1704 new_mode |= VMXNET3_RXM_ALL_MULTI; 1705 else 1706 if (!netdev_mc_empty(netdev)) { 1707 new_table = vmxnet3_copy_mc(netdev); 1708 if (new_table) { 1709 new_mode |= VMXNET3_RXM_MCAST; 1710 rxConf->mfTableLen = cpu_to_le16( 1711 netdev_mc_count(netdev) * ETH_ALEN); 1712 rxConf->mfTablePA = cpu_to_le64(virt_to_phys( 1713 new_table)); 1714 } else { 1715 printk(KERN_INFO "%s: failed to copy mcast list" 1716 ", setting ALL_MULTI\n", netdev->name); 1717 new_mode |= VMXNET3_RXM_ALL_MULTI; 1718 } 1719 } 1720 1721 1722 if (!(new_mode & VMXNET3_RXM_MCAST)) { 1723 rxConf->mfTableLen = 0; 1724 rxConf->mfTablePA = 0; 1725 } 1726 1727 if (new_mode != rxConf->rxMode) { 1728 rxConf->rxMode = cpu_to_le32(new_mode); 1729 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1730 VMXNET3_CMD_UPDATE_RX_MODE); 1731 } 1732 1733 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1734 VMXNET3_CMD_UPDATE_MAC_FILTERS); 1735 1736 kfree(new_table); 1737} 1738 1739 1740/* 1741 * Set up driver_shared based on settings in adapter. 1742 */ 1743 1744static void 1745vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter) 1746{ 1747 struct Vmxnet3_DriverShared *shared = adapter->shared; 1748 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 1749 struct Vmxnet3_TxQueueConf *tqc; 1750 struct Vmxnet3_RxQueueConf *rqc; 1751 int i; 1752 1753 memset(shared, 0, sizeof(*shared)); 1754 1755 /* driver settings */ 1756 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC); 1757 devRead->misc.driverInfo.version = cpu_to_le32( 1758 VMXNET3_DRIVER_VERSION_NUM); 1759 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ? 1760 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64); 1761 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 1762 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32( 1763 *((u32 *)&devRead->misc.driverInfo.gos)); 1764 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1); 1765 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1); 1766 1767 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter)); 1768 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter)); 1769 1770 /* set up feature flags */ 1771 if (adapter->rxcsum) 1772 set_flag_le64(&devRead->misc.uptFeatures, UPT1_F_RXCSUM); 1773 1774 if (adapter->lro) { 1775 set_flag_le64(&devRead->misc.uptFeatures, UPT1_F_LRO); 1776 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS); 1777 } 1778 if ((adapter->netdev->features & NETIF_F_HW_VLAN_RX) && 1779 adapter->vlan_grp) { 1780 set_flag_le64(&devRead->misc.uptFeatures, UPT1_F_RXVLAN); 1781 } 1782 1783 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu); 1784 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa); 1785 devRead->misc.queueDescLen = cpu_to_le32( 1786 sizeof(struct Vmxnet3_TxQueueDesc) + 1787 sizeof(struct Vmxnet3_RxQueueDesc)); 1788 1789 /* tx queue settings */ 1790 BUG_ON(adapter->tx_queue.tx_ring.base == NULL); 1791 1792 devRead->misc.numTxQueues = 1; 1793 tqc = &adapter->tqd_start->conf; 1794 tqc->txRingBasePA = cpu_to_le64(adapter->tx_queue.tx_ring.basePA); 1795 tqc->dataRingBasePA = cpu_to_le64(adapter->tx_queue.data_ring.basePA); 1796 tqc->compRingBasePA = cpu_to_le64(adapter->tx_queue.comp_ring.basePA); 1797 tqc->ddPA = cpu_to_le64(virt_to_phys( 1798 adapter->tx_queue.buf_info)); 1799 tqc->txRingSize = cpu_to_le32(adapter->tx_queue.tx_ring.size); 1800 tqc->dataRingSize = cpu_to_le32(adapter->tx_queue.data_ring.size); 1801 tqc->compRingSize = cpu_to_le32(adapter->tx_queue.comp_ring.size); 1802 tqc->ddLen = cpu_to_le32(sizeof(struct vmxnet3_tx_buf_info) * 1803 tqc->txRingSize); 1804 tqc->intrIdx = adapter->tx_queue.comp_ring.intr_idx; 1805 1806 /* rx queue settings */ 1807 devRead->misc.numRxQueues = 1; 1808 rqc = &adapter->rqd_start->conf; 1809 rqc->rxRingBasePA[0] = cpu_to_le64(adapter->rx_queue.rx_ring[0].basePA); 1810 rqc->rxRingBasePA[1] = cpu_to_le64(adapter->rx_queue.rx_ring[1].basePA); 1811 rqc->compRingBasePA = cpu_to_le64(adapter->rx_queue.comp_ring.basePA); 1812 rqc->ddPA = cpu_to_le64(virt_to_phys( 1813 adapter->rx_queue.buf_info)); 1814 rqc->rxRingSize[0] = cpu_to_le32(adapter->rx_queue.rx_ring[0].size); 1815 rqc->rxRingSize[1] = cpu_to_le32(adapter->rx_queue.rx_ring[1].size); 1816 rqc->compRingSize = cpu_to_le32(adapter->rx_queue.comp_ring.size); 1817 rqc->ddLen = cpu_to_le32(sizeof(struct vmxnet3_rx_buf_info) * 1818 (rqc->rxRingSize[0] + rqc->rxRingSize[1])); 1819 rqc->intrIdx = adapter->rx_queue.comp_ring.intr_idx; 1820 1821 /* intr settings */ 1822 devRead->intrConf.autoMask = adapter->intr.mask_mode == 1823 VMXNET3_IMM_AUTO; 1824 devRead->intrConf.numIntrs = adapter->intr.num_intrs; 1825 for (i = 0; i < adapter->intr.num_intrs; i++) 1826 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; 1827 1828 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; 1829 1830 /* rx filter settings */ 1831 devRead->rxFilterConf.rxMode = 0; 1832 vmxnet3_restore_vlan(adapter); 1833 /* the rest are already zeroed */ 1834} 1835 1836 1837int 1838vmxnet3_activate_dev(struct vmxnet3_adapter *adapter) 1839{ 1840 int err; 1841 u32 ret; 1842 1843 dev_dbg(&adapter->netdev->dev, 1844 "%s: skb_buf_size %d, rx_buf_per_pkt %d, ring sizes" 1845 " %u %u %u\n", adapter->netdev->name, adapter->skb_buf_size, 1846 adapter->rx_buf_per_pkt, adapter->tx_queue.tx_ring.size, 1847 adapter->rx_queue.rx_ring[0].size, 1848 adapter->rx_queue.rx_ring[1].size); 1849 1850 vmxnet3_tq_init(&adapter->tx_queue, adapter); 1851 err = vmxnet3_rq_init(&adapter->rx_queue, adapter); 1852 if (err) { 1853 printk(KERN_ERR "Failed to init rx queue for %s: error %d\n", 1854 adapter->netdev->name, err); 1855 goto rq_err; 1856 } 1857 1858 err = vmxnet3_request_irqs(adapter); 1859 if (err) { 1860 printk(KERN_ERR "Failed to setup irq for %s: error %d\n", 1861 adapter->netdev->name, err); 1862 goto irq_err; 1863 } 1864 1865 vmxnet3_setup_driver_shared(adapter); 1866 1867 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO( 1868 adapter->shared_pa)); 1869 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI( 1870 adapter->shared_pa)); 1871 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1872 VMXNET3_CMD_ACTIVATE_DEV); 1873 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 1874 1875 if (ret != 0) { 1876 printk(KERN_ERR "Failed to activate dev %s: error %u\n", 1877 adapter->netdev->name, ret); 1878 err = -EINVAL; 1879 goto activate_err; 1880 } 1881 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_RXPROD, 1882 adapter->rx_queue.rx_ring[0].next2fill); 1883 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_RXPROD2, 1884 adapter->rx_queue.rx_ring[1].next2fill); 1885 1886 /* Apply the rx filter settins last. */ 1887 vmxnet3_set_mc(adapter->netdev); 1888 1889 /* 1890 * Check link state when first activating device. It will start the 1891 * tx queue if the link is up. 1892 */ 1893 vmxnet3_check_link(adapter); 1894 1895 napi_enable(&adapter->napi); 1896 vmxnet3_enable_all_intrs(adapter); 1897 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 1898 return 0; 1899 1900activate_err: 1901 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0); 1902 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0); 1903 vmxnet3_free_irqs(adapter); 1904irq_err: 1905rq_err: 1906 /* free up buffers we allocated */ 1907 vmxnet3_rq_cleanup(&adapter->rx_queue, adapter); 1908 return err; 1909} 1910 1911 1912void 1913vmxnet3_reset_dev(struct vmxnet3_adapter *adapter) 1914{ 1915 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 1916} 1917 1918 1919int 1920vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter) 1921{ 1922 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state)) 1923 return 0; 1924 1925 1926 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1927 VMXNET3_CMD_QUIESCE_DEV); 1928 vmxnet3_disable_all_intrs(adapter); 1929 1930 napi_disable(&adapter->napi); 1931 netif_tx_disable(adapter->netdev); 1932 adapter->link_speed = 0; 1933 netif_carrier_off(adapter->netdev); 1934 1935 vmxnet3_tq_cleanup(&adapter->tx_queue, adapter); 1936 vmxnet3_rq_cleanup(&adapter->rx_queue, adapter); 1937 vmxnet3_free_irqs(adapter); 1938 return 0; 1939} 1940 1941 1942static void 1943vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 1944{ 1945 u32 tmp; 1946 1947 tmp = *(u32 *)mac; 1948 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp); 1949 1950 tmp = (mac[5] << 8) | mac[4]; 1951 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp); 1952} 1953 1954 1955static int 1956vmxnet3_set_mac_addr(struct net_device *netdev, void *p) 1957{ 1958 struct sockaddr *addr = p; 1959 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1960 1961 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1962 vmxnet3_write_mac_addr(adapter, addr->sa_data); 1963 1964 return 0; 1965} 1966 1967 1968/* ==================== initialization and cleanup routines ============ */ 1969 1970static int 1971vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64) 1972{ 1973 int err; 1974 unsigned long mmio_start, mmio_len; 1975 struct pci_dev *pdev = adapter->pdev; 1976 1977 err = pci_enable_device(pdev); 1978 if (err) { 1979 printk(KERN_ERR "Failed to enable adapter %s: error %d\n", 1980 pci_name(pdev), err); 1981 return err; 1982 } 1983 1984 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) { 1985 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) { 1986 printk(KERN_ERR "pci_set_consistent_dma_mask failed " 1987 "for adapter %s\n", pci_name(pdev)); 1988 err = -EIO; 1989 goto err_set_mask; 1990 } 1991 *dma64 = true; 1992 } else { 1993 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) { 1994 printk(KERN_ERR "pci_set_dma_mask failed for adapter " 1995 "%s\n", pci_name(pdev)); 1996 err = -EIO; 1997 goto err_set_mask; 1998 } 1999 *dma64 = false; 2000 } 2001 2002 err = pci_request_selected_regions(pdev, (1 << 2) - 1, 2003 vmxnet3_driver_name); 2004 if (err) { 2005 printk(KERN_ERR "Failed to request region for adapter %s: " 2006 "error %d\n", pci_name(pdev), err); 2007 goto err_set_mask; 2008 } 2009 2010 pci_set_master(pdev); 2011 2012 mmio_start = pci_resource_start(pdev, 0); 2013 mmio_len = pci_resource_len(pdev, 0); 2014 adapter->hw_addr0 = ioremap(mmio_start, mmio_len); 2015 if (!adapter->hw_addr0) { 2016 printk(KERN_ERR "Failed to map bar0 for adapter %s\n", 2017 pci_name(pdev)); 2018 err = -EIO; 2019 goto err_ioremap; 2020 } 2021 2022 mmio_start = pci_resource_start(pdev, 1); 2023 mmio_len = pci_resource_len(pdev, 1); 2024 adapter->hw_addr1 = ioremap(mmio_start, mmio_len); 2025 if (!adapter->hw_addr1) { 2026 printk(KERN_ERR "Failed to map bar1 for adapter %s\n", 2027 pci_name(pdev)); 2028 err = -EIO; 2029 goto err_bar1; 2030 } 2031 return 0; 2032 2033err_bar1: 2034 iounmap(adapter->hw_addr0); 2035err_ioremap: 2036 pci_release_selected_regions(pdev, (1 << 2) - 1); 2037err_set_mask: 2038 pci_disable_device(pdev); 2039 return err; 2040} 2041 2042 2043static void 2044vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter) 2045{ 2046 BUG_ON(!adapter->pdev); 2047 2048 iounmap(adapter->hw_addr0); 2049 iounmap(adapter->hw_addr1); 2050 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1); 2051 pci_disable_device(adapter->pdev); 2052} 2053 2054 2055static void 2056vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter) 2057{ 2058 size_t sz; 2059 2060 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE - 2061 VMXNET3_MAX_ETH_HDR_SIZE) { 2062 adapter->skb_buf_size = adapter->netdev->mtu + 2063 VMXNET3_MAX_ETH_HDR_SIZE; 2064 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE) 2065 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE; 2066 2067 adapter->rx_buf_per_pkt = 1; 2068 } else { 2069 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE; 2070 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE + 2071 VMXNET3_MAX_ETH_HDR_SIZE; 2072 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE; 2073 } 2074 2075 /* 2076 * for simplicity, force the ring0 size to be a multiple of 2077 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN 2078 */ 2079 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN; 2080 adapter->rx_queue.rx_ring[0].size = (adapter->rx_queue.rx_ring[0].size + 2081 sz - 1) / sz * sz; 2082 adapter->rx_queue.rx_ring[0].size = min_t(u32, 2083 adapter->rx_queue.rx_ring[0].size, 2084 VMXNET3_RX_RING_MAX_SIZE / sz * sz); 2085} 2086 2087 2088int 2089vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size, 2090 u32 rx_ring_size, u32 rx_ring2_size) 2091{ 2092 int err; 2093 2094 adapter->tx_queue.tx_ring.size = tx_ring_size; 2095 adapter->tx_queue.data_ring.size = tx_ring_size; 2096 adapter->tx_queue.comp_ring.size = tx_ring_size; 2097 adapter->tx_queue.shared = &adapter->tqd_start->ctrl; 2098 adapter->tx_queue.stopped = true; 2099 err = vmxnet3_tq_create(&adapter->tx_queue, adapter); 2100 if (err) 2101 return err; 2102 2103 adapter->rx_queue.rx_ring[0].size = rx_ring_size; 2104 adapter->rx_queue.rx_ring[1].size = rx_ring2_size; 2105 vmxnet3_adjust_rx_ring_size(adapter); 2106 adapter->rx_queue.comp_ring.size = adapter->rx_queue.rx_ring[0].size + 2107 adapter->rx_queue.rx_ring[1].size; 2108 adapter->rx_queue.qid = 0; 2109 adapter->rx_queue.qid2 = 1; 2110 adapter->rx_queue.shared = &adapter->rqd_start->ctrl; 2111 err = vmxnet3_rq_create(&adapter->rx_queue, adapter); 2112 if (err) 2113 vmxnet3_tq_destroy(&adapter->tx_queue, adapter); 2114 2115 return err; 2116} 2117 2118static int 2119vmxnet3_open(struct net_device *netdev) 2120{ 2121 struct vmxnet3_adapter *adapter; 2122 int err; 2123 2124 adapter = netdev_priv(netdev); 2125 2126 spin_lock_init(&adapter->tx_queue.tx_lock); 2127 2128 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE, 2129 VMXNET3_DEF_RX_RING_SIZE, 2130 VMXNET3_DEF_RX_RING_SIZE); 2131 if (err) 2132 goto queue_err; 2133 2134 err = vmxnet3_activate_dev(adapter); 2135 if (err) 2136 goto activate_err; 2137 2138 return 0; 2139 2140activate_err: 2141 vmxnet3_rq_destroy(&adapter->rx_queue, adapter); 2142 vmxnet3_tq_destroy(&adapter->tx_queue, adapter); 2143queue_err: 2144 return err; 2145} 2146 2147 2148static int 2149vmxnet3_close(struct net_device *netdev) 2150{ 2151 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2152 2153 /* 2154 * Reset_work may be in the middle of resetting the device, wait for its 2155 * completion. 2156 */ 2157 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2158 msleep(1); 2159 2160 vmxnet3_quiesce_dev(adapter); 2161 2162 vmxnet3_rq_destroy(&adapter->rx_queue, adapter); 2163 vmxnet3_tq_destroy(&adapter->tx_queue, adapter); 2164 2165 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2166 2167 2168 return 0; 2169} 2170 2171 2172void 2173vmxnet3_force_close(struct vmxnet3_adapter *adapter) 2174{ 2175 /* 2176 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise 2177 * vmxnet3_close() will deadlock. 2178 */ 2179 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)); 2180 2181 /* we need to enable NAPI, otherwise dev_close will deadlock */ 2182 napi_enable(&adapter->napi); 2183 dev_close(adapter->netdev); 2184} 2185 2186 2187static int 2188vmxnet3_change_mtu(struct net_device *netdev, int new_mtu) 2189{ 2190 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2191 int err = 0; 2192 2193 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU) 2194 return -EINVAL; 2195 2196 if (new_mtu > 1500 && !adapter->jumbo_frame) 2197 return -EINVAL; 2198 2199 netdev->mtu = new_mtu; 2200 2201 /* 2202 * Reset_work may be in the middle of resetting the device, wait for its 2203 * completion. 2204 */ 2205 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2206 msleep(1); 2207 2208 if (netif_running(netdev)) { 2209 vmxnet3_quiesce_dev(adapter); 2210 vmxnet3_reset_dev(adapter); 2211 2212 /* we need to re-create the rx queue based on the new mtu */ 2213 vmxnet3_rq_destroy(&adapter->rx_queue, adapter); 2214 vmxnet3_adjust_rx_ring_size(adapter); 2215 adapter->rx_queue.comp_ring.size = 2216 adapter->rx_queue.rx_ring[0].size + 2217 adapter->rx_queue.rx_ring[1].size; 2218 err = vmxnet3_rq_create(&adapter->rx_queue, adapter); 2219 if (err) { 2220 printk(KERN_ERR "%s: failed to re-create rx queue," 2221 " error %d. Closing it.\n", netdev->name, err); 2222 goto out; 2223 } 2224 2225 err = vmxnet3_activate_dev(adapter); 2226 if (err) { 2227 printk(KERN_ERR "%s: failed to re-activate, error %d. " 2228 "Closing it\n", netdev->name, err); 2229 goto out; 2230 } 2231 } 2232 2233out: 2234 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2235 if (err) 2236 vmxnet3_force_close(adapter); 2237 2238 return err; 2239} 2240 2241 2242static void 2243vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64) 2244{ 2245 struct net_device *netdev = adapter->netdev; 2246 2247 netdev->features = NETIF_F_SG | 2248 NETIF_F_HW_CSUM | 2249 NETIF_F_HW_VLAN_TX | 2250 NETIF_F_HW_VLAN_RX | 2251 NETIF_F_HW_VLAN_FILTER | 2252 NETIF_F_TSO | 2253 NETIF_F_TSO6 | 2254 NETIF_F_LRO; 2255 2256 printk(KERN_INFO "features: sg csum vlan jf tso tsoIPv6 lro"); 2257 2258 adapter->rxcsum = true; 2259 adapter->jumbo_frame = true; 2260 adapter->lro = true; 2261 2262 if (dma64) { 2263 netdev->features |= NETIF_F_HIGHDMA; 2264 printk(" highDMA"); 2265 } 2266 2267 netdev->vlan_features = netdev->features; 2268 printk("\n"); 2269} 2270 2271 2272static void 2273vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2274{ 2275 u32 tmp; 2276 2277 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL); 2278 *(u32 *)mac = tmp; 2279 2280 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH); 2281 mac[4] = tmp & 0xff; 2282 mac[5] = (tmp >> 8) & 0xff; 2283} 2284 2285 2286static void 2287vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter) 2288{ 2289 u32 cfg; 2290 2291 /* intr settings */ 2292 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2293 VMXNET3_CMD_GET_CONF_INTR); 2294 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2295 adapter->intr.type = cfg & 0x3; 2296 adapter->intr.mask_mode = (cfg >> 2) & 0x3; 2297 2298 if (adapter->intr.type == VMXNET3_IT_AUTO) { 2299 int err; 2300 2301#ifdef CONFIG_PCI_MSI 2302 adapter->intr.msix_entries[0].entry = 0; 2303 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries, 2304 VMXNET3_LINUX_MAX_MSIX_VECT); 2305 if (!err) { 2306 adapter->intr.num_intrs = 1; 2307 adapter->intr.type = VMXNET3_IT_MSIX; 2308 return; 2309 } 2310#endif 2311 2312 err = pci_enable_msi(adapter->pdev); 2313 if (!err) { 2314 adapter->intr.num_intrs = 1; 2315 adapter->intr.type = VMXNET3_IT_MSI; 2316 return; 2317 } 2318 } 2319 2320 adapter->intr.type = VMXNET3_IT_INTX; 2321 2322 /* INT-X related setting */ 2323 adapter->intr.num_intrs = 1; 2324} 2325 2326 2327static void 2328vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter) 2329{ 2330 if (adapter->intr.type == VMXNET3_IT_MSIX) 2331 pci_disable_msix(adapter->pdev); 2332 else if (adapter->intr.type == VMXNET3_IT_MSI) 2333 pci_disable_msi(adapter->pdev); 2334 else 2335 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); 2336} 2337 2338 2339static void 2340vmxnet3_tx_timeout(struct net_device *netdev) 2341{ 2342 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2343 adapter->tx_timeout_count++; 2344 2345 printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name); 2346 schedule_work(&adapter->work); 2347} 2348 2349 2350static void 2351vmxnet3_reset_work(struct work_struct *data) 2352{ 2353 struct vmxnet3_adapter *adapter; 2354 2355 adapter = container_of(data, struct vmxnet3_adapter, work); 2356 2357 /* if another thread is resetting the device, no need to proceed */ 2358 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2359 return; 2360 2361 /* if the device is closed, we must leave it alone */ 2362 if (netif_running(adapter->netdev)) { 2363 printk(KERN_INFO "%s: resetting\n", adapter->netdev->name); 2364 vmxnet3_quiesce_dev(adapter); 2365 vmxnet3_reset_dev(adapter); 2366 vmxnet3_activate_dev(adapter); 2367 } else { 2368 printk(KERN_INFO "%s: already closed\n", adapter->netdev->name); 2369 } 2370 2371 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2372} 2373 2374 2375static int __devinit 2376vmxnet3_probe_device(struct pci_dev *pdev, 2377 const struct pci_device_id *id) 2378{ 2379 static const struct net_device_ops vmxnet3_netdev_ops = { 2380 .ndo_open = vmxnet3_open, 2381 .ndo_stop = vmxnet3_close, 2382 .ndo_start_xmit = vmxnet3_xmit_frame, 2383 .ndo_set_mac_address = vmxnet3_set_mac_addr, 2384 .ndo_change_mtu = vmxnet3_change_mtu, 2385 .ndo_get_stats = vmxnet3_get_stats, 2386 .ndo_tx_timeout = vmxnet3_tx_timeout, 2387 .ndo_set_multicast_list = vmxnet3_set_mc, 2388 .ndo_vlan_rx_register = vmxnet3_vlan_rx_register, 2389 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid, 2390 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid, 2391#ifdef CONFIG_NET_POLL_CONTROLLER 2392 .ndo_poll_controller = vmxnet3_netpoll, 2393#endif 2394 }; 2395 int err; 2396 bool dma64 = false; /* stupid gcc */ 2397 u32 ver; 2398 struct net_device *netdev; 2399 struct vmxnet3_adapter *adapter; 2400 u8 mac[ETH_ALEN]; 2401 2402 netdev = alloc_etherdev(sizeof(struct vmxnet3_adapter)); 2403 if (!netdev) { 2404 printk(KERN_ERR "Failed to alloc ethernet device for adapter " 2405 "%s\n", pci_name(pdev)); 2406 return -ENOMEM; 2407 } 2408 2409 pci_set_drvdata(pdev, netdev); 2410 adapter = netdev_priv(netdev); 2411 adapter->netdev = netdev; 2412 adapter->pdev = pdev; 2413 2414 adapter->shared = pci_alloc_consistent(adapter->pdev, 2415 sizeof(struct Vmxnet3_DriverShared), 2416 &adapter->shared_pa); 2417 if (!adapter->shared) { 2418 printk(KERN_ERR "Failed to allocate memory for %s\n", 2419 pci_name(pdev)); 2420 err = -ENOMEM; 2421 goto err_alloc_shared; 2422 } 2423 2424 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, 2425 sizeof(struct Vmxnet3_TxQueueDesc) + 2426 sizeof(struct Vmxnet3_RxQueueDesc), 2427 &adapter->queue_desc_pa); 2428 2429 if (!adapter->tqd_start) { 2430 printk(KERN_ERR "Failed to allocate memory for %s\n", 2431 pci_name(pdev)); 2432 err = -ENOMEM; 2433 goto err_alloc_queue_desc; 2434 } 2435 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start 2436 + 1); 2437 2438 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL); 2439 if (adapter->pm_conf == NULL) { 2440 printk(KERN_ERR "Failed to allocate memory for %s\n", 2441 pci_name(pdev)); 2442 err = -ENOMEM; 2443 goto err_alloc_pm; 2444 } 2445 2446 err = vmxnet3_alloc_pci_resources(adapter, &dma64); 2447 if (err < 0) 2448 goto err_alloc_pci; 2449 2450 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS); 2451 if (ver & 1) { 2452 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1); 2453 } else { 2454 printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter" 2455 " %s\n", ver, pci_name(pdev)); 2456 err = -EBUSY; 2457 goto err_ver; 2458 } 2459 2460 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS); 2461 if (ver & 1) { 2462 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1); 2463 } else { 2464 printk(KERN_ERR "Incompatible upt version (0x%x) for " 2465 "adapter %s\n", ver, pci_name(pdev)); 2466 err = -EBUSY; 2467 goto err_ver; 2468 } 2469 2470 vmxnet3_declare_features(adapter, dma64); 2471 2472 adapter->dev_number = atomic_read(&devices_found); 2473 vmxnet3_alloc_intr_resources(adapter); 2474 2475 vmxnet3_read_mac_addr(adapter, mac); 2476 memcpy(netdev->dev_addr, mac, netdev->addr_len); 2477 2478 netdev->netdev_ops = &vmxnet3_netdev_ops; 2479 netdev->watchdog_timeo = 5 * HZ; 2480 vmxnet3_set_ethtool_ops(netdev); 2481 2482 INIT_WORK(&adapter->work, vmxnet3_reset_work); 2483 2484 netif_napi_add(netdev, &adapter->napi, vmxnet3_poll, 64); 2485 SET_NETDEV_DEV(netdev, &pdev->dev); 2486 err = register_netdev(netdev); 2487 2488 if (err) { 2489 printk(KERN_ERR "Failed to register adapter %s\n", 2490 pci_name(pdev)); 2491 goto err_register; 2492 } 2493 2494 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2495 atomic_inc(&devices_found); 2496 return 0; 2497 2498err_register: 2499 vmxnet3_free_intr_resources(adapter); 2500err_ver: 2501 vmxnet3_free_pci_resources(adapter); 2502err_alloc_pci: 2503 kfree(adapter->pm_conf); 2504err_alloc_pm: 2505 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_TxQueueDesc) + 2506 sizeof(struct Vmxnet3_RxQueueDesc), 2507 adapter->tqd_start, adapter->queue_desc_pa); 2508err_alloc_queue_desc: 2509 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared), 2510 adapter->shared, adapter->shared_pa); 2511err_alloc_shared: 2512 pci_set_drvdata(pdev, NULL); 2513 free_netdev(netdev); 2514 return err; 2515} 2516 2517 2518static void __devexit 2519vmxnet3_remove_device(struct pci_dev *pdev) 2520{ 2521 struct net_device *netdev = pci_get_drvdata(pdev); 2522 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2523 2524 flush_scheduled_work(); 2525 2526 unregister_netdev(netdev); 2527 2528 vmxnet3_free_intr_resources(adapter); 2529 vmxnet3_free_pci_resources(adapter); 2530 kfree(adapter->pm_conf); 2531 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_TxQueueDesc) + 2532 sizeof(struct Vmxnet3_RxQueueDesc), 2533 adapter->tqd_start, adapter->queue_desc_pa); 2534 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared), 2535 adapter->shared, adapter->shared_pa); 2536 free_netdev(netdev); 2537} 2538 2539 2540#ifdef CONFIG_PM 2541 2542static int 2543vmxnet3_suspend(struct device *device) 2544{ 2545 struct pci_dev *pdev = to_pci_dev(device); 2546 struct net_device *netdev = pci_get_drvdata(pdev); 2547 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2548 struct Vmxnet3_PMConf *pmConf; 2549 struct ethhdr *ehdr; 2550 struct arphdr *ahdr; 2551 u8 *arpreq; 2552 struct in_device *in_dev; 2553 struct in_ifaddr *ifa; 2554 int i = 0; 2555 2556 if (!netif_running(netdev)) 2557 return 0; 2558 2559 vmxnet3_disable_all_intrs(adapter); 2560 vmxnet3_free_irqs(adapter); 2561 vmxnet3_free_intr_resources(adapter); 2562 2563 netif_device_detach(netdev); 2564 netif_stop_queue(netdev); 2565 2566 /* Create wake-up filters. */ 2567 pmConf = adapter->pm_conf; 2568 memset(pmConf, 0, sizeof(*pmConf)); 2569 2570 if (adapter->wol & WAKE_UCAST) { 2571 pmConf->filters[i].patternSize = ETH_ALEN; 2572 pmConf->filters[i].maskSize = 1; 2573 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN); 2574 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ 2575 2576 set_flag_le16(&pmConf->wakeUpEvents, VMXNET3_PM_WAKEUP_FILTER); 2577 i++; 2578 } 2579 2580 if (adapter->wol & WAKE_ARP) { 2581 in_dev = in_dev_get(netdev); 2582 if (!in_dev) 2583 goto skip_arp; 2584 2585 ifa = (struct in_ifaddr *)in_dev->ifa_list; 2586 if (!ifa) 2587 goto skip_arp; 2588 2589 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/ 2590 sizeof(struct arphdr) + /* ARP header */ 2591 2 * ETH_ALEN + /* 2 Ethernet addresses*/ 2592 2 * sizeof(u32); /*2 IPv4 addresses */ 2593 pmConf->filters[i].maskSize = 2594 (pmConf->filters[i].patternSize - 1) / 8 + 1; 2595 2596 /* ETH_P_ARP in Ethernet header. */ 2597 ehdr = (struct ethhdr *)pmConf->filters[i].pattern; 2598 ehdr->h_proto = htons(ETH_P_ARP); 2599 2600 /* ARPOP_REQUEST in ARP header. */ 2601 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN]; 2602 ahdr->ar_op = htons(ARPOP_REQUEST); 2603 arpreq = (u8 *)(ahdr + 1); 2604 2605 /* The Unicast IPv4 address in 'tip' field. */ 2606 arpreq += 2 * ETH_ALEN + sizeof(u32); 2607 *(u32 *)arpreq = ifa->ifa_address; 2608 2609 /* The mask for the relevant bits. */ 2610 pmConf->filters[i].mask[0] = 0x00; 2611 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ 2612 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ 2613 pmConf->filters[i].mask[3] = 0x00; 2614 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ 2615 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ 2616 in_dev_put(in_dev); 2617 2618 set_flag_le16(&pmConf->wakeUpEvents, VMXNET3_PM_WAKEUP_FILTER); 2619 i++; 2620 } 2621 2622skip_arp: 2623 if (adapter->wol & WAKE_MAGIC) 2624 set_flag_le16(&pmConf->wakeUpEvents, VMXNET3_PM_WAKEUP_MAGIC); 2625 2626 pmConf->numFilters = i; 2627 2628 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 2629 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 2630 *pmConf)); 2631 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys( 2632 pmConf)); 2633 2634 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2635 VMXNET3_CMD_UPDATE_PMCFG); 2636 2637 pci_save_state(pdev); 2638 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND), 2639 adapter->wol); 2640 pci_disable_device(pdev); 2641 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND)); 2642 2643 return 0; 2644} 2645 2646 2647static int 2648vmxnet3_resume(struct device *device) 2649{ 2650 int err; 2651 struct pci_dev *pdev = to_pci_dev(device); 2652 struct net_device *netdev = pci_get_drvdata(pdev); 2653 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2654 struct Vmxnet3_PMConf *pmConf; 2655 2656 if (!netif_running(netdev)) 2657 return 0; 2658 2659 /* Destroy wake-up filters. */ 2660 pmConf = adapter->pm_conf; 2661 memset(pmConf, 0, sizeof(*pmConf)); 2662 2663 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 2664 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 2665 *pmConf)); 2666 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le32(virt_to_phys( 2667 pmConf)); 2668 2669 netif_device_attach(netdev); 2670 pci_set_power_state(pdev, PCI_D0); 2671 pci_restore_state(pdev); 2672 err = pci_enable_device_mem(pdev); 2673 if (err != 0) 2674 return err; 2675 2676 pci_enable_wake(pdev, PCI_D0, 0); 2677 2678 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2679 VMXNET3_CMD_UPDATE_PMCFG); 2680 vmxnet3_alloc_intr_resources(adapter); 2681 vmxnet3_request_irqs(adapter); 2682 vmxnet3_enable_all_intrs(adapter); 2683 2684 return 0; 2685} 2686 2687static const struct dev_pm_ops vmxnet3_pm_ops = { 2688 .suspend = vmxnet3_suspend, 2689 .resume = vmxnet3_resume, 2690}; 2691#endif 2692 2693static struct pci_driver vmxnet3_driver = { 2694 .name = vmxnet3_driver_name, 2695 .id_table = vmxnet3_pciid_table, 2696 .probe = vmxnet3_probe_device, 2697 .remove = __devexit_p(vmxnet3_remove_device), 2698#ifdef CONFIG_PM 2699 .driver.pm = &vmxnet3_pm_ops, 2700#endif 2701}; 2702 2703 2704static int __init 2705vmxnet3_init_module(void) 2706{ 2707 printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC, 2708 VMXNET3_DRIVER_VERSION_REPORT); 2709 return pci_register_driver(&vmxnet3_driver); 2710} 2711 2712module_init(vmxnet3_init_module); 2713 2714 2715static void 2716vmxnet3_exit_module(void) 2717{ 2718 pci_unregister_driver(&vmxnet3_driver); 2719} 2720 2721module_exit(vmxnet3_exit_module); 2722 2723MODULE_AUTHOR("VMware, Inc."); 2724MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC); 2725MODULE_LICENSE("GPL v2"); 2726MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING); 2727