vmxnet3_drv.c revision c068e7774f6382a15e7a5ee7cd31ea662d2a5f97
1/* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com> 24 * 25 */ 26 27#include <linux/module.h> 28#include <net/ip6_checksum.h> 29 30#include "vmxnet3_int.h" 31 32char vmxnet3_driver_name[] = "vmxnet3"; 33#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver" 34 35/* 36 * PCI Device ID Table 37 * Last entry must be all 0s 38 */ 39static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = { 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)}, 41 {0} 42}; 43 44MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table); 45 46static atomic_t devices_found; 47 48#define VMXNET3_MAX_DEVICES 10 49static int enable_mq = 1; 50static int irq_share_mode; 51 52static void 53vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac); 54 55/* 56 * Enable/Disable the given intr 57 */ 58static void 59vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 60{ 61 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0); 62} 63 64 65static void 66vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 67{ 68 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1); 69} 70 71 72/* 73 * Enable/Disable all intrs used by the device 74 */ 75static void 76vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter) 77{ 78 int i; 79 80 for (i = 0; i < adapter->intr.num_intrs; i++) 81 vmxnet3_enable_intr(adapter, i); 82 adapter->shared->devRead.intrConf.intrCtrl &= 83 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL); 84} 85 86 87static void 88vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter) 89{ 90 int i; 91 92 adapter->shared->devRead.intrConf.intrCtrl |= 93 cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 94 for (i = 0; i < adapter->intr.num_intrs; i++) 95 vmxnet3_disable_intr(adapter, i); 96} 97 98 99static void 100vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events) 101{ 102 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events); 103} 104 105 106static bool 107vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 108{ 109 return tq->stopped; 110} 111 112 113static void 114vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 115{ 116 tq->stopped = false; 117 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue); 118} 119 120 121static void 122vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 123{ 124 tq->stopped = false; 125 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 126} 127 128 129static void 130vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 131{ 132 tq->stopped = true; 133 tq->num_stop++; 134 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 135} 136 137 138/* 139 * Check the link state. This may start or stop the tx queue. 140 */ 141static void 142vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue) 143{ 144 u32 ret; 145 int i; 146 unsigned long flags; 147 148 spin_lock_irqsave(&adapter->cmd_lock, flags); 149 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 150 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 151 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 152 153 adapter->link_speed = ret >> 16; 154 if (ret & 1) { /* Link is up. */ 155 printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n", 156 adapter->netdev->name, adapter->link_speed); 157 if (!netif_carrier_ok(adapter->netdev)) 158 netif_carrier_on(adapter->netdev); 159 160 if (affectTxQueue) { 161 for (i = 0; i < adapter->num_tx_queues; i++) 162 vmxnet3_tq_start(&adapter->tx_queue[i], 163 adapter); 164 } 165 } else { 166 printk(KERN_INFO "%s: NIC Link is Down\n", 167 adapter->netdev->name); 168 if (netif_carrier_ok(adapter->netdev)) 169 netif_carrier_off(adapter->netdev); 170 171 if (affectTxQueue) { 172 for (i = 0; i < adapter->num_tx_queues; i++) 173 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter); 174 } 175 } 176} 177 178static void 179vmxnet3_process_events(struct vmxnet3_adapter *adapter) 180{ 181 int i; 182 unsigned long flags; 183 u32 events = le32_to_cpu(adapter->shared->ecr); 184 if (!events) 185 return; 186 187 vmxnet3_ack_events(adapter, events); 188 189 /* Check if link state has changed */ 190 if (events & VMXNET3_ECR_LINK) 191 vmxnet3_check_link(adapter, true); 192 193 /* Check if there is an error on xmit/recv queues */ 194 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 195 spin_lock_irqsave(&adapter->cmd_lock, flags); 196 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 197 VMXNET3_CMD_GET_QUEUE_STATUS); 198 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 199 200 for (i = 0; i < adapter->num_tx_queues; i++) 201 if (adapter->tqd_start[i].status.stopped) 202 dev_err(&adapter->netdev->dev, 203 "%s: tq[%d] error 0x%x\n", 204 adapter->netdev->name, i, le32_to_cpu( 205 adapter->tqd_start[i].status.error)); 206 for (i = 0; i < adapter->num_rx_queues; i++) 207 if (adapter->rqd_start[i].status.stopped) 208 dev_err(&adapter->netdev->dev, 209 "%s: rq[%d] error 0x%x\n", 210 adapter->netdev->name, i, 211 adapter->rqd_start[i].status.error); 212 213 schedule_work(&adapter->work); 214 } 215} 216 217#ifdef __BIG_ENDIAN_BITFIELD 218/* 219 * The device expects the bitfields in shared structures to be written in 220 * little endian. When CPU is big endian, the following routines are used to 221 * correctly read and write into ABI. 222 * The general technique used here is : double word bitfields are defined in 223 * opposite order for big endian architecture. Then before reading them in 224 * driver the complete double word is translated using le32_to_cpu. Similarly 225 * After the driver writes into bitfields, cpu_to_le32 is used to translate the 226 * double words into required format. 227 * In order to avoid touching bits in shared structure more than once, temporary 228 * descriptors are used. These are passed as srcDesc to following functions. 229 */ 230static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc, 231 struct Vmxnet3_RxDesc *dstDesc) 232{ 233 u32 *src = (u32 *)srcDesc + 2; 234 u32 *dst = (u32 *)dstDesc + 2; 235 dstDesc->addr = le64_to_cpu(srcDesc->addr); 236 *dst = le32_to_cpu(*src); 237 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1); 238} 239 240static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc, 241 struct Vmxnet3_TxDesc *dstDesc) 242{ 243 int i; 244 u32 *src = (u32 *)(srcDesc + 1); 245 u32 *dst = (u32 *)(dstDesc + 1); 246 247 /* Working backwards so that the gen bit is set at the end. */ 248 for (i = 2; i > 0; i--) { 249 src--; 250 dst--; 251 *dst = cpu_to_le32(*src); 252 } 253} 254 255 256static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc, 257 struct Vmxnet3_RxCompDesc *dstDesc) 258{ 259 int i = 0; 260 u32 *src = (u32 *)srcDesc; 261 u32 *dst = (u32 *)dstDesc; 262 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) { 263 *dst = le32_to_cpu(*src); 264 src++; 265 dst++; 266 } 267} 268 269 270/* Used to read bitfield values from double words. */ 271static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size) 272{ 273 u32 temp = le32_to_cpu(*bitfield); 274 u32 mask = ((1 << size) - 1) << pos; 275 temp &= mask; 276 temp >>= pos; 277 return temp; 278} 279 280 281 282#endif /* __BIG_ENDIAN_BITFIELD */ 283 284#ifdef __BIG_ENDIAN_BITFIELD 285 286# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \ 287 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \ 288 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE) 289# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \ 290 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \ 291 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE) 292# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \ 293 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \ 294 VMXNET3_TCD_GEN_SIZE) 295# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \ 296 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE) 297# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \ 298 (dstrcd) = (tmp); \ 299 vmxnet3_RxCompToCPU((rcd), (tmp)); \ 300 } while (0) 301# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \ 302 (dstrxd) = (tmp); \ 303 vmxnet3_RxDescToCPU((rxd), (tmp)); \ 304 } while (0) 305 306#else 307 308# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen) 309# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop) 310# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen) 311# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx) 312# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd) 313# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd) 314 315#endif /* __BIG_ENDIAN_BITFIELD */ 316 317 318static void 319vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi, 320 struct pci_dev *pdev) 321{ 322 if (tbi->map_type == VMXNET3_MAP_SINGLE) 323 pci_unmap_single(pdev, tbi->dma_addr, tbi->len, 324 PCI_DMA_TODEVICE); 325 else if (tbi->map_type == VMXNET3_MAP_PAGE) 326 pci_unmap_page(pdev, tbi->dma_addr, tbi->len, 327 PCI_DMA_TODEVICE); 328 else 329 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE); 330 331 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */ 332} 333 334 335static int 336vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq, 337 struct pci_dev *pdev, struct vmxnet3_adapter *adapter) 338{ 339 struct sk_buff *skb; 340 int entries = 0; 341 342 /* no out of order completion */ 343 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp); 344 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); 345 346 skb = tq->buf_info[eop_idx].skb; 347 BUG_ON(skb == NULL); 348 tq->buf_info[eop_idx].skb = NULL; 349 350 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size); 351 352 while (tq->tx_ring.next2comp != eop_idx) { 353 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp, 354 pdev); 355 356 /* update next2comp w/o tx_lock. Since we are marking more, 357 * instead of less, tx ring entries avail, the worst case is 358 * that the tx routine incorrectly re-queues a pkt due to 359 * insufficient tx ring entries. 360 */ 361 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 362 entries++; 363 } 364 365 dev_kfree_skb_any(skb); 366 return entries; 367} 368 369 370static int 371vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq, 372 struct vmxnet3_adapter *adapter) 373{ 374 int completed = 0; 375 union Vmxnet3_GenericDesc *gdesc; 376 377 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 378 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) { 379 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX( 380 &gdesc->tcd), tq, adapter->pdev, 381 adapter); 382 383 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring); 384 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 385 } 386 387 if (completed) { 388 spin_lock(&tq->tx_lock); 389 if (unlikely(vmxnet3_tq_stopped(tq, adapter) && 390 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) > 391 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) && 392 netif_carrier_ok(adapter->netdev))) { 393 vmxnet3_tq_wake(tq, adapter); 394 } 395 spin_unlock(&tq->tx_lock); 396 } 397 return completed; 398} 399 400 401static void 402vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq, 403 struct vmxnet3_adapter *adapter) 404{ 405 int i; 406 407 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) { 408 struct vmxnet3_tx_buf_info *tbi; 409 410 tbi = tq->buf_info + tq->tx_ring.next2comp; 411 412 vmxnet3_unmap_tx_buf(tbi, adapter->pdev); 413 if (tbi->skb) { 414 dev_kfree_skb_any(tbi->skb); 415 tbi->skb = NULL; 416 } 417 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 418 } 419 420 /* sanity check, verify all buffers are indeed unmapped and freed */ 421 for (i = 0; i < tq->tx_ring.size; i++) { 422 BUG_ON(tq->buf_info[i].skb != NULL || 423 tq->buf_info[i].map_type != VMXNET3_MAP_NONE); 424 } 425 426 tq->tx_ring.gen = VMXNET3_INIT_GEN; 427 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 428 429 tq->comp_ring.gen = VMXNET3_INIT_GEN; 430 tq->comp_ring.next2proc = 0; 431} 432 433 434static void 435vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq, 436 struct vmxnet3_adapter *adapter) 437{ 438 if (tq->tx_ring.base) { 439 pci_free_consistent(adapter->pdev, tq->tx_ring.size * 440 sizeof(struct Vmxnet3_TxDesc), 441 tq->tx_ring.base, tq->tx_ring.basePA); 442 tq->tx_ring.base = NULL; 443 } 444 if (tq->data_ring.base) { 445 pci_free_consistent(adapter->pdev, tq->data_ring.size * 446 sizeof(struct Vmxnet3_TxDataDesc), 447 tq->data_ring.base, tq->data_ring.basePA); 448 tq->data_ring.base = NULL; 449 } 450 if (tq->comp_ring.base) { 451 pci_free_consistent(adapter->pdev, tq->comp_ring.size * 452 sizeof(struct Vmxnet3_TxCompDesc), 453 tq->comp_ring.base, tq->comp_ring.basePA); 454 tq->comp_ring.base = NULL; 455 } 456 kfree(tq->buf_info); 457 tq->buf_info = NULL; 458} 459 460 461/* Destroy all tx queues */ 462void 463vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter) 464{ 465 int i; 466 467 for (i = 0; i < adapter->num_tx_queues; i++) 468 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter); 469} 470 471 472static void 473vmxnet3_tq_init(struct vmxnet3_tx_queue *tq, 474 struct vmxnet3_adapter *adapter) 475{ 476 int i; 477 478 /* reset the tx ring contents to 0 and reset the tx ring states */ 479 memset(tq->tx_ring.base, 0, tq->tx_ring.size * 480 sizeof(struct Vmxnet3_TxDesc)); 481 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 482 tq->tx_ring.gen = VMXNET3_INIT_GEN; 483 484 memset(tq->data_ring.base, 0, tq->data_ring.size * 485 sizeof(struct Vmxnet3_TxDataDesc)); 486 487 /* reset the tx comp ring contents to 0 and reset comp ring states */ 488 memset(tq->comp_ring.base, 0, tq->comp_ring.size * 489 sizeof(struct Vmxnet3_TxCompDesc)); 490 tq->comp_ring.next2proc = 0; 491 tq->comp_ring.gen = VMXNET3_INIT_GEN; 492 493 /* reset the bookkeeping data */ 494 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size); 495 for (i = 0; i < tq->tx_ring.size; i++) 496 tq->buf_info[i].map_type = VMXNET3_MAP_NONE; 497 498 /* stats are not reset */ 499} 500 501 502static int 503vmxnet3_tq_create(struct vmxnet3_tx_queue *tq, 504 struct vmxnet3_adapter *adapter) 505{ 506 BUG_ON(tq->tx_ring.base || tq->data_ring.base || 507 tq->comp_ring.base || tq->buf_info); 508 509 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size 510 * sizeof(struct Vmxnet3_TxDesc), 511 &tq->tx_ring.basePA); 512 if (!tq->tx_ring.base) { 513 printk(KERN_ERR "%s: failed to allocate tx ring\n", 514 adapter->netdev->name); 515 goto err; 516 } 517 518 tq->data_ring.base = pci_alloc_consistent(adapter->pdev, 519 tq->data_ring.size * 520 sizeof(struct Vmxnet3_TxDataDesc), 521 &tq->data_ring.basePA); 522 if (!tq->data_ring.base) { 523 printk(KERN_ERR "%s: failed to allocate data ring\n", 524 adapter->netdev->name); 525 goto err; 526 } 527 528 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev, 529 tq->comp_ring.size * 530 sizeof(struct Vmxnet3_TxCompDesc), 531 &tq->comp_ring.basePA); 532 if (!tq->comp_ring.base) { 533 printk(KERN_ERR "%s: failed to allocate tx comp ring\n", 534 adapter->netdev->name); 535 goto err; 536 } 537 538 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]), 539 GFP_KERNEL); 540 if (!tq->buf_info) 541 goto err; 542 543 return 0; 544 545err: 546 vmxnet3_tq_destroy(tq, adapter); 547 return -ENOMEM; 548} 549 550static void 551vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter) 552{ 553 int i; 554 555 for (i = 0; i < adapter->num_tx_queues; i++) 556 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter); 557} 558 559/* 560 * starting from ring->next2fill, allocate rx buffers for the given ring 561 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers 562 * are allocated or allocation fails 563 */ 564 565static int 566vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx, 567 int num_to_alloc, struct vmxnet3_adapter *adapter) 568{ 569 int num_allocated = 0; 570 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx]; 571 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx]; 572 u32 val; 573 574 while (num_allocated <= num_to_alloc) { 575 struct vmxnet3_rx_buf_info *rbi; 576 union Vmxnet3_GenericDesc *gd; 577 578 rbi = rbi_base + ring->next2fill; 579 gd = ring->base + ring->next2fill; 580 581 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) { 582 if (rbi->skb == NULL) { 583 rbi->skb = dev_alloc_skb(rbi->len + 584 NET_IP_ALIGN); 585 if (unlikely(rbi->skb == NULL)) { 586 rq->stats.rx_buf_alloc_failure++; 587 break; 588 } 589 rbi->skb->dev = adapter->netdev; 590 591 skb_reserve(rbi->skb, NET_IP_ALIGN); 592 rbi->dma_addr = pci_map_single(adapter->pdev, 593 rbi->skb->data, rbi->len, 594 PCI_DMA_FROMDEVICE); 595 } else { 596 /* rx buffer skipped by the device */ 597 } 598 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; 599 } else { 600 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE || 601 rbi->len != PAGE_SIZE); 602 603 if (rbi->page == NULL) { 604 rbi->page = alloc_page(GFP_ATOMIC); 605 if (unlikely(rbi->page == NULL)) { 606 rq->stats.rx_buf_alloc_failure++; 607 break; 608 } 609 rbi->dma_addr = pci_map_page(adapter->pdev, 610 rbi->page, 0, PAGE_SIZE, 611 PCI_DMA_FROMDEVICE); 612 } else { 613 /* rx buffers skipped by the device */ 614 } 615 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; 616 } 617 618 BUG_ON(rbi->dma_addr == 0); 619 gd->rxd.addr = cpu_to_le64(rbi->dma_addr); 620 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT) 621 | val | rbi->len); 622 623 /* Fill the last buffer but dont mark it ready, or else the 624 * device will think that the queue is full */ 625 if (num_allocated == num_to_alloc) 626 break; 627 628 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT); 629 num_allocated++; 630 vmxnet3_cmd_ring_adv_next2fill(ring); 631 } 632 rq->uncommitted[ring_idx] += num_allocated; 633 634 dev_dbg(&adapter->netdev->dev, 635 "alloc_rx_buf: %d allocated, next2fill %u, next2comp " 636 "%u, uncommitted %u\n", num_allocated, ring->next2fill, 637 ring->next2comp, rq->uncommitted[ring_idx]); 638 639 /* so that the device can distinguish a full ring and an empty ring */ 640 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp); 641 642 return num_allocated; 643} 644 645 646static void 647vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd, 648 struct vmxnet3_rx_buf_info *rbi) 649{ 650 struct skb_frag_struct *frag = skb_shinfo(skb)->frags + 651 skb_shinfo(skb)->nr_frags; 652 653 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS); 654 655 __skb_frag_set_page(frag, rbi->page); 656 frag->page_offset = 0; 657 skb_frag_size_set(frag, rcd->len); 658 skb->data_len += rcd->len; 659 skb->truesize += PAGE_SIZE; 660 skb_shinfo(skb)->nr_frags++; 661} 662 663 664static void 665vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, 666 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev, 667 struct vmxnet3_adapter *adapter) 668{ 669 u32 dw2, len; 670 unsigned long buf_offset; 671 int i; 672 union Vmxnet3_GenericDesc *gdesc; 673 struct vmxnet3_tx_buf_info *tbi = NULL; 674 675 BUG_ON(ctx->copy_size > skb_headlen(skb)); 676 677 /* use the previous gen bit for the SOP desc */ 678 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT; 679 680 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; 681 gdesc = ctx->sop_txd; /* both loops below can be skipped */ 682 683 /* no need to map the buffer if headers are copied */ 684 if (ctx->copy_size) { 685 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA + 686 tq->tx_ring.next2fill * 687 sizeof(struct Vmxnet3_TxDataDesc)); 688 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size); 689 ctx->sop_txd->dword[3] = 0; 690 691 tbi = tq->buf_info + tq->tx_ring.next2fill; 692 tbi->map_type = VMXNET3_MAP_NONE; 693 694 dev_dbg(&adapter->netdev->dev, 695 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 696 tq->tx_ring.next2fill, 697 le64_to_cpu(ctx->sop_txd->txd.addr), 698 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]); 699 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 700 701 /* use the right gen for non-SOP desc */ 702 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 703 } 704 705 /* linear part can use multiple tx desc if it's big */ 706 len = skb_headlen(skb) - ctx->copy_size; 707 buf_offset = ctx->copy_size; 708 while (len) { 709 u32 buf_size; 710 711 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 712 buf_size = len; 713 dw2 |= len; 714 } else { 715 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 716 /* spec says that for TxDesc.len, 0 == 2^14 */ 717 } 718 719 tbi = tq->buf_info + tq->tx_ring.next2fill; 720 tbi->map_type = VMXNET3_MAP_SINGLE; 721 tbi->dma_addr = pci_map_single(adapter->pdev, 722 skb->data + buf_offset, buf_size, 723 PCI_DMA_TODEVICE); 724 725 tbi->len = buf_size; 726 727 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 728 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 729 730 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 731 gdesc->dword[2] = cpu_to_le32(dw2); 732 gdesc->dword[3] = 0; 733 734 dev_dbg(&adapter->netdev->dev, 735 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 736 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 737 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 738 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 739 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 740 741 len -= buf_size; 742 buf_offset += buf_size; 743 } 744 745 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 746 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 747 748 tbi = tq->buf_info + tq->tx_ring.next2fill; 749 tbi->map_type = VMXNET3_MAP_PAGE; 750 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag, 751 0, skb_frag_size(frag), 752 DMA_TO_DEVICE); 753 754 tbi->len = skb_frag_size(frag); 755 756 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 757 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 758 759 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 760 gdesc->dword[2] = cpu_to_le32(dw2 | skb_frag_size(frag)); 761 gdesc->dword[3] = 0; 762 763 dev_dbg(&adapter->netdev->dev, 764 "txd[%u]: 0x%llu %u %u\n", 765 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 766 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 767 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 768 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 769 } 770 771 ctx->eop_txd = gdesc; 772 773 /* set the last buf_info for the pkt */ 774 tbi->skb = skb; 775 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; 776} 777 778 779/* Init all tx queues */ 780static void 781vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter) 782{ 783 int i; 784 785 for (i = 0; i < adapter->num_tx_queues; i++) 786 vmxnet3_tq_init(&adapter->tx_queue[i], adapter); 787} 788 789 790/* 791 * parse and copy relevant protocol headers: 792 * For a tso pkt, relevant headers are L2/3/4 including options 793 * For a pkt requesting csum offloading, they are L2/3 and may include L4 794 * if it's a TCP/UDP pkt 795 * 796 * Returns: 797 * -1: error happens during parsing 798 * 0: protocol headers parsed, but too big to be copied 799 * 1: protocol headers parsed and copied 800 * 801 * Other effects: 802 * 1. related *ctx fields are updated. 803 * 2. ctx->copy_size is # of bytes copied 804 * 3. the portion copied is guaranteed to be in the linear part 805 * 806 */ 807static int 808vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 809 struct vmxnet3_tx_ctx *ctx, 810 struct vmxnet3_adapter *adapter) 811{ 812 struct Vmxnet3_TxDataDesc *tdd; 813 814 if (ctx->mss) { /* TSO */ 815 ctx->eth_ip_hdr_size = skb_transport_offset(skb); 816 ctx->l4_hdr_size = tcp_hdrlen(skb); 817 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size; 818 } else { 819 if (skb->ip_summed == CHECKSUM_PARTIAL) { 820 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb); 821 822 if (ctx->ipv4) { 823 const struct iphdr *iph = ip_hdr(skb); 824 825 if (iph->protocol == IPPROTO_TCP) 826 ctx->l4_hdr_size = tcp_hdrlen(skb); 827 else if (iph->protocol == IPPROTO_UDP) 828 ctx->l4_hdr_size = sizeof(struct udphdr); 829 else 830 ctx->l4_hdr_size = 0; 831 } else { 832 /* for simplicity, don't copy L4 headers */ 833 ctx->l4_hdr_size = 0; 834 } 835 ctx->copy_size = min(ctx->eth_ip_hdr_size + 836 ctx->l4_hdr_size, skb->len); 837 } else { 838 ctx->eth_ip_hdr_size = 0; 839 ctx->l4_hdr_size = 0; 840 /* copy as much as allowed */ 841 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE 842 , skb_headlen(skb)); 843 } 844 845 /* make sure headers are accessible directly */ 846 if (unlikely(!pskb_may_pull(skb, ctx->copy_size))) 847 goto err; 848 } 849 850 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) { 851 tq->stats.oversized_hdr++; 852 ctx->copy_size = 0; 853 return 0; 854 } 855 856 tdd = tq->data_ring.base + tq->tx_ring.next2fill; 857 858 memcpy(tdd->data, skb->data, ctx->copy_size); 859 dev_dbg(&adapter->netdev->dev, 860 "copy %u bytes to dataRing[%u]\n", 861 ctx->copy_size, tq->tx_ring.next2fill); 862 return 1; 863 864err: 865 return -1; 866} 867 868 869static void 870vmxnet3_prepare_tso(struct sk_buff *skb, 871 struct vmxnet3_tx_ctx *ctx) 872{ 873 struct tcphdr *tcph = tcp_hdr(skb); 874 875 if (ctx->ipv4) { 876 struct iphdr *iph = ip_hdr(skb); 877 878 iph->check = 0; 879 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 880 IPPROTO_TCP, 0); 881 } else { 882 struct ipv6hdr *iph = ipv6_hdr(skb); 883 884 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0, 885 IPPROTO_TCP, 0); 886 } 887} 888 889 890/* 891 * Transmits a pkt thru a given tq 892 * Returns: 893 * NETDEV_TX_OK: descriptors are setup successfully 894 * NETDEV_TX_OK: error occurred, the pkt is dropped 895 * NETDEV_TX_BUSY: tx ring is full, queue is stopped 896 * 897 * Side-effects: 898 * 1. tx ring may be changed 899 * 2. tq stats may be updated accordingly 900 * 3. shared->txNumDeferred may be updated 901 */ 902 903static int 904vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 905 struct vmxnet3_adapter *adapter, struct net_device *netdev) 906{ 907 int ret; 908 u32 count; 909 unsigned long flags; 910 struct vmxnet3_tx_ctx ctx; 911 union Vmxnet3_GenericDesc *gdesc; 912#ifdef __BIG_ENDIAN_BITFIELD 913 /* Use temporary descriptor to avoid touching bits multiple times */ 914 union Vmxnet3_GenericDesc tempTxDesc; 915#endif 916 917 /* conservatively estimate # of descriptors to use */ 918 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 919 skb_shinfo(skb)->nr_frags + 1; 920 921 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP)); 922 923 ctx.mss = skb_shinfo(skb)->gso_size; 924 if (ctx.mss) { 925 if (skb_header_cloned(skb)) { 926 if (unlikely(pskb_expand_head(skb, 0, 0, 927 GFP_ATOMIC) != 0)) { 928 tq->stats.drop_tso++; 929 goto drop_pkt; 930 } 931 tq->stats.copy_skb_header++; 932 } 933 vmxnet3_prepare_tso(skb, &ctx); 934 } else { 935 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) { 936 937 /* non-tso pkts must not use more than 938 * VMXNET3_MAX_TXD_PER_PKT entries 939 */ 940 if (skb_linearize(skb) != 0) { 941 tq->stats.drop_too_many_frags++; 942 goto drop_pkt; 943 } 944 tq->stats.linearized++; 945 946 /* recalculate the # of descriptors to use */ 947 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 948 } 949 } 950 951 spin_lock_irqsave(&tq->tx_lock, flags); 952 953 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) { 954 tq->stats.tx_ring_full++; 955 dev_dbg(&adapter->netdev->dev, 956 "tx queue stopped on %s, next2comp %u" 957 " next2fill %u\n", adapter->netdev->name, 958 tq->tx_ring.next2comp, tq->tx_ring.next2fill); 959 960 vmxnet3_tq_stop(tq, adapter); 961 spin_unlock_irqrestore(&tq->tx_lock, flags); 962 return NETDEV_TX_BUSY; 963 } 964 965 966 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter); 967 if (ret >= 0) { 968 BUG_ON(ret <= 0 && ctx.copy_size != 0); 969 /* hdrs parsed, check against other limits */ 970 if (ctx.mss) { 971 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size > 972 VMXNET3_MAX_TX_BUF_SIZE)) { 973 goto hdr_too_big; 974 } 975 } else { 976 if (skb->ip_summed == CHECKSUM_PARTIAL) { 977 if (unlikely(ctx.eth_ip_hdr_size + 978 skb->csum_offset > 979 VMXNET3_MAX_CSUM_OFFSET)) { 980 goto hdr_too_big; 981 } 982 } 983 } 984 } else { 985 tq->stats.drop_hdr_inspect_err++; 986 goto unlock_drop_pkt; 987 } 988 989 /* fill tx descs related to addr & len */ 990 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter); 991 992 /* setup the EOP desc */ 993 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP); 994 995 /* setup the SOP desc */ 996#ifdef __BIG_ENDIAN_BITFIELD 997 gdesc = &tempTxDesc; 998 gdesc->dword[2] = ctx.sop_txd->dword[2]; 999 gdesc->dword[3] = ctx.sop_txd->dword[3]; 1000#else 1001 gdesc = ctx.sop_txd; 1002#endif 1003 if (ctx.mss) { 1004 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size; 1005 gdesc->txd.om = VMXNET3_OM_TSO; 1006 gdesc->txd.msscof = ctx.mss; 1007 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len - 1008 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss); 1009 } else { 1010 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1011 gdesc->txd.hlen = ctx.eth_ip_hdr_size; 1012 gdesc->txd.om = VMXNET3_OM_CSUM; 1013 gdesc->txd.msscof = ctx.eth_ip_hdr_size + 1014 skb->csum_offset; 1015 } else { 1016 gdesc->txd.om = 0; 1017 gdesc->txd.msscof = 0; 1018 } 1019 le32_add_cpu(&tq->shared->txNumDeferred, 1); 1020 } 1021 1022 if (vlan_tx_tag_present(skb)) { 1023 gdesc->txd.ti = 1; 1024 gdesc->txd.tci = vlan_tx_tag_get(skb); 1025 } 1026 1027 /* finally flips the GEN bit of the SOP desc. */ 1028 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^ 1029 VMXNET3_TXD_GEN); 1030#ifdef __BIG_ENDIAN_BITFIELD 1031 /* Finished updating in bitfields of Tx Desc, so write them in original 1032 * place. 1033 */ 1034 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc, 1035 (struct Vmxnet3_TxDesc *)ctx.sop_txd); 1036 gdesc = ctx.sop_txd; 1037#endif 1038 dev_dbg(&adapter->netdev->dev, 1039 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n", 1040 (u32)(ctx.sop_txd - 1041 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), 1042 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3])); 1043 1044 spin_unlock_irqrestore(&tq->tx_lock, flags); 1045 1046 if (le32_to_cpu(tq->shared->txNumDeferred) >= 1047 le32_to_cpu(tq->shared->txThreshold)) { 1048 tq->shared->txNumDeferred = 0; 1049 VMXNET3_WRITE_BAR0_REG(adapter, 1050 VMXNET3_REG_TXPROD + tq->qid * 8, 1051 tq->tx_ring.next2fill); 1052 } 1053 1054 return NETDEV_TX_OK; 1055 1056hdr_too_big: 1057 tq->stats.drop_oversized_hdr++; 1058unlock_drop_pkt: 1059 spin_unlock_irqrestore(&tq->tx_lock, flags); 1060drop_pkt: 1061 tq->stats.drop_total++; 1062 dev_kfree_skb(skb); 1063 return NETDEV_TX_OK; 1064} 1065 1066 1067static netdev_tx_t 1068vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1069{ 1070 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1071 1072 BUG_ON(skb->queue_mapping > adapter->num_tx_queues); 1073 return vmxnet3_tq_xmit(skb, 1074 &adapter->tx_queue[skb->queue_mapping], 1075 adapter, netdev); 1076} 1077 1078 1079static void 1080vmxnet3_rx_csum(struct vmxnet3_adapter *adapter, 1081 struct sk_buff *skb, 1082 union Vmxnet3_GenericDesc *gdesc) 1083{ 1084 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) { 1085 /* typical case: TCP/UDP over IP and both csums are correct */ 1086 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) == 1087 VMXNET3_RCD_CSUM_OK) { 1088 skb->ip_summed = CHECKSUM_UNNECESSARY; 1089 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1090 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6)); 1091 BUG_ON(gdesc->rcd.frg); 1092 } else { 1093 if (gdesc->rcd.csum) { 1094 skb->csum = htons(gdesc->rcd.csum); 1095 skb->ip_summed = CHECKSUM_PARTIAL; 1096 } else { 1097 skb_checksum_none_assert(skb); 1098 } 1099 } 1100 } else { 1101 skb_checksum_none_assert(skb); 1102 } 1103} 1104 1105 1106static void 1107vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd, 1108 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter) 1109{ 1110 rq->stats.drop_err++; 1111 if (!rcd->fcs) 1112 rq->stats.drop_fcs++; 1113 1114 rq->stats.drop_total++; 1115 1116 /* 1117 * We do not unmap and chain the rx buffer to the skb. 1118 * We basically pretend this buffer is not used and will be recycled 1119 * by vmxnet3_rq_alloc_rx_buf() 1120 */ 1121 1122 /* 1123 * ctx->skb may be NULL if this is the first and the only one 1124 * desc for the pkt 1125 */ 1126 if (ctx->skb) 1127 dev_kfree_skb_irq(ctx->skb); 1128 1129 ctx->skb = NULL; 1130} 1131 1132 1133static int 1134vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq, 1135 struct vmxnet3_adapter *adapter, int quota) 1136{ 1137 static const u32 rxprod_reg[2] = { 1138 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2 1139 }; 1140 u32 num_rxd = 0; 1141 bool skip_page_frags = false; 1142 struct Vmxnet3_RxCompDesc *rcd; 1143 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx; 1144#ifdef __BIG_ENDIAN_BITFIELD 1145 struct Vmxnet3_RxDesc rxCmdDesc; 1146 struct Vmxnet3_RxCompDesc rxComp; 1147#endif 1148 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, 1149 &rxComp); 1150 while (rcd->gen == rq->comp_ring.gen) { 1151 struct vmxnet3_rx_buf_info *rbi; 1152 struct sk_buff *skb, *new_skb = NULL; 1153 struct page *new_page = NULL; 1154 int num_to_alloc; 1155 struct Vmxnet3_RxDesc *rxd; 1156 u32 idx, ring_idx; 1157 struct vmxnet3_cmd_ring *ring = NULL; 1158 if (num_rxd >= quota) { 1159 /* we may stop even before we see the EOP desc of 1160 * the current pkt 1161 */ 1162 break; 1163 } 1164 num_rxd++; 1165 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2); 1166 idx = rcd->rxdIdx; 1167 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1; 1168 ring = rq->rx_ring + ring_idx; 1169 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, 1170 &rxCmdDesc); 1171 rbi = rq->buf_info[ring_idx] + idx; 1172 1173 BUG_ON(rxd->addr != rbi->dma_addr || 1174 rxd->len != rbi->len); 1175 1176 if (unlikely(rcd->eop && rcd->err)) { 1177 vmxnet3_rx_error(rq, rcd, ctx, adapter); 1178 goto rcd_done; 1179 } 1180 1181 if (rcd->sop) { /* first buf of the pkt */ 1182 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD || 1183 rcd->rqID != rq->qid); 1184 1185 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB); 1186 BUG_ON(ctx->skb != NULL || rbi->skb == NULL); 1187 1188 if (unlikely(rcd->len == 0)) { 1189 /* Pretend the rx buffer is skipped. */ 1190 BUG_ON(!(rcd->sop && rcd->eop)); 1191 dev_dbg(&adapter->netdev->dev, 1192 "rxRing[%u][%u] 0 length\n", 1193 ring_idx, idx); 1194 goto rcd_done; 1195 } 1196 1197 skip_page_frags = false; 1198 ctx->skb = rbi->skb; 1199 new_skb = dev_alloc_skb(rbi->len + NET_IP_ALIGN); 1200 if (new_skb == NULL) { 1201 /* Skb allocation failed, do not handover this 1202 * skb to stack. Reuse it. Drop the existing pkt 1203 */ 1204 rq->stats.rx_buf_alloc_failure++; 1205 ctx->skb = NULL; 1206 rq->stats.drop_total++; 1207 skip_page_frags = true; 1208 goto rcd_done; 1209 } 1210 1211 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len, 1212 PCI_DMA_FROMDEVICE); 1213 1214 skb_put(ctx->skb, rcd->len); 1215 1216 /* Immediate refill */ 1217 new_skb->dev = adapter->netdev; 1218 skb_reserve(new_skb, NET_IP_ALIGN); 1219 rbi->skb = new_skb; 1220 rbi->dma_addr = pci_map_single(adapter->pdev, 1221 rbi->skb->data, rbi->len, 1222 PCI_DMA_FROMDEVICE); 1223 rxd->addr = cpu_to_le64(rbi->dma_addr); 1224 rxd->len = rbi->len; 1225 1226 } else { 1227 BUG_ON(ctx->skb == NULL && !skip_page_frags); 1228 1229 /* non SOP buffer must be type 1 in most cases */ 1230 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE); 1231 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY); 1232 1233 /* If an sop buffer was dropped, skip all 1234 * following non-sop fragments. They will be reused. 1235 */ 1236 if (skip_page_frags) 1237 goto rcd_done; 1238 1239 new_page = alloc_page(GFP_ATOMIC); 1240 if (unlikely(new_page == NULL)) { 1241 /* Replacement page frag could not be allocated. 1242 * Reuse this page. Drop the pkt and free the 1243 * skb which contained this page as a frag. Skip 1244 * processing all the following non-sop frags. 1245 */ 1246 rq->stats.rx_buf_alloc_failure++; 1247 dev_kfree_skb(ctx->skb); 1248 ctx->skb = NULL; 1249 skip_page_frags = true; 1250 goto rcd_done; 1251 } 1252 1253 if (rcd->len) { 1254 pci_unmap_page(adapter->pdev, 1255 rbi->dma_addr, rbi->len, 1256 PCI_DMA_FROMDEVICE); 1257 1258 vmxnet3_append_frag(ctx->skb, rcd, rbi); 1259 } 1260 1261 /* Immediate refill */ 1262 rbi->page = new_page; 1263 rbi->dma_addr = pci_map_page(adapter->pdev, rbi->page, 1264 0, PAGE_SIZE, 1265 PCI_DMA_FROMDEVICE); 1266 rxd->addr = cpu_to_le64(rbi->dma_addr); 1267 rxd->len = rbi->len; 1268 } 1269 1270 1271 skb = ctx->skb; 1272 if (rcd->eop) { 1273 skb->len += skb->data_len; 1274 1275 vmxnet3_rx_csum(adapter, skb, 1276 (union Vmxnet3_GenericDesc *)rcd); 1277 skb->protocol = eth_type_trans(skb, adapter->netdev); 1278 1279 if (unlikely(rcd->ts)) 1280 __vlan_hwaccel_put_tag(skb, rcd->tci); 1281 1282 if (adapter->netdev->features & NETIF_F_LRO) 1283 netif_receive_skb(skb); 1284 else 1285 napi_gro_receive(&rq->napi, skb); 1286 1287 ctx->skb = NULL; 1288 } 1289 1290rcd_done: 1291 /* device may have skipped some rx descs */ 1292 ring->next2comp = idx; 1293 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring); 1294 ring = rq->rx_ring + ring_idx; 1295 while (num_to_alloc) { 1296 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd, 1297 &rxCmdDesc); 1298 BUG_ON(!rxd->addr); 1299 1300 /* Recv desc is ready to be used by the device */ 1301 rxd->gen = ring->gen; 1302 vmxnet3_cmd_ring_adv_next2fill(ring); 1303 num_to_alloc--; 1304 } 1305 1306 /* if needed, update the register */ 1307 if (unlikely(rq->shared->updateRxProd)) { 1308 VMXNET3_WRITE_BAR0_REG(adapter, 1309 rxprod_reg[ring_idx] + rq->qid * 8, 1310 ring->next2fill); 1311 rq->uncommitted[ring_idx] = 0; 1312 } 1313 1314 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring); 1315 vmxnet3_getRxComp(rcd, 1316 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); 1317 } 1318 1319 return num_rxd; 1320} 1321 1322 1323static void 1324vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq, 1325 struct vmxnet3_adapter *adapter) 1326{ 1327 u32 i, ring_idx; 1328 struct Vmxnet3_RxDesc *rxd; 1329 1330 for (ring_idx = 0; ring_idx < 2; ring_idx++) { 1331 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) { 1332#ifdef __BIG_ENDIAN_BITFIELD 1333 struct Vmxnet3_RxDesc rxDesc; 1334#endif 1335 vmxnet3_getRxDesc(rxd, 1336 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); 1337 1338 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD && 1339 rq->buf_info[ring_idx][i].skb) { 1340 pci_unmap_single(adapter->pdev, rxd->addr, 1341 rxd->len, PCI_DMA_FROMDEVICE); 1342 dev_kfree_skb(rq->buf_info[ring_idx][i].skb); 1343 rq->buf_info[ring_idx][i].skb = NULL; 1344 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY && 1345 rq->buf_info[ring_idx][i].page) { 1346 pci_unmap_page(adapter->pdev, rxd->addr, 1347 rxd->len, PCI_DMA_FROMDEVICE); 1348 put_page(rq->buf_info[ring_idx][i].page); 1349 rq->buf_info[ring_idx][i].page = NULL; 1350 } 1351 } 1352 1353 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN; 1354 rq->rx_ring[ring_idx].next2fill = 1355 rq->rx_ring[ring_idx].next2comp = 0; 1356 rq->uncommitted[ring_idx] = 0; 1357 } 1358 1359 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1360 rq->comp_ring.next2proc = 0; 1361} 1362 1363 1364static void 1365vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter) 1366{ 1367 int i; 1368 1369 for (i = 0; i < adapter->num_rx_queues; i++) 1370 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter); 1371} 1372 1373 1374void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq, 1375 struct vmxnet3_adapter *adapter) 1376{ 1377 int i; 1378 int j; 1379 1380 /* all rx buffers must have already been freed */ 1381 for (i = 0; i < 2; i++) { 1382 if (rq->buf_info[i]) { 1383 for (j = 0; j < rq->rx_ring[i].size; j++) 1384 BUG_ON(rq->buf_info[i][j].page != NULL); 1385 } 1386 } 1387 1388 1389 kfree(rq->buf_info[0]); 1390 1391 for (i = 0; i < 2; i++) { 1392 if (rq->rx_ring[i].base) { 1393 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size 1394 * sizeof(struct Vmxnet3_RxDesc), 1395 rq->rx_ring[i].base, 1396 rq->rx_ring[i].basePA); 1397 rq->rx_ring[i].base = NULL; 1398 } 1399 rq->buf_info[i] = NULL; 1400 } 1401 1402 if (rq->comp_ring.base) { 1403 pci_free_consistent(adapter->pdev, rq->comp_ring.size * 1404 sizeof(struct Vmxnet3_RxCompDesc), 1405 rq->comp_ring.base, rq->comp_ring.basePA); 1406 rq->comp_ring.base = NULL; 1407 } 1408} 1409 1410 1411static int 1412vmxnet3_rq_init(struct vmxnet3_rx_queue *rq, 1413 struct vmxnet3_adapter *adapter) 1414{ 1415 int i; 1416 1417 /* initialize buf_info */ 1418 for (i = 0; i < rq->rx_ring[0].size; i++) { 1419 1420 /* 1st buf for a pkt is skbuff */ 1421 if (i % adapter->rx_buf_per_pkt == 0) { 1422 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB; 1423 rq->buf_info[0][i].len = adapter->skb_buf_size; 1424 } else { /* subsequent bufs for a pkt is frag */ 1425 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE; 1426 rq->buf_info[0][i].len = PAGE_SIZE; 1427 } 1428 } 1429 for (i = 0; i < rq->rx_ring[1].size; i++) { 1430 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE; 1431 rq->buf_info[1][i].len = PAGE_SIZE; 1432 } 1433 1434 /* reset internal state and allocate buffers for both rings */ 1435 for (i = 0; i < 2; i++) { 1436 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0; 1437 rq->uncommitted[i] = 0; 1438 1439 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * 1440 sizeof(struct Vmxnet3_RxDesc)); 1441 rq->rx_ring[i].gen = VMXNET3_INIT_GEN; 1442 } 1443 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1, 1444 adapter) == 0) { 1445 /* at least has 1 rx buffer for the 1st ring */ 1446 return -ENOMEM; 1447 } 1448 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter); 1449 1450 /* reset the comp ring */ 1451 rq->comp_ring.next2proc = 0; 1452 memset(rq->comp_ring.base, 0, rq->comp_ring.size * 1453 sizeof(struct Vmxnet3_RxCompDesc)); 1454 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1455 1456 /* reset rxctx */ 1457 rq->rx_ctx.skb = NULL; 1458 1459 /* stats are not reset */ 1460 return 0; 1461} 1462 1463 1464static int 1465vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter) 1466{ 1467 int i, err = 0; 1468 1469 for (i = 0; i < adapter->num_rx_queues; i++) { 1470 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter); 1471 if (unlikely(err)) { 1472 dev_err(&adapter->netdev->dev, "%s: failed to " 1473 "initialize rx queue%i\n", 1474 adapter->netdev->name, i); 1475 break; 1476 } 1477 } 1478 return err; 1479 1480} 1481 1482 1483static int 1484vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter) 1485{ 1486 int i; 1487 size_t sz; 1488 struct vmxnet3_rx_buf_info *bi; 1489 1490 for (i = 0; i < 2; i++) { 1491 1492 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc); 1493 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz, 1494 &rq->rx_ring[i].basePA); 1495 if (!rq->rx_ring[i].base) { 1496 printk(KERN_ERR "%s: failed to allocate rx ring %d\n", 1497 adapter->netdev->name, i); 1498 goto err; 1499 } 1500 } 1501 1502 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc); 1503 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz, 1504 &rq->comp_ring.basePA); 1505 if (!rq->comp_ring.base) { 1506 printk(KERN_ERR "%s: failed to allocate rx comp ring\n", 1507 adapter->netdev->name); 1508 goto err; 1509 } 1510 1511 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size + 1512 rq->rx_ring[1].size); 1513 bi = kzalloc(sz, GFP_KERNEL); 1514 if (!bi) 1515 goto err; 1516 1517 rq->buf_info[0] = bi; 1518 rq->buf_info[1] = bi + rq->rx_ring[0].size; 1519 1520 return 0; 1521 1522err: 1523 vmxnet3_rq_destroy(rq, adapter); 1524 return -ENOMEM; 1525} 1526 1527 1528static int 1529vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter) 1530{ 1531 int i, err = 0; 1532 1533 for (i = 0; i < adapter->num_rx_queues; i++) { 1534 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter); 1535 if (unlikely(err)) { 1536 dev_err(&adapter->netdev->dev, 1537 "%s: failed to create rx queue%i\n", 1538 adapter->netdev->name, i); 1539 goto err_out; 1540 } 1541 } 1542 return err; 1543err_out: 1544 vmxnet3_rq_destroy_all(adapter); 1545 return err; 1546 1547} 1548 1549/* Multiple queue aware polling function for tx and rx */ 1550 1551static int 1552vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget) 1553{ 1554 int rcd_done = 0, i; 1555 if (unlikely(adapter->shared->ecr)) 1556 vmxnet3_process_events(adapter); 1557 for (i = 0; i < adapter->num_tx_queues; i++) 1558 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter); 1559 1560 for (i = 0; i < adapter->num_rx_queues; i++) 1561 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i], 1562 adapter, budget); 1563 return rcd_done; 1564} 1565 1566 1567static int 1568vmxnet3_poll(struct napi_struct *napi, int budget) 1569{ 1570 struct vmxnet3_rx_queue *rx_queue = container_of(napi, 1571 struct vmxnet3_rx_queue, napi); 1572 int rxd_done; 1573 1574 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget); 1575 1576 if (rxd_done < budget) { 1577 napi_complete(napi); 1578 vmxnet3_enable_all_intrs(rx_queue->adapter); 1579 } 1580 return rxd_done; 1581} 1582 1583/* 1584 * NAPI polling function for MSI-X mode with multiple Rx queues 1585 * Returns the # of the NAPI credit consumed (# of rx descriptors processed) 1586 */ 1587 1588static int 1589vmxnet3_poll_rx_only(struct napi_struct *napi, int budget) 1590{ 1591 struct vmxnet3_rx_queue *rq = container_of(napi, 1592 struct vmxnet3_rx_queue, napi); 1593 struct vmxnet3_adapter *adapter = rq->adapter; 1594 int rxd_done; 1595 1596 /* When sharing interrupt with corresponding tx queue, process 1597 * tx completions in that queue as well 1598 */ 1599 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) { 1600 struct vmxnet3_tx_queue *tq = 1601 &adapter->tx_queue[rq - adapter->rx_queue]; 1602 vmxnet3_tq_tx_complete(tq, adapter); 1603 } 1604 1605 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget); 1606 1607 if (rxd_done < budget) { 1608 napi_complete(napi); 1609 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx); 1610 } 1611 return rxd_done; 1612} 1613 1614 1615#ifdef CONFIG_PCI_MSI 1616 1617/* 1618 * Handle completion interrupts on tx queues 1619 * Returns whether or not the intr is handled 1620 */ 1621 1622static irqreturn_t 1623vmxnet3_msix_tx(int irq, void *data) 1624{ 1625 struct vmxnet3_tx_queue *tq = data; 1626 struct vmxnet3_adapter *adapter = tq->adapter; 1627 1628 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1629 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx); 1630 1631 /* Handle the case where only one irq is allocate for all tx queues */ 1632 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 1633 int i; 1634 for (i = 0; i < adapter->num_tx_queues; i++) { 1635 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i]; 1636 vmxnet3_tq_tx_complete(txq, adapter); 1637 } 1638 } else { 1639 vmxnet3_tq_tx_complete(tq, adapter); 1640 } 1641 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx); 1642 1643 return IRQ_HANDLED; 1644} 1645 1646 1647/* 1648 * Handle completion interrupts on rx queues. Returns whether or not the 1649 * intr is handled 1650 */ 1651 1652static irqreturn_t 1653vmxnet3_msix_rx(int irq, void *data) 1654{ 1655 struct vmxnet3_rx_queue *rq = data; 1656 struct vmxnet3_adapter *adapter = rq->adapter; 1657 1658 /* disable intr if needed */ 1659 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1660 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx); 1661 napi_schedule(&rq->napi); 1662 1663 return IRQ_HANDLED; 1664} 1665 1666/* 1667 *---------------------------------------------------------------------------- 1668 * 1669 * vmxnet3_msix_event -- 1670 * 1671 * vmxnet3 msix event intr handler 1672 * 1673 * Result: 1674 * whether or not the intr is handled 1675 * 1676 *---------------------------------------------------------------------------- 1677 */ 1678 1679static irqreturn_t 1680vmxnet3_msix_event(int irq, void *data) 1681{ 1682 struct net_device *dev = data; 1683 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1684 1685 /* disable intr if needed */ 1686 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1687 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx); 1688 1689 if (adapter->shared->ecr) 1690 vmxnet3_process_events(adapter); 1691 1692 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx); 1693 1694 return IRQ_HANDLED; 1695} 1696 1697#endif /* CONFIG_PCI_MSI */ 1698 1699 1700/* Interrupt handler for vmxnet3 */ 1701static irqreturn_t 1702vmxnet3_intr(int irq, void *dev_id) 1703{ 1704 struct net_device *dev = dev_id; 1705 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1706 1707 if (adapter->intr.type == VMXNET3_IT_INTX) { 1708 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR); 1709 if (unlikely(icr == 0)) 1710 /* not ours */ 1711 return IRQ_NONE; 1712 } 1713 1714 1715 /* disable intr if needed */ 1716 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1717 vmxnet3_disable_all_intrs(adapter); 1718 1719 napi_schedule(&adapter->rx_queue[0].napi); 1720 1721 return IRQ_HANDLED; 1722} 1723 1724#ifdef CONFIG_NET_POLL_CONTROLLER 1725 1726/* netpoll callback. */ 1727static void 1728vmxnet3_netpoll(struct net_device *netdev) 1729{ 1730 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1731 1732 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1733 vmxnet3_disable_all_intrs(adapter); 1734 1735 vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size); 1736 vmxnet3_enable_all_intrs(adapter); 1737 1738} 1739#endif /* CONFIG_NET_POLL_CONTROLLER */ 1740 1741static int 1742vmxnet3_request_irqs(struct vmxnet3_adapter *adapter) 1743{ 1744 struct vmxnet3_intr *intr = &adapter->intr; 1745 int err = 0, i; 1746 int vector = 0; 1747 1748#ifdef CONFIG_PCI_MSI 1749 if (adapter->intr.type == VMXNET3_IT_MSIX) { 1750 for (i = 0; i < adapter->num_tx_queues; i++) { 1751 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 1752 sprintf(adapter->tx_queue[i].name, "%s-tx-%d", 1753 adapter->netdev->name, vector); 1754 err = request_irq( 1755 intr->msix_entries[vector].vector, 1756 vmxnet3_msix_tx, 0, 1757 adapter->tx_queue[i].name, 1758 &adapter->tx_queue[i]); 1759 } else { 1760 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d", 1761 adapter->netdev->name, vector); 1762 } 1763 if (err) { 1764 dev_err(&adapter->netdev->dev, 1765 "Failed to request irq for MSIX, %s, " 1766 "error %d\n", 1767 adapter->tx_queue[i].name, err); 1768 return err; 1769 } 1770 1771 /* Handle the case where only 1 MSIx was allocated for 1772 * all tx queues */ 1773 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 1774 for (; i < adapter->num_tx_queues; i++) 1775 adapter->tx_queue[i].comp_ring.intr_idx 1776 = vector; 1777 vector++; 1778 break; 1779 } else { 1780 adapter->tx_queue[i].comp_ring.intr_idx 1781 = vector++; 1782 } 1783 } 1784 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) 1785 vector = 0; 1786 1787 for (i = 0; i < adapter->num_rx_queues; i++) { 1788 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) 1789 sprintf(adapter->rx_queue[i].name, "%s-rx-%d", 1790 adapter->netdev->name, vector); 1791 else 1792 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d", 1793 adapter->netdev->name, vector); 1794 err = request_irq(intr->msix_entries[vector].vector, 1795 vmxnet3_msix_rx, 0, 1796 adapter->rx_queue[i].name, 1797 &(adapter->rx_queue[i])); 1798 if (err) { 1799 printk(KERN_ERR "Failed to request irq for MSIX" 1800 ", %s, error %d\n", 1801 adapter->rx_queue[i].name, err); 1802 return err; 1803 } 1804 1805 adapter->rx_queue[i].comp_ring.intr_idx = vector++; 1806 } 1807 1808 sprintf(intr->event_msi_vector_name, "%s-event-%d", 1809 adapter->netdev->name, vector); 1810 err = request_irq(intr->msix_entries[vector].vector, 1811 vmxnet3_msix_event, 0, 1812 intr->event_msi_vector_name, adapter->netdev); 1813 intr->event_intr_idx = vector; 1814 1815 } else if (intr->type == VMXNET3_IT_MSI) { 1816 adapter->num_rx_queues = 1; 1817 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0, 1818 adapter->netdev->name, adapter->netdev); 1819 } else { 1820#endif 1821 adapter->num_rx_queues = 1; 1822 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 1823 IRQF_SHARED, adapter->netdev->name, 1824 adapter->netdev); 1825#ifdef CONFIG_PCI_MSI 1826 } 1827#endif 1828 intr->num_intrs = vector + 1; 1829 if (err) { 1830 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error" 1831 ":%d\n", adapter->netdev->name, intr->type, err); 1832 } else { 1833 /* Number of rx queues will not change after this */ 1834 for (i = 0; i < adapter->num_rx_queues; i++) { 1835 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 1836 rq->qid = i; 1837 rq->qid2 = i + adapter->num_rx_queues; 1838 } 1839 1840 1841 1842 /* init our intr settings */ 1843 for (i = 0; i < intr->num_intrs; i++) 1844 intr->mod_levels[i] = UPT1_IML_ADAPTIVE; 1845 if (adapter->intr.type != VMXNET3_IT_MSIX) { 1846 adapter->intr.event_intr_idx = 0; 1847 for (i = 0; i < adapter->num_tx_queues; i++) 1848 adapter->tx_queue[i].comp_ring.intr_idx = 0; 1849 adapter->rx_queue[0].comp_ring.intr_idx = 0; 1850 } 1851 1852 printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors " 1853 "allocated\n", adapter->netdev->name, intr->type, 1854 intr->mask_mode, intr->num_intrs); 1855 } 1856 1857 return err; 1858} 1859 1860 1861static void 1862vmxnet3_free_irqs(struct vmxnet3_adapter *adapter) 1863{ 1864 struct vmxnet3_intr *intr = &adapter->intr; 1865 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0); 1866 1867 switch (intr->type) { 1868#ifdef CONFIG_PCI_MSI 1869 case VMXNET3_IT_MSIX: 1870 { 1871 int i, vector = 0; 1872 1873 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 1874 for (i = 0; i < adapter->num_tx_queues; i++) { 1875 free_irq(intr->msix_entries[vector++].vector, 1876 &(adapter->tx_queue[i])); 1877 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) 1878 break; 1879 } 1880 } 1881 1882 for (i = 0; i < adapter->num_rx_queues; i++) { 1883 free_irq(intr->msix_entries[vector++].vector, 1884 &(adapter->rx_queue[i])); 1885 } 1886 1887 free_irq(intr->msix_entries[vector].vector, 1888 adapter->netdev); 1889 BUG_ON(vector >= intr->num_intrs); 1890 break; 1891 } 1892#endif 1893 case VMXNET3_IT_MSI: 1894 free_irq(adapter->pdev->irq, adapter->netdev); 1895 break; 1896 case VMXNET3_IT_INTX: 1897 free_irq(adapter->pdev->irq, adapter->netdev); 1898 break; 1899 default: 1900 BUG(); 1901 } 1902} 1903 1904 1905static void 1906vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter) 1907{ 1908 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1909 u16 vid; 1910 1911 /* allow untagged pkts */ 1912 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 1913 1914 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 1915 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 1916} 1917 1918 1919static int 1920vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 1921{ 1922 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1923 1924 if (!(netdev->flags & IFF_PROMISC)) { 1925 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1926 unsigned long flags; 1927 1928 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 1929 spin_lock_irqsave(&adapter->cmd_lock, flags); 1930 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1931 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1932 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 1933 } 1934 1935 set_bit(vid, adapter->active_vlans); 1936 1937 return 0; 1938} 1939 1940 1941static int 1942vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 1943{ 1944 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1945 1946 if (!(netdev->flags & IFF_PROMISC)) { 1947 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1948 unsigned long flags; 1949 1950 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid); 1951 spin_lock_irqsave(&adapter->cmd_lock, flags); 1952 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1953 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1954 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 1955 } 1956 1957 clear_bit(vid, adapter->active_vlans); 1958 1959 return 0; 1960} 1961 1962 1963static u8 * 1964vmxnet3_copy_mc(struct net_device *netdev) 1965{ 1966 u8 *buf = NULL; 1967 u32 sz = netdev_mc_count(netdev) * ETH_ALEN; 1968 1969 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */ 1970 if (sz <= 0xffff) { 1971 /* We may be called with BH disabled */ 1972 buf = kmalloc(sz, GFP_ATOMIC); 1973 if (buf) { 1974 struct netdev_hw_addr *ha; 1975 int i = 0; 1976 1977 netdev_for_each_mc_addr(ha, netdev) 1978 memcpy(buf + i++ * ETH_ALEN, ha->addr, 1979 ETH_ALEN); 1980 } 1981 } 1982 return buf; 1983} 1984 1985 1986static void 1987vmxnet3_set_mc(struct net_device *netdev) 1988{ 1989 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1990 unsigned long flags; 1991 struct Vmxnet3_RxFilterConf *rxConf = 1992 &adapter->shared->devRead.rxFilterConf; 1993 u8 *new_table = NULL; 1994 u32 new_mode = VMXNET3_RXM_UCAST; 1995 1996 if (netdev->flags & IFF_PROMISC) { 1997 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1998 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable)); 1999 2000 new_mode |= VMXNET3_RXM_PROMISC; 2001 } else { 2002 vmxnet3_restore_vlan(adapter); 2003 } 2004 2005 if (netdev->flags & IFF_BROADCAST) 2006 new_mode |= VMXNET3_RXM_BCAST; 2007 2008 if (netdev->flags & IFF_ALLMULTI) 2009 new_mode |= VMXNET3_RXM_ALL_MULTI; 2010 else 2011 if (!netdev_mc_empty(netdev)) { 2012 new_table = vmxnet3_copy_mc(netdev); 2013 if (new_table) { 2014 new_mode |= VMXNET3_RXM_MCAST; 2015 rxConf->mfTableLen = cpu_to_le16( 2016 netdev_mc_count(netdev) * ETH_ALEN); 2017 rxConf->mfTablePA = cpu_to_le64(virt_to_phys( 2018 new_table)); 2019 } else { 2020 printk(KERN_INFO "%s: failed to copy mcast list" 2021 ", setting ALL_MULTI\n", netdev->name); 2022 new_mode |= VMXNET3_RXM_ALL_MULTI; 2023 } 2024 } 2025 2026 2027 if (!(new_mode & VMXNET3_RXM_MCAST)) { 2028 rxConf->mfTableLen = 0; 2029 rxConf->mfTablePA = 0; 2030 } 2031 2032 spin_lock_irqsave(&adapter->cmd_lock, flags); 2033 if (new_mode != rxConf->rxMode) { 2034 rxConf->rxMode = cpu_to_le32(new_mode); 2035 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2036 VMXNET3_CMD_UPDATE_RX_MODE); 2037 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2038 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2039 } 2040 2041 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2042 VMXNET3_CMD_UPDATE_MAC_FILTERS); 2043 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2044 2045 kfree(new_table); 2046} 2047 2048void 2049vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter) 2050{ 2051 int i; 2052 2053 for (i = 0; i < adapter->num_rx_queues; i++) 2054 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter); 2055} 2056 2057 2058/* 2059 * Set up driver_shared based on settings in adapter. 2060 */ 2061 2062static void 2063vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter) 2064{ 2065 struct Vmxnet3_DriverShared *shared = adapter->shared; 2066 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 2067 struct Vmxnet3_TxQueueConf *tqc; 2068 struct Vmxnet3_RxQueueConf *rqc; 2069 int i; 2070 2071 memset(shared, 0, sizeof(*shared)); 2072 2073 /* driver settings */ 2074 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC); 2075 devRead->misc.driverInfo.version = cpu_to_le32( 2076 VMXNET3_DRIVER_VERSION_NUM); 2077 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ? 2078 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64); 2079 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 2080 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32( 2081 *((u32 *)&devRead->misc.driverInfo.gos)); 2082 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1); 2083 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1); 2084 2085 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter)); 2086 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter)); 2087 2088 /* set up feature flags */ 2089 if (adapter->netdev->features & NETIF_F_RXCSUM) 2090 devRead->misc.uptFeatures |= UPT1_F_RXCSUM; 2091 2092 if (adapter->netdev->features & NETIF_F_LRO) { 2093 devRead->misc.uptFeatures |= UPT1_F_LRO; 2094 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS); 2095 } 2096 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) 2097 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 2098 2099 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu); 2100 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa); 2101 devRead->misc.queueDescLen = cpu_to_le32( 2102 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 2103 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc)); 2104 2105 /* tx queue settings */ 2106 devRead->misc.numTxQueues = adapter->num_tx_queues; 2107 for (i = 0; i < adapter->num_tx_queues; i++) { 2108 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2109 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL); 2110 tqc = &adapter->tqd_start[i].conf; 2111 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA); 2112 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA); 2113 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA); 2114 tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info)); 2115 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size); 2116 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size); 2117 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size); 2118 tqc->ddLen = cpu_to_le32( 2119 sizeof(struct vmxnet3_tx_buf_info) * 2120 tqc->txRingSize); 2121 tqc->intrIdx = tq->comp_ring.intr_idx; 2122 } 2123 2124 /* rx queue settings */ 2125 devRead->misc.numRxQueues = adapter->num_rx_queues; 2126 for (i = 0; i < adapter->num_rx_queues; i++) { 2127 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2128 rqc = &adapter->rqd_start[i].conf; 2129 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA); 2130 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA); 2131 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA); 2132 rqc->ddPA = cpu_to_le64(virt_to_phys( 2133 rq->buf_info)); 2134 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size); 2135 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size); 2136 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size); 2137 rqc->ddLen = cpu_to_le32( 2138 sizeof(struct vmxnet3_rx_buf_info) * 2139 (rqc->rxRingSize[0] + 2140 rqc->rxRingSize[1])); 2141 rqc->intrIdx = rq->comp_ring.intr_idx; 2142 } 2143 2144#ifdef VMXNET3_RSS 2145 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf)); 2146 2147 if (adapter->rss) { 2148 struct UPT1_RSSConf *rssConf = adapter->rss_conf; 2149 devRead->misc.uptFeatures |= UPT1_F_RSS; 2150 devRead->misc.numRxQueues = adapter->num_rx_queues; 2151 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 | 2152 UPT1_RSS_HASH_TYPE_IPV4 | 2153 UPT1_RSS_HASH_TYPE_TCP_IPV6 | 2154 UPT1_RSS_HASH_TYPE_IPV6; 2155 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ; 2156 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE; 2157 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE; 2158 get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize); 2159 for (i = 0; i < rssConf->indTableSize; i++) 2160 rssConf->indTable[i] = ethtool_rxfh_indir_default( 2161 i, adapter->num_rx_queues); 2162 2163 devRead->rssConfDesc.confVer = 1; 2164 devRead->rssConfDesc.confLen = sizeof(*rssConf); 2165 devRead->rssConfDesc.confPA = virt_to_phys(rssConf); 2166 } 2167 2168#endif /* VMXNET3_RSS */ 2169 2170 /* intr settings */ 2171 devRead->intrConf.autoMask = adapter->intr.mask_mode == 2172 VMXNET3_IMM_AUTO; 2173 devRead->intrConf.numIntrs = adapter->intr.num_intrs; 2174 for (i = 0; i < adapter->intr.num_intrs; i++) 2175 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; 2176 2177 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; 2178 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 2179 2180 /* rx filter settings */ 2181 devRead->rxFilterConf.rxMode = 0; 2182 vmxnet3_restore_vlan(adapter); 2183 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr); 2184 2185 /* the rest are already zeroed */ 2186} 2187 2188 2189int 2190vmxnet3_activate_dev(struct vmxnet3_adapter *adapter) 2191{ 2192 int err, i; 2193 u32 ret; 2194 unsigned long flags; 2195 2196 dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d," 2197 " ring sizes %u %u %u\n", adapter->netdev->name, 2198 adapter->skb_buf_size, adapter->rx_buf_per_pkt, 2199 adapter->tx_queue[0].tx_ring.size, 2200 adapter->rx_queue[0].rx_ring[0].size, 2201 adapter->rx_queue[0].rx_ring[1].size); 2202 2203 vmxnet3_tq_init_all(adapter); 2204 err = vmxnet3_rq_init_all(adapter); 2205 if (err) { 2206 printk(KERN_ERR "Failed to init rx queue for %s: error %d\n", 2207 adapter->netdev->name, err); 2208 goto rq_err; 2209 } 2210 2211 err = vmxnet3_request_irqs(adapter); 2212 if (err) { 2213 printk(KERN_ERR "Failed to setup irq for %s: error %d\n", 2214 adapter->netdev->name, err); 2215 goto irq_err; 2216 } 2217 2218 vmxnet3_setup_driver_shared(adapter); 2219 2220 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO( 2221 adapter->shared_pa)); 2222 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI( 2223 adapter->shared_pa)); 2224 spin_lock_irqsave(&adapter->cmd_lock, flags); 2225 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2226 VMXNET3_CMD_ACTIVATE_DEV); 2227 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2228 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2229 2230 if (ret != 0) { 2231 printk(KERN_ERR "Failed to activate dev %s: error %u\n", 2232 adapter->netdev->name, ret); 2233 err = -EINVAL; 2234 goto activate_err; 2235 } 2236 2237 for (i = 0; i < adapter->num_rx_queues; i++) { 2238 VMXNET3_WRITE_BAR0_REG(adapter, 2239 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN, 2240 adapter->rx_queue[i].rx_ring[0].next2fill); 2241 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 + 2242 (i * VMXNET3_REG_ALIGN)), 2243 adapter->rx_queue[i].rx_ring[1].next2fill); 2244 } 2245 2246 /* Apply the rx filter settins last. */ 2247 vmxnet3_set_mc(adapter->netdev); 2248 2249 /* 2250 * Check link state when first activating device. It will start the 2251 * tx queue if the link is up. 2252 */ 2253 vmxnet3_check_link(adapter, true); 2254 for (i = 0; i < adapter->num_rx_queues; i++) 2255 napi_enable(&adapter->rx_queue[i].napi); 2256 vmxnet3_enable_all_intrs(adapter); 2257 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2258 return 0; 2259 2260activate_err: 2261 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0); 2262 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0); 2263 vmxnet3_free_irqs(adapter); 2264irq_err: 2265rq_err: 2266 /* free up buffers we allocated */ 2267 vmxnet3_rq_cleanup_all(adapter); 2268 return err; 2269} 2270 2271 2272void 2273vmxnet3_reset_dev(struct vmxnet3_adapter *adapter) 2274{ 2275 unsigned long flags; 2276 spin_lock_irqsave(&adapter->cmd_lock, flags); 2277 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 2278 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2279} 2280 2281 2282int 2283vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter) 2284{ 2285 int i; 2286 unsigned long flags; 2287 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state)) 2288 return 0; 2289 2290 2291 spin_lock_irqsave(&adapter->cmd_lock, flags); 2292 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2293 VMXNET3_CMD_QUIESCE_DEV); 2294 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2295 vmxnet3_disable_all_intrs(adapter); 2296 2297 for (i = 0; i < adapter->num_rx_queues; i++) 2298 napi_disable(&adapter->rx_queue[i].napi); 2299 netif_tx_disable(adapter->netdev); 2300 adapter->link_speed = 0; 2301 netif_carrier_off(adapter->netdev); 2302 2303 vmxnet3_tq_cleanup_all(adapter); 2304 vmxnet3_rq_cleanup_all(adapter); 2305 vmxnet3_free_irqs(adapter); 2306 return 0; 2307} 2308 2309 2310static void 2311vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2312{ 2313 u32 tmp; 2314 2315 tmp = *(u32 *)mac; 2316 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp); 2317 2318 tmp = (mac[5] << 8) | mac[4]; 2319 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp); 2320} 2321 2322 2323static int 2324vmxnet3_set_mac_addr(struct net_device *netdev, void *p) 2325{ 2326 struct sockaddr *addr = p; 2327 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2328 2329 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2330 vmxnet3_write_mac_addr(adapter, addr->sa_data); 2331 2332 return 0; 2333} 2334 2335 2336/* ==================== initialization and cleanup routines ============ */ 2337 2338static int 2339vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64) 2340{ 2341 int err; 2342 unsigned long mmio_start, mmio_len; 2343 struct pci_dev *pdev = adapter->pdev; 2344 2345 err = pci_enable_device(pdev); 2346 if (err) { 2347 printk(KERN_ERR "Failed to enable adapter %s: error %d\n", 2348 pci_name(pdev), err); 2349 return err; 2350 } 2351 2352 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) { 2353 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) { 2354 printk(KERN_ERR "pci_set_consistent_dma_mask failed " 2355 "for adapter %s\n", pci_name(pdev)); 2356 err = -EIO; 2357 goto err_set_mask; 2358 } 2359 *dma64 = true; 2360 } else { 2361 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) { 2362 printk(KERN_ERR "pci_set_dma_mask failed for adapter " 2363 "%s\n", pci_name(pdev)); 2364 err = -EIO; 2365 goto err_set_mask; 2366 } 2367 *dma64 = false; 2368 } 2369 2370 err = pci_request_selected_regions(pdev, (1 << 2) - 1, 2371 vmxnet3_driver_name); 2372 if (err) { 2373 printk(KERN_ERR "Failed to request region for adapter %s: " 2374 "error %d\n", pci_name(pdev), err); 2375 goto err_set_mask; 2376 } 2377 2378 pci_set_master(pdev); 2379 2380 mmio_start = pci_resource_start(pdev, 0); 2381 mmio_len = pci_resource_len(pdev, 0); 2382 adapter->hw_addr0 = ioremap(mmio_start, mmio_len); 2383 if (!adapter->hw_addr0) { 2384 printk(KERN_ERR "Failed to map bar0 for adapter %s\n", 2385 pci_name(pdev)); 2386 err = -EIO; 2387 goto err_ioremap; 2388 } 2389 2390 mmio_start = pci_resource_start(pdev, 1); 2391 mmio_len = pci_resource_len(pdev, 1); 2392 adapter->hw_addr1 = ioremap(mmio_start, mmio_len); 2393 if (!adapter->hw_addr1) { 2394 printk(KERN_ERR "Failed to map bar1 for adapter %s\n", 2395 pci_name(pdev)); 2396 err = -EIO; 2397 goto err_bar1; 2398 } 2399 return 0; 2400 2401err_bar1: 2402 iounmap(adapter->hw_addr0); 2403err_ioremap: 2404 pci_release_selected_regions(pdev, (1 << 2) - 1); 2405err_set_mask: 2406 pci_disable_device(pdev); 2407 return err; 2408} 2409 2410 2411static void 2412vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter) 2413{ 2414 BUG_ON(!adapter->pdev); 2415 2416 iounmap(adapter->hw_addr0); 2417 iounmap(adapter->hw_addr1); 2418 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1); 2419 pci_disable_device(adapter->pdev); 2420} 2421 2422 2423static void 2424vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter) 2425{ 2426 size_t sz, i, ring0_size, ring1_size, comp_size; 2427 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0]; 2428 2429 2430 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE - 2431 VMXNET3_MAX_ETH_HDR_SIZE) { 2432 adapter->skb_buf_size = adapter->netdev->mtu + 2433 VMXNET3_MAX_ETH_HDR_SIZE; 2434 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE) 2435 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE; 2436 2437 adapter->rx_buf_per_pkt = 1; 2438 } else { 2439 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE; 2440 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE + 2441 VMXNET3_MAX_ETH_HDR_SIZE; 2442 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE; 2443 } 2444 2445 /* 2446 * for simplicity, force the ring0 size to be a multiple of 2447 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN 2448 */ 2449 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN; 2450 ring0_size = adapter->rx_queue[0].rx_ring[0].size; 2451 ring0_size = (ring0_size + sz - 1) / sz * sz; 2452 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE / 2453 sz * sz); 2454 ring1_size = adapter->rx_queue[0].rx_ring[1].size; 2455 comp_size = ring0_size + ring1_size; 2456 2457 for (i = 0; i < adapter->num_rx_queues; i++) { 2458 rq = &adapter->rx_queue[i]; 2459 rq->rx_ring[0].size = ring0_size; 2460 rq->rx_ring[1].size = ring1_size; 2461 rq->comp_ring.size = comp_size; 2462 } 2463} 2464 2465 2466int 2467vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size, 2468 u32 rx_ring_size, u32 rx_ring2_size) 2469{ 2470 int err = 0, i; 2471 2472 for (i = 0; i < adapter->num_tx_queues; i++) { 2473 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2474 tq->tx_ring.size = tx_ring_size; 2475 tq->data_ring.size = tx_ring_size; 2476 tq->comp_ring.size = tx_ring_size; 2477 tq->shared = &adapter->tqd_start[i].ctrl; 2478 tq->stopped = true; 2479 tq->adapter = adapter; 2480 tq->qid = i; 2481 err = vmxnet3_tq_create(tq, adapter); 2482 /* 2483 * Too late to change num_tx_queues. We cannot do away with 2484 * lesser number of queues than what we asked for 2485 */ 2486 if (err) 2487 goto queue_err; 2488 } 2489 2490 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size; 2491 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size; 2492 vmxnet3_adjust_rx_ring_size(adapter); 2493 for (i = 0; i < adapter->num_rx_queues; i++) { 2494 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2495 /* qid and qid2 for rx queues will be assigned later when num 2496 * of rx queues is finalized after allocating intrs */ 2497 rq->shared = &adapter->rqd_start[i].ctrl; 2498 rq->adapter = adapter; 2499 err = vmxnet3_rq_create(rq, adapter); 2500 if (err) { 2501 if (i == 0) { 2502 printk(KERN_ERR "Could not allocate any rx" 2503 "queues. Aborting.\n"); 2504 goto queue_err; 2505 } else { 2506 printk(KERN_INFO "Number of rx queues changed " 2507 "to : %d.\n", i); 2508 adapter->num_rx_queues = i; 2509 err = 0; 2510 break; 2511 } 2512 } 2513 } 2514 return err; 2515queue_err: 2516 vmxnet3_tq_destroy_all(adapter); 2517 return err; 2518} 2519 2520static int 2521vmxnet3_open(struct net_device *netdev) 2522{ 2523 struct vmxnet3_adapter *adapter; 2524 int err, i; 2525 2526 adapter = netdev_priv(netdev); 2527 2528 for (i = 0; i < adapter->num_tx_queues; i++) 2529 spin_lock_init(&adapter->tx_queue[i].tx_lock); 2530 2531 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE, 2532 VMXNET3_DEF_RX_RING_SIZE, 2533 VMXNET3_DEF_RX_RING_SIZE); 2534 if (err) 2535 goto queue_err; 2536 2537 err = vmxnet3_activate_dev(adapter); 2538 if (err) 2539 goto activate_err; 2540 2541 return 0; 2542 2543activate_err: 2544 vmxnet3_rq_destroy_all(adapter); 2545 vmxnet3_tq_destroy_all(adapter); 2546queue_err: 2547 return err; 2548} 2549 2550 2551static int 2552vmxnet3_close(struct net_device *netdev) 2553{ 2554 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2555 2556 /* 2557 * Reset_work may be in the middle of resetting the device, wait for its 2558 * completion. 2559 */ 2560 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2561 msleep(1); 2562 2563 vmxnet3_quiesce_dev(adapter); 2564 2565 vmxnet3_rq_destroy_all(adapter); 2566 vmxnet3_tq_destroy_all(adapter); 2567 2568 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2569 2570 2571 return 0; 2572} 2573 2574 2575void 2576vmxnet3_force_close(struct vmxnet3_adapter *adapter) 2577{ 2578 int i; 2579 2580 /* 2581 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise 2582 * vmxnet3_close() will deadlock. 2583 */ 2584 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)); 2585 2586 /* we need to enable NAPI, otherwise dev_close will deadlock */ 2587 for (i = 0; i < adapter->num_rx_queues; i++) 2588 napi_enable(&adapter->rx_queue[i].napi); 2589 dev_close(adapter->netdev); 2590} 2591 2592 2593static int 2594vmxnet3_change_mtu(struct net_device *netdev, int new_mtu) 2595{ 2596 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2597 int err = 0; 2598 2599 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU) 2600 return -EINVAL; 2601 2602 netdev->mtu = new_mtu; 2603 2604 /* 2605 * Reset_work may be in the middle of resetting the device, wait for its 2606 * completion. 2607 */ 2608 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2609 msleep(1); 2610 2611 if (netif_running(netdev)) { 2612 vmxnet3_quiesce_dev(adapter); 2613 vmxnet3_reset_dev(adapter); 2614 2615 /* we need to re-create the rx queue based on the new mtu */ 2616 vmxnet3_rq_destroy_all(adapter); 2617 vmxnet3_adjust_rx_ring_size(adapter); 2618 err = vmxnet3_rq_create_all(adapter); 2619 if (err) { 2620 printk(KERN_ERR "%s: failed to re-create rx queues," 2621 " error %d. Closing it.\n", netdev->name, err); 2622 goto out; 2623 } 2624 2625 err = vmxnet3_activate_dev(adapter); 2626 if (err) { 2627 printk(KERN_ERR "%s: failed to re-activate, error %d. " 2628 "Closing it\n", netdev->name, err); 2629 goto out; 2630 } 2631 } 2632 2633out: 2634 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2635 if (err) 2636 vmxnet3_force_close(adapter); 2637 2638 return err; 2639} 2640 2641 2642static void 2643vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64) 2644{ 2645 struct net_device *netdev = adapter->netdev; 2646 2647 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 2648 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_TX | 2649 NETIF_F_HW_VLAN_RX | NETIF_F_TSO | NETIF_F_TSO6 | 2650 NETIF_F_LRO; 2651 if (dma64) 2652 netdev->hw_features |= NETIF_F_HIGHDMA; 2653 netdev->vlan_features = netdev->hw_features & 2654 ~(NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); 2655 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_FILTER; 2656 2657 netdev_info(adapter->netdev, 2658 "features: sg csum vlan jf tso tsoIPv6 lro%s\n", 2659 dma64 ? " highDMA" : ""); 2660} 2661 2662 2663static void 2664vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2665{ 2666 u32 tmp; 2667 2668 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL); 2669 *(u32 *)mac = tmp; 2670 2671 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH); 2672 mac[4] = tmp & 0xff; 2673 mac[5] = (tmp >> 8) & 0xff; 2674} 2675 2676#ifdef CONFIG_PCI_MSI 2677 2678/* 2679 * Enable MSIx vectors. 2680 * Returns : 2681 * 0 on successful enabling of required vectors, 2682 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required 2683 * could be enabled. 2684 * number of vectors which can be enabled otherwise (this number is smaller 2685 * than VMXNET3_LINUX_MIN_MSIX_VECT) 2686 */ 2687 2688static int 2689vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, 2690 int vectors) 2691{ 2692 int err = 0, vector_threshold; 2693 vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT; 2694 2695 while (vectors >= vector_threshold) { 2696 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries, 2697 vectors); 2698 if (!err) { 2699 adapter->intr.num_intrs = vectors; 2700 return 0; 2701 } else if (err < 0) { 2702 netdev_err(adapter->netdev, 2703 "Failed to enable MSI-X, error: %d\n", err); 2704 vectors = 0; 2705 } else if (err < vector_threshold) { 2706 break; 2707 } else { 2708 /* If fails to enable required number of MSI-x vectors 2709 * try enabling minimum number of vectors required. 2710 */ 2711 netdev_err(adapter->netdev, 2712 "Failed to enable %d MSI-X, trying %d instead\n", 2713 vectors, vector_threshold); 2714 vectors = vector_threshold; 2715 } 2716 } 2717 2718 netdev_info(adapter->netdev, 2719 "Number of MSI-X interrupts which can be allocated are lower than min threshold required.\n"); 2720 return err; 2721} 2722 2723 2724#endif /* CONFIG_PCI_MSI */ 2725 2726static void 2727vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter) 2728{ 2729 u32 cfg; 2730 unsigned long flags; 2731 2732 /* intr settings */ 2733 spin_lock_irqsave(&adapter->cmd_lock, flags); 2734 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2735 VMXNET3_CMD_GET_CONF_INTR); 2736 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2737 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2738 adapter->intr.type = cfg & 0x3; 2739 adapter->intr.mask_mode = (cfg >> 2) & 0x3; 2740 2741 if (adapter->intr.type == VMXNET3_IT_AUTO) { 2742 adapter->intr.type = VMXNET3_IT_MSIX; 2743 } 2744 2745#ifdef CONFIG_PCI_MSI 2746 if (adapter->intr.type == VMXNET3_IT_MSIX) { 2747 int vector, err = 0; 2748 2749 adapter->intr.num_intrs = (adapter->share_intr == 2750 VMXNET3_INTR_TXSHARE) ? 1 : 2751 adapter->num_tx_queues; 2752 adapter->intr.num_intrs += (adapter->share_intr == 2753 VMXNET3_INTR_BUDDYSHARE) ? 0 : 2754 adapter->num_rx_queues; 2755 adapter->intr.num_intrs += 1; /* for link event */ 2756 2757 adapter->intr.num_intrs = (adapter->intr.num_intrs > 2758 VMXNET3_LINUX_MIN_MSIX_VECT 2759 ? adapter->intr.num_intrs : 2760 VMXNET3_LINUX_MIN_MSIX_VECT); 2761 2762 for (vector = 0; vector < adapter->intr.num_intrs; vector++) 2763 adapter->intr.msix_entries[vector].entry = vector; 2764 2765 err = vmxnet3_acquire_msix_vectors(adapter, 2766 adapter->intr.num_intrs); 2767 /* If we cannot allocate one MSIx vector per queue 2768 * then limit the number of rx queues to 1 2769 */ 2770 if (err == VMXNET3_LINUX_MIN_MSIX_VECT) { 2771 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE 2772 || adapter->num_rx_queues != 1) { 2773 adapter->share_intr = VMXNET3_INTR_TXSHARE; 2774 printk(KERN_ERR "Number of rx queues : 1\n"); 2775 adapter->num_rx_queues = 1; 2776 adapter->intr.num_intrs = 2777 VMXNET3_LINUX_MIN_MSIX_VECT; 2778 } 2779 return; 2780 } 2781 if (!err) 2782 return; 2783 2784 /* If we cannot allocate MSIx vectors use only one rx queue */ 2785 netdev_info(adapter->netdev, 2786 "Failed to enable MSI-X, error %d . Limiting #rx queues to 1, try MSI.\n", 2787 err); 2788 2789 adapter->intr.type = VMXNET3_IT_MSI; 2790 } 2791 2792 if (adapter->intr.type == VMXNET3_IT_MSI) { 2793 int err; 2794 err = pci_enable_msi(adapter->pdev); 2795 if (!err) { 2796 adapter->num_rx_queues = 1; 2797 adapter->intr.num_intrs = 1; 2798 return; 2799 } 2800 } 2801#endif /* CONFIG_PCI_MSI */ 2802 2803 adapter->num_rx_queues = 1; 2804 printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n"); 2805 adapter->intr.type = VMXNET3_IT_INTX; 2806 2807 /* INT-X related setting */ 2808 adapter->intr.num_intrs = 1; 2809} 2810 2811 2812static void 2813vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter) 2814{ 2815 if (adapter->intr.type == VMXNET3_IT_MSIX) 2816 pci_disable_msix(adapter->pdev); 2817 else if (adapter->intr.type == VMXNET3_IT_MSI) 2818 pci_disable_msi(adapter->pdev); 2819 else 2820 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); 2821} 2822 2823 2824static void 2825vmxnet3_tx_timeout(struct net_device *netdev) 2826{ 2827 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2828 adapter->tx_timeout_count++; 2829 2830 printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name); 2831 schedule_work(&adapter->work); 2832 netif_wake_queue(adapter->netdev); 2833} 2834 2835 2836static void 2837vmxnet3_reset_work(struct work_struct *data) 2838{ 2839 struct vmxnet3_adapter *adapter; 2840 2841 adapter = container_of(data, struct vmxnet3_adapter, work); 2842 2843 /* if another thread is resetting the device, no need to proceed */ 2844 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2845 return; 2846 2847 /* if the device is closed, we must leave it alone */ 2848 rtnl_lock(); 2849 if (netif_running(adapter->netdev)) { 2850 printk(KERN_INFO "%s: resetting\n", adapter->netdev->name); 2851 vmxnet3_quiesce_dev(adapter); 2852 vmxnet3_reset_dev(adapter); 2853 vmxnet3_activate_dev(adapter); 2854 } else { 2855 printk(KERN_INFO "%s: already closed\n", adapter->netdev->name); 2856 } 2857 rtnl_unlock(); 2858 2859 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2860} 2861 2862 2863static int __devinit 2864vmxnet3_probe_device(struct pci_dev *pdev, 2865 const struct pci_device_id *id) 2866{ 2867 static const struct net_device_ops vmxnet3_netdev_ops = { 2868 .ndo_open = vmxnet3_open, 2869 .ndo_stop = vmxnet3_close, 2870 .ndo_start_xmit = vmxnet3_xmit_frame, 2871 .ndo_set_mac_address = vmxnet3_set_mac_addr, 2872 .ndo_change_mtu = vmxnet3_change_mtu, 2873 .ndo_set_features = vmxnet3_set_features, 2874 .ndo_get_stats64 = vmxnet3_get_stats64, 2875 .ndo_tx_timeout = vmxnet3_tx_timeout, 2876 .ndo_set_rx_mode = vmxnet3_set_mc, 2877 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid, 2878 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid, 2879#ifdef CONFIG_NET_POLL_CONTROLLER 2880 .ndo_poll_controller = vmxnet3_netpoll, 2881#endif 2882 }; 2883 int err; 2884 bool dma64 = false; /* stupid gcc */ 2885 u32 ver; 2886 struct net_device *netdev; 2887 struct vmxnet3_adapter *adapter; 2888 u8 mac[ETH_ALEN]; 2889 int size; 2890 int num_tx_queues; 2891 int num_rx_queues; 2892 2893 if (!pci_msi_enabled()) 2894 enable_mq = 0; 2895 2896#ifdef VMXNET3_RSS 2897 if (enable_mq) 2898 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 2899 (int)num_online_cpus()); 2900 else 2901#endif 2902 num_rx_queues = 1; 2903 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 2904 2905 if (enable_mq) 2906 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES, 2907 (int)num_online_cpus()); 2908 else 2909 num_tx_queues = 1; 2910 2911 num_tx_queues = rounddown_pow_of_two(num_tx_queues); 2912 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter), 2913 max(num_tx_queues, num_rx_queues)); 2914 printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n", 2915 num_tx_queues, num_rx_queues); 2916 2917 if (!netdev) 2918 return -ENOMEM; 2919 2920 pci_set_drvdata(pdev, netdev); 2921 adapter = netdev_priv(netdev); 2922 adapter->netdev = netdev; 2923 adapter->pdev = pdev; 2924 2925 spin_lock_init(&adapter->cmd_lock); 2926 adapter->shared = pci_alloc_consistent(adapter->pdev, 2927 sizeof(struct Vmxnet3_DriverShared), 2928 &adapter->shared_pa); 2929 if (!adapter->shared) { 2930 printk(KERN_ERR "Failed to allocate memory for %s\n", 2931 pci_name(pdev)); 2932 err = -ENOMEM; 2933 goto err_alloc_shared; 2934 } 2935 2936 adapter->num_rx_queues = num_rx_queues; 2937 adapter->num_tx_queues = num_tx_queues; 2938 2939 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 2940 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues; 2941 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size, 2942 &adapter->queue_desc_pa); 2943 2944 if (!adapter->tqd_start) { 2945 printk(KERN_ERR "Failed to allocate memory for %s\n", 2946 pci_name(pdev)); 2947 err = -ENOMEM; 2948 goto err_alloc_queue_desc; 2949 } 2950 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start + 2951 adapter->num_tx_queues); 2952 2953 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL); 2954 if (adapter->pm_conf == NULL) { 2955 err = -ENOMEM; 2956 goto err_alloc_pm; 2957 } 2958 2959#ifdef VMXNET3_RSS 2960 2961 adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL); 2962 if (adapter->rss_conf == NULL) { 2963 err = -ENOMEM; 2964 goto err_alloc_rss; 2965 } 2966#endif /* VMXNET3_RSS */ 2967 2968 err = vmxnet3_alloc_pci_resources(adapter, &dma64); 2969 if (err < 0) 2970 goto err_alloc_pci; 2971 2972 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS); 2973 if (ver & 1) { 2974 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1); 2975 } else { 2976 printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter" 2977 " %s\n", ver, pci_name(pdev)); 2978 err = -EBUSY; 2979 goto err_ver; 2980 } 2981 2982 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS); 2983 if (ver & 1) { 2984 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1); 2985 } else { 2986 printk(KERN_ERR "Incompatible upt version (0x%x) for " 2987 "adapter %s\n", ver, pci_name(pdev)); 2988 err = -EBUSY; 2989 goto err_ver; 2990 } 2991 2992 SET_NETDEV_DEV(netdev, &pdev->dev); 2993 vmxnet3_declare_features(adapter, dma64); 2994 2995 adapter->dev_number = atomic_read(&devices_found); 2996 2997 adapter->share_intr = irq_share_mode; 2998 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE && 2999 adapter->num_tx_queues != adapter->num_rx_queues) 3000 adapter->share_intr = VMXNET3_INTR_DONTSHARE; 3001 3002 vmxnet3_alloc_intr_resources(adapter); 3003 3004#ifdef VMXNET3_RSS 3005 if (adapter->num_rx_queues > 1 && 3006 adapter->intr.type == VMXNET3_IT_MSIX) { 3007 adapter->rss = true; 3008 printk(KERN_INFO "RSS is enabled.\n"); 3009 } else { 3010 adapter->rss = false; 3011 } 3012#endif 3013 3014 vmxnet3_read_mac_addr(adapter, mac); 3015 memcpy(netdev->dev_addr, mac, netdev->addr_len); 3016 3017 netdev->netdev_ops = &vmxnet3_netdev_ops; 3018 vmxnet3_set_ethtool_ops(netdev); 3019 netdev->watchdog_timeo = 5 * HZ; 3020 3021 INIT_WORK(&adapter->work, vmxnet3_reset_work); 3022 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3023 3024 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3025 int i; 3026 for (i = 0; i < adapter->num_rx_queues; i++) { 3027 netif_napi_add(adapter->netdev, 3028 &adapter->rx_queue[i].napi, 3029 vmxnet3_poll_rx_only, 64); 3030 } 3031 } else { 3032 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi, 3033 vmxnet3_poll, 64); 3034 } 3035 3036 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 3037 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues); 3038 3039 err = register_netdev(netdev); 3040 3041 if (err) { 3042 printk(KERN_ERR "Failed to register adapter %s\n", 3043 pci_name(pdev)); 3044 goto err_register; 3045 } 3046 3047 vmxnet3_check_link(adapter, false); 3048 atomic_inc(&devices_found); 3049 return 0; 3050 3051err_register: 3052 vmxnet3_free_intr_resources(adapter); 3053err_ver: 3054 vmxnet3_free_pci_resources(adapter); 3055err_alloc_pci: 3056#ifdef VMXNET3_RSS 3057 kfree(adapter->rss_conf); 3058err_alloc_rss: 3059#endif 3060 kfree(adapter->pm_conf); 3061err_alloc_pm: 3062 pci_free_consistent(adapter->pdev, size, adapter->tqd_start, 3063 adapter->queue_desc_pa); 3064err_alloc_queue_desc: 3065 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared), 3066 adapter->shared, adapter->shared_pa); 3067err_alloc_shared: 3068 pci_set_drvdata(pdev, NULL); 3069 free_netdev(netdev); 3070 return err; 3071} 3072 3073 3074static void __devexit 3075vmxnet3_remove_device(struct pci_dev *pdev) 3076{ 3077 struct net_device *netdev = pci_get_drvdata(pdev); 3078 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3079 int size = 0; 3080 int num_rx_queues; 3081 3082#ifdef VMXNET3_RSS 3083 if (enable_mq) 3084 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3085 (int)num_online_cpus()); 3086 else 3087#endif 3088 num_rx_queues = 1; 3089 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3090 3091 cancel_work_sync(&adapter->work); 3092 3093 unregister_netdev(netdev); 3094 3095 vmxnet3_free_intr_resources(adapter); 3096 vmxnet3_free_pci_resources(adapter); 3097#ifdef VMXNET3_RSS 3098 kfree(adapter->rss_conf); 3099#endif 3100 kfree(adapter->pm_conf); 3101 3102 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3103 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues; 3104 pci_free_consistent(adapter->pdev, size, adapter->tqd_start, 3105 adapter->queue_desc_pa); 3106 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared), 3107 adapter->shared, adapter->shared_pa); 3108 free_netdev(netdev); 3109} 3110 3111 3112#ifdef CONFIG_PM 3113 3114static int 3115vmxnet3_suspend(struct device *device) 3116{ 3117 struct pci_dev *pdev = to_pci_dev(device); 3118 struct net_device *netdev = pci_get_drvdata(pdev); 3119 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3120 struct Vmxnet3_PMConf *pmConf; 3121 struct ethhdr *ehdr; 3122 struct arphdr *ahdr; 3123 u8 *arpreq; 3124 struct in_device *in_dev; 3125 struct in_ifaddr *ifa; 3126 unsigned long flags; 3127 int i = 0; 3128 3129 if (!netif_running(netdev)) 3130 return 0; 3131 3132 for (i = 0; i < adapter->num_rx_queues; i++) 3133 napi_disable(&adapter->rx_queue[i].napi); 3134 3135 vmxnet3_disable_all_intrs(adapter); 3136 vmxnet3_free_irqs(adapter); 3137 vmxnet3_free_intr_resources(adapter); 3138 3139 netif_device_detach(netdev); 3140 netif_tx_stop_all_queues(netdev); 3141 3142 /* Create wake-up filters. */ 3143 pmConf = adapter->pm_conf; 3144 memset(pmConf, 0, sizeof(*pmConf)); 3145 3146 if (adapter->wol & WAKE_UCAST) { 3147 pmConf->filters[i].patternSize = ETH_ALEN; 3148 pmConf->filters[i].maskSize = 1; 3149 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN); 3150 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ 3151 3152 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3153 i++; 3154 } 3155 3156 if (adapter->wol & WAKE_ARP) { 3157 in_dev = in_dev_get(netdev); 3158 if (!in_dev) 3159 goto skip_arp; 3160 3161 ifa = (struct in_ifaddr *)in_dev->ifa_list; 3162 if (!ifa) 3163 goto skip_arp; 3164 3165 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/ 3166 sizeof(struct arphdr) + /* ARP header */ 3167 2 * ETH_ALEN + /* 2 Ethernet addresses*/ 3168 2 * sizeof(u32); /*2 IPv4 addresses */ 3169 pmConf->filters[i].maskSize = 3170 (pmConf->filters[i].patternSize - 1) / 8 + 1; 3171 3172 /* ETH_P_ARP in Ethernet header. */ 3173 ehdr = (struct ethhdr *)pmConf->filters[i].pattern; 3174 ehdr->h_proto = htons(ETH_P_ARP); 3175 3176 /* ARPOP_REQUEST in ARP header. */ 3177 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN]; 3178 ahdr->ar_op = htons(ARPOP_REQUEST); 3179 arpreq = (u8 *)(ahdr + 1); 3180 3181 /* The Unicast IPv4 address in 'tip' field. */ 3182 arpreq += 2 * ETH_ALEN + sizeof(u32); 3183 *(u32 *)arpreq = ifa->ifa_address; 3184 3185 /* The mask for the relevant bits. */ 3186 pmConf->filters[i].mask[0] = 0x00; 3187 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ 3188 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ 3189 pmConf->filters[i].mask[3] = 0x00; 3190 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ 3191 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ 3192 in_dev_put(in_dev); 3193 3194 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3195 i++; 3196 } 3197 3198skip_arp: 3199 if (adapter->wol & WAKE_MAGIC) 3200 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC; 3201 3202 pmConf->numFilters = i; 3203 3204 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3205 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3206 *pmConf)); 3207 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys( 3208 pmConf)); 3209 3210 spin_lock_irqsave(&adapter->cmd_lock, flags); 3211 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3212 VMXNET3_CMD_UPDATE_PMCFG); 3213 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3214 3215 pci_save_state(pdev); 3216 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND), 3217 adapter->wol); 3218 pci_disable_device(pdev); 3219 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND)); 3220 3221 return 0; 3222} 3223 3224 3225static int 3226vmxnet3_resume(struct device *device) 3227{ 3228 int err, i = 0; 3229 unsigned long flags; 3230 struct pci_dev *pdev = to_pci_dev(device); 3231 struct net_device *netdev = pci_get_drvdata(pdev); 3232 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3233 struct Vmxnet3_PMConf *pmConf; 3234 3235 if (!netif_running(netdev)) 3236 return 0; 3237 3238 /* Destroy wake-up filters. */ 3239 pmConf = adapter->pm_conf; 3240 memset(pmConf, 0, sizeof(*pmConf)); 3241 3242 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3243 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3244 *pmConf)); 3245 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys( 3246 pmConf)); 3247 3248 netif_device_attach(netdev); 3249 pci_set_power_state(pdev, PCI_D0); 3250 pci_restore_state(pdev); 3251 err = pci_enable_device_mem(pdev); 3252 if (err != 0) 3253 return err; 3254 3255 pci_enable_wake(pdev, PCI_D0, 0); 3256 3257 spin_lock_irqsave(&adapter->cmd_lock, flags); 3258 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3259 VMXNET3_CMD_UPDATE_PMCFG); 3260 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3261 vmxnet3_alloc_intr_resources(adapter); 3262 vmxnet3_request_irqs(adapter); 3263 for (i = 0; i < adapter->num_rx_queues; i++) 3264 napi_enable(&adapter->rx_queue[i].napi); 3265 vmxnet3_enable_all_intrs(adapter); 3266 3267 return 0; 3268} 3269 3270static const struct dev_pm_ops vmxnet3_pm_ops = { 3271 .suspend = vmxnet3_suspend, 3272 .resume = vmxnet3_resume, 3273}; 3274#endif 3275 3276static struct pci_driver vmxnet3_driver = { 3277 .name = vmxnet3_driver_name, 3278 .id_table = vmxnet3_pciid_table, 3279 .probe = vmxnet3_probe_device, 3280 .remove = __devexit_p(vmxnet3_remove_device), 3281#ifdef CONFIG_PM 3282 .driver.pm = &vmxnet3_pm_ops, 3283#endif 3284}; 3285 3286 3287static int __init 3288vmxnet3_init_module(void) 3289{ 3290 printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC, 3291 VMXNET3_DRIVER_VERSION_REPORT); 3292 return pci_register_driver(&vmxnet3_driver); 3293} 3294 3295module_init(vmxnet3_init_module); 3296 3297 3298static void 3299vmxnet3_exit_module(void) 3300{ 3301 pci_unregister_driver(&vmxnet3_driver); 3302} 3303 3304module_exit(vmxnet3_exit_module); 3305 3306MODULE_AUTHOR("VMware, Inc."); 3307MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC); 3308MODULE_LICENSE("GPL v2"); 3309MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING); 3310