hd64572.c revision 09fd65aa8ac934ea4ce7e55945a687292731e9c9
1/* 2 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux 3 * 4 * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * Source of information: HD64572 SCA-II User's Manual 11 * 12 * We use the following SCA memory map: 13 * 14 * Packet buffer descriptor rings - starting from winbase or win0base: 15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring 16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring 17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used) 18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used) 19 * 20 * Packet data buffers - starting from winbase + buff_offset: 21 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers 22 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers 23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used) 24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used) 25 */ 26 27#include <linux/bitops.h> 28#include <linux/errno.h> 29#include <linux/fcntl.h> 30#include <linux/hdlc.h> 31#include <linux/in.h> 32#include <linux/init.h> 33#include <linux/interrupt.h> 34#include <linux/ioport.h> 35#include <linux/jiffies.h> 36#include <linux/kernel.h> 37#include <linux/module.h> 38#include <linux/netdevice.h> 39#include <linux/skbuff.h> 40#include <linux/slab.h> 41#include <linux/string.h> 42#include <linux/types.h> 43#include <asm/io.h> 44#include <asm/system.h> 45#include <asm/uaccess.h> 46#include "hd64572.h" 47 48#define NAPI_WEIGHT 16 49 50#define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) 51#define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET) 52#define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET) 53 54#define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01) 55#define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02) 56#define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04) 57 58static int sca_poll(struct napi_struct *napi, int budget); 59 60static inline struct net_device *port_to_dev(port_t *port) 61{ 62 return port->dev; 63} 64 65static inline int sca_intr_status(card_t *card) 66{ 67 u8 result = 0; 68 u32 isr0 = sca_inl(ISR0, card); 69 70 if (isr0 & 0x0000000F) result |= SCA_INTR_DMAC_RX(0); 71 if (isr0 & 0x000000F0) result |= SCA_INTR_DMAC_TX(0); 72 if (isr0 & 0x00000F00) result |= SCA_INTR_DMAC_RX(1); 73 if (isr0 & 0x0000F000) result |= SCA_INTR_DMAC_TX(1); 74 if (isr0 & 0x003E0000) result |= SCA_INTR_MSCI(0); 75 if (isr0 & 0x3E000000) result |= SCA_INTR_MSCI(1); 76 77 if (!(result & SCA_INTR_DMAC_TX(0))) 78 if (sca_in(DSR_TX(0), card) & DSR_EOM) 79 result |= SCA_INTR_DMAC_TX(0); 80 if (!(result & SCA_INTR_DMAC_TX(1))) 81 if (sca_in(DSR_TX(1), card) & DSR_EOM) 82 result |= SCA_INTR_DMAC_TX(1); 83 84 return result; 85} 86 87static inline port_t* dev_to_port(struct net_device *dev) 88{ 89 return dev_to_hdlc(dev)->priv; 90} 91 92static inline void enable_intr(port_t *port) 93{ 94 /* DMA & MSCI IRQ enable */ 95 /* IR0_TXINT | IR0_RXINTA | IR0_DMIB* | IR0_DMIA* */ 96 sca_outl(sca_inl(IER0, port->card) | 97 (phy_node(port) ? 0x0A006600 : 0x000A0066), IER0, port->card); 98} 99 100static inline void disable_intr(port_t *port) 101{ 102 sca_outl(sca_inl(IER0, port->card) & 103 (phy_node(port) ? 0x00FF00FF : 0xFF00FF00), IER0, port->card); 104} 105 106static inline u16 next_desc(port_t *port, u16 desc, int transmit) 107{ 108 return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers 109 : port_to_card(port)->rx_ring_buffers); 110} 111 112 113static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit) 114{ 115 u16 rx_buffs = port_to_card(port)->rx_ring_buffers; 116 u16 tx_buffs = port_to_card(port)->tx_ring_buffers; 117 118 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc. 119 return log_node(port) * (rx_buffs + tx_buffs) + 120 transmit * rx_buffs + desc; 121} 122 123 124static inline u16 desc_offset(port_t *port, u16 desc, int transmit) 125{ 126 /* Descriptor offset always fits in 16 bytes */ 127 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc); 128} 129 130 131static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, 132 int transmit) 133{ 134 return (pkt_desc __iomem *)(winbase(port_to_card(port)) 135 + desc_offset(port, desc, transmit)); 136} 137 138 139static inline u32 buffer_offset(port_t *port, u16 desc, int transmit) 140{ 141 return port_to_card(port)->buff_offset + 142 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU; 143} 144 145 146static inline void sca_set_carrier(port_t *port) 147{ 148 if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) { 149#ifdef DEBUG_LINK 150 printk(KERN_DEBUG "%s: sca_set_carrier on\n", 151 port_to_dev(port)->name); 152#endif 153 netif_carrier_on(port_to_dev(port)); 154 } else { 155#ifdef DEBUG_LINK 156 printk(KERN_DEBUG "%s: sca_set_carrier off\n", 157 port_to_dev(port)->name); 158#endif 159 netif_carrier_off(port_to_dev(port)); 160 } 161} 162 163 164static void sca_init_port(port_t *port) 165{ 166 card_t *card = port_to_card(port); 167 int transmit, i; 168 169 port->rxin = 0; 170 port->txin = 0; 171 port->txlast = 0; 172 173 for (transmit = 0; transmit < 2; transmit++) { 174 u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port); 175 u16 buffs = transmit ? card->tx_ring_buffers 176 : card->rx_ring_buffers; 177 178 for (i = 0; i < buffs; i++) { 179 pkt_desc __iomem *desc = desc_address(port, i, transmit); 180 u16 chain_off = desc_offset(port, i + 1, transmit); 181 u32 buff_off = buffer_offset(port, i, transmit); 182 183 writel(chain_off, &desc->cp); 184 writel(buff_off, &desc->bp); 185 writew(0, &desc->len); 186 writeb(0, &desc->stat); 187 } 188 189 /* DMA disable - to halt state */ 190 sca_out(0, transmit ? DSR_TX(phy_node(port)) : 191 DSR_RX(phy_node(port)), card); 192 /* software ABORT - to initial state */ 193 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) : 194 DCR_RX(phy_node(port)), card); 195 196 /* current desc addr */ 197 sca_outl(desc_offset(port, 0, transmit), dmac + CDAL, card); 198 if (!transmit) 199 sca_outl(desc_offset(port, buffs - 1, transmit), 200 dmac + EDAL, card); 201 else 202 sca_outl(desc_offset(port, 0, transmit), dmac + EDAL, 203 card); 204 205 /* clear frame end interrupt counter */ 206 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) : 207 DCR_RX(phy_node(port)), card); 208 209 if (!transmit) { /* Receive */ 210 /* set buffer length */ 211 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card); 212 /* Chain mode, Multi-frame */ 213 sca_out(0x14, DMR_RX(phy_node(port)), card); 214 sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)), 215 card); 216 /* DMA enable */ 217 sca_out(DSR_DE, DSR_RX(phy_node(port)), card); 218 } else { /* Transmit */ 219 /* Chain mode, Multi-frame */ 220 sca_out(0x14, DMR_TX(phy_node(port)), card); 221 /* enable underflow interrupts */ 222 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card); 223 } 224 } 225 sca_set_carrier(port); 226 netif_napi_add(port_to_dev(port), &port->napi, sca_poll, NAPI_WEIGHT); 227} 228 229 230/* MSCI interrupt service */ 231static inline void sca_msci_intr(port_t *port) 232{ 233 u16 msci = get_msci(port); 234 card_t* card = port_to_card(port); 235 u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */ 236 237 /* Reset MSCI TX underrun and CDCD status bit */ 238 sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card); 239 240 if (stat & ST1_UDRN) { 241 /* TX Underrun error detected */ 242 port_to_dev(port)->stats.tx_errors++; 243 port_to_dev(port)->stats.tx_fifo_errors++; 244 } 245 246 if (stat & ST1_CDCD) 247 sca_set_carrier(port); 248} 249 250 251static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, 252 u16 rxin) 253{ 254 struct net_device *dev = port_to_dev(port); 255 struct sk_buff *skb; 256 u16 len; 257 u32 buff; 258 259 len = readw(&desc->len); 260 skb = dev_alloc_skb(len); 261 if (!skb) { 262 dev->stats.rx_dropped++; 263 return; 264 } 265 266 buff = buffer_offset(port, rxin, 0); 267 memcpy_fromio(skb->data, winbase(card) + buff, len); 268 269 skb_put(skb, len); 270#ifdef DEBUG_PKT 271 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len); 272 debug_frame(skb); 273#endif 274 dev->stats.rx_packets++; 275 dev->stats.rx_bytes += skb->len; 276 skb->protocol = hdlc_type_trans(skb, dev); 277 netif_receive_skb(skb); 278} 279 280 281/* Receive DMA service */ 282static inline int sca_rx_done(port_t *port, int budget) 283{ 284 struct net_device *dev = port_to_dev(port); 285 u16 dmac = get_dmac_rx(port); 286 card_t *card = port_to_card(port); 287 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */ 288 int received = 0; 289 290 /* Reset DSR status bits */ 291 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 292 DSR_RX(phy_node(port)), card); 293 294 if (stat & DSR_BOF) 295 /* Dropped one or more frames */ 296 dev->stats.rx_over_errors++; 297 298 while (received < budget) { 299 u32 desc_off = desc_offset(port, port->rxin, 0); 300 pkt_desc __iomem *desc; 301 u32 cda = sca_inl(dmac + CDAL, card); 302 303 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) 304 break; /* No frame received */ 305 306 desc = desc_address(port, port->rxin, 0); 307 stat = readb(&desc->stat); 308 if (!(stat & ST_RX_EOM)) 309 port->rxpart = 1; /* partial frame received */ 310 else if ((stat & ST_ERROR_MASK) || port->rxpart) { 311 dev->stats.rx_errors++; 312 if (stat & ST_RX_OVERRUN) 313 dev->stats.rx_fifo_errors++; 314 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | 315 ST_RX_RESBIT)) || port->rxpart) 316 dev->stats.rx_frame_errors++; 317 else if (stat & ST_RX_CRC) 318 dev->stats.rx_crc_errors++; 319 if (stat & ST_RX_EOM) 320 port->rxpart = 0; /* received last fragment */ 321 } else { 322 sca_rx(card, port, desc, port->rxin); 323 received++; 324 } 325 326 /* Set new error descriptor address */ 327 sca_outl(desc_off, dmac + EDAL, card); 328 port->rxin = next_desc(port, port->rxin, 0); 329 } 330 331 /* make sure RX DMA is enabled */ 332 sca_out(DSR_DE, DSR_RX(phy_node(port)), card); 333 return received; 334} 335 336 337/* Transmit DMA service */ 338static inline void sca_tx_done(port_t *port) 339{ 340 struct net_device *dev = port_to_dev(port); 341 card_t* card = port_to_card(port); 342 u8 stat; 343 344 spin_lock(&port->lock); 345 346 stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */ 347 348 /* Reset DSR status bits */ 349 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 350 DSR_TX(phy_node(port)), card); 351 352 while (1) { 353 pkt_desc __iomem *desc = desc_address(port, port->txlast, 1); 354 355 if (!(readb(&desc->stat) & ST_TX_OWNRSHP)) 356 break; /* not yet transmitted */ 357 dev->stats.tx_packets++; 358 dev->stats.tx_bytes += readw(&desc->len); 359 writeb(0, &desc->stat); /* Free descriptor */ 360 port->txlast = next_desc(port, port->txlast, 1); 361 } 362 363 netif_wake_queue(dev); 364 spin_unlock(&port->lock); 365} 366 367 368static int sca_poll(struct napi_struct *napi, int budget) 369{ 370 port_t *port = container_of(napi, port_t, napi); 371 u8 stat = sca_intr_status(port->card); 372 int received = 0; 373 374 if (stat & SCA_INTR_MSCI(port->phy_node)) 375 sca_msci_intr(port); 376 377 if (stat & SCA_INTR_DMAC_TX(port->phy_node)) 378 sca_tx_done(port); 379 380 if (stat & SCA_INTR_DMAC_RX(port->phy_node)) 381 received = sca_rx_done(port, budget); 382 383 if (received < budget) { 384 netif_rx_complete(port->dev, napi); 385 enable_intr(port); 386 } 387 388 return received; 389} 390 391static irqreturn_t sca_intr(int irq, void* dev_id) 392{ 393 card_t *card = dev_id; 394 int i; 395 u8 stat = sca_intr_status(card); 396 int handled = 0; 397 398 for (i = 0; i < 2; i++) { 399 port_t *port = get_port(card, i); 400 if (port && (stat & (SCA_INTR_MSCI(i) | SCA_INTR_DMAC_RX(i) | 401 SCA_INTR_DMAC_TX(i)))) { 402 handled = 1; 403 disable_intr(port); 404 netif_rx_schedule(port->dev, &port->napi); 405 } 406 } 407 408 return IRQ_RETVAL(handled); 409} 410 411 412static void sca_set_port(port_t *port) 413{ 414 card_t* card = port_to_card(port); 415 u16 msci = get_msci(port); 416 u8 md2 = sca_in(msci + MD2, card); 417 unsigned int tmc, br = 10, brv = 1024; 418 419 420 if (port->settings.clock_rate > 0) { 421 /* Try lower br for better accuracy*/ 422 do { 423 br--; 424 brv >>= 1; /* brv = 2^9 = 512 max in specs */ 425 426 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ 427 tmc = CLOCK_BASE / brv / port->settings.clock_rate; 428 }while (br > 1 && tmc <= 128); 429 430 if (tmc < 1) { 431 tmc = 1; 432 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ 433 brv = 1; 434 } else if (tmc > 255) 435 tmc = 256; /* tmc=0 means 256 - low baud rates */ 436 437 port->settings.clock_rate = CLOCK_BASE / brv / tmc; 438 } else { 439 br = 9; /* Minimum clock rate */ 440 tmc = 256; /* 8bit = 0 */ 441 port->settings.clock_rate = CLOCK_BASE / (256 * 512); 442 } 443 444 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br; 445 port->txs = (port->txs & ~CLK_BRG_MASK) | br; 446 port->tmc = tmc; 447 448 /* baud divisor - time constant*/ 449 sca_out(port->tmc, msci + TMCR, card); 450 sca_out(port->tmc, msci + TMCT, card); 451 452 /* Set BRG bits */ 453 sca_out(port->rxs, msci + RXS, card); 454 sca_out(port->txs, msci + TXS, card); 455 456 if (port->settings.loopback) 457 md2 |= MD2_LOOPBACK; 458 else 459 md2 &= ~MD2_LOOPBACK; 460 461 sca_out(md2, msci + MD2, card); 462 463} 464 465 466static void sca_open(struct net_device *dev) 467{ 468 port_t *port = dev_to_port(dev); 469 card_t* card = port_to_card(port); 470 u16 msci = get_msci(port); 471 u8 md0, md2; 472 473 switch(port->encoding) { 474 case ENCODING_NRZ: md2 = MD2_NRZ; break; 475 case ENCODING_NRZI: md2 = MD2_NRZI; break; 476 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break; 477 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break; 478 default: md2 = MD2_MANCHESTER; 479 } 480 481 if (port->settings.loopback) 482 md2 |= MD2_LOOPBACK; 483 484 switch(port->parity) { 485 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break; 486 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break; 487 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break; 488 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break; 489 default: md0 = MD0_HDLC | MD0_CRC_NONE; 490 } 491 492 sca_out(CMD_RESET, msci + CMD, card); 493 sca_out(md0, msci + MD0, card); 494 sca_out(0x00, msci + MD1, card); /* no address field check */ 495 sca_out(md2, msci + MD2, card); 496 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */ 497 /* Skip the rest of underrun frame */ 498 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card); 499 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */ 500 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */ 501 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */ 502 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */ 503 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/ 504 505/* We're using the following interrupts: 506 - TXINT (DMAC completed all transmissions, underrun or DCD change) 507 - all DMA interrupts 508*/ 509 /* MSCI TXINT and RXINTA interrupt enable */ 510 sca_outl(IE0_TXINT | IE0_RXINTA | IE0_UDRN | IE0_CDCD, msci + IE0, 511 card); 512 513 sca_out(port->tmc, msci + TMCR, card); 514 sca_out(port->tmc, msci + TMCT, card); 515 sca_out(port->rxs, msci + RXS, card); 516 sca_out(port->txs, msci + TXS, card); 517 sca_out(CMD_TX_ENABLE, msci + CMD, card); 518 sca_out(CMD_RX_ENABLE, msci + CMD, card); 519 520 sca_set_carrier(port); 521 enable_intr(port); 522 napi_enable(&port->napi); 523 netif_start_queue(dev); 524} 525 526 527static void sca_close(struct net_device *dev) 528{ 529 port_t *port = dev_to_port(dev); 530 531 /* reset channel */ 532 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port)); 533 disable_intr(port); 534 napi_disable(&port->napi); 535 netif_stop_queue(dev); 536} 537 538 539static int sca_attach(struct net_device *dev, unsigned short encoding, 540 unsigned short parity) 541{ 542 if (encoding != ENCODING_NRZ && 543 encoding != ENCODING_NRZI && 544 encoding != ENCODING_FM_MARK && 545 encoding != ENCODING_FM_SPACE && 546 encoding != ENCODING_MANCHESTER) 547 return -EINVAL; 548 549 if (parity != PARITY_NONE && 550 parity != PARITY_CRC16_PR0 && 551 parity != PARITY_CRC16_PR1 && 552 parity != PARITY_CRC32_PR1_CCITT && 553 parity != PARITY_CRC16_PR1_CCITT) 554 return -EINVAL; 555 556 dev_to_port(dev)->encoding = encoding; 557 dev_to_port(dev)->parity = parity; 558 return 0; 559} 560 561 562#ifdef DEBUG_RINGS 563static void sca_dump_rings(struct net_device *dev) 564{ 565 port_t *port = dev_to_port(dev); 566 card_t *card = port_to_card(port); 567 u16 cnt; 568 569 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive", 570 sca_inl(get_dmac_rx(port) + CDAL, card), 571 sca_inl(get_dmac_rx(port) + EDAL, card), 572 sca_in(DSR_RX(phy_node(port)), card), port->rxin, 573 sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in"); 574 for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++) 575 printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat))); 576 577 printk("\n" KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u " 578 "last=%u %sactive", 579 sca_inl(get_dmac_tx(port) + CDAL, card), 580 sca_inl(get_dmac_tx(port) + EDAL, card), 581 sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast, 582 sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in"); 583 584 for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++) 585 printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat))); 586 printk("\n"); 587 588 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x," 589 " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n", 590 sca_in(get_msci(port) + MD0, card), 591 sca_in(get_msci(port) + MD1, card), 592 sca_in(get_msci(port) + MD2, card), 593 sca_in(get_msci(port) + ST0, card), 594 sca_in(get_msci(port) + ST1, card), 595 sca_in(get_msci(port) + ST2, card), 596 sca_in(get_msci(port) + ST3, card), 597 sca_in(get_msci(port) + ST4, card), 598 sca_in(get_msci(port) + FST, card), 599 sca_in(get_msci(port) + CST0, card), 600 sca_in(get_msci(port) + CST1, card)); 601 602 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card), 603 sca_inl(ISR0, card), sca_inl(ISR1, card)); 604} 605#endif /* DEBUG_RINGS */ 606 607 608static int sca_xmit(struct sk_buff *skb, struct net_device *dev) 609{ 610 port_t *port = dev_to_port(dev); 611 card_t *card = port_to_card(port); 612 pkt_desc __iomem *desc; 613 u32 buff, len; 614 615 spin_lock_irq(&port->lock); 616 617 desc = desc_address(port, port->txin + 1, 1); 618 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */ 619 620#ifdef DEBUG_PKT 621 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); 622 debug_frame(skb); 623#endif 624 625 desc = desc_address(port, port->txin, 1); 626 buff = buffer_offset(port, port->txin, 1); 627 len = skb->len; 628 memcpy_toio(winbase(card) + buff, skb->data, len); 629 630 writew(len, &desc->len); 631 writeb(ST_TX_EOM, &desc->stat); 632 dev->trans_start = jiffies; 633 634 port->txin = next_desc(port, port->txin, 1); 635 sca_outl(desc_offset(port, port->txin, 1), 636 get_dmac_tx(port) + EDAL, card); 637 638 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */ 639 640 desc = desc_address(port, port->txin + 1, 1); 641 if (readb(&desc->stat)) /* allow 1 packet gap */ 642 netif_stop_queue(dev); 643 644 spin_unlock_irq(&port->lock); 645 646 dev_kfree_skb(skb); 647 return 0; 648} 649 650 651static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase, 652 u32 ramsize) 653{ 654 /* Round RAM size to 32 bits, fill from end to start */ 655 u32 i = ramsize &= ~3; 656 657 do { 658 i -= 4; 659 writel(i ^ 0x12345678, rambase + i); 660 } while (i > 0); 661 662 for (i = 0; i < ramsize ; i += 4) { 663 if (readl(rambase + i) != (i ^ 0x12345678)) 664 break; 665 } 666 667 return i; 668} 669 670 671static void __devinit sca_init(card_t *card, int wait_states) 672{ 673 sca_out(wait_states, WCRL, card); /* Wait Control */ 674 sca_out(wait_states, WCRM, card); 675 sca_out(wait_states, WCRH, card); 676 677 sca_out(0, DMER, card); /* DMA Master disable */ 678 sca_out(0x03, PCR, card); /* DMA priority */ 679 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */ 680 sca_out(0, DSR_TX(0), card); 681 sca_out(0, DSR_RX(1), card); 682 sca_out(0, DSR_TX(1), card); 683 sca_out(DMER_DME, DMER, card); /* DMA Master enable */ 684} 685