hd64572.c revision 12a3bfefc8c1e43ddb50950cb74f8a11d680567a
1/* 2 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux 3 * 4 * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * Source of information: HD64572 SCA-II User's Manual 11 * 12 * We use the following SCA memory map: 13 * 14 * Packet buffer descriptor rings - starting from card->rambase: 15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring 16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring 17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used) 18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used) 19 * 20 * Packet data buffers - starting from card->rambase + buff_offset: 21 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers 22 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers 23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used) 24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used) 25 */ 26 27#include <linux/bitops.h> 28#include <linux/errno.h> 29#include <linux/fcntl.h> 30#include <linux/hdlc.h> 31#include <linux/in.h> 32#include <linux/init.h> 33#include <linux/interrupt.h> 34#include <linux/ioport.h> 35#include <linux/jiffies.h> 36#include <linux/kernel.h> 37#include <linux/module.h> 38#include <linux/netdevice.h> 39#include <linux/skbuff.h> 40#include <linux/string.h> 41#include <linux/types.h> 42#include <asm/io.h> 43#include <asm/system.h> 44#include <asm/uaccess.h> 45#include "hd64572.h" 46 47#define NAPI_WEIGHT 16 48 49#define get_msci(port) (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) 50#define get_dmac_rx(port) (port->chan ? DMAC1RX_OFFSET : DMAC0RX_OFFSET) 51#define get_dmac_tx(port) (port->chan ? DMAC1TX_OFFSET : DMAC0TX_OFFSET) 52 53#define sca_in(reg, card) readb(card->scabase + (reg)) 54#define sca_out(value, reg, card) writeb(value, card->scabase + (reg)) 55#define sca_inw(reg, card) readw(card->scabase + (reg)) 56#define sca_outw(value, reg, card) writew(value, card->scabase + (reg)) 57#define sca_inl(reg, card) readl(card->scabase + (reg)) 58#define sca_outl(value, reg, card) writel(value, card->scabase + (reg)) 59 60static int sca_poll(struct napi_struct *napi, int budget); 61 62static inline port_t* dev_to_port(struct net_device *dev) 63{ 64 return dev_to_hdlc(dev)->priv; 65} 66 67static inline void enable_intr(port_t *port) 68{ 69 /* enable DMIB and MSCI RXINTA interrupts */ 70 sca_outl(sca_inl(IER0, port->card) | 71 (port->chan ? 0x08002200 : 0x00080022), IER0, port->card); 72} 73 74static inline void disable_intr(port_t *port) 75{ 76 sca_outl(sca_inl(IER0, port->card) & 77 (port->chan ? 0x00FF00FF : 0xFF00FF00), IER0, port->card); 78} 79 80static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit) 81{ 82 u16 rx_buffs = port->card->rx_ring_buffers; 83 u16 tx_buffs = port->card->tx_ring_buffers; 84 85 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc. 86 return port->chan * (rx_buffs + tx_buffs) + transmit * rx_buffs + desc; 87} 88 89 90static inline u16 desc_offset(port_t *port, u16 desc, int transmit) 91{ 92 /* Descriptor offset always fits in 16 bits */ 93 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc); 94} 95 96 97static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, 98 int transmit) 99{ 100 return (pkt_desc __iomem *)(port->card->rambase + 101 desc_offset(port, desc, transmit)); 102} 103 104 105static inline u32 buffer_offset(port_t *port, u16 desc, int transmit) 106{ 107 return port->card->buff_offset + 108 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU; 109} 110 111 112static inline void sca_set_carrier(port_t *port) 113{ 114 if (!(sca_in(get_msci(port) + ST3, port->card) & ST3_DCD)) { 115#ifdef DEBUG_LINK 116 printk(KERN_DEBUG "%s: sca_set_carrier on\n", 117 port->netdev.name); 118#endif 119 netif_carrier_on(port->netdev); 120 } else { 121#ifdef DEBUG_LINK 122 printk(KERN_DEBUG "%s: sca_set_carrier off\n", 123 port->netdev.name); 124#endif 125 netif_carrier_off(port->netdev); 126 } 127} 128 129 130static void sca_init_port(port_t *port) 131{ 132 card_t *card = port->card; 133 u16 dmac_rx = get_dmac_rx(port), dmac_tx = get_dmac_tx(port); 134 int transmit, i; 135 136 port->rxin = 0; 137 port->txin = 0; 138 port->txlast = 0; 139 140 for (transmit = 0; transmit < 2; transmit++) { 141 u16 buffs = transmit ? card->tx_ring_buffers 142 : card->rx_ring_buffers; 143 144 for (i = 0; i < buffs; i++) { 145 pkt_desc __iomem *desc = desc_address(port, i, transmit); 146 u16 chain_off = desc_offset(port, i + 1, transmit); 147 u32 buff_off = buffer_offset(port, i, transmit); 148 149 writel(chain_off, &desc->cp); 150 writel(buff_off, &desc->bp); 151 writew(0, &desc->len); 152 writeb(0, &desc->stat); 153 } 154 } 155 156 /* DMA disable - to halt state */ 157 sca_out(0, DSR_RX(port->chan), card); 158 sca_out(0, DSR_TX(port->chan), card); 159 160 /* software ABORT - to initial state */ 161 sca_out(DCR_ABORT, DCR_RX(port->chan), card); 162 sca_out(DCR_ABORT, DCR_TX(port->chan), card); 163 164 /* current desc addr */ 165 sca_outl(desc_offset(port, 0, 0), dmac_rx + CDAL, card); 166 sca_outl(desc_offset(port, card->tx_ring_buffers - 1, 0), 167 dmac_rx + EDAL, card); 168 sca_outl(desc_offset(port, 0, 1), dmac_tx + CDAL, card); 169 sca_outl(desc_offset(port, 0, 1), dmac_tx + EDAL, card); 170 171 /* clear frame end interrupt counter */ 172 sca_out(DCR_CLEAR_EOF, DCR_RX(port->chan), card); 173 sca_out(DCR_CLEAR_EOF, DCR_TX(port->chan), card); 174 175 /* Receive */ 176 sca_outw(HDLC_MAX_MRU, dmac_rx + BFLL, card); /* set buffer length */ 177 sca_out(0x14, DMR_RX(port->chan), card); /* Chain mode, Multi-frame */ 178 sca_out(DIR_EOME, DIR_RX(port->chan), card); /* enable interrupts */ 179 sca_out(DSR_DE, DSR_RX(port->chan), card); /* DMA enable */ 180 181 /* Transmit */ 182 sca_out(0x14, DMR_TX(port->chan), card); /* Chain mode, Multi-frame */ 183 sca_out(DIR_EOME, DIR_TX(port->chan), card); /* enable interrupts */ 184 185 sca_set_carrier(port); 186 netif_napi_add(port->netdev, &port->napi, sca_poll, NAPI_WEIGHT); 187} 188 189 190/* MSCI interrupt service */ 191static inline void sca_msci_intr(port_t *port) 192{ 193 u16 msci = get_msci(port); 194 card_t* card = port->card; 195 196 if (sca_in(msci + ST1, card) & ST1_CDCD) { 197 /* Reset MSCI CDCD status bit */ 198 sca_out(ST1_CDCD, msci + ST1, card); 199 sca_set_carrier(port); 200 } 201} 202 203 204static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, 205 u16 rxin) 206{ 207 struct net_device *dev = port->netdev; 208 struct sk_buff *skb; 209 u16 len; 210 u32 buff; 211 212 len = readw(&desc->len); 213 skb = dev_alloc_skb(len); 214 if (!skb) { 215 dev->stats.rx_dropped++; 216 return; 217 } 218 219 buff = buffer_offset(port, rxin, 0); 220 memcpy_fromio(skb->data, card->rambase + buff, len); 221 222 skb_put(skb, len); 223#ifdef DEBUG_PKT 224 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len); 225 debug_frame(skb); 226#endif 227 dev->stats.rx_packets++; 228 dev->stats.rx_bytes += skb->len; 229 skb->protocol = hdlc_type_trans(skb, dev); 230 netif_receive_skb(skb); 231} 232 233 234/* Receive DMA service */ 235static inline int sca_rx_done(port_t *port, int budget) 236{ 237 struct net_device *dev = port->netdev; 238 u16 dmac = get_dmac_rx(port); 239 card_t *card = port->card; 240 u8 stat = sca_in(DSR_RX(port->chan), card); /* read DMA Status */ 241 int received = 0; 242 243 /* Reset DSR status bits */ 244 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 245 DSR_RX(port->chan), card); 246 247 if (stat & DSR_BOF) 248 /* Dropped one or more frames */ 249 dev->stats.rx_over_errors++; 250 251 while (received < budget) { 252 u32 desc_off = desc_offset(port, port->rxin, 0); 253 pkt_desc __iomem *desc; 254 u32 cda = sca_inl(dmac + CDAL, card); 255 256 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) 257 break; /* No frame received */ 258 259 desc = desc_address(port, port->rxin, 0); 260 stat = readb(&desc->stat); 261 if (!(stat & ST_RX_EOM)) 262 port->rxpart = 1; /* partial frame received */ 263 else if ((stat & ST_ERROR_MASK) || port->rxpart) { 264 dev->stats.rx_errors++; 265 if (stat & ST_RX_OVERRUN) 266 dev->stats.rx_fifo_errors++; 267 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | 268 ST_RX_RESBIT)) || port->rxpart) 269 dev->stats.rx_frame_errors++; 270 else if (stat & ST_RX_CRC) 271 dev->stats.rx_crc_errors++; 272 if (stat & ST_RX_EOM) 273 port->rxpart = 0; /* received last fragment */ 274 } else { 275 sca_rx(card, port, desc, port->rxin); 276 received++; 277 } 278 279 /* Set new error descriptor address */ 280 sca_outl(desc_off, dmac + EDAL, card); 281 port->rxin = (port->rxin + 1) % card->rx_ring_buffers; 282 } 283 284 /* make sure RX DMA is enabled */ 285 sca_out(DSR_DE, DSR_RX(port->chan), card); 286 return received; 287} 288 289 290/* Transmit DMA service */ 291static inline void sca_tx_done(port_t *port) 292{ 293 struct net_device *dev = port->netdev; 294 card_t* card = port->card; 295 u8 stat; 296 unsigned count = 0; 297 298 spin_lock(&port->lock); 299 300 stat = sca_in(DSR_TX(port->chan), card); /* read DMA Status */ 301 302 /* Reset DSR status bits */ 303 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 304 DSR_TX(port->chan), card); 305 306 while (1) { 307 pkt_desc __iomem *desc = desc_address(port, port->txlast, 1); 308 u8 stat = readb(&desc->stat); 309 310 if (!(stat & ST_TX_OWNRSHP)) 311 break; /* not yet transmitted */ 312 if (stat & ST_TX_UNDRRUN) { 313 dev->stats.tx_errors++; 314 dev->stats.tx_fifo_errors++; 315 } else { 316 dev->stats.tx_packets++; 317 dev->stats.tx_bytes += readw(&desc->len); 318 } 319 writeb(0, &desc->stat); /* Free descriptor */ 320 count++; 321 port->txlast = (port->txlast + 1) % card->tx_ring_buffers; 322 } 323 324 if (count) 325 netif_wake_queue(dev); 326 spin_unlock(&port->lock); 327} 328 329 330static int sca_poll(struct napi_struct *napi, int budget) 331{ 332 port_t *port = container_of(napi, port_t, napi); 333 u32 isr0 = sca_inl(ISR0, port->card); 334 int received = 0; 335 336 if (isr0 & (port->chan ? 0x08000000 : 0x00080000)) 337 sca_msci_intr(port); 338 339 if (isr0 & (port->chan ? 0x00002000 : 0x00000020)) 340 sca_tx_done(port); 341 342 if (isr0 & (port->chan ? 0x00000200 : 0x00000002)) 343 received = sca_rx_done(port, budget); 344 345 if (received < budget) { 346 napi_complete(napi); 347 enable_intr(port); 348 } 349 350 return received; 351} 352 353static irqreturn_t sca_intr(int irq, void *dev_id) 354{ 355 card_t *card = dev_id; 356 u32 isr0 = sca_inl(ISR0, card); 357 int i, handled = 0; 358 359 for (i = 0; i < 2; i++) { 360 port_t *port = get_port(card, i); 361 if (port && (isr0 & (i ? 0x08002200 : 0x00080022))) { 362 handled = 1; 363 disable_intr(port); 364 napi_schedule(&port->napi); 365 } 366 } 367 368 return IRQ_RETVAL(handled); 369} 370 371 372static void sca_set_port(port_t *port) 373{ 374 card_t* card = port->card; 375 u16 msci = get_msci(port); 376 u8 md2 = sca_in(msci + MD2, card); 377 unsigned int tmc, br = 10, brv = 1024; 378 379 380 if (port->settings.clock_rate > 0) { 381 /* Try lower br for better accuracy*/ 382 do { 383 br--; 384 brv >>= 1; /* brv = 2^9 = 512 max in specs */ 385 386 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ 387 tmc = CLOCK_BASE / brv / port->settings.clock_rate; 388 }while (br > 1 && tmc <= 128); 389 390 if (tmc < 1) { 391 tmc = 1; 392 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ 393 brv = 1; 394 } else if (tmc > 255) 395 tmc = 256; /* tmc=0 means 256 - low baud rates */ 396 397 port->settings.clock_rate = CLOCK_BASE / brv / tmc; 398 } else { 399 br = 9; /* Minimum clock rate */ 400 tmc = 256; /* 8bit = 0 */ 401 port->settings.clock_rate = CLOCK_BASE / (256 * 512); 402 } 403 404 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br; 405 port->txs = (port->txs & ~CLK_BRG_MASK) | br; 406 port->tmc = tmc; 407 408 /* baud divisor - time constant*/ 409 sca_out(port->tmc, msci + TMCR, card); 410 sca_out(port->tmc, msci + TMCT, card); 411 412 /* Set BRG bits */ 413 sca_out(port->rxs, msci + RXS, card); 414 sca_out(port->txs, msci + TXS, card); 415 416 if (port->settings.loopback) 417 md2 |= MD2_LOOPBACK; 418 else 419 md2 &= ~MD2_LOOPBACK; 420 421 sca_out(md2, msci + MD2, card); 422 423} 424 425 426static void sca_open(struct net_device *dev) 427{ 428 port_t *port = dev_to_port(dev); 429 card_t* card = port->card; 430 u16 msci = get_msci(port); 431 u8 md0, md2; 432 433 switch(port->encoding) { 434 case ENCODING_NRZ: md2 = MD2_NRZ; break; 435 case ENCODING_NRZI: md2 = MD2_NRZI; break; 436 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break; 437 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break; 438 default: md2 = MD2_MANCHESTER; 439 } 440 441 if (port->settings.loopback) 442 md2 |= MD2_LOOPBACK; 443 444 switch(port->parity) { 445 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break; 446 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break; 447 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break; 448 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break; 449 default: md0 = MD0_HDLC | MD0_CRC_NONE; 450 } 451 452 sca_out(CMD_RESET, msci + CMD, card); 453 sca_out(md0, msci + MD0, card); 454 sca_out(0x00, msci + MD1, card); /* no address field check */ 455 sca_out(md2, msci + MD2, card); 456 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */ 457 /* Skip the rest of underrun frame */ 458 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card); 459 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */ 460 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */ 461 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */ 462 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */ 463 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/ 464 465/* We're using the following interrupts: 466 - RXINTA (DCD changes only) 467 - DMIB (EOM - single frame transfer complete) 468*/ 469 sca_outl(IE0_RXINTA | IE0_CDCD, msci + IE0, card); 470 471 sca_out(port->tmc, msci + TMCR, card); 472 sca_out(port->tmc, msci + TMCT, card); 473 sca_out(port->rxs, msci + RXS, card); 474 sca_out(port->txs, msci + TXS, card); 475 sca_out(CMD_TX_ENABLE, msci + CMD, card); 476 sca_out(CMD_RX_ENABLE, msci + CMD, card); 477 478 sca_set_carrier(port); 479 enable_intr(port); 480 napi_enable(&port->napi); 481 netif_start_queue(dev); 482} 483 484 485static void sca_close(struct net_device *dev) 486{ 487 port_t *port = dev_to_port(dev); 488 489 /* reset channel */ 490 sca_out(CMD_RESET, get_msci(port) + CMD, port->card); 491 disable_intr(port); 492 napi_disable(&port->napi); 493 netif_stop_queue(dev); 494} 495 496 497static int sca_attach(struct net_device *dev, unsigned short encoding, 498 unsigned short parity) 499{ 500 if (encoding != ENCODING_NRZ && 501 encoding != ENCODING_NRZI && 502 encoding != ENCODING_FM_MARK && 503 encoding != ENCODING_FM_SPACE && 504 encoding != ENCODING_MANCHESTER) 505 return -EINVAL; 506 507 if (parity != PARITY_NONE && 508 parity != PARITY_CRC16_PR0 && 509 parity != PARITY_CRC16_PR1 && 510 parity != PARITY_CRC32_PR1_CCITT && 511 parity != PARITY_CRC16_PR1_CCITT) 512 return -EINVAL; 513 514 dev_to_port(dev)->encoding = encoding; 515 dev_to_port(dev)->parity = parity; 516 return 0; 517} 518 519 520#ifdef DEBUG_RINGS 521static void sca_dump_rings(struct net_device *dev) 522{ 523 port_t *port = dev_to_port(dev); 524 card_t *card = port->card; 525 u16 cnt; 526 527 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive", 528 sca_inl(get_dmac_rx(port) + CDAL, card), 529 sca_inl(get_dmac_rx(port) + EDAL, card), 530 sca_in(DSR_RX(port->chan), card), port->rxin, 531 sca_in(DSR_RX(port->chan), card) & DSR_DE ? "" : "in"); 532 for (cnt = 0; cnt < port->card->rx_ring_buffers; cnt++) 533 pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat))); 534 pr_cont("\n"); 535 536 printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u " 537 "last=%u %sactive", 538 sca_inl(get_dmac_tx(port) + CDAL, card), 539 sca_inl(get_dmac_tx(port) + EDAL, card), 540 sca_in(DSR_TX(port->chan), card), port->txin, port->txlast, 541 sca_in(DSR_TX(port->chan), card) & DSR_DE ? "" : "in"); 542 543 for (cnt = 0; cnt < port->card->tx_ring_buffers; cnt++) 544 pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat))); 545 pr_cont("\n"); 546 547 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x," 548 " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n", 549 sca_in(get_msci(port) + MD0, card), 550 sca_in(get_msci(port) + MD1, card), 551 sca_in(get_msci(port) + MD2, card), 552 sca_in(get_msci(port) + ST0, card), 553 sca_in(get_msci(port) + ST1, card), 554 sca_in(get_msci(port) + ST2, card), 555 sca_in(get_msci(port) + ST3, card), 556 sca_in(get_msci(port) + ST4, card), 557 sca_in(get_msci(port) + FST, card), 558 sca_in(get_msci(port) + CST0, card), 559 sca_in(get_msci(port) + CST1, card)); 560 561 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card), 562 sca_inl(ISR0, card), sca_inl(ISR1, card)); 563} 564#endif /* DEBUG_RINGS */ 565 566 567static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev) 568{ 569 port_t *port = dev_to_port(dev); 570 card_t *card = port->card; 571 pkt_desc __iomem *desc; 572 u32 buff, len; 573 574 spin_lock_irq(&port->lock); 575 576 desc = desc_address(port, port->txin + 1, 1); 577 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */ 578 579#ifdef DEBUG_PKT 580 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); 581 debug_frame(skb); 582#endif 583 584 desc = desc_address(port, port->txin, 1); 585 buff = buffer_offset(port, port->txin, 1); 586 len = skb->len; 587 memcpy_toio(card->rambase + buff, skb->data, len); 588 589 writew(len, &desc->len); 590 writeb(ST_TX_EOM, &desc->stat); 591 592 port->txin = (port->txin + 1) % card->tx_ring_buffers; 593 sca_outl(desc_offset(port, port->txin, 1), 594 get_dmac_tx(port) + EDAL, card); 595 596 sca_out(DSR_DE, DSR_TX(port->chan), card); /* Enable TX DMA */ 597 598 desc = desc_address(port, port->txin + 1, 1); 599 if (readb(&desc->stat)) /* allow 1 packet gap */ 600 netif_stop_queue(dev); 601 602 spin_unlock_irq(&port->lock); 603 604 dev_kfree_skb(skb); 605 return NETDEV_TX_OK; 606} 607 608 609static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase, 610 u32 ramsize) 611{ 612 /* Round RAM size to 32 bits, fill from end to start */ 613 u32 i = ramsize &= ~3; 614 615 do { 616 i -= 4; 617 writel(i ^ 0x12345678, rambase + i); 618 } while (i > 0); 619 620 for (i = 0; i < ramsize ; i += 4) { 621 if (readl(rambase + i) != (i ^ 0x12345678)) 622 break; 623 } 624 625 return i; 626} 627 628 629static void __devinit sca_init(card_t *card, int wait_states) 630{ 631 sca_out(wait_states, WCRL, card); /* Wait Control */ 632 sca_out(wait_states, WCRM, card); 633 sca_out(wait_states, WCRH, card); 634 635 sca_out(0, DMER, card); /* DMA Master disable */ 636 sca_out(0x03, PCR, card); /* DMA priority */ 637 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */ 638 sca_out(0, DSR_TX(0), card); 639 sca_out(0, DSR_RX(1), card); 640 sca_out(0, DSR_TX(1), card); 641 sca_out(DMER_DME, DMER, card); /* DMA Master enable */ 642} 643