pci200syn.c revision abc9d91a35a924c8db0e949cd443471672e37cdb
1/* 2 * Goramo PCI200SYN synchronous serial card driver for Linux 3 * 4 * Copyright (C) 2002-2003 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/> 11 * 12 * Sources of information: 13 * Hitachi HD64572 SCA-II User's Manual 14 * PLX Technology Inc. PCI9052 Data Book 15 */ 16 17#include <linux/module.h> 18#include <linux/kernel.h> 19#include <linux/slab.h> 20#include <linux/types.h> 21#include <linux/fcntl.h> 22#include <linux/in.h> 23#include <linux/string.h> 24#include <linux/errno.h> 25#include <linux/init.h> 26#include <linux/ioport.h> 27#include <linux/moduleparam.h> 28#include <linux/netdevice.h> 29#include <linux/hdlc.h> 30#include <linux/pci.h> 31#include <linux/delay.h> 32#include <asm/io.h> 33 34#include "hd64572.h" 35 36static const char* version = "Goramo PCI200SYN driver version: 1.16"; 37static const char* devname = "PCI200SYN"; 38 39#undef DEBUG_PKT 40#define DEBUG_RINGS 41 42#define PCI200SYN_PLX_SIZE 0x80 /* PLX control window size (128b) */ 43#define PCI200SYN_SCA_SIZE 0x400 /* SCA window size (1Kb) */ 44#define MAX_TX_BUFFERS 10 45 46static int pci_clock_freq = 33000000; 47#define CLOCK_BASE pci_clock_freq 48 49/* 50 * PLX PCI9052 local configuration and shared runtime registers. 51 * This structure can be used to access 9052 registers (memory mapped). 52 */ 53typedef struct { 54 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ 55 u32 loc_rom_range; /* 10h : Local ROM Range */ 56 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ 57 u32 loc_rom_base; /* 24h : Local ROM Base */ 58 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ 59 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */ 60 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ 61 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ 62 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ 63}plx9052; 64 65 66 67typedef struct port_s { 68 struct napi_struct napi; 69 struct net_device *dev; 70 struct card_s *card; 71 spinlock_t lock; /* TX lock */ 72 sync_serial_settings settings; 73 int rxpart; /* partial frame received, next frame invalid*/ 74 unsigned short encoding; 75 unsigned short parity; 76 u16 rxin; /* rx ring buffer 'in' pointer */ 77 u16 txin; /* tx ring buffer 'in' and 'last' pointers */ 78 u16 txlast; 79 u8 rxs, txs, tmc; /* SCA registers */ 80 u8 phy_node; /* physical port # - 0 or 1 */ 81}port_t; 82 83 84 85typedef struct card_s { 86 u8 __iomem *rambase; /* buffer memory base (virtual) */ 87 u8 __iomem *scabase; /* SCA memory base (virtual) */ 88 plx9052 __iomem *plxbase;/* PLX registers memory base (virtual) */ 89 u16 rx_ring_buffers; /* number of buffers in a ring */ 90 u16 tx_ring_buffers; 91 u16 buff_offset; /* offset of first buffer of first channel */ 92 u8 irq; /* interrupt request level */ 93 94 port_t ports[2]; 95}card_t; 96 97 98#define sca_in(reg, card) readb(card->scabase + (reg)) 99#define sca_out(value, reg, card) writeb(value, card->scabase + (reg)) 100#define sca_inw(reg, card) readw(card->scabase + (reg)) 101#define sca_outw(value, reg, card) writew(value, card->scabase + (reg)) 102#define sca_inl(reg, card) readl(card->scabase + (reg)) 103#define sca_outl(value, reg, card) writel(value, card->scabase + (reg)) 104 105#define port_to_card(port) (port->card) 106#define log_node(port) (port->phy_node) 107#define phy_node(port) (port->phy_node) 108#define winbase(card) (card->rambase) 109#define get_port(card, port) (&card->ports[port]) 110#define sca_flush(card) (sca_in(IER0, card)); 111 112static inline void new_memcpy_toio(char __iomem *dest, char *src, int length) 113{ 114 int len; 115 do { 116 len = length > 256 ? 256 : length; 117 memcpy_toio(dest, src, len); 118 dest += len; 119 src += len; 120 length -= len; 121 readb(dest); 122 } while (len); 123} 124 125#undef memcpy_toio 126#define memcpy_toio new_memcpy_toio 127 128#include "hd64572.c" 129 130 131static void pci200_set_iface(port_t *port) 132{ 133 card_t *card = port->card; 134 u16 msci = get_msci(port); 135 u8 rxs = port->rxs & CLK_BRG_MASK; 136 u8 txs = port->txs & CLK_BRG_MASK; 137 138 sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, 139 port_to_card(port)); 140 switch(port->settings.clock_type) { 141 case CLOCK_INT: 142 rxs |= CLK_BRG; /* BRG output */ 143 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ 144 break; 145 146 case CLOCK_TXINT: 147 rxs |= CLK_LINE; /* RXC input */ 148 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */ 149 break; 150 151 case CLOCK_TXFROMRX: 152 rxs |= CLK_LINE; /* RXC input */ 153 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ 154 break; 155 156 default: /* EXTernal clock */ 157 rxs |= CLK_LINE; /* RXC input */ 158 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */ 159 break; 160 } 161 162 port->rxs = rxs; 163 port->txs = txs; 164 sca_out(rxs, msci + RXS, card); 165 sca_out(txs, msci + TXS, card); 166 sca_set_port(port); 167} 168 169 170 171static int pci200_open(struct net_device *dev) 172{ 173 port_t *port = dev_to_port(dev); 174 175 int result = hdlc_open(dev); 176 if (result) 177 return result; 178 179 sca_open(dev); 180 pci200_set_iface(port); 181 sca_flush(port_to_card(port)); 182 return 0; 183} 184 185 186 187static int pci200_close(struct net_device *dev) 188{ 189 sca_close(dev); 190 sca_flush(port_to_card(dev_to_port(dev))); 191 hdlc_close(dev); 192 return 0; 193} 194 195 196 197static int pci200_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 198{ 199 const size_t size = sizeof(sync_serial_settings); 200 sync_serial_settings new_line; 201 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 202 port_t *port = dev_to_port(dev); 203 204#ifdef DEBUG_RINGS 205 if (cmd == SIOCDEVPRIVATE) { 206 sca_dump_rings(dev); 207 return 0; 208 } 209#endif 210 if (cmd != SIOCWANDEV) 211 return hdlc_ioctl(dev, ifr, cmd); 212 213 switch(ifr->ifr_settings.type) { 214 case IF_GET_IFACE: 215 ifr->ifr_settings.type = IF_IFACE_V35; 216 if (ifr->ifr_settings.size < size) { 217 ifr->ifr_settings.size = size; /* data size wanted */ 218 return -ENOBUFS; 219 } 220 if (copy_to_user(line, &port->settings, size)) 221 return -EFAULT; 222 return 0; 223 224 case IF_IFACE_V35: 225 case IF_IFACE_SYNC_SERIAL: 226 if (!capable(CAP_NET_ADMIN)) 227 return -EPERM; 228 229 if (copy_from_user(&new_line, line, size)) 230 return -EFAULT; 231 232 if (new_line.clock_type != CLOCK_EXT && 233 new_line.clock_type != CLOCK_TXFROMRX && 234 new_line.clock_type != CLOCK_INT && 235 new_line.clock_type != CLOCK_TXINT) 236 return -EINVAL; /* No such clock setting */ 237 238 if (new_line.loopback != 0 && new_line.loopback != 1) 239 return -EINVAL; 240 241 memcpy(&port->settings, &new_line, size); /* Update settings */ 242 pci200_set_iface(port); 243 sca_flush(port_to_card(port)); 244 return 0; 245 246 default: 247 return hdlc_ioctl(dev, ifr, cmd); 248 } 249} 250 251 252 253static void pci200_pci_remove_one(struct pci_dev *pdev) 254{ 255 int i; 256 card_t *card = pci_get_drvdata(pdev); 257 258 for (i = 0; i < 2; i++) 259 if (card->ports[i].card) { 260 struct net_device *dev = port_to_dev(&card->ports[i]); 261 unregister_hdlc_device(dev); 262 } 263 264 if (card->irq) 265 free_irq(card->irq, card); 266 267 if (card->rambase) 268 iounmap(card->rambase); 269 if (card->scabase) 270 iounmap(card->scabase); 271 if (card->plxbase) 272 iounmap(card->plxbase); 273 274 pci_release_regions(pdev); 275 pci_disable_device(pdev); 276 pci_set_drvdata(pdev, NULL); 277 if (card->ports[0].dev) 278 free_netdev(card->ports[0].dev); 279 if (card->ports[1].dev) 280 free_netdev(card->ports[1].dev); 281 kfree(card); 282} 283 284 285 286static int __devinit pci200_pci_init_one(struct pci_dev *pdev, 287 const struct pci_device_id *ent) 288{ 289 card_t *card; 290 u32 __iomem *p; 291 int i; 292 u32 ramsize; 293 u32 ramphys; /* buffer memory base */ 294 u32 scaphys; /* SCA memory base */ 295 u32 plxphys; /* PLX registers memory base */ 296 297#ifndef MODULE 298 static int printed_version; 299 if (!printed_version++) 300 printk(KERN_INFO "%s\n", version); 301#endif 302 303 i = pci_enable_device(pdev); 304 if (i) 305 return i; 306 307 i = pci_request_regions(pdev, "PCI200SYN"); 308 if (i) { 309 pci_disable_device(pdev); 310 return i; 311 } 312 313 card = kzalloc(sizeof(card_t), GFP_KERNEL); 314 if (card == NULL) { 315 printk(KERN_ERR "pci200syn: unable to allocate memory\n"); 316 pci_release_regions(pdev); 317 pci_disable_device(pdev); 318 return -ENOBUFS; 319 } 320 pci_set_drvdata(pdev, card); 321 card->ports[0].dev = alloc_hdlcdev(&card->ports[0]); 322 card->ports[1].dev = alloc_hdlcdev(&card->ports[1]); 323 if (!card->ports[0].dev || !card->ports[1].dev) { 324 printk(KERN_ERR "pci200syn: unable to allocate memory\n"); 325 pci200_pci_remove_one(pdev); 326 return -ENOMEM; 327 } 328 329 if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE || 330 pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE || 331 pci_resource_len(pdev, 3) < 16384) { 332 printk(KERN_ERR "pci200syn: invalid card EEPROM parameters\n"); 333 pci200_pci_remove_one(pdev); 334 return -EFAULT; 335 } 336 337 plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK; 338 card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE); 339 340 scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK; 341 card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE); 342 343 ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK; 344 card->rambase = pci_ioremap_bar(pdev, 3); 345 346 if (card->plxbase == NULL || 347 card->scabase == NULL || 348 card->rambase == NULL) { 349 printk(KERN_ERR "pci200syn: ioremap() failed\n"); 350 pci200_pci_remove_one(pdev); 351 return -EFAULT; 352 } 353 354 /* Reset PLX */ 355 p = &card->plxbase->init_ctrl; 356 writel(readl(p) | 0x40000000, p); 357 readl(p); /* Flush the write - do not use sca_flush */ 358 udelay(1); 359 360 writel(readl(p) & ~0x40000000, p); 361 readl(p); /* Flush the write - do not use sca_flush */ 362 udelay(1); 363 364 ramsize = sca_detect_ram(card, card->rambase, 365 pci_resource_len(pdev, 3)); 366 367 /* number of TX + RX buffers for one port - this is dual port card */ 368 i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU)); 369 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS); 370 card->rx_ring_buffers = i - card->tx_ring_buffers; 371 372 card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers + 373 card->rx_ring_buffers); 374 375 printk(KERN_INFO "pci200syn: %u KB RAM at 0x%x, IRQ%u, using %u TX +" 376 " %u RX packets rings\n", ramsize / 1024, ramphys, 377 pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers); 378 379 if (pdev->subsystem_device == PCI_DEVICE_ID_PLX_9050) { 380 printk(KERN_ERR "Detected PCI200SYN card with old " 381 "configuration data.\n"); 382 printk(KERN_ERR "See <http://www.kernel.org/pub/" 383 "linux/utils/net/hdlc/pci200syn/> for update.\n"); 384 printk(KERN_ERR "The card will stop working with" 385 " future versions of Linux if not updated.\n"); 386 } 387 388 if (card->tx_ring_buffers < 1) { 389 printk(KERN_ERR "pci200syn: RAM test failed\n"); 390 pci200_pci_remove_one(pdev); 391 return -EFAULT; 392 } 393 394 /* Enable interrupts on the PCI bridge */ 395 p = &card->plxbase->intr_ctrl_stat; 396 writew(readw(p) | 0x0040, p); 397 398 /* Allocate IRQ */ 399 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, devname, card)) { 400 printk(KERN_WARNING "pci200syn: could not allocate IRQ%d.\n", 401 pdev->irq); 402 pci200_pci_remove_one(pdev); 403 return -EBUSY; 404 } 405 card->irq = pdev->irq; 406 407 sca_init(card, 0); 408 409 for (i = 0; i < 2; i++) { 410 port_t *port = &card->ports[i]; 411 struct net_device *dev = port_to_dev(port); 412 hdlc_device *hdlc = dev_to_hdlc(dev); 413 port->phy_node = i; 414 415 spin_lock_init(&port->lock); 416 dev->irq = card->irq; 417 dev->mem_start = ramphys; 418 dev->mem_end = ramphys + ramsize - 1; 419 dev->tx_queue_len = 50; 420 dev->do_ioctl = pci200_ioctl; 421 dev->open = pci200_open; 422 dev->stop = pci200_close; 423 hdlc->attach = sca_attach; 424 hdlc->xmit = sca_xmit; 425 port->settings.clock_type = CLOCK_EXT; 426 port->card = card; 427 sca_init_port(port); 428 if (register_hdlc_device(dev)) { 429 printk(KERN_ERR "pci200syn: unable to register hdlc " 430 "device\n"); 431 port->card = NULL; 432 pci200_pci_remove_one(pdev); 433 return -ENOBUFS; 434 } 435 436 printk(KERN_INFO "%s: PCI200SYN node %d\n", 437 dev->name, port->phy_node); 438 } 439 440 sca_flush(card); 441 return 0; 442} 443 444 445 446static struct pci_device_id pci200_pci_tbl[] __devinitdata = { 447 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX, 448 PCI_DEVICE_ID_PLX_9050, 0, 0, 0 }, 449 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX, 450 PCI_DEVICE_ID_PLX_PCI200SYN, 0, 0, 0 }, 451 { 0, } 452}; 453 454 455static struct pci_driver pci200_pci_driver = { 456 .name = "PCI200SYN", 457 .id_table = pci200_pci_tbl, 458 .probe = pci200_pci_init_one, 459 .remove = pci200_pci_remove_one, 460}; 461 462 463static int __init pci200_init_module(void) 464{ 465#ifdef MODULE 466 printk(KERN_INFO "%s\n", version); 467#endif 468 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) { 469 printk(KERN_ERR "pci200syn: Invalid PCI clock frequency\n"); 470 return -EINVAL; 471 } 472 return pci_register_driver(&pci200_pci_driver); 473} 474 475 476 477static void __exit pci200_cleanup_module(void) 478{ 479 pci_unregister_driver(&pci200_pci_driver); 480} 481 482MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 483MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver"); 484MODULE_LICENSE("GPL v2"); 485MODULE_DEVICE_TABLE(pci, pci200_pci_tbl); 486module_param(pci_clock_freq, int, 0444); 487MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz"); 488module_init(pci200_init_module); 489module_exit(pci200_cleanup_module); 490