pci200syn.c revision cd354f1ae75e6466a7e31b727faede57a1f89ca5
1/* 2 * Goramo PCI200SYN synchronous serial card driver for Linux 3 * 4 * Copyright (C) 2002-2003 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/> 11 * 12 * Sources of information: 13 * Hitachi HD64572 SCA-II User's Manual 14 * PLX Technology Inc. PCI9052 Data Book 15 */ 16 17#include <linux/module.h> 18#include <linux/kernel.h> 19#include <linux/slab.h> 20#include <linux/types.h> 21#include <linux/fcntl.h> 22#include <linux/in.h> 23#include <linux/string.h> 24#include <linux/errno.h> 25#include <linux/init.h> 26#include <linux/ioport.h> 27#include <linux/moduleparam.h> 28#include <linux/netdevice.h> 29#include <linux/hdlc.h> 30#include <linux/pci.h> 31#include <linux/delay.h> 32#include <asm/io.h> 33 34#include "hd64572.h" 35 36static const char* version = "Goramo PCI200SYN driver version: 1.16"; 37static const char* devname = "PCI200SYN"; 38 39#undef DEBUG_PKT 40#define DEBUG_RINGS 41 42#define PCI200SYN_PLX_SIZE 0x80 /* PLX control window size (128b) */ 43#define PCI200SYN_SCA_SIZE 0x400 /* SCA window size (1Kb) */ 44#define ALL_PAGES_ALWAYS_MAPPED 45#define NEED_DETECT_RAM 46#define NEED_SCA_MSCI_INTR 47#define MAX_TX_BUFFERS 10 48 49static int pci_clock_freq = 33000000; 50#define CLOCK_BASE pci_clock_freq 51 52/* 53 * PLX PCI9052 local configuration and shared runtime registers. 54 * This structure can be used to access 9052 registers (memory mapped). 55 */ 56typedef struct { 57 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ 58 u32 loc_rom_range; /* 10h : Local ROM Range */ 59 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ 60 u32 loc_rom_base; /* 24h : Local ROM Base */ 61 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ 62 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */ 63 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ 64 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ 65 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ 66}plx9052; 67 68 69 70typedef struct port_s { 71 struct net_device *dev; 72 struct card_s *card; 73 spinlock_t lock; /* TX lock */ 74 sync_serial_settings settings; 75 int rxpart; /* partial frame received, next frame invalid*/ 76 unsigned short encoding; 77 unsigned short parity; 78 u16 rxin; /* rx ring buffer 'in' pointer */ 79 u16 txin; /* tx ring buffer 'in' and 'last' pointers */ 80 u16 txlast; 81 u8 rxs, txs, tmc; /* SCA registers */ 82 u8 phy_node; /* physical port # - 0 or 1 */ 83}port_t; 84 85 86 87typedef struct card_s { 88 u8 __iomem *rambase; /* buffer memory base (virtual) */ 89 u8 __iomem *scabase; /* SCA memory base (virtual) */ 90 plx9052 __iomem *plxbase;/* PLX registers memory base (virtual) */ 91 u16 rx_ring_buffers; /* number of buffers in a ring */ 92 u16 tx_ring_buffers; 93 u16 buff_offset; /* offset of first buffer of first channel */ 94 u8 irq; /* interrupt request level */ 95 96 port_t ports[2]; 97}card_t; 98 99 100#define sca_in(reg, card) readb(card->scabase + (reg)) 101#define sca_out(value, reg, card) writeb(value, card->scabase + (reg)) 102#define sca_inw(reg, card) readw(card->scabase + (reg)) 103#define sca_outw(value, reg, card) writew(value, card->scabase + (reg)) 104#define sca_inl(reg, card) readl(card->scabase + (reg)) 105#define sca_outl(value, reg, card) writel(value, card->scabase + (reg)) 106 107#define port_to_card(port) (port->card) 108#define log_node(port) (port->phy_node) 109#define phy_node(port) (port->phy_node) 110#define winbase(card) (card->rambase) 111#define get_port(card, port) (&card->ports[port]) 112#define sca_flush(card) (sca_in(IER0, card)); 113 114static inline void new_memcpy_toio(char __iomem *dest, char *src, int length) 115{ 116 int len; 117 do { 118 len = length > 256 ? 256 : length; 119 memcpy_toio(dest, src, len); 120 dest += len; 121 src += len; 122 length -= len; 123 readb(dest); 124 } while (len); 125} 126 127#undef memcpy_toio 128#define memcpy_toio new_memcpy_toio 129 130#include "hd6457x.c" 131 132 133static void pci200_set_iface(port_t *port) 134{ 135 card_t *card = port->card; 136 u16 msci = get_msci(port); 137 u8 rxs = port->rxs & CLK_BRG_MASK; 138 u8 txs = port->txs & CLK_BRG_MASK; 139 140 sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, 141 port_to_card(port)); 142 switch(port->settings.clock_type) { 143 case CLOCK_INT: 144 rxs |= CLK_BRG; /* BRG output */ 145 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ 146 break; 147 148 case CLOCK_TXINT: 149 rxs |= CLK_LINE; /* RXC input */ 150 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */ 151 break; 152 153 case CLOCK_TXFROMRX: 154 rxs |= CLK_LINE; /* RXC input */ 155 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ 156 break; 157 158 default: /* EXTernal clock */ 159 rxs |= CLK_LINE; /* RXC input */ 160 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */ 161 break; 162 } 163 164 port->rxs = rxs; 165 port->txs = txs; 166 sca_out(rxs, msci + RXS, card); 167 sca_out(txs, msci + TXS, card); 168 sca_set_port(port); 169} 170 171 172 173static int pci200_open(struct net_device *dev) 174{ 175 port_t *port = dev_to_port(dev); 176 177 int result = hdlc_open(dev); 178 if (result) 179 return result; 180 181 sca_open(dev); 182 pci200_set_iface(port); 183 sca_flush(port_to_card(port)); 184 return 0; 185} 186 187 188 189static int pci200_close(struct net_device *dev) 190{ 191 sca_close(dev); 192 sca_flush(port_to_card(dev_to_port(dev))); 193 hdlc_close(dev); 194 return 0; 195} 196 197 198 199static int pci200_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 200{ 201 const size_t size = sizeof(sync_serial_settings); 202 sync_serial_settings new_line; 203 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 204 port_t *port = dev_to_port(dev); 205 206#ifdef DEBUG_RINGS 207 if (cmd == SIOCDEVPRIVATE) { 208 sca_dump_rings(dev); 209 return 0; 210 } 211#endif 212 if (cmd != SIOCWANDEV) 213 return hdlc_ioctl(dev, ifr, cmd); 214 215 switch(ifr->ifr_settings.type) { 216 case IF_GET_IFACE: 217 ifr->ifr_settings.type = IF_IFACE_V35; 218 if (ifr->ifr_settings.size < size) { 219 ifr->ifr_settings.size = size; /* data size wanted */ 220 return -ENOBUFS; 221 } 222 if (copy_to_user(line, &port->settings, size)) 223 return -EFAULT; 224 return 0; 225 226 case IF_IFACE_V35: 227 case IF_IFACE_SYNC_SERIAL: 228 if (!capable(CAP_NET_ADMIN)) 229 return -EPERM; 230 231 if (copy_from_user(&new_line, line, size)) 232 return -EFAULT; 233 234 if (new_line.clock_type != CLOCK_EXT && 235 new_line.clock_type != CLOCK_TXFROMRX && 236 new_line.clock_type != CLOCK_INT && 237 new_line.clock_type != CLOCK_TXINT) 238 return -EINVAL; /* No such clock setting */ 239 240 if (new_line.loopback != 0 && new_line.loopback != 1) 241 return -EINVAL; 242 243 memcpy(&port->settings, &new_line, size); /* Update settings */ 244 pci200_set_iface(port); 245 sca_flush(port_to_card(port)); 246 return 0; 247 248 default: 249 return hdlc_ioctl(dev, ifr, cmd); 250 } 251} 252 253 254 255static void pci200_pci_remove_one(struct pci_dev *pdev) 256{ 257 int i; 258 card_t *card = pci_get_drvdata(pdev); 259 260 for (i = 0; i < 2; i++) 261 if (card->ports[i].card) { 262 struct net_device *dev = port_to_dev(&card->ports[i]); 263 unregister_hdlc_device(dev); 264 } 265 266 if (card->irq) 267 free_irq(card->irq, card); 268 269 if (card->rambase) 270 iounmap(card->rambase); 271 if (card->scabase) 272 iounmap(card->scabase); 273 if (card->plxbase) 274 iounmap(card->plxbase); 275 276 pci_release_regions(pdev); 277 pci_disable_device(pdev); 278 pci_set_drvdata(pdev, NULL); 279 if (card->ports[0].dev) 280 free_netdev(card->ports[0].dev); 281 if (card->ports[1].dev) 282 free_netdev(card->ports[1].dev); 283 kfree(card); 284} 285 286 287 288static int __devinit pci200_pci_init_one(struct pci_dev *pdev, 289 const struct pci_device_id *ent) 290{ 291 card_t *card; 292 u8 rev_id; 293 u32 __iomem *p; 294 int i; 295 u32 ramsize; 296 u32 ramphys; /* buffer memory base */ 297 u32 scaphys; /* SCA memory base */ 298 u32 plxphys; /* PLX registers memory base */ 299 300#ifndef MODULE 301 static int printed_version; 302 if (!printed_version++) 303 printk(KERN_INFO "%s\n", version); 304#endif 305 306 i = pci_enable_device(pdev); 307 if (i) 308 return i; 309 310 i = pci_request_regions(pdev, "PCI200SYN"); 311 if (i) { 312 pci_disable_device(pdev); 313 return i; 314 } 315 316 card = kmalloc(sizeof(card_t), GFP_KERNEL); 317 if (card == NULL) { 318 printk(KERN_ERR "pci200syn: unable to allocate memory\n"); 319 pci_release_regions(pdev); 320 pci_disable_device(pdev); 321 return -ENOBUFS; 322 } 323 memset(card, 0, sizeof(card_t)); 324 pci_set_drvdata(pdev, card); 325 card->ports[0].dev = alloc_hdlcdev(&card->ports[0]); 326 card->ports[1].dev = alloc_hdlcdev(&card->ports[1]); 327 if (!card->ports[0].dev || !card->ports[1].dev) { 328 printk(KERN_ERR "pci200syn: unable to allocate memory\n"); 329 pci200_pci_remove_one(pdev); 330 return -ENOMEM; 331 } 332 333 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 334 if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE || 335 pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE || 336 pci_resource_len(pdev, 3) < 16384) { 337 printk(KERN_ERR "pci200syn: invalid card EEPROM parameters\n"); 338 pci200_pci_remove_one(pdev); 339 return -EFAULT; 340 } 341 342 plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK; 343 card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE); 344 345 scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK; 346 card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE); 347 348 ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK; 349 card->rambase = ioremap(ramphys, pci_resource_len(pdev,3)); 350 351 if (card->plxbase == NULL || 352 card->scabase == NULL || 353 card->rambase == NULL) { 354 printk(KERN_ERR "pci200syn: ioremap() failed\n"); 355 pci200_pci_remove_one(pdev); 356 return -EFAULT; 357 } 358 359 /* Reset PLX */ 360 p = &card->plxbase->init_ctrl; 361 writel(readl(p) | 0x40000000, p); 362 readl(p); /* Flush the write - do not use sca_flush */ 363 udelay(1); 364 365 writel(readl(p) & ~0x40000000, p); 366 readl(p); /* Flush the write - do not use sca_flush */ 367 udelay(1); 368 369 ramsize = sca_detect_ram(card, card->rambase, 370 pci_resource_len(pdev, 3)); 371 372 /* number of TX + RX buffers for one port - this is dual port card */ 373 i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU)); 374 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS); 375 card->rx_ring_buffers = i - card->tx_ring_buffers; 376 377 card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers + 378 card->rx_ring_buffers); 379 380 printk(KERN_INFO "pci200syn: %u KB RAM at 0x%x, IRQ%u, using %u TX +" 381 " %u RX packets rings\n", ramsize / 1024, ramphys, 382 pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers); 383 384 if (pdev->subsystem_device == PCI_DEVICE_ID_PLX_9050) { 385 printk(KERN_ERR "Detected PCI200SYN card with old " 386 "configuration data.\n"); 387 printk(KERN_ERR "See <http://www.kernel.org/pub/" 388 "linux/utils/net/hdlc/pci200syn/> for update.\n"); 389 printk(KERN_ERR "The card will stop working with" 390 " future versions of Linux if not updated.\n"); 391 } 392 393 if (card->tx_ring_buffers < 1) { 394 printk(KERN_ERR "pci200syn: RAM test failed\n"); 395 pci200_pci_remove_one(pdev); 396 return -EFAULT; 397 } 398 399 /* Enable interrupts on the PCI bridge */ 400 p = &card->plxbase->intr_ctrl_stat; 401 writew(readw(p) | 0x0040, p); 402 403 /* Allocate IRQ */ 404 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, devname, card)) { 405 printk(KERN_WARNING "pci200syn: could not allocate IRQ%d.\n", 406 pdev->irq); 407 pci200_pci_remove_one(pdev); 408 return -EBUSY; 409 } 410 card->irq = pdev->irq; 411 412 sca_init(card, 0); 413 414 for (i = 0; i < 2; i++) { 415 port_t *port = &card->ports[i]; 416 struct net_device *dev = port_to_dev(port); 417 hdlc_device *hdlc = dev_to_hdlc(dev); 418 port->phy_node = i; 419 420 spin_lock_init(&port->lock); 421 SET_MODULE_OWNER(dev); 422 dev->irq = card->irq; 423 dev->mem_start = ramphys; 424 dev->mem_end = ramphys + ramsize - 1; 425 dev->tx_queue_len = 50; 426 dev->do_ioctl = pci200_ioctl; 427 dev->open = pci200_open; 428 dev->stop = pci200_close; 429 hdlc->attach = sca_attach; 430 hdlc->xmit = sca_xmit; 431 port->settings.clock_type = CLOCK_EXT; 432 port->card = card; 433 if (register_hdlc_device(dev)) { 434 printk(KERN_ERR "pci200syn: unable to register hdlc " 435 "device\n"); 436 port->card = NULL; 437 pci200_pci_remove_one(pdev); 438 return -ENOBUFS; 439 } 440 sca_init_sync_port(port); /* Set up SCA memory */ 441 442 printk(KERN_INFO "%s: PCI200SYN node %d\n", 443 dev->name, port->phy_node); 444 } 445 446 sca_flush(card); 447 return 0; 448} 449 450 451 452static struct pci_device_id pci200_pci_tbl[] __devinitdata = { 453 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX, 454 PCI_DEVICE_ID_PLX_9050, 0, 0, 0 }, 455 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX, 456 PCI_DEVICE_ID_PLX_PCI200SYN, 0, 0, 0 }, 457 { 0, } 458}; 459 460 461static struct pci_driver pci200_pci_driver = { 462 .name = "PCI200SYN", 463 .id_table = pci200_pci_tbl, 464 .probe = pci200_pci_init_one, 465 .remove = pci200_pci_remove_one, 466}; 467 468 469static int __init pci200_init_module(void) 470{ 471#ifdef MODULE 472 printk(KERN_INFO "%s\n", version); 473#endif 474 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) { 475 printk(KERN_ERR "pci200syn: Invalid PCI clock frequency\n"); 476 return -EINVAL; 477 } 478 return pci_register_driver(&pci200_pci_driver); 479} 480 481 482 483static void __exit pci200_cleanup_module(void) 484{ 485 pci_unregister_driver(&pci200_pci_driver); 486} 487 488MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 489MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver"); 490MODULE_LICENSE("GPL v2"); 491MODULE_DEVICE_TABLE(pci, pci200_pci_tbl); 492module_param(pci_clock_freq, int, 0444); 493MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz"); 494module_init(pci200_init_module); 495module_exit(pci200_cleanup_module); 496