wanxl.c revision a6b7a407865aab9f849dd99a71072b7cd1175116
1/* 2 * wanXL serial card driver for Linux 3 * host part 4 * 5 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of version 2 of the GNU General Public License 9 * as published by the Free Software Foundation. 10 * 11 * Status: 12 * - Only DTE (external clock) support with NRZ and NRZI encodings 13 * - wanXL100 will require minor driver modifications, no access to hw 14 */ 15 16#include <linux/module.h> 17#include <linux/kernel.h> 18#include <linux/slab.h> 19#include <linux/sched.h> 20#include <linux/types.h> 21#include <linux/fcntl.h> 22#include <linux/string.h> 23#include <linux/errno.h> 24#include <linux/init.h> 25#include <linux/interrupt.h> 26#include <linux/ioport.h> 27#include <linux/netdevice.h> 28#include <linux/hdlc.h> 29#include <linux/pci.h> 30#include <linux/dma-mapping.h> 31#include <linux/delay.h> 32#include <asm/io.h> 33 34#include "wanxl.h" 35 36static const char* version = "wanXL serial card driver version: 0.48"; 37 38#define PLX_CTL_RESET 0x40000000 /* adapter reset */ 39 40#undef DEBUG_PKT 41#undef DEBUG_PCI 42 43/* MAILBOX #1 - PUTS COMMANDS */ 44#define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */ 45#ifdef __LITTLE_ENDIAN 46#define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */ 47#else 48#define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */ 49#endif 50 51/* MAILBOX #2 - DRAM SIZE */ 52#define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */ 53 54 55typedef struct { 56 struct net_device *dev; 57 struct card_t *card; 58 spinlock_t lock; /* for wanxl_xmit */ 59 int node; /* physical port #0 - 3 */ 60 unsigned int clock_type; 61 int tx_in, tx_out; 62 struct sk_buff *tx_skbs[TX_BUFFERS]; 63}port_t; 64 65 66typedef struct { 67 desc_t rx_descs[RX_QUEUE_LENGTH]; 68 port_status_t port_status[4]; 69}card_status_t; 70 71 72typedef struct card_t { 73 int n_ports; /* 1, 2 or 4 ports */ 74 u8 irq; 75 76 u8 __iomem *plx; /* PLX PCI9060 virtual base address */ 77 struct pci_dev *pdev; /* for pci_name(pdev) */ 78 int rx_in; 79 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH]; 80 card_status_t *status; /* shared between host and card */ 81 dma_addr_t status_address; 82 port_t ports[0]; /* 1 - 4 port_t structures follow */ 83}card_t; 84 85 86 87static inline port_t* dev_to_port(struct net_device *dev) 88{ 89 return (port_t *)dev_to_hdlc(dev)->priv; 90} 91 92 93static inline port_status_t* get_status(port_t *port) 94{ 95 return &port->card->status->port_status[port->node]; 96} 97 98 99#ifdef DEBUG_PCI 100static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr, 101 size_t size, int direction) 102{ 103 dma_addr_t addr = pci_map_single(pdev, ptr, size, direction); 104 if (addr + size > 0x100000000LL) 105 printk(KERN_CRIT "wanXL %s: pci_map_single() returned memory" 106 " at 0x%LX!\n", pci_name(pdev), 107 (unsigned long long)addr); 108 return addr; 109} 110 111#undef pci_map_single 112#define pci_map_single pci_map_single_debug 113#endif 114 115 116/* Cable and/or personality module change interrupt service */ 117static inline void wanxl_cable_intr(port_t *port) 118{ 119 u32 value = get_status(port)->cable; 120 int valid = 1; 121 const char *cable, *pm, *dte = "", *dsr = "", *dcd = ""; 122 123 switch(value & 0x7) { 124 case STATUS_CABLE_V35: cable = "V.35"; break; 125 case STATUS_CABLE_X21: cable = "X.21"; break; 126 case STATUS_CABLE_V24: cable = "V.24"; break; 127 case STATUS_CABLE_EIA530: cable = "EIA530"; break; 128 case STATUS_CABLE_NONE: cable = "no"; break; 129 default: cable = "invalid"; 130 } 131 132 switch((value >> STATUS_CABLE_PM_SHIFT) & 0x7) { 133 case STATUS_CABLE_V35: pm = "V.35"; break; 134 case STATUS_CABLE_X21: pm = "X.21"; break; 135 case STATUS_CABLE_V24: pm = "V.24"; break; 136 case STATUS_CABLE_EIA530: pm = "EIA530"; break; 137 case STATUS_CABLE_NONE: pm = "no personality"; valid = 0; break; 138 default: pm = "invalid personality"; valid = 0; 139 } 140 141 if (valid) { 142 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) { 143 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" : 144 ", DSR off"; 145 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" : 146 ", carrier off"; 147 } 148 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE"; 149 } 150 printk(KERN_INFO "%s: %s%s module, %s cable%s%s\n", 151 port->dev->name, pm, dte, cable, dsr, dcd); 152 153 if (value & STATUS_CABLE_DCD) 154 netif_carrier_on(port->dev); 155 else 156 netif_carrier_off(port->dev); 157} 158 159 160 161/* Transmit complete interrupt service */ 162static inline void wanxl_tx_intr(port_t *port) 163{ 164 struct net_device *dev = port->dev; 165 while (1) { 166 desc_t *desc = &get_status(port)->tx_descs[port->tx_in]; 167 struct sk_buff *skb = port->tx_skbs[port->tx_in]; 168 169 switch (desc->stat) { 170 case PACKET_FULL: 171 case PACKET_EMPTY: 172 netif_wake_queue(dev); 173 return; 174 175 case PACKET_UNDERRUN: 176 dev->stats.tx_errors++; 177 dev->stats.tx_fifo_errors++; 178 break; 179 180 default: 181 dev->stats.tx_packets++; 182 dev->stats.tx_bytes += skb->len; 183 } 184 desc->stat = PACKET_EMPTY; /* Free descriptor */ 185 pci_unmap_single(port->card->pdev, desc->address, skb->len, 186 PCI_DMA_TODEVICE); 187 dev_kfree_skb_irq(skb); 188 port->tx_in = (port->tx_in + 1) % TX_BUFFERS; 189 } 190} 191 192 193 194/* Receive complete interrupt service */ 195static inline void wanxl_rx_intr(card_t *card) 196{ 197 desc_t *desc; 198 while (desc = &card->status->rx_descs[card->rx_in], 199 desc->stat != PACKET_EMPTY) { 200 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports) 201 printk(KERN_CRIT "wanXL %s: received packet for" 202 " nonexistent port\n", pci_name(card->pdev)); 203 else { 204 struct sk_buff *skb = card->rx_skbs[card->rx_in]; 205 port_t *port = &card->ports[desc->stat & 206 PACKET_PORT_MASK]; 207 struct net_device *dev = port->dev; 208 209 if (!skb) 210 dev->stats.rx_dropped++; 211 else { 212 pci_unmap_single(card->pdev, desc->address, 213 BUFFER_LENGTH, 214 PCI_DMA_FROMDEVICE); 215 skb_put(skb, desc->length); 216 217#ifdef DEBUG_PKT 218 printk(KERN_DEBUG "%s RX(%i):", dev->name, 219 skb->len); 220 debug_frame(skb); 221#endif 222 dev->stats.rx_packets++; 223 dev->stats.rx_bytes += skb->len; 224 skb->protocol = hdlc_type_trans(skb, dev); 225 netif_rx(skb); 226 skb = NULL; 227 } 228 229 if (!skb) { 230 skb = dev_alloc_skb(BUFFER_LENGTH); 231 desc->address = skb ? 232 pci_map_single(card->pdev, skb->data, 233 BUFFER_LENGTH, 234 PCI_DMA_FROMDEVICE) : 0; 235 card->rx_skbs[card->rx_in] = skb; 236 } 237 } 238 desc->stat = PACKET_EMPTY; /* Free descriptor */ 239 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH; 240 } 241} 242 243 244 245static irqreturn_t wanxl_intr(int irq, void* dev_id) 246{ 247 card_t *card = dev_id; 248 int i; 249 u32 stat; 250 int handled = 0; 251 252 253 while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) { 254 handled = 1; 255 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD); 256 257 for (i = 0; i < card->n_ports; i++) { 258 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i))) 259 wanxl_tx_intr(&card->ports[i]); 260 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i))) 261 wanxl_cable_intr(&card->ports[i]); 262 } 263 if (stat & (1 << DOORBELL_FROM_CARD_RX)) 264 wanxl_rx_intr(card); 265 } 266 267 return IRQ_RETVAL(handled); 268} 269 270 271 272static netdev_tx_t wanxl_xmit(struct sk_buff *skb, struct net_device *dev) 273{ 274 port_t *port = dev_to_port(dev); 275 desc_t *desc; 276 277 spin_lock(&port->lock); 278 279 desc = &get_status(port)->tx_descs[port->tx_out]; 280 if (desc->stat != PACKET_EMPTY) { 281 /* should never happen - previous xmit should stop queue */ 282#ifdef DEBUG_PKT 283 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name); 284#endif 285 netif_stop_queue(dev); 286 spin_unlock_irq(&port->lock); 287 return NETDEV_TX_BUSY; /* request packet to be queued */ 288 } 289 290#ifdef DEBUG_PKT 291 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); 292 debug_frame(skb); 293#endif 294 295 port->tx_skbs[port->tx_out] = skb; 296 desc->address = pci_map_single(port->card->pdev, skb->data, skb->len, 297 PCI_DMA_TODEVICE); 298 desc->length = skb->len; 299 desc->stat = PACKET_FULL; 300 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node), 301 port->card->plx + PLX_DOORBELL_TO_CARD); 302 303 port->tx_out = (port->tx_out + 1) % TX_BUFFERS; 304 305 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) { 306 netif_stop_queue(dev); 307#ifdef DEBUG_PKT 308 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name); 309#endif 310 } 311 312 spin_unlock(&port->lock); 313 return NETDEV_TX_OK; 314} 315 316 317 318static int wanxl_attach(struct net_device *dev, unsigned short encoding, 319 unsigned short parity) 320{ 321 port_t *port = dev_to_port(dev); 322 323 if (encoding != ENCODING_NRZ && 324 encoding != ENCODING_NRZI) 325 return -EINVAL; 326 327 if (parity != PARITY_NONE && 328 parity != PARITY_CRC32_PR1_CCITT && 329 parity != PARITY_CRC16_PR1_CCITT && 330 parity != PARITY_CRC32_PR0_CCITT && 331 parity != PARITY_CRC16_PR0_CCITT) 332 return -EINVAL; 333 334 get_status(port)->encoding = encoding; 335 get_status(port)->parity = parity; 336 return 0; 337} 338 339 340 341static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 342{ 343 const size_t size = sizeof(sync_serial_settings); 344 sync_serial_settings line; 345 port_t *port = dev_to_port(dev); 346 347 if (cmd != SIOCWANDEV) 348 return hdlc_ioctl(dev, ifr, cmd); 349 350 switch (ifr->ifr_settings.type) { 351 case IF_GET_IFACE: 352 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 353 if (ifr->ifr_settings.size < size) { 354 ifr->ifr_settings.size = size; /* data size wanted */ 355 return -ENOBUFS; 356 } 357 line.clock_type = get_status(port)->clocking; 358 line.clock_rate = 0; 359 line.loopback = 0; 360 361 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size)) 362 return -EFAULT; 363 return 0; 364 365 case IF_IFACE_SYNC_SERIAL: 366 if (!capable(CAP_NET_ADMIN)) 367 return -EPERM; 368 if (dev->flags & IFF_UP) 369 return -EBUSY; 370 371 if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync, 372 size)) 373 return -EFAULT; 374 375 if (line.clock_type != CLOCK_EXT && 376 line.clock_type != CLOCK_TXFROMRX) 377 return -EINVAL; /* No such clock setting */ 378 379 if (line.loopback != 0) 380 return -EINVAL; 381 382 get_status(port)->clocking = line.clock_type; 383 return 0; 384 385 default: 386 return hdlc_ioctl(dev, ifr, cmd); 387 } 388} 389 390 391 392static int wanxl_open(struct net_device *dev) 393{ 394 port_t *port = dev_to_port(dev); 395 u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD; 396 unsigned long timeout; 397 int i; 398 399 if (get_status(port)->open) { 400 printk(KERN_ERR "%s: port already open\n", dev->name); 401 return -EIO; 402 } 403 if ((i = hdlc_open(dev)) != 0) 404 return i; 405 406 port->tx_in = port->tx_out = 0; 407 for (i = 0; i < TX_BUFFERS; i++) 408 get_status(port)->tx_descs[i].stat = PACKET_EMPTY; 409 /* signal the card */ 410 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr); 411 412 timeout = jiffies + HZ; 413 do { 414 if (get_status(port)->open) { 415 netif_start_queue(dev); 416 return 0; 417 } 418 } while (time_after(timeout, jiffies)); 419 420 printk(KERN_ERR "%s: unable to open port\n", dev->name); 421 /* ask the card to close the port, should it be still alive */ 422 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr); 423 return -EFAULT; 424} 425 426 427 428static int wanxl_close(struct net_device *dev) 429{ 430 port_t *port = dev_to_port(dev); 431 unsigned long timeout; 432 int i; 433 434 hdlc_close(dev); 435 /* signal the card */ 436 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), 437 port->card->plx + PLX_DOORBELL_TO_CARD); 438 439 timeout = jiffies + HZ; 440 do { 441 if (!get_status(port)->open) 442 break; 443 } while (time_after(timeout, jiffies)); 444 445 if (get_status(port)->open) 446 printk(KERN_ERR "%s: unable to close port\n", dev->name); 447 448 netif_stop_queue(dev); 449 450 for (i = 0; i < TX_BUFFERS; i++) { 451 desc_t *desc = &get_status(port)->tx_descs[i]; 452 453 if (desc->stat != PACKET_EMPTY) { 454 desc->stat = PACKET_EMPTY; 455 pci_unmap_single(port->card->pdev, desc->address, 456 port->tx_skbs[i]->len, 457 PCI_DMA_TODEVICE); 458 dev_kfree_skb(port->tx_skbs[i]); 459 } 460 } 461 return 0; 462} 463 464 465 466static struct net_device_stats *wanxl_get_stats(struct net_device *dev) 467{ 468 port_t *port = dev_to_port(dev); 469 470 dev->stats.rx_over_errors = get_status(port)->rx_overruns; 471 dev->stats.rx_frame_errors = get_status(port)->rx_frame_errors; 472 dev->stats.rx_errors = dev->stats.rx_over_errors + 473 dev->stats.rx_frame_errors; 474 return &dev->stats; 475} 476 477 478 479static int wanxl_puts_command(card_t *card, u32 cmd) 480{ 481 unsigned long timeout = jiffies + 5 * HZ; 482 483 writel(cmd, card->plx + PLX_MAILBOX_1); 484 do { 485 if (readl(card->plx + PLX_MAILBOX_1) == 0) 486 return 0; 487 488 schedule(); 489 }while (time_after(timeout, jiffies)); 490 491 return -1; 492} 493 494 495 496static void wanxl_reset(card_t *card) 497{ 498 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET; 499 500 writel(0x80, card->plx + PLX_MAILBOX_0); 501 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL); 502 readl(card->plx + PLX_CONTROL); /* wait for posted write */ 503 udelay(1); 504 writel(old_value, card->plx + PLX_CONTROL); 505 readl(card->plx + PLX_CONTROL); /* wait for posted write */ 506} 507 508 509 510static void wanxl_pci_remove_one(struct pci_dev *pdev) 511{ 512 card_t *card = pci_get_drvdata(pdev); 513 int i; 514 515 for (i = 0; i < card->n_ports; i++) { 516 unregister_hdlc_device(card->ports[i].dev); 517 free_netdev(card->ports[i].dev); 518 } 519 520 /* unregister and free all host resources */ 521 if (card->irq) 522 free_irq(card->irq, card); 523 524 wanxl_reset(card); 525 526 for (i = 0; i < RX_QUEUE_LENGTH; i++) 527 if (card->rx_skbs[i]) { 528 pci_unmap_single(card->pdev, 529 card->status->rx_descs[i].address, 530 BUFFER_LENGTH, PCI_DMA_FROMDEVICE); 531 dev_kfree_skb(card->rx_skbs[i]); 532 } 533 534 if (card->plx) 535 iounmap(card->plx); 536 537 if (card->status) 538 pci_free_consistent(pdev, sizeof(card_status_t), 539 card->status, card->status_address); 540 541 pci_release_regions(pdev); 542 pci_disable_device(pdev); 543 pci_set_drvdata(pdev, NULL); 544 kfree(card); 545} 546 547 548#include "wanxlfw.inc" 549 550static const struct net_device_ops wanxl_ops = { 551 .ndo_open = wanxl_open, 552 .ndo_stop = wanxl_close, 553 .ndo_change_mtu = hdlc_change_mtu, 554 .ndo_start_xmit = hdlc_start_xmit, 555 .ndo_do_ioctl = wanxl_ioctl, 556 .ndo_get_stats = wanxl_get_stats, 557}; 558 559static int __devinit wanxl_pci_init_one(struct pci_dev *pdev, 560 const struct pci_device_id *ent) 561{ 562 card_t *card; 563 u32 ramsize, stat; 564 unsigned long timeout; 565 u32 plx_phy; /* PLX PCI base address */ 566 u32 mem_phy; /* memory PCI base addr */ 567 u8 __iomem *mem; /* memory virtual base addr */ 568 int i, ports, alloc_size; 569 570#ifndef MODULE 571 static int printed_version; 572 if (!printed_version) { 573 printed_version++; 574 printk(KERN_INFO "%s\n", version); 575 } 576#endif 577 578 i = pci_enable_device(pdev); 579 if (i) 580 return i; 581 582 /* QUICC can only access first 256 MB of host RAM directly, 583 but PLX9060 DMA does 32-bits for actual packet data transfers */ 584 585 /* FIXME when PCI/DMA subsystems are fixed. 586 We set both dma_mask and consistent_dma_mask to 28 bits 587 and pray pci_alloc_consistent() will use this info. It should 588 work on most platforms */ 589 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(28)) || 590 pci_set_dma_mask(pdev, DMA_BIT_MASK(28))) { 591 printk(KERN_ERR "wanXL: No usable DMA configuration\n"); 592 return -EIO; 593 } 594 595 i = pci_request_regions(pdev, "wanXL"); 596 if (i) { 597 pci_disable_device(pdev); 598 return i; 599 } 600 601 switch (pdev->device) { 602 case PCI_DEVICE_ID_SBE_WANXL100: ports = 1; break; 603 case PCI_DEVICE_ID_SBE_WANXL200: ports = 2; break; 604 default: ports = 4; 605 } 606 607 alloc_size = sizeof(card_t) + ports * sizeof(port_t); 608 card = kzalloc(alloc_size, GFP_KERNEL); 609 if (card == NULL) { 610 printk(KERN_ERR "wanXL %s: unable to allocate memory\n", 611 pci_name(pdev)); 612 pci_release_regions(pdev); 613 pci_disable_device(pdev); 614 return -ENOBUFS; 615 } 616 617 pci_set_drvdata(pdev, card); 618 card->pdev = pdev; 619 620 card->status = pci_alloc_consistent(pdev, sizeof(card_status_t), 621 &card->status_address); 622 if (card->status == NULL) { 623 wanxl_pci_remove_one(pdev); 624 return -ENOBUFS; 625 } 626 627#ifdef DEBUG_PCI 628 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory" 629 " at 0x%LX\n", pci_name(pdev), 630 (unsigned long long)card->status_address); 631#endif 632 633 /* FIXME when PCI/DMA subsystems are fixed. 634 We set both dma_mask and consistent_dma_mask back to 32 bits 635 to indicate the card can do 32-bit DMA addressing */ 636 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) || 637 pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 638 printk(KERN_ERR "wanXL: No usable DMA configuration\n"); 639 wanxl_pci_remove_one(pdev); 640 return -EIO; 641 } 642 643 /* set up PLX mapping */ 644 plx_phy = pci_resource_start(pdev, 0); 645 646 card->plx = ioremap_nocache(plx_phy, 0x70); 647 if (!card->plx) { 648 printk(KERN_ERR "wanxl: ioremap() failed\n"); 649 wanxl_pci_remove_one(pdev); 650 return -EFAULT; 651 } 652 653#if RESET_WHILE_LOADING 654 wanxl_reset(card); 655#endif 656 657 timeout = jiffies + 20 * HZ; 658 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) { 659 if (time_before(timeout, jiffies)) { 660 printk(KERN_WARNING "wanXL %s: timeout waiting for" 661 " PUTS to complete\n", pci_name(pdev)); 662 wanxl_pci_remove_one(pdev); 663 return -ENODEV; 664 } 665 666 switch(stat & 0xC0) { 667 case 0x00: /* hmm - PUTS completed with non-zero code? */ 668 case 0x80: /* PUTS still testing the hardware */ 669 break; 670 671 default: 672 printk(KERN_WARNING "wanXL %s: PUTS test 0x%X" 673 " failed\n", pci_name(pdev), stat & 0x30); 674 wanxl_pci_remove_one(pdev); 675 return -ENODEV; 676 } 677 678 schedule(); 679 } 680 681 /* get on-board memory size (PUTS detects no more than 4 MB) */ 682 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK; 683 684 /* set up on-board RAM mapping */ 685 mem_phy = pci_resource_start(pdev, 2); 686 687 688 /* sanity check the board's reported memory size */ 689 if (ramsize < BUFFERS_ADDR + 690 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) { 691 printk(KERN_WARNING "wanXL %s: no enough on-board RAM" 692 " (%u bytes detected, %u bytes required)\n", 693 pci_name(pdev), ramsize, BUFFERS_ADDR + 694 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports); 695 wanxl_pci_remove_one(pdev); 696 return -ENODEV; 697 } 698 699 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) { 700 printk(KERN_WARNING "wanXL %s: unable to Set Byte Swap" 701 " Mode\n", pci_name(pdev)); 702 wanxl_pci_remove_one(pdev); 703 return -ENODEV; 704 } 705 706 for (i = 0; i < RX_QUEUE_LENGTH; i++) { 707 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH); 708 card->rx_skbs[i] = skb; 709 if (skb) 710 card->status->rx_descs[i].address = 711 pci_map_single(card->pdev, skb->data, 712 BUFFER_LENGTH, 713 PCI_DMA_FROMDEVICE); 714 } 715 716 mem = ioremap_nocache(mem_phy, PDM_OFFSET + sizeof(firmware)); 717 if (!mem) { 718 printk(KERN_ERR "wanxl: ioremap() failed\n"); 719 wanxl_pci_remove_one(pdev); 720 return -EFAULT; 721 } 722 723 for (i = 0; i < sizeof(firmware); i += 4) 724 writel(ntohl(*(__be32*)(firmware + i)), mem + PDM_OFFSET + i); 725 726 for (i = 0; i < ports; i++) 727 writel(card->status_address + 728 (void *)&card->status->port_status[i] - 729 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4); 730 writel(card->status_address, mem + PDM_OFFSET + 20); 731 writel(PDM_OFFSET, mem); 732 iounmap(mem); 733 734 writel(0, card->plx + PLX_MAILBOX_5); 735 736 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) { 737 printk(KERN_WARNING "wanXL %s: unable to Abort and Jump\n", 738 pci_name(pdev)); 739 wanxl_pci_remove_one(pdev); 740 return -ENODEV; 741 } 742 743 stat = 0; 744 timeout = jiffies + 5 * HZ; 745 do { 746 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0) 747 break; 748 schedule(); 749 }while (time_after(timeout, jiffies)); 750 751 if (!stat) { 752 printk(KERN_WARNING "wanXL %s: timeout while initializing card " 753 "firmware\n", pci_name(pdev)); 754 wanxl_pci_remove_one(pdev); 755 return -ENODEV; 756 } 757 758#if DETECT_RAM 759 ramsize = stat; 760#endif 761 762 printk(KERN_INFO "wanXL %s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n", 763 pci_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq); 764 765 /* Allocate IRQ */ 766 if (request_irq(pdev->irq, wanxl_intr, IRQF_SHARED, "wanXL", card)) { 767 printk(KERN_WARNING "wanXL %s: could not allocate IRQ%i.\n", 768 pci_name(pdev), pdev->irq); 769 wanxl_pci_remove_one(pdev); 770 return -EBUSY; 771 } 772 card->irq = pdev->irq; 773 774 for (i = 0; i < ports; i++) { 775 hdlc_device *hdlc; 776 port_t *port = &card->ports[i]; 777 struct net_device *dev = alloc_hdlcdev(port); 778 if (!dev) { 779 printk(KERN_ERR "wanXL %s: unable to allocate" 780 " memory\n", pci_name(pdev)); 781 wanxl_pci_remove_one(pdev); 782 return -ENOMEM; 783 } 784 785 port->dev = dev; 786 hdlc = dev_to_hdlc(dev); 787 spin_lock_init(&port->lock); 788 dev->tx_queue_len = 50; 789 dev->netdev_ops = &wanxl_ops; 790 hdlc->attach = wanxl_attach; 791 hdlc->xmit = wanxl_xmit; 792 port->card = card; 793 port->node = i; 794 get_status(port)->clocking = CLOCK_EXT; 795 if (register_hdlc_device(dev)) { 796 printk(KERN_ERR "wanXL %s: unable to register hdlc" 797 " device\n", pci_name(pdev)); 798 free_netdev(dev); 799 wanxl_pci_remove_one(pdev); 800 return -ENOBUFS; 801 } 802 card->n_ports++; 803 } 804 805 printk(KERN_INFO "wanXL %s: port", pci_name(pdev)); 806 for (i = 0; i < ports; i++) 807 printk("%s #%i: %s", i ? "," : "", i, 808 card->ports[i].dev->name); 809 printk("\n"); 810 811 for (i = 0; i < ports; i++) 812 wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/ 813 814 return 0; 815} 816 817static DEFINE_PCI_DEVICE_TABLE(wanxl_pci_tbl) = { 818 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID, 819 PCI_ANY_ID, 0, 0, 0 }, 820 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID, 821 PCI_ANY_ID, 0, 0, 0 }, 822 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID, 823 PCI_ANY_ID, 0, 0, 0 }, 824 { 0, } 825}; 826 827 828static struct pci_driver wanxl_pci_driver = { 829 .name = "wanXL", 830 .id_table = wanxl_pci_tbl, 831 .probe = wanxl_pci_init_one, 832 .remove = wanxl_pci_remove_one, 833}; 834 835 836static int __init wanxl_init_module(void) 837{ 838#ifdef MODULE 839 printk(KERN_INFO "%s\n", version); 840#endif 841 return pci_register_driver(&wanxl_pci_driver); 842} 843 844static void __exit wanxl_cleanup_module(void) 845{ 846 pci_unregister_driver(&wanxl_pci_driver); 847} 848 849 850MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 851MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver"); 852MODULE_LICENSE("GPL v2"); 853MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl); 854 855module_init(wanxl_init_module); 856module_exit(wanxl_cleanup_module); 857