z85230.h revision 52e8a6a2d8dc19002d1757870d16051157ce999c
1/* 2 * Description of Z8530 Z85C30 and Z85230 communications chips 3 * 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1998 Alan Cox <alan@redhat.com> 6 */ 7 8#ifndef _Z8530_H 9#define _Z8530_H 10 11#include <linux/tty.h> 12#include <linux/interrupt.h> 13 14/* Conversion routines to/from brg time constants from/to bits 15 * per second. 16 */ 17#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) 18#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) 19 20/* The Zilog register set */ 21 22#define FLAG 0x7e 23 24/* Write Register 0 */ 25#define R0 0 /* Register selects */ 26#define R1 1 27#define R2 2 28#define R3 3 29#define R4 4 30#define R5 5 31#define R6 6 32#define R7 7 33#define R8 8 34#define R9 9 35#define R10 10 36#define R11 11 37#define R12 12 38#define R13 13 39#define R14 14 40#define R15 15 41 42#define RPRIME 16 /* Indicate a prime register access on 230 */ 43 44#define NULLCODE 0 /* Null Code */ 45#define POINT_HIGH 0x8 /* Select upper half of registers */ 46#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 47#define SEND_ABORT 0x18 /* HDLC Abort */ 48#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 49#define RES_Tx_P 0x28 /* Reset TxINT Pending */ 50#define ERR_RES 0x30 /* Error Reset */ 51#define RES_H_IUS 0x38 /* Reset highest IUS */ 52 53#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 54#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 55#define RES_EOM_L 0xC0 /* Reset EOM latch */ 56 57/* Write Register 1 */ 58 59#define EXT_INT_ENAB 0x1 /* Ext Int Enable */ 60#define TxINT_ENAB 0x2 /* Tx Int Enable */ 61#define PAR_SPEC 0x4 /* Parity is special condition */ 62 63#define RxINT_DISAB 0 /* Rx Int Disable */ 64#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ 65#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */ 66#define INT_ERR_Rx 0x18 /* Int on error only */ 67 68#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */ 69#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */ 70#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */ 71 72/* Write Register #2 (Interrupt Vector) */ 73 74/* Write Register 3 */ 75 76#define RxENABLE 0x1 /* Rx Enable */ 77#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ 78#define ADD_SM 0x4 /* Address Search Mode (SDLC) */ 79#define RxCRC_ENAB 0x8 /* Rx CRC Enable */ 80#define ENT_HM 0x10 /* Enter Hunt Mode */ 81#define AUTO_ENAB 0x20 /* Auto Enables */ 82#define Rx5 0x0 /* Rx 5 Bits/Character */ 83#define Rx7 0x40 /* Rx 7 Bits/Character */ 84#define Rx6 0x80 /* Rx 6 Bits/Character */ 85#define Rx8 0xc0 /* Rx 8 Bits/Character */ 86 87/* Write Register 4 */ 88 89#define PAR_ENA 0x1 /* Parity Enable */ 90#define PAR_EVEN 0x2 /* Parity Even/Odd* */ 91 92#define SYNC_ENAB 0 /* Sync Modes Enable */ 93#define SB1 0x4 /* 1 stop bit/char */ 94#define SB15 0x8 /* 1.5 stop bits/char */ 95#define SB2 0xc /* 2 stop bits/char */ 96 97#define MONSYNC 0 /* 8 Bit Sync character */ 98#define BISYNC 0x10 /* 16 bit sync character */ 99#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ 100#define EXTSYNC 0x30 /* External Sync Mode */ 101 102#define X1CLK 0x0 /* x1 clock mode */ 103#define X16CLK 0x40 /* x16 clock mode */ 104#define X32CLK 0x80 /* x32 clock mode */ 105#define X64CLK 0xC0 /* x64 clock mode */ 106 107/* Write Register 5 */ 108 109#define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 110#define RTS 0x2 /* RTS */ 111#define SDLC_CRC 0x4 /* SDLC/CRC-16 */ 112#define TxENAB 0x8 /* Tx Enable */ 113#define SND_BRK 0x10 /* Send Break */ 114#define Tx5 0x0 /* Tx 5 bits (or less)/character */ 115#define Tx7 0x20 /* Tx 7 bits/character */ 116#define Tx6 0x40 /* Tx 6 bits/character */ 117#define Tx8 0x60 /* Tx 8 bits/character */ 118#define DTR 0x80 /* DTR */ 119 120/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ 121 122/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ 123 124/* Write Register 8 (transmit buffer) */ 125 126/* Write Register 9 (Master interrupt control) */ 127#define VIS 1 /* Vector Includes Status */ 128#define NV 2 /* No Vector */ 129#define DLC 4 /* Disable Lower Chain */ 130#define MIE 8 /* Master Interrupt Enable */ 131#define STATHI 0x10 /* Status high */ 132#define NORESET 0 /* No reset on write to R9 */ 133#define CHRB 0x40 /* Reset channel B */ 134#define CHRA 0x80 /* Reset channel A */ 135#define FHWRES 0xc0 /* Force hardware reset */ 136 137/* Write Register 10 (misc control bits) */ 138#define BIT6 1 /* 6 bit/8bit sync */ 139#define LOOPMODE 2 /* SDLC Loop mode */ 140#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */ 141#define MARKIDLE 8 /* Mark/flag on idle */ 142#define GAOP 0x10 /* Go active on poll */ 143#define NRZ 0 /* NRZ mode */ 144#define NRZI 0x20 /* NRZI mode */ 145#define FM1 0x40 /* FM1 (transition = 1) */ 146#define FM0 0x60 /* FM0 (transition = 0) */ 147#define CRCPS 0x80 /* CRC Preset I/O */ 148 149/* Write Register 11 (Clock Mode control) */ 150#define TRxCXT 0 /* TRxC = Xtal output */ 151#define TRxCTC 1 /* TRxC = Transmit clock */ 152#define TRxCBR 2 /* TRxC = BR Generator Output */ 153#define TRxCDP 3 /* TRxC = DPLL output */ 154#define TRxCOI 4 /* TRxC O/I */ 155#define TCRTxCP 0 /* Transmit clock = RTxC pin */ 156#define TCTRxCP 8 /* Transmit clock = TRxC pin */ 157#define TCBR 0x10 /* Transmit clock = BR Generator output */ 158#define TCDPLL 0x18 /* Transmit clock = DPLL output */ 159#define RCRTxCP 0 /* Receive clock = RTxC pin */ 160#define RCTRxCP 0x20 /* Receive clock = TRxC pin */ 161#define RCBR 0x40 /* Receive clock = BR Generator output */ 162#define RCDPLL 0x60 /* Receive clock = DPLL output */ 163#define RTxCX 0x80 /* RTxC Xtal/No Xtal */ 164 165/* Write Register 12 (lower byte of baud rate generator time constant) */ 166 167/* Write Register 13 (upper byte of baud rate generator time constant) */ 168 169/* Write Register 14 (Misc control bits) */ 170#define BRENABL 1 /* Baud rate generator enable */ 171#define BRSRC 2 /* Baud rate generator source */ 172#define DTRREQ 4 /* DTR/Request function */ 173#define AUTOECHO 8 /* Auto Echo */ 174#define LOOPBAK 0x10 /* Local loopback */ 175#define SEARCH 0x20 /* Enter search mode */ 176#define RMC 0x40 /* Reset missing clock */ 177#define DISDPLL 0x60 /* Disable DPLL */ 178#define SSBR 0x80 /* Set DPLL source = BR generator */ 179#define SSRTxC 0xa0 /* Set DPLL source = RTxC */ 180#define SFMM 0xc0 /* Set FM mode */ 181#define SNRZI 0xe0 /* Set NRZI mode */ 182 183/* Write Register 15 (external/status interrupt control) */ 184#define PRIME 1 /* R5' etc register access (Z85C30/230 only) */ 185#define ZCIE 2 /* Zero count IE */ 186#define FIFOE 4 /* Z85230 only */ 187#define DCDIE 8 /* DCD IE */ 188#define SYNCIE 0x10 /* Sync/hunt IE */ 189#define CTSIE 0x20 /* CTS IE */ 190#define TxUIE 0x40 /* Tx Underrun/EOM IE */ 191#define BRKIE 0x80 /* Break/Abort IE */ 192 193 194/* Read Register 0 */ 195#define Rx_CH_AV 0x1 /* Rx Character Available */ 196#define ZCOUNT 0x2 /* Zero count */ 197#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */ 198#define DCD 0x8 /* DCD */ 199#define SYNC_HUNT 0x10 /* Sync/hunt */ 200#define CTS 0x20 /* CTS */ 201#define TxEOM 0x40 /* Tx underrun */ 202#define BRK_ABRT 0x80 /* Break/Abort */ 203 204/* Read Register 1 */ 205#define ALL_SNT 0x1 /* All sent */ 206/* Residue Data for 8 Rx bits/char programmed */ 207#define RES3 0x8 /* 0/3 */ 208#define RES4 0x4 /* 0/4 */ 209#define RES5 0xc /* 0/5 */ 210#define RES6 0x2 /* 0/6 */ 211#define RES7 0xa /* 0/7 */ 212#define RES8 0x6 /* 0/8 */ 213#define RES18 0xe /* 1/8 */ 214#define RES28 0x0 /* 2/8 */ 215/* Special Rx Condition Interrupts */ 216#define PAR_ERR 0x10 /* Parity error */ 217#define Rx_OVR 0x20 /* Rx Overrun Error */ 218#define CRC_ERR 0x40 /* CRC/Framing Error */ 219#define END_FR 0x80 /* End of Frame (SDLC) */ 220 221/* Read Register 2 (channel b only) - Interrupt vector */ 222 223/* Read Register 3 (interrupt pending register) ch a only */ 224#define CHBEXT 0x1 /* Channel B Ext/Stat IP */ 225#define CHBTxIP 0x2 /* Channel B Tx IP */ 226#define CHBRxIP 0x4 /* Channel B Rx IP */ 227#define CHAEXT 0x8 /* Channel A Ext/Stat IP */ 228#define CHATxIP 0x10 /* Channel A Tx IP */ 229#define CHARxIP 0x20 /* Channel A Rx IP */ 230 231/* Read Register 8 (receive data register) */ 232 233/* Read Register 10 (misc status bits) */ 234#define ONLOOP 2 /* On loop */ 235#define LOOPSEND 0x10 /* Loop sending */ 236#define CLK2MIS 0x40 /* Two clocks missing */ 237#define CLK1MIS 0x80 /* One clock missing */ 238 239/* Read Register 12 (lower byte of baud rate generator constant) */ 240 241/* Read Register 13 (upper byte of baud rate generator constant) */ 242 243/* Read Register 15 (value of WR 15) */ 244 245 246/* 247 * Interrupt handling functions for this SCC 248 */ 249 250struct z8530_channel; 251 252struct z8530_irqhandler 253{ 254 void (*rx)(struct z8530_channel *); 255 void (*tx)(struct z8530_channel *); 256 void (*status)(struct z8530_channel *); 257}; 258 259/* 260 * A channel of the Z8530 261 */ 262 263struct z8530_channel 264{ 265 struct z8530_irqhandler *irqs; /* IRQ handlers */ 266 /* 267 * Synchronous 268 */ 269 u16 count; /* Buyes received */ 270 u16 max; /* Most we can receive this frame */ 271 u16 mtu; /* MTU of the device */ 272 u8 *dptr; /* Pointer into rx buffer */ 273 struct sk_buff *skb; /* Buffer dptr points into */ 274 struct sk_buff *skb2; /* Pending buffer */ 275 u8 status; /* Current DCD */ 276 u8 dcdcheck; /* which bit to check for line */ 277 u8 sync; /* Set if in sync mode */ 278 279 u8 regs[32]; /* Register map for the chip */ 280 u8 pendregs[32]; /* Pending register values */ 281 282 struct sk_buff *tx_skb; /* Buffer being transmitted */ 283 struct sk_buff *tx_next_skb; /* Next transmit buffer */ 284 u8 *tx_ptr; /* Byte pointer into the buffer */ 285 u8 *tx_next_ptr; /* Next pointer to use */ 286 u8 *tx_dma_buf[2]; /* TX flip buffers for DMA */ 287 u8 tx_dma_used; /* Flip buffer usage toggler */ 288 u16 txcount; /* Count of bytes to transmit */ 289 290 void (*rx_function)(struct z8530_channel *, struct sk_buff *); 291 292 /* 293 * Sync DMA 294 */ 295 296 u8 rxdma; /* DMA channels */ 297 u8 txdma; 298 u8 rxdma_on; /* DMA active if flag set */ 299 u8 txdma_on; 300 u8 dma_num; /* Buffer we are DMAing into */ 301 u8 dma_ready; /* Is the other buffer free */ 302 u8 dma_tx; /* TX is to use DMA */ 303 u8 *rx_buf[2]; /* The flip buffers */ 304 305 /* 306 * System 307 */ 308 309 struct z8530_dev *dev; /* Z85230 chip instance we are from */ 310 unsigned long ctrlio; /* I/O ports */ 311 unsigned long dataio; 312 313 /* 314 * For PC we encode this way. 315 */ 316#define Z8530_PORT_SLEEP 0x80000000 317#define Z8530_PORT_OF(x) ((x)&0xFFFF) 318 319 u32 rx_overrun; /* Overruns - not done yet */ 320 u32 rx_crc_err; 321 322 /* 323 * Bound device pointers 324 */ 325 326 void *private; /* For our owner */ 327 struct net_device *netdevice; /* Network layer device */ 328 329 /* 330 * Async features 331 */ 332 333 struct tty_struct *tty; /* Attached terminal */ 334 int line; /* Minor number */ 335 wait_queue_head_t open_wait; /* Tasks waiting to open */ 336 wait_queue_head_t close_wait; /* and for close to end */ 337 unsigned long event; /* Pending events */ 338 int fdcount; /* # of fd on device */ 339 int blocked_open; /* # of blocked opens */ 340 int x_char; /* XON/XOF char */ 341 unsigned char *xmit_buf; /* Transmit pointer */ 342 int xmit_head; /* Transmit ring */ 343 int xmit_tail; 344 int xmit_cnt; 345 int flags; 346 int timeout; 347 int xmit_fifo_size; /* Transmit FIFO info */ 348 349 int close_delay; /* Do we wait for drain on close ? */ 350 unsigned short closing_wait; 351 352 /* We need to know the current clock divisor 353 * to read the bps rate the chip has currently 354 * loaded. 355 */ 356 357 unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */ 358 int zs_baud; 359 360 int magic; 361 int baud_base; /* Baud parameters */ 362 int custom_divisor; 363 364 365 unsigned char tx_active; /* character is being xmitted */ 366 unsigned char tx_stopped; /* output is suspended */ 367 368 spinlock_t *lock; /* Device lock */ 369}; 370 371/* 372 * Each Z853x0 device. 373 */ 374 375struct z8530_dev 376{ 377 char *name; /* Device instance name */ 378 struct z8530_channel chanA; /* SCC channel A */ 379 struct z8530_channel chanB; /* SCC channel B */ 380 int type; 381#define Z8530 0 /* NMOS dinosaur */ 382#define Z85C30 1 /* CMOS - better */ 383#define Z85230 2 /* CMOS with real FIFO */ 384 int irq; /* Interrupt for the device */ 385 int active; /* Soft interrupt enable - the Mac doesn't 386 always have a hard disable on its 8530s... */ 387 spinlock_t lock; 388}; 389 390 391/* 392 * Functions 393 */ 394 395extern u8 z8530_dead_port[]; 396extern u8 z8530_hdlc_kilostream_85230[]; 397extern u8 z8530_hdlc_kilostream[]; 398extern irqreturn_t z8530_interrupt(int, void *); 399extern void z8530_describe(struct z8530_dev *, char *mapping, unsigned long io); 400extern int z8530_init(struct z8530_dev *); 401extern int z8530_shutdown(struct z8530_dev *); 402extern int z8530_sync_open(struct net_device *, struct z8530_channel *); 403extern int z8530_sync_close(struct net_device *, struct z8530_channel *); 404extern int z8530_sync_dma_open(struct net_device *, struct z8530_channel *); 405extern int z8530_sync_dma_close(struct net_device *, struct z8530_channel *); 406extern int z8530_sync_txdma_open(struct net_device *, struct z8530_channel *); 407extern int z8530_sync_txdma_close(struct net_device *, struct z8530_channel *); 408extern int z8530_channel_load(struct z8530_channel *, u8 *); 409extern int z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb); 410extern void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb); 411 412 413/* 414 * Standard interrupt vector sets 415 */ 416 417extern struct z8530_irqhandler z8530_sync, z8530_async, z8530_nop; 418 419/* 420 * Asynchronous Interfacing 421 */ 422 423#define SERIAL_MAGIC 0x5301 424 425/* 426 * The size of the serial xmit buffer is 1 page, or 4096 bytes 427 */ 428 429#define SERIAL_XMIT_SIZE 4096 430#define WAKEUP_CHARS 256 431 432/* 433 * Events are used to schedule things to happen at timer-interrupt 434 * time, instead of at rs interrupt time. 435 */ 436#define RS_EVENT_WRITE_WAKEUP 0 437 438/* Internal flags used only by kernel/chr_drv/serial.c */ 439#define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */ 440#define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */ 441#define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */ 442#define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */ 443#define ZILOG_CLOSING 0x08000000 /* Serial port is closing */ 444#define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */ 445#define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */ 446 447#endif /* !(_Z8530_H) */ 448