1/* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _CE_H_ 19#define _CE_H_ 20 21#include "hif.h" 22 23/* Maximum number of Copy Engine's supported */ 24#define CE_COUNT_MAX 8 25#define CE_HTT_H2T_MSG_SRC_NENTRIES 4096 26 27/* Descriptor rings must be aligned to this boundary */ 28#define CE_DESC_RING_ALIGN 8 29#define CE_SEND_FLAG_GATHER 0x00010000 30 31/* 32 * Copy Engine support: low-level Target-side Copy Engine API. 33 * This is a hardware access layer used by code that understands 34 * how to use copy engines. 35 */ 36 37struct ath10k_ce_pipe; 38 39#define CE_DESC_FLAGS_GATHER (1 << 0) 40#define CE_DESC_FLAGS_BYTE_SWAP (1 << 1) 41#define CE_DESC_FLAGS_META_DATA_MASK 0xFFFC 42#define CE_DESC_FLAGS_META_DATA_LSB 3 43 44struct ce_desc { 45 __le32 addr; 46 __le16 nbytes; 47 __le16 flags; /* %CE_DESC_FLAGS_ */ 48}; 49 50struct ath10k_ce_ring { 51 /* Number of entries in this ring; must be power of 2 */ 52 unsigned int nentries; 53 unsigned int nentries_mask; 54 55 /* 56 * For dest ring, this is the next index to be processed 57 * by software after it was/is received into. 58 * 59 * For src ring, this is the last descriptor that was sent 60 * and completion processed by software. 61 * 62 * Regardless of src or dest ring, this is an invariant 63 * (modulo ring size): 64 * write index >= read index >= sw_index 65 */ 66 unsigned int sw_index; 67 /* cached copy */ 68 unsigned int write_index; 69 /* 70 * For src ring, this is the next index not yet processed by HW. 71 * This is a cached copy of the real HW index (read index), used 72 * for avoiding reading the HW index register more often than 73 * necessary. 74 * This extends the invariant: 75 * write index >= read index >= hw_index >= sw_index 76 * 77 * For dest ring, this is currently unused. 78 */ 79 /* cached copy */ 80 unsigned int hw_index; 81 82 /* Start of DMA-coherent area reserved for descriptors */ 83 /* Host address space */ 84 void *base_addr_owner_space_unaligned; 85 /* CE address space */ 86 u32 base_addr_ce_space_unaligned; 87 88 /* 89 * Actual start of descriptors. 90 * Aligned to descriptor-size boundary. 91 * Points into reserved DMA-coherent area, above. 92 */ 93 /* Host address space */ 94 void *base_addr_owner_space; 95 96 /* CE address space */ 97 u32 base_addr_ce_space; 98 /* 99 * Start of shadow copy of descriptors, within regular memory. 100 * Aligned to descriptor-size boundary. 101 */ 102 void *shadow_base_unaligned; 103 struct ce_desc *shadow_base; 104 105 /* keep last */ 106 void *per_transfer_context[0]; 107}; 108 109struct ath10k_ce_pipe { 110 struct ath10k *ar; 111 unsigned int id; 112 113 unsigned int attr_flags; 114 115 u32 ctrl_addr; 116 117 void (*send_cb)(struct ath10k_ce_pipe *); 118 void (*recv_cb)(struct ath10k_ce_pipe *); 119 120 unsigned int src_sz_max; 121 struct ath10k_ce_ring *src_ring; 122 struct ath10k_ce_ring *dest_ring; 123}; 124 125/* Copy Engine settable attributes */ 126struct ce_attr; 127 128/*==================Send====================*/ 129 130/* ath10k_ce_send flags */ 131#define CE_SEND_FLAG_BYTE_SWAP 1 132 133/* 134 * Queue a source buffer to be sent to an anonymous destination buffer. 135 * ce - which copy engine to use 136 * buffer - address of buffer 137 * nbytes - number of bytes to send 138 * transfer_id - arbitrary ID; reflected to destination 139 * flags - CE_SEND_FLAG_* values 140 * Returns 0 on success; otherwise an error status. 141 * 142 * Note: If no flags are specified, use CE's default data swap mode. 143 * 144 * Implementation note: pushes 1 buffer to Source ring 145 */ 146int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 147 void *per_transfer_send_context, 148 u32 buffer, 149 unsigned int nbytes, 150 /* 14 bits */ 151 unsigned int transfer_id, 152 unsigned int flags); 153 154int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, 155 void *per_transfer_context, 156 u32 buffer, 157 unsigned int nbytes, 158 unsigned int transfer_id, 159 unsigned int flags); 160 161void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe); 162 163int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe); 164 165/*==================Recv=======================*/ 166 167int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe); 168int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr); 169int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr); 170 171/* recv flags */ 172/* Data is byte-swapped */ 173#define CE_RECV_FLAG_SWAPPED 1 174 175/* 176 * Supply data for the next completed unprocessed receive descriptor. 177 * Pops buffer from Dest ring. 178 */ 179int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, 180 void **per_transfer_contextp, 181 u32 *bufferp, 182 unsigned int *nbytesp, 183 unsigned int *transfer_idp, 184 unsigned int *flagsp); 185/* 186 * Supply data for the next completed unprocessed send descriptor. 187 * Pops 1 completed send buffer from Source ring. 188 */ 189int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 190 void **per_transfer_contextp, 191 u32 *bufferp, 192 unsigned int *nbytesp, 193 unsigned int *transfer_idp); 194 195/*==================CE Engine Initialization=======================*/ 196 197int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id, 198 const struct ce_attr *attr, 199 void (*send_cb)(struct ath10k_ce_pipe *), 200 void (*recv_cb)(struct ath10k_ce_pipe *)); 201void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id); 202int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, 203 const struct ce_attr *attr); 204void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id); 205 206/*==================CE Engine Shutdown=======================*/ 207/* 208 * Support clean shutdown by allowing the caller to revoke 209 * receive buffers. Target DMA must be stopped before using 210 * this API. 211 */ 212int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 213 void **per_transfer_contextp, 214 u32 *bufferp); 215 216/* 217 * Support clean shutdown by allowing the caller to cancel 218 * pending sends. Target DMA must be stopped before using 219 * this API. 220 */ 221int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 222 void **per_transfer_contextp, 223 u32 *bufferp, 224 unsigned int *nbytesp, 225 unsigned int *transfer_idp); 226 227/*==================CE Interrupt Handlers====================*/ 228void ath10k_ce_per_engine_service_any(struct ath10k *ar); 229void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id); 230int ath10k_ce_disable_interrupts(struct ath10k *ar); 231void ath10k_ce_enable_interrupts(struct ath10k *ar); 232 233/* ce_attr.flags values */ 234/* Use NonSnooping PCIe accesses? */ 235#define CE_ATTR_NO_SNOOP 1 236 237/* Byte swap data words */ 238#define CE_ATTR_BYTE_SWAP_DATA 2 239 240/* Swizzle descriptors? */ 241#define CE_ATTR_SWIZZLE_DESCRIPTORS 4 242 243/* no interrupt on copy completion */ 244#define CE_ATTR_DIS_INTR 8 245 246/* Attributes of an instance of a Copy Engine */ 247struct ce_attr { 248 /* CE_ATTR_* values */ 249 unsigned int flags; 250 251 /* #entries in source ring - Must be a power of 2 */ 252 unsigned int src_nentries; 253 254 /* 255 * Max source send size for this CE. 256 * This is also the minimum size of a destination buffer. 257 */ 258 unsigned int src_sz_max; 259 260 /* #entries in destination ring - Must be a power of 2 */ 261 unsigned int dest_nentries; 262}; 263 264#define SR_BA_ADDRESS 0x0000 265#define SR_SIZE_ADDRESS 0x0004 266#define DR_BA_ADDRESS 0x0008 267#define DR_SIZE_ADDRESS 0x000c 268#define CE_CMD_ADDRESS 0x0018 269 270#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17 271#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 272#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 273#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 274 (((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 275 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 276 277#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16 278#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 279#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 280#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \ 281 (((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \ 282 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 283#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 284 (((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 285 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 286 287#define CE_CTRL1_DMAX_LENGTH_MSB 15 288#define CE_CTRL1_DMAX_LENGTH_LSB 0 289#define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff 290#define CE_CTRL1_DMAX_LENGTH_GET(x) \ 291 (((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB) 292#define CE_CTRL1_DMAX_LENGTH_SET(x) \ 293 (((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 294 295#define CE_CTRL1_ADDRESS 0x0010 296#define CE_CTRL1_HW_MASK 0x0007ffff 297#define CE_CTRL1_SW_MASK 0x0007ffff 298#define CE_CTRL1_HW_WRITE_MASK 0x00000000 299#define CE_CTRL1_SW_WRITE_MASK 0x0007ffff 300#define CE_CTRL1_RSTMASK 0xffffffff 301#define CE_CTRL1_RESET 0x00000080 302 303#define CE_CMD_HALT_STATUS_MSB 3 304#define CE_CMD_HALT_STATUS_LSB 3 305#define CE_CMD_HALT_STATUS_MASK 0x00000008 306#define CE_CMD_HALT_STATUS_GET(x) \ 307 (((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB) 308#define CE_CMD_HALT_STATUS_SET(x) \ 309 (((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK) 310#define CE_CMD_HALT_STATUS_RESET 0 311#define CE_CMD_HALT_MSB 0 312#define CE_CMD_HALT_MASK 0x00000001 313 314#define HOST_IE_COPY_COMPLETE_MSB 0 315#define HOST_IE_COPY_COMPLETE_LSB 0 316#define HOST_IE_COPY_COMPLETE_MASK 0x00000001 317#define HOST_IE_COPY_COMPLETE_GET(x) \ 318 (((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB) 319#define HOST_IE_COPY_COMPLETE_SET(x) \ 320 (((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK) 321#define HOST_IE_COPY_COMPLETE_RESET 0 322#define HOST_IE_ADDRESS 0x002c 323 324#define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 325#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 326#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 327#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 328#define HOST_IS_COPY_COMPLETE_MASK 0x00000001 329#define HOST_IS_ADDRESS 0x0030 330 331#define MISC_IE_ADDRESS 0x0034 332 333#define MISC_IS_AXI_ERR_MASK 0x00000400 334 335#define MISC_IS_DST_ADDR_ERR_MASK 0x00000200 336#define MISC_IS_SRC_LEN_ERR_MASK 0x00000100 337#define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 338#define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 339#define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 340 341#define MISC_IS_ADDRESS 0x0038 342 343#define SR_WR_INDEX_ADDRESS 0x003c 344 345#define DST_WR_INDEX_ADDRESS 0x0040 346 347#define CURRENT_SRRI_ADDRESS 0x0044 348 349#define CURRENT_DRRI_ADDRESS 0x0048 350 351#define SRC_WATERMARK_LOW_MSB 31 352#define SRC_WATERMARK_LOW_LSB 16 353#define SRC_WATERMARK_LOW_MASK 0xffff0000 354#define SRC_WATERMARK_LOW_GET(x) \ 355 (((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB) 356#define SRC_WATERMARK_LOW_SET(x) \ 357 (((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 358#define SRC_WATERMARK_LOW_RESET 0 359#define SRC_WATERMARK_HIGH_MSB 15 360#define SRC_WATERMARK_HIGH_LSB 0 361#define SRC_WATERMARK_HIGH_MASK 0x0000ffff 362#define SRC_WATERMARK_HIGH_GET(x) \ 363 (((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB) 364#define SRC_WATERMARK_HIGH_SET(x) \ 365 (((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 366#define SRC_WATERMARK_HIGH_RESET 0 367#define SRC_WATERMARK_ADDRESS 0x004c 368 369#define DST_WATERMARK_LOW_LSB 16 370#define DST_WATERMARK_LOW_MASK 0xffff0000 371#define DST_WATERMARK_LOW_SET(x) \ 372 (((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 373#define DST_WATERMARK_LOW_RESET 0 374#define DST_WATERMARK_HIGH_MSB 15 375#define DST_WATERMARK_HIGH_LSB 0 376#define DST_WATERMARK_HIGH_MASK 0x0000ffff 377#define DST_WATERMARK_HIGH_GET(x) \ 378 (((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB) 379#define DST_WATERMARK_HIGH_SET(x) \ 380 (((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 381#define DST_WATERMARK_HIGH_RESET 0 382#define DST_WATERMARK_ADDRESS 0x0050 383 384static inline u32 ath10k_ce_base_address(unsigned int ce_id) 385{ 386 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id; 387} 388 389#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \ 390 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \ 391 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \ 392 HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 393 394#define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \ 395 MISC_IS_DST_ADDR_ERR_MASK | \ 396 MISC_IS_SRC_LEN_ERR_MASK | \ 397 MISC_IS_DST_MAX_LEN_VIO_MASK | \ 398 MISC_IS_DST_RING_OVERFLOW_MASK | \ 399 MISC_IS_SRC_RING_OVERFLOW_MASK) 400 401#define CE_SRC_RING_TO_DESC(baddr, idx) \ 402 (&(((struct ce_desc *)baddr)[idx])) 403 404#define CE_DEST_RING_TO_DESC(baddr, idx) \ 405 (&(((struct ce_desc *)baddr)[idx])) 406 407/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ 408#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ 409 (((int)(toidx)-(int)(fromidx)) & (nentries_mask)) 410 411#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 412 413#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8 414#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00 415#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ 416 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 417 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 418#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 419 420#define CE_INTERRUPT_SUMMARY(ar) \ 421 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ 422 ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \ 423 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)) 424 425#endif /* _CE_H_ */ 426