ath5k.h revision 26c7fc436422de5d6d2b491f777e965e96f5c3a2
1/* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _ATH5K_H 19#define _ATH5K_H 20 21/* TODO: Clean up channel debuging -doesn't work anyway- and start 22 * working on reg. control code using all available eeprom information 23 * -rev. engineering needed- */ 24#define CHAN_DEBUG 0 25 26#include <linux/io.h> 27#include <linux/types.h> 28#include <linux/average.h> 29#include <net/mac80211.h> 30 31/* RX/TX descriptor hw structs 32 * TODO: Driver part should only see sw structs */ 33#include "desc.h" 34 35/* EEPROM structs/offsets 36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 37 * and clean up common bits, then introduce set/get functions in eeprom.c */ 38#include "eeprom.h" 39#include "../ath.h" 40 41/* PCI IDs */ 42#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 43#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 44#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 45#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 46#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 47#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 48#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 49#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 50#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 51#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 52#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 53#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 54#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 55#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 58#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 59#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 60#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 61#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 62#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 63#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 64#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 65#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 66#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 67#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 68#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 69#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 70 71/****************************\ 72 GENERIC DRIVER DEFINITIONS 73\****************************/ 74 75#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 76 77#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 78 printk(_level "ath5k %s: " _fmt, \ 79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 80 ##__VA_ARGS__) 81 82#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 83 if (net_ratelimit()) \ 84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 85 } while (0) 86 87#define ATH5K_INFO(_sc, _fmt, ...) \ 88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 89 90#define ATH5K_WARN(_sc, _fmt, ...) \ 91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 92 93#define ATH5K_ERR(_sc, _fmt, ...) \ 94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 95 96/* 97 * AR5K REGISTER ACCESS 98 */ 99 100/* Some macros to read/write fields */ 101 102/* First shift, then mask */ 103#define AR5K_REG_SM(_val, _flags) \ 104 (((_val) << _flags##_S) & (_flags)) 105 106/* First mask, then shift */ 107#define AR5K_REG_MS(_val, _flags) \ 108 (((_val) & (_flags)) >> _flags##_S) 109 110/* Some registers can hold multiple values of interest. For this 111 * reason when we want to write to these registers we must first 112 * retrieve the values which we do not want to clear (lets call this 113 * old_data) and then set the register with this and our new_value: 114 * ( old_data | new_value) */ 115#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 117 (((_val) << _flags##_S) & (_flags)), _reg) 118 119#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 121 (_mask)) | (_flags), _reg) 122 123#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 125 126#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 128 129/* Access to PHY registers */ 130#define AR5K_PHY_READ(ah, _reg) \ 131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 132 133#define AR5K_PHY_WRITE(ah, _reg, _val) \ 134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 135 136/* Access QCU registers per queue */ 137#define AR5K_REG_READ_Q(ah, _reg, _queue) \ 138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 139 140#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 141 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 142 143#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 144 _reg |= 1 << _queue; \ 145} while (0) 146 147#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 148 _reg &= ~(1 << _queue); \ 149} while (0) 150 151/* Used while writing initvals */ 152#define AR5K_REG_WAIT(_i) do { \ 153 if (_i % 64) \ 154 udelay(1); \ 155} while (0) 156 157/* Register dumps are done per operation mode */ 158#define AR5K_INI_RFGAIN_5GHZ 0 159#define AR5K_INI_RFGAIN_2GHZ 1 160 161/* 162 * Some tuneable values (these should be changeable by the user) 163 * TODO: Make use of them and add more options OR use debug/configfs 164 */ 165#define AR5K_TUNE_DMA_BEACON_RESP 2 166#define AR5K_TUNE_SW_BEACON_RESP 10 167#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 168#define AR5K_TUNE_RADAR_ALERT false 169#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 170#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1) 171#define AR5K_TUNE_REGISTER_TIMEOUT 20000 172/* Register for RSSI threshold has a mask of 0xff, so 255 seems to 173 * be the max value. */ 174#define AR5K_TUNE_RSSI_THRES 129 175/* This must be set when setting the RSSI threshold otherwise it can 176 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 177 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 178 * track of it. Max value depends on harware. For AR5210 this is just 7. 179 * For AR5211+ this seems to be up to 255. */ 180#define AR5K_TUNE_BMISS_THRES 7 181#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 182#define AR5K_TUNE_BEACON_INTERVAL 100 183#define AR5K_TUNE_AIFS 2 184#define AR5K_TUNE_AIFS_11B 2 185#define AR5K_TUNE_AIFS_XR 0 186#define AR5K_TUNE_CWMIN 15 187#define AR5K_TUNE_CWMIN_11B 31 188#define AR5K_TUNE_CWMIN_XR 3 189#define AR5K_TUNE_CWMAX 1023 190#define AR5K_TUNE_CWMAX_11B 1023 191#define AR5K_TUNE_CWMAX_XR 7 192#define AR5K_TUNE_NOISE_FLOOR -72 193#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 194#define AR5K_TUNE_MAX_TXPOWER 63 195#define AR5K_TUNE_DEFAULT_TXPOWER 25 196#define AR5K_TUNE_TPC_TXPOWER false 197#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ 198#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ 199#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ 200 201#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */ 202 203#define AR5K_INIT_CARR_SENSE_EN 1 204 205/*Swap RX/TX Descriptor for big endian archs*/ 206#if defined(__BIG_ENDIAN) 207#define AR5K_INIT_CFG ( \ 208 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 209) 210#else 211#define AR5K_INIT_CFG 0x00000000 212#endif 213 214/* Initial values */ 215#define AR5K_INIT_CYCRSSI_THR1 2 216 217/* Tx retry limits */ 218#define AR5K_INIT_SH_RETRY 10 219#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY 220/* For station mode */ 221#define AR5K_INIT_SSH_RETRY 32 222#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY 223#define AR5K_INIT_TX_RETRY 10 224 225 226/* Slot time */ 227#define AR5K_INIT_SLOT_TIME_TURBO 6 228#define AR5K_INIT_SLOT_TIME_DEFAULT 9 229#define AR5K_INIT_SLOT_TIME_HALF_RATE 13 230#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21 231#define AR5K_INIT_SLOT_TIME_B 20 232#define AR5K_SLOT_TIME_MAX 0xffff 233 234/* SIFS */ 235#define AR5K_INIT_SIFS_TURBO 6 236/* XXX: 8 from initvals 10 from standard */ 237#define AR5K_INIT_SIFS_DEFAULT_BG 8 238#define AR5K_INIT_SIFS_DEFAULT_A 16 239#define AR5K_INIT_SIFS_HALF_RATE 32 240#define AR5K_INIT_SIFS_QUARTER_RATE 64 241 242/* Used to calculate tx time for non 5/10/40MHz 243 * operation */ 244/* It's preamble time + signal time (16 + 4) */ 245#define AR5K_INIT_OFDM_PREAMPLE_TIME 20 246/* Preamble time for 40MHz (turbo) operation (min ?) */ 247#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14 248#define AR5K_INIT_OFDM_SYMBOL_TIME 4 249#define AR5K_INIT_OFDM_PLCP_BITS 22 250 251/* Rx latency for 5 and 10MHz operation (max ?) */ 252#define AR5K_INIT_RX_LAT_MAX 63 253/* Tx latencies from initvals (5212 only but no problem 254 * because we only tweak them on 5212) */ 255#define AR5K_INIT_TX_LAT_A 54 256#define AR5K_INIT_TX_LAT_BG 384 257/* Tx latency for 40MHz (turbo) operation (min ?) */ 258#define AR5K_INIT_TX_LAT_MIN 32 259/* Default Tx/Rx latencies (same for 5211)*/ 260#define AR5K_INIT_TX_LATENCY_5210 54 261#define AR5K_INIT_RX_LATENCY_5210 29 262 263/* Tx frame to Tx data start delay */ 264#define AR5K_INIT_TXF2TXD_START_DEFAULT 14 265#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12 266#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13 267 268/* We need to increase PHY switch and agc settling time 269 * on turbo mode */ 270#define AR5K_SWITCH_SETTLING 5760 271#define AR5K_SWITCH_SETTLING_TURBO 7168 272 273#define AR5K_AGC_SETTLING 28 274/* 38 on 5210 but shouldn't matter */ 275#define AR5K_AGC_SETTLING_TURBO 37 276 277 278/* GENERIC CHIPSET DEFINITIONS */ 279 280/* MAC Chips */ 281enum ath5k_version { 282 AR5K_AR5210 = 0, 283 AR5K_AR5211 = 1, 284 AR5K_AR5212 = 2, 285}; 286 287/* PHY Chips */ 288enum ath5k_radio { 289 AR5K_RF5110 = 0, 290 AR5K_RF5111 = 1, 291 AR5K_RF5112 = 2, 292 AR5K_RF2413 = 3, 293 AR5K_RF5413 = 4, 294 AR5K_RF2316 = 5, 295 AR5K_RF2317 = 6, 296 AR5K_RF2425 = 7, 297}; 298 299/* 300 * Common silicon revision/version values 301 */ 302 303enum ath5k_srev_type { 304 AR5K_VERSION_MAC, 305 AR5K_VERSION_RAD, 306}; 307 308struct ath5k_srev_name { 309 const char *sr_name; 310 enum ath5k_srev_type sr_type; 311 u_int sr_val; 312}; 313 314#define AR5K_SREV_UNKNOWN 0xffff 315 316#define AR5K_SREV_AR5210 0x00 /* Crete */ 317#define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 318#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 319#define AR5K_SREV_AR5311B 0x30 /* Spirit */ 320#define AR5K_SREV_AR5211 0x40 /* Oahu */ 321#define AR5K_SREV_AR5212 0x50 /* Venice */ 322#define AR5K_SREV_AR5312_R2 0x52 /* AP31 */ 323#define AR5K_SREV_AR5212_V4 0x54 /* ??? */ 324#define AR5K_SREV_AR5213 0x55 /* ??? */ 325#define AR5K_SREV_AR5312_R7 0x57 /* AP30 */ 326#define AR5K_SREV_AR2313_R8 0x58 /* AP43 */ 327#define AR5K_SREV_AR5213A 0x59 /* Hainan */ 328#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 329#define AR5K_SREV_AR2414 0x70 /* Griffin */ 330#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */ 331#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */ 332#define AR5K_SREV_AR5424 0x90 /* Condor */ 333#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */ 334#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */ 335#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 336#define AR5K_SREV_AR5414 0xa0 /* Eagle */ 337#define AR5K_SREV_AR2415 0xb0 /* Talon */ 338#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 339#define AR5K_SREV_AR5418 0xca /* PCI-E */ 340#define AR5K_SREV_AR2425 0xe0 /* Swan */ 341#define AR5K_SREV_AR2417 0xf0 /* Nala */ 342 343#define AR5K_SREV_RAD_5110 0x00 344#define AR5K_SREV_RAD_5111 0x10 345#define AR5K_SREV_RAD_5111A 0x15 346#define AR5K_SREV_RAD_2111 0x20 347#define AR5K_SREV_RAD_5112 0x30 348#define AR5K_SREV_RAD_5112A 0x35 349#define AR5K_SREV_RAD_5112B 0x36 350#define AR5K_SREV_RAD_2112 0x40 351#define AR5K_SREV_RAD_2112A 0x45 352#define AR5K_SREV_RAD_2112B 0x46 353#define AR5K_SREV_RAD_2413 0x50 354#define AR5K_SREV_RAD_5413 0x60 355#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 356#define AR5K_SREV_RAD_2317 0x80 357#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 358#define AR5K_SREV_RAD_2425 0xa2 359#define AR5K_SREV_RAD_5133 0xc0 360 361#define AR5K_SREV_PHY_5211 0x30 362#define AR5K_SREV_PHY_5212 0x41 363#define AR5K_SREV_PHY_5212A 0x42 364#define AR5K_SREV_PHY_5212B 0x43 365#define AR5K_SREV_PHY_2413 0x45 366#define AR5K_SREV_PHY_5413 0x61 367#define AR5K_SREV_PHY_2425 0x70 368 369/* TODO add support to mac80211 for vendor-specific rates and modes */ 370 371/* 372 * Some of this information is based on Documentation from: 373 * 374 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 375 * 376 * Modulation for Atheros' eXtended Range - range enhancing extension that is 377 * supposed to double the distance an Atheros client device can keep a 378 * connection with an Atheros access point. This is achieved by increasing 379 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 380 * the 802.11 specifications demand. In addition, new (proprietary) data rates 381 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 382 * 383 * Please note that can you either use XR or TURBO but you cannot use both, 384 * they are exclusive. 385 * 386 */ 387#define MODULATION_XR 0x00000200 388/* 389 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 390 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 391 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 392 * channels. To use this feature your Access Point must also suport it. 393 * There is also a distinction between "static" and "dynamic" turbo modes: 394 * 395 * - Static: is the dumb version: devices set to this mode stick to it until 396 * the mode is turned off. 397 * - Dynamic: is the intelligent version, the network decides itself if it 398 * is ok to use turbo. As soon as traffic is detected on adjacent channels 399 * (which would get used in turbo mode), or when a non-turbo station joins 400 * the network, turbo mode won't be used until the situation changes again. 401 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 402 * monitors the used radio band in order to decide whether turbo mode may 403 * be used or not. 404 * 405 * This article claims Super G sticks to bonding of channels 5 and 6 for 406 * USA: 407 * 408 * http://www.pcworld.com/article/id,113428-page,1/article.html 409 * 410 * The channel bonding seems to be driver specific though. In addition to 411 * deciding what channels will be used, these "Turbo" modes are accomplished 412 * by also enabling the following features: 413 * 414 * - Bursting: allows multiple frames to be sent at once, rather than pausing 415 * after each frame. Bursting is a standards-compliant feature that can be 416 * used with any Access Point. 417 * - Fast frames: increases the amount of information that can be sent per 418 * frame, also resulting in a reduction of transmission overhead. It is a 419 * proprietary feature that needs to be supported by the Access Point. 420 * - Compression: data frames are compressed in real time using a Lempel Ziv 421 * algorithm. This is done transparently. Once this feature is enabled, 422 * compression and decompression takes place inside the chipset, without 423 * putting additional load on the host CPU. 424 * 425 */ 426#define MODULATION_TURBO 0x00000080 427 428enum ath5k_driver_mode { 429 AR5K_MODE_11A = 0, 430 AR5K_MODE_11B = 1, 431 AR5K_MODE_11G = 2, 432 AR5K_MODE_XR = 0, 433 AR5K_MODE_MAX = 3 434}; 435 436enum ath5k_ant_mode { 437 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 438 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 439 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 440 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 441 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 442 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 443 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 444 AR5K_ANTMODE_MAX, 445}; 446 447enum ath5k_bw_mode { 448 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ 449 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ 450 AR5K_BWMODE_10MHZ = 2, /* Half rate */ 451 AR5K_BWMODE_40MHZ = 3 /* Turbo */ 452}; 453 454/****************\ 455 TX DEFINITIONS 456\****************/ 457 458/* 459 * TX Status descriptor 460 */ 461struct ath5k_tx_status { 462 u16 ts_seqnum; 463 u16 ts_tstamp; 464 u8 ts_status; 465 u8 ts_rate[4]; 466 u8 ts_retry[4]; 467 u8 ts_final_idx; 468 s8 ts_rssi; 469 u8 ts_shortretry; 470 u8 ts_longretry; 471 u8 ts_virtcol; 472 u8 ts_antenna; 473}; 474 475#define AR5K_TXSTAT_ALTRATE 0x80 476#define AR5K_TXERR_XRETRY 0x01 477#define AR5K_TXERR_FILT 0x02 478#define AR5K_TXERR_FIFO 0x04 479 480/** 481 * enum ath5k_tx_queue - Queue types used to classify tx queues. 482 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 483 * @AR5K_TX_QUEUE_DATA: A normal data queue 484 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 485 * @AR5K_TX_QUEUE_BEACON: The beacon queue 486 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 487 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 488 */ 489enum ath5k_tx_queue { 490 AR5K_TX_QUEUE_INACTIVE = 0, 491 AR5K_TX_QUEUE_DATA, 492 AR5K_TX_QUEUE_XR_DATA, 493 AR5K_TX_QUEUE_BEACON, 494 AR5K_TX_QUEUE_CAB, 495 AR5K_TX_QUEUE_UAPSD, 496}; 497 498#define AR5K_NUM_TX_QUEUES 10 499#define AR5K_NUM_TX_QUEUES_NOQCU 2 500 501/* 502 * Queue syb-types to classify normal data queues. 503 * These are the 4 Access Categories as defined in 504 * WME spec. 0 is the lowest priority and 4 is the 505 * highest. Normal data that hasn't been classified 506 * goes to the Best Effort AC. 507 */ 508enum ath5k_tx_queue_subtype { 509 AR5K_WME_AC_BK = 0, /*Background traffic*/ 510 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 511 AR5K_WME_AC_VI, /*Video traffic*/ 512 AR5K_WME_AC_VO, /*Voice traffic*/ 513}; 514 515/* 516 * Queue ID numbers as returned by the hw functions, each number 517 * represents a hw queue. If hw does not support hw queues 518 * (eg 5210) all data goes in one queue. These match 519 * d80211 definitions (net80211/MadWiFi don't use them). 520 */ 521enum ath5k_tx_queue_id { 522 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 523 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 524 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 525 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ 526 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 527 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 528 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 529 AR5K_TX_QUEUE_ID_UAPSD = 8, 530 AR5K_TX_QUEUE_ID_XR_DATA = 9, 531}; 532 533/* 534 * Flags to set hw queue's parameters... 535 */ 536#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 537#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 538#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 539#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 540#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 541#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 542#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 543#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 544#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 545#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 546#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 547#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 548#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 549#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 550 551/* 552 * A struct to hold tx queue's parameters 553 */ 554struct ath5k_txq_info { 555 enum ath5k_tx_queue tqi_type; 556 enum ath5k_tx_queue_subtype tqi_subtype; 557 u16 tqi_flags; /* Tx queue flags (see above) */ 558 u8 tqi_aifs; /* Arbitrated Interframe Space */ 559 u16 tqi_cw_min; /* Minimum Contention Window */ 560 u16 tqi_cw_max; /* Maximum Contention Window */ 561 u32 tqi_cbr_period; /* Constant bit rate period */ 562 u32 tqi_cbr_overflow_limit; 563 u32 tqi_burst_time; 564 u32 tqi_ready_time; /* Time queue waits after an event */ 565}; 566 567/* 568 * Transmit packet types. 569 * used on tx control descriptor 570 */ 571enum ath5k_pkt_type { 572 AR5K_PKT_TYPE_NORMAL = 0, 573 AR5K_PKT_TYPE_ATIM = 1, 574 AR5K_PKT_TYPE_PSPOLL = 2, 575 AR5K_PKT_TYPE_BEACON = 3, 576 AR5K_PKT_TYPE_PROBE_RESP = 4, 577 AR5K_PKT_TYPE_PIFS = 5, 578}; 579 580/* 581 * TX power and TPC settings 582 */ 583#define AR5K_TXPOWER_OFDM(_r, _v) ( \ 584 ((0 & 1) << ((_v) + 6)) | \ 585 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 586) 587 588#define AR5K_TXPOWER_CCK(_r, _v) ( \ 589 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 590) 591 592/* 593 * DMA size definitions (2^(n+2)) 594 */ 595enum ath5k_dmasize { 596 AR5K_DMASIZE_4B = 0, 597 AR5K_DMASIZE_8B, 598 AR5K_DMASIZE_16B, 599 AR5K_DMASIZE_32B, 600 AR5K_DMASIZE_64B, 601 AR5K_DMASIZE_128B, 602 AR5K_DMASIZE_256B, 603 AR5K_DMASIZE_512B 604}; 605 606 607/****************\ 608 RX DEFINITIONS 609\****************/ 610 611/* 612 * RX Status descriptor 613 */ 614struct ath5k_rx_status { 615 u16 rs_datalen; 616 u16 rs_tstamp; 617 u8 rs_status; 618 u8 rs_phyerr; 619 s8 rs_rssi; 620 u8 rs_keyix; 621 u8 rs_rate; 622 u8 rs_antenna; 623 u8 rs_more; 624}; 625 626#define AR5K_RXERR_CRC 0x01 627#define AR5K_RXERR_PHY 0x02 628#define AR5K_RXERR_FIFO 0x04 629#define AR5K_RXERR_DECRYPT 0x08 630#define AR5K_RXERR_MIC 0x10 631#define AR5K_RXKEYIX_INVALID ((u8) - 1) 632#define AR5K_TXKEYIX_INVALID ((u32) - 1) 633 634 635/**************************\ 636 BEACON TIMERS DEFINITIONS 637\**************************/ 638 639#define AR5K_BEACON_PERIOD 0x0000ffff 640#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 641#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 642 643 644/* 645 * TSF to TU conversion: 646 * 647 * TSF is a 64bit value in usec (microseconds). 648 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 649 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 650 */ 651#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 652 653 654/*******************************\ 655 GAIN OPTIMIZATION DEFINITIONS 656\*******************************/ 657 658enum ath5k_rfgain { 659 AR5K_RFGAIN_INACTIVE = 0, 660 AR5K_RFGAIN_ACTIVE, 661 AR5K_RFGAIN_READ_REQUESTED, 662 AR5K_RFGAIN_NEED_CHANGE, 663}; 664 665struct ath5k_gain { 666 u8 g_step_idx; 667 u8 g_current; 668 u8 g_target; 669 u8 g_low; 670 u8 g_high; 671 u8 g_f_corr; 672 u8 g_state; 673}; 674 675/********************\ 676 COMMON DEFINITIONS 677\********************/ 678 679#define AR5K_SLOT_TIME_9 396 680#define AR5K_SLOT_TIME_20 880 681#define AR5K_SLOT_TIME_MAX 0xffff 682 683/* channel_flags */ 684#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 685#define CHANNEL_CCK 0x0020 /* CCK channel */ 686#define CHANNEL_OFDM 0x0040 /* OFDM channel */ 687#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 688#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 689#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 690#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 691#define CHANNEL_XR 0x0800 /* XR channel */ 692 693#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 694#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 695#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 696#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 697 698#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ) 699 700#define CHANNEL_MODES CHANNEL_ALL 701 702/* 703 * Used internaly for reset_tx_queue). 704 * Also see struct struct ieee80211_channel. 705 */ 706#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 707#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) 708 709/* 710 * The following structure is used to map 2GHz channels to 711 * 5GHz Atheros channels. 712 * TODO: Clean up 713 */ 714struct ath5k_athchan_2ghz { 715 u32 a2_flags; 716 u16 a2_athchan; 717}; 718 719 720/******************\ 721 RATE DEFINITIONS 722\******************/ 723 724/** 725 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 726 * 727 * The rate code is used to get the RX rate or set the TX rate on the 728 * hardware descriptors. It is also used for internal modulation control 729 * and settings. 730 * 731 * This is the hardware rate map we are aware of: 732 * 733 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 734 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 735 * 736 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 737 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 738 * 739 * rate_code 17 18 19 20 21 22 23 24 740 * rate_kbps ? ? ? ? ? ? ? 11000 741 * 742 * rate_code 25 26 27 28 29 30 31 32 743 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 744 * 745 * "S" indicates CCK rates with short preamble. 746 * 747 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 748 * lowest 4 bits, so they are the same as below with a 0xF mask. 749 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 750 * We handle this in ath5k_setup_bands(). 751 */ 752#define AR5K_MAX_RATES 32 753 754/* B */ 755#define ATH5K_RATE_CODE_1M 0x1B 756#define ATH5K_RATE_CODE_2M 0x1A 757#define ATH5K_RATE_CODE_5_5M 0x19 758#define ATH5K_RATE_CODE_11M 0x18 759/* A and G */ 760#define ATH5K_RATE_CODE_6M 0x0B 761#define ATH5K_RATE_CODE_9M 0x0F 762#define ATH5K_RATE_CODE_12M 0x0A 763#define ATH5K_RATE_CODE_18M 0x0E 764#define ATH5K_RATE_CODE_24M 0x09 765#define ATH5K_RATE_CODE_36M 0x0D 766#define ATH5K_RATE_CODE_48M 0x08 767#define ATH5K_RATE_CODE_54M 0x0C 768/* XR */ 769#define ATH5K_RATE_CODE_XR_500K 0x07 770#define ATH5K_RATE_CODE_XR_1M 0x02 771#define ATH5K_RATE_CODE_XR_2M 0x06 772#define ATH5K_RATE_CODE_XR_3M 0x01 773 774/* adding this flag to rate_code enables short preamble */ 775#define AR5K_SET_SHORT_PREAMBLE 0x04 776 777/* 778 * Crypto definitions 779 */ 780 781#define AR5K_KEYCACHE_SIZE 8 782 783/***********************\ 784 HW RELATED DEFINITIONS 785\***********************/ 786 787/* 788 * Misc definitions 789 */ 790#define AR5K_RSSI_EP_MULTIPLIER (1<<7) 791 792#define AR5K_ASSERT_ENTRY(_e, _s) do { \ 793 if (_e >= _s) \ 794 return (false); \ 795} while (0) 796 797/* 798 * Hardware interrupt abstraction 799 */ 800 801/** 802 * enum ath5k_int - Hardware interrupt masks helpers 803 * 804 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 805 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 806 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 807 * @AR5K_INT_RXNOFRM: No frame received (?) 808 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 809 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 810 * LinkPtr is NULL. For more details, refer to: 811 * http://www.freepatentsonline.com/20030225739.html 812 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 813 * Note that Rx overrun is not always fatal, on some chips we can continue 814 * operation without reseting the card, that's why int_fatal is not 815 * common for all chips. 816 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 817 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 818 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 819 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 820 * We currently do increments on interrupt by 821 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 822 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 823 * one of the PHY error counters reached the maximum value and should be 824 * read and cleared. 825 * @AR5K_INT_RXPHY: RX PHY Error 826 * @AR5K_INT_RXKCM: RX Key cache miss 827 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 828 * beacon that must be handled in software. The alternative is if you 829 * have VEOL support, in that case you let the hardware deal with things. 830 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 831 * beacons from the AP have associated with, we should probably try to 832 * reassociate. When in IBSS mode this might mean we have not received 833 * any beacons from any local stations. Note that every station in an 834 * IBSS schedules to send beacons at the Target Beacon Transmission Time 835 * (TBTT) with a random backoff. 836 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 837 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 838 * until properly handled 839 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 840 * errors. These types of errors we can enable seem to be of type 841 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 842 * @AR5K_INT_GLOBAL: Used to clear and set the IER 843 * @AR5K_INT_NOCARD: signals the card has been removed 844 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 845 * bit value 846 * 847 * These are mapped to take advantage of some common bits 848 * between the MACs, to be able to set intr properties 849 * easier. Some of them are not used yet inside hw.c. Most map 850 * to the respective hw interrupt value as they are common amogst different 851 * MACs. 852 */ 853enum ath5k_int { 854 AR5K_INT_RXOK = 0x00000001, 855 AR5K_INT_RXDESC = 0x00000002, 856 AR5K_INT_RXERR = 0x00000004, 857 AR5K_INT_RXNOFRM = 0x00000008, 858 AR5K_INT_RXEOL = 0x00000010, 859 AR5K_INT_RXORN = 0x00000020, 860 AR5K_INT_TXOK = 0x00000040, 861 AR5K_INT_TXDESC = 0x00000080, 862 AR5K_INT_TXERR = 0x00000100, 863 AR5K_INT_TXNOFRM = 0x00000200, 864 AR5K_INT_TXEOL = 0x00000400, 865 AR5K_INT_TXURN = 0x00000800, 866 AR5K_INT_MIB = 0x00001000, 867 AR5K_INT_SWI = 0x00002000, 868 AR5K_INT_RXPHY = 0x00004000, 869 AR5K_INT_RXKCM = 0x00008000, 870 AR5K_INT_SWBA = 0x00010000, 871 AR5K_INT_BRSSI = 0x00020000, 872 AR5K_INT_BMISS = 0x00040000, 873 AR5K_INT_FATAL = 0x00080000, /* Non common */ 874 AR5K_INT_BNR = 0x00100000, /* Non common */ 875 AR5K_INT_TIM = 0x00200000, /* Non common */ 876 AR5K_INT_DTIM = 0x00400000, /* Non common */ 877 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 878 AR5K_INT_GPIO = 0x01000000, 879 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 880 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 881 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 882 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 883 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 884 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 885 AR5K_INT_GLOBAL = 0x80000000, 886 887 AR5K_INT_COMMON = AR5K_INT_RXOK 888 | AR5K_INT_RXDESC 889 | AR5K_INT_RXERR 890 | AR5K_INT_RXNOFRM 891 | AR5K_INT_RXEOL 892 | AR5K_INT_RXORN 893 | AR5K_INT_TXOK 894 | AR5K_INT_TXDESC 895 | AR5K_INT_TXERR 896 | AR5K_INT_TXNOFRM 897 | AR5K_INT_TXEOL 898 | AR5K_INT_TXURN 899 | AR5K_INT_MIB 900 | AR5K_INT_SWI 901 | AR5K_INT_RXPHY 902 | AR5K_INT_RXKCM 903 | AR5K_INT_SWBA 904 | AR5K_INT_BRSSI 905 | AR5K_INT_BMISS 906 | AR5K_INT_GPIO 907 | AR5K_INT_GLOBAL, 908 909 AR5K_INT_NOCARD = 0xffffffff 910}; 911 912/* mask which calibration is active at the moment */ 913enum ath5k_calibration_mask { 914 AR5K_CALIBRATION_FULL = 0x01, 915 AR5K_CALIBRATION_SHORT = 0x02, 916 AR5K_CALIBRATION_ANI = 0x04, 917}; 918 919/* 920 * Power management 921 */ 922enum ath5k_power_mode { 923 AR5K_PM_UNDEFINED = 0, 924 AR5K_PM_AUTO, 925 AR5K_PM_AWAKE, 926 AR5K_PM_FULL_SLEEP, 927 AR5K_PM_NETWORK_SLEEP, 928}; 929 930/* 931 * These match net80211 definitions (not used in 932 * mac80211). 933 * TODO: Clean this up 934 */ 935#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 936#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 937#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 938#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 939#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 940 941/* GPIO-controlled software LED */ 942#define AR5K_SOFTLED_PIN 0 943#define AR5K_SOFTLED_ON 0 944#define AR5K_SOFTLED_OFF 1 945 946/* 947 * Chipset capabilities -see ath5k_hw_get_capability- 948 * get_capability function is not yet fully implemented 949 * in ath5k so most of these don't work yet... 950 * TODO: Implement these & merge with _TUNE_ stuff above 951 */ 952enum ath5k_capability_type { 953 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 954 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 955 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 956 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 957 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 958 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 959 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 960 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 961 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 962 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 963 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 964 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 965 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 966 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 967 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 968 AR5K_CAP_XR = 16, /* Supports XR mode */ 969 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 970 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 971 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 972 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 973}; 974 975 976/* XXX: we *may* move cap_range stuff to struct wiphy */ 977struct ath5k_capabilities { 978 /* 979 * Supported PHY modes 980 * (ie. CHANNEL_A, CHANNEL_B, ...) 981 */ 982 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 983 984 /* 985 * Frequency range (without regulation restrictions) 986 */ 987 struct { 988 u16 range_2ghz_min; 989 u16 range_2ghz_max; 990 u16 range_5ghz_min; 991 u16 range_5ghz_max; 992 } cap_range; 993 994 /* 995 * Values stored in the EEPROM (some of them...) 996 */ 997 struct ath5k_eeprom_info cap_eeprom; 998 999 /* 1000 * Queue information 1001 */ 1002 struct { 1003 u8 q_tx_num; 1004 } cap_queues; 1005 1006 bool cap_has_phyerr_counters; 1007}; 1008 1009/* size of noise floor history (keep it a power of two) */ 1010#define ATH5K_NF_CAL_HIST_MAX 8 1011struct ath5k_nfcal_hist 1012{ 1013 s16 index; /* current index into nfval */ 1014 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 1015}; 1016 1017/** 1018 * struct avg_val - Helper structure for average calculation 1019 * @avg: contains the actual average value 1020 * @avg_weight: is used internally during calculation to prevent rounding errors 1021 */ 1022struct ath5k_avg_val { 1023 int avg; 1024 int avg_weight; 1025}; 1026 1027/***************************************\ 1028 HARDWARE ABSTRACTION LAYER STRUCTURE 1029\***************************************/ 1030 1031/* 1032 * Misc defines 1033 */ 1034 1035#define AR5K_MAX_GPIO 10 1036#define AR5K_MAX_RF_BANKS 8 1037 1038/* TODO: Clean up and merge with ath5k_softc */ 1039struct ath5k_hw { 1040 struct ath_common common; 1041 1042 struct ath5k_softc *ah_sc; 1043 void __iomem *ah_iobase; 1044 1045 enum ath5k_int ah_imr; 1046 1047 struct ieee80211_channel *ah_current_channel; 1048 bool ah_calibration; 1049 bool ah_single_chip; 1050 1051 enum ath5k_version ah_version; 1052 enum ath5k_radio ah_radio; 1053 u32 ah_phy; 1054 u32 ah_mac_srev; 1055 u16 ah_mac_version; 1056 u16 ah_mac_revision; 1057 u16 ah_phy_revision; 1058 u16 ah_radio_5ghz_revision; 1059 u16 ah_radio_2ghz_revision; 1060 1061#define ah_modes ah_capabilities.cap_mode 1062#define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1063 1064 u32 ah_limit_tx_retries; 1065 u8 ah_coverage_class; 1066 bool ah_ack_bitrate_high; 1067 u8 ah_bwmode; 1068 1069 /* Antenna Control */ 1070 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1071 u8 ah_ant_mode; 1072 u8 ah_tx_ant; 1073 u8 ah_def_ant; 1074 bool ah_software_retry; 1075 1076 struct ath5k_capabilities ah_capabilities; 1077 1078 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1079 u32 ah_txq_status; 1080 u32 ah_txq_imr_txok; 1081 u32 ah_txq_imr_txerr; 1082 u32 ah_txq_imr_txurn; 1083 u32 ah_txq_imr_txdesc; 1084 u32 ah_txq_imr_txeol; 1085 u32 ah_txq_imr_cbrorn; 1086 u32 ah_txq_imr_cbrurn; 1087 u32 ah_txq_imr_qtrig; 1088 u32 ah_txq_imr_nofrm; 1089 u32 ah_txq_isr; 1090 u32 *ah_rf_banks; 1091 size_t ah_rf_banks_size; 1092 size_t ah_rf_regs_count; 1093 struct ath5k_gain ah_gain; 1094 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1095 1096 1097 struct { 1098 /* Temporary tables used for interpolation */ 1099 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1100 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1101 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1102 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1103 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1104 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1105 u8 txp_min_idx; 1106 bool txp_tpc; 1107 /* Values in 0.25dB units */ 1108 s16 txp_min_pwr; 1109 s16 txp_max_pwr; 1110 /* Values in 0.5dB units */ 1111 s16 txp_offset; 1112 s16 txp_ofdm; 1113 s16 txp_cck_ofdm_gainf_delta; 1114 /* Value in dB units */ 1115 s16 txp_cck_ofdm_pwr_delta; 1116 bool txp_setup; 1117 } ah_txpower; 1118 1119 struct { 1120 bool r_enabled; 1121 int r_last_alert; 1122 struct ieee80211_channel r_last_channel; 1123 } ah_radar; 1124 1125 struct ath5k_nfcal_hist ah_nfcal_hist; 1126 1127 /* average beacon RSSI in our BSS (used by ANI) */ 1128 struct ewma ah_beacon_rssi_avg; 1129 1130 /* noise floor from last periodic calibration */ 1131 s32 ah_noise_floor; 1132 1133 /* Calibration timestamp */ 1134 unsigned long ah_cal_next_full; 1135 unsigned long ah_cal_next_ani; 1136 unsigned long ah_cal_next_nf; 1137 1138 /* Calibration mask */ 1139 u8 ah_cal_mask; 1140 1141 /* 1142 * Function pointers 1143 */ 1144 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1145 unsigned int, unsigned int, int, enum ath5k_pkt_type, 1146 unsigned int, unsigned int, unsigned int, unsigned int, 1147 unsigned int, unsigned int, unsigned int, unsigned int); 1148 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1149 struct ath5k_tx_status *); 1150 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1151 struct ath5k_rx_status *); 1152}; 1153 1154/* 1155 * Prototypes 1156 */ 1157extern const struct ieee80211_ops ath5k_hw_ops; 1158 1159/* Initialization and detach functions */ 1160int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops); 1161void ath5k_deinit_softc(struct ath5k_softc *sc); 1162int ath5k_hw_init(struct ath5k_softc *sc); 1163void ath5k_hw_deinit(struct ath5k_hw *ah); 1164 1165int ath5k_sysfs_register(struct ath5k_softc *sc); 1166void ath5k_sysfs_unregister(struct ath5k_softc *sc); 1167 1168/*Chip id helper functions */ 1169const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val); 1170int ath5k_hw_read_srev(struct ath5k_hw *ah); 1171 1172/* LED functions */ 1173int ath5k_init_leds(struct ath5k_softc *sc); 1174void ath5k_led_enable(struct ath5k_softc *sc); 1175void ath5k_led_off(struct ath5k_softc *sc); 1176void ath5k_unregister_leds(struct ath5k_softc *sc); 1177 1178 1179/* Reset Functions */ 1180int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1181int ath5k_hw_on_hold(struct ath5k_hw *ah); 1182int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1183 struct ieee80211_channel *channel, bool fast, bool skip_pcu); 1184int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 1185 bool is_set); 1186/* Power management functions */ 1187 1188 1189/* Clock rate related functions */ 1190unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1191unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1192void ath5k_hw_set_clockrate(struct ath5k_hw *ah); 1193 1194 1195/* DMA Related Functions */ 1196void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1197u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1198int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1199int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1200int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue); 1201u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1202int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1203 u32 phys_addr); 1204int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1205/* Interrupt handling */ 1206bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1207int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1208enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1209void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); 1210/* Init/Stop functions */ 1211void ath5k_hw_dma_init(struct ath5k_hw *ah); 1212int ath5k_hw_dma_stop(struct ath5k_hw *ah); 1213 1214/* EEPROM access functions */ 1215int ath5k_eeprom_init(struct ath5k_hw *ah); 1216void ath5k_eeprom_detach(struct ath5k_hw *ah); 1217int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1218 1219 1220/* Protocol Control Unit Functions */ 1221/* Helpers */ 1222int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 1223 int len, struct ieee80211_rate *rate); 1224unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah); 1225unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah); 1226extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1227void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1228/* RX filter control*/ 1229int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1230void ath5k_hw_set_bssid(struct ath5k_hw *ah); 1231void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1232void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1233u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1234void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1235/* Receive (DRU) start/stop functions */ 1236void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1237void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1238/* Beacon control functions */ 1239u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1240void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1241void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1242void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1243bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); 1244/* Init function */ 1245void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1246 u8 mode); 1247 1248/* Queue Control Unit, DFS Control Unit Functions */ 1249int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1250 struct ath5k_txq_info *queue_info); 1251int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1252 const struct ath5k_txq_info *queue_info); 1253int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1254 enum ath5k_tx_queue queue_type, 1255 struct ath5k_txq_info *queue_info); 1256u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1257void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1258int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1259int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time); 1260/* Init function */ 1261int ath5k_hw_init_queues(struct ath5k_hw *ah); 1262 1263/* Hardware Descriptor Functions */ 1264int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1265int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1266 u32 size, unsigned int flags); 1267int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1268 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 1269 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); 1270 1271 1272/* GPIO Functions */ 1273void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1274int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1275int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1276u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1277int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1278void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 1279 u32 interrupt_level); 1280 1281 1282/* RFkill Functions */ 1283void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1284void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1285 1286 1287/* Misc functions TODO: Cleanup */ 1288int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1289int ath5k_hw_get_capability(struct ath5k_hw *ah, 1290 enum ath5k_capability_type cap_type, u32 capability, 1291 u32 *result); 1292int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1293int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1294 1295 1296/* Initial register settings functions */ 1297int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1298 1299 1300/* PHY functions */ 1301/* Misc PHY functions */ 1302u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1303int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1304/* Gain_F optimization */ 1305enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1306int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1307/* PHY/RF channel functions */ 1308bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1309/* PHY calibration */ 1310void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1311int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1312 struct ieee80211_channel *channel); 1313void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); 1314/* Spur mitigation */ 1315bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1316 struct ieee80211_channel *channel); 1317/* Antenna control */ 1318void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1319void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); 1320/* TX power setup */ 1321int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1322/* Init function */ 1323int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 1324 u8 mode, u8 ee_mode, u8 freq, bool fast); 1325 1326/* 1327 * Functions used internaly 1328 */ 1329 1330static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1331{ 1332 return &ah->common; 1333} 1334 1335static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1336{ 1337 return &(ath5k_hw_common(ah)->regulatory); 1338} 1339 1340#ifdef CONFIG_ATHEROS_AR231X 1341#define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000) 1342 1343static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg) 1344{ 1345 /* On AR2315 and AR2317 the PCI clock domain registers 1346 * are outside of the WMAC register space */ 1347 if (unlikely((reg >= 0x4000) && (reg < 0x5000) && 1348 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6))) 1349 return AR5K_AR2315_PCI_BASE + reg; 1350 1351 return ah->ah_iobase + reg; 1352} 1353 1354static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1355{ 1356 return __raw_readl(ath5k_ahb_reg(ah, reg)); 1357} 1358 1359static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1360{ 1361 __raw_writel(val, ath5k_ahb_reg(ah, reg)); 1362} 1363 1364#else 1365 1366static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1367{ 1368 return ioread32(ah->ah_iobase + reg); 1369} 1370 1371static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1372{ 1373 iowrite32(val, ah->ah_iobase + reg); 1374} 1375 1376#endif 1377 1378static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah) 1379{ 1380 return ath5k_hw_common(ah)->bus_ops->ath_bus_type; 1381} 1382 1383static inline void ath5k_read_cachesize(struct ath_common *common, int *csz) 1384{ 1385 common->bus_ops->read_cachesize(common, csz); 1386} 1387 1388static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data) 1389{ 1390 struct ath_common *common = ath5k_hw_common(ah); 1391 return common->bus_ops->eeprom_read(common, off, data); 1392} 1393 1394static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1395{ 1396 u32 retval = 0, bit, i; 1397 1398 for (i = 0; i < bits; i++) { 1399 bit = (val >> i) & 1; 1400 retval = (retval << 1) | bit; 1401 } 1402 1403 return retval; 1404} 1405 1406#endif 1407