ath5k.h revision 488a50176c169eb36544b4f970c8bba68ede30a1
1/* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _ATH5K_H 19#define _ATH5K_H 20 21/* TODO: Clean up channel debuging -doesn't work anyway- and start 22 * working on reg. control code using all available eeprom information 23 * -rev. engineering needed- */ 24#define CHAN_DEBUG 0 25 26#include <linux/io.h> 27#include <linux/types.h> 28#include <linux/average.h> 29#include <net/mac80211.h> 30 31/* RX/TX descriptor hw structs 32 * TODO: Driver part should only see sw structs */ 33#include "desc.h" 34 35/* EEPROM structs/offsets 36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 37 * and clean up common bits, then introduce set/get functions in eeprom.c */ 38#include "eeprom.h" 39#include "../ath.h" 40 41/* PCI IDs */ 42#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 43#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 44#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 45#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 46#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 47#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 48#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 49#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 50#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 51#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 52#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 53#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 54#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 55#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 58#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 59#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 60#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 61#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 62#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 63#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 64#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 65#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 66#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 67#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 68#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 69#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 70 71/****************************\ 72 GENERIC DRIVER DEFINITIONS 73\****************************/ 74 75#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 76 77#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 78 printk(_level "ath5k %s: " _fmt, \ 79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 80 ##__VA_ARGS__) 81 82#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 83 if (net_ratelimit()) \ 84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 85 } while (0) 86 87#define ATH5K_INFO(_sc, _fmt, ...) \ 88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 89 90#define ATH5K_WARN(_sc, _fmt, ...) \ 91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 92 93#define ATH5K_ERR(_sc, _fmt, ...) \ 94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 95 96/* 97 * AR5K REGISTER ACCESS 98 */ 99 100/* Some macros to read/write fields */ 101 102/* First shift, then mask */ 103#define AR5K_REG_SM(_val, _flags) \ 104 (((_val) << _flags##_S) & (_flags)) 105 106/* First mask, then shift */ 107#define AR5K_REG_MS(_val, _flags) \ 108 (((_val) & (_flags)) >> _flags##_S) 109 110/* Some registers can hold multiple values of interest. For this 111 * reason when we want to write to these registers we must first 112 * retrieve the values which we do not want to clear (lets call this 113 * old_data) and then set the register with this and our new_value: 114 * ( old_data | new_value) */ 115#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 117 (((_val) << _flags##_S) & (_flags)), _reg) 118 119#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 121 (_mask)) | (_flags), _reg) 122 123#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 125 126#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 128 129/* Access to PHY registers */ 130#define AR5K_PHY_READ(ah, _reg) \ 131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 132 133#define AR5K_PHY_WRITE(ah, _reg, _val) \ 134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 135 136/* Access QCU registers per queue */ 137#define AR5K_REG_READ_Q(ah, _reg, _queue) \ 138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 139 140#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 141 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 142 143#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 144 _reg |= 1 << _queue; \ 145} while (0) 146 147#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 148 _reg &= ~(1 << _queue); \ 149} while (0) 150 151/* Used while writing initvals */ 152#define AR5K_REG_WAIT(_i) do { \ 153 if (_i % 64) \ 154 udelay(1); \ 155} while (0) 156 157/* 158 * Some tuneable values (these should be changeable by the user) 159 * TODO: Make use of them and add more options OR use debug/configfs 160 */ 161#define AR5K_TUNE_DMA_BEACON_RESP 2 162#define AR5K_TUNE_SW_BEACON_RESP 10 163#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 164#define AR5K_TUNE_RADAR_ALERT false 165#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 166#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1) 167#define AR5K_TUNE_REGISTER_TIMEOUT 20000 168/* Register for RSSI threshold has a mask of 0xff, so 255 seems to 169 * be the max value. */ 170#define AR5K_TUNE_RSSI_THRES 129 171/* This must be set when setting the RSSI threshold otherwise it can 172 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 173 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 174 * track of it. Max value depends on harware. For AR5210 this is just 7. 175 * For AR5211+ this seems to be up to 255. */ 176#define AR5K_TUNE_BMISS_THRES 7 177#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 178#define AR5K_TUNE_BEACON_INTERVAL 100 179#define AR5K_TUNE_AIFS 2 180#define AR5K_TUNE_AIFS_11B 2 181#define AR5K_TUNE_AIFS_XR 0 182#define AR5K_TUNE_CWMIN 15 183#define AR5K_TUNE_CWMIN_11B 31 184#define AR5K_TUNE_CWMIN_XR 3 185#define AR5K_TUNE_CWMAX 1023 186#define AR5K_TUNE_CWMAX_11B 1023 187#define AR5K_TUNE_CWMAX_XR 7 188#define AR5K_TUNE_NOISE_FLOOR -72 189#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 190#define AR5K_TUNE_MAX_TXPOWER 63 191#define AR5K_TUNE_DEFAULT_TXPOWER 25 192#define AR5K_TUNE_TPC_TXPOWER false 193#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ 194#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ 195#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ 196 197#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */ 198 199#define AR5K_INIT_CARR_SENSE_EN 1 200 201/*Swap RX/TX Descriptor for big endian archs*/ 202#if defined(__BIG_ENDIAN) 203#define AR5K_INIT_CFG ( \ 204 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 205) 206#else 207#define AR5K_INIT_CFG 0x00000000 208#endif 209 210/* Initial values */ 211#define AR5K_INIT_CYCRSSI_THR1 2 212 213/* Tx retry limit defaults from standard */ 214#define AR5K_INIT_RETRY_SHORT 7 215#define AR5K_INIT_RETRY_LONG 4 216 217/* Slot time */ 218#define AR5K_INIT_SLOT_TIME_TURBO 6 219#define AR5K_INIT_SLOT_TIME_DEFAULT 9 220#define AR5K_INIT_SLOT_TIME_HALF_RATE 13 221#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21 222#define AR5K_INIT_SLOT_TIME_B 20 223#define AR5K_SLOT_TIME_MAX 0xffff 224 225/* SIFS */ 226#define AR5K_INIT_SIFS_TURBO 6 227#define AR5K_INIT_SIFS_DEFAULT_BG 10 228#define AR5K_INIT_SIFS_DEFAULT_A 16 229#define AR5K_INIT_SIFS_HALF_RATE 32 230#define AR5K_INIT_SIFS_QUARTER_RATE 64 231 232/* Used to calculate tx time for non 5/10/40MHz 233 * operation */ 234/* It's preamble time + signal time (16 + 4) */ 235#define AR5K_INIT_OFDM_PREAMPLE_TIME 20 236/* Preamble time for 40MHz (turbo) operation (min ?) */ 237#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14 238#define AR5K_INIT_OFDM_SYMBOL_TIME 4 239#define AR5K_INIT_OFDM_PLCP_BITS 22 240 241/* Rx latency for 5 and 10MHz operation (max ?) */ 242#define AR5K_INIT_RX_LAT_MAX 63 243/* Tx latencies from initvals (5212 only but no problem 244 * because we only tweak them on 5212) */ 245#define AR5K_INIT_TX_LAT_A 54 246#define AR5K_INIT_TX_LAT_BG 384 247/* Tx latency for 40MHz (turbo) operation (min ?) */ 248#define AR5K_INIT_TX_LAT_MIN 32 249/* Default Tx/Rx latencies (same for 5211)*/ 250#define AR5K_INIT_TX_LATENCY_5210 54 251#define AR5K_INIT_RX_LATENCY_5210 29 252 253/* Tx frame to Tx data start delay */ 254#define AR5K_INIT_TXF2TXD_START_DEFAULT 14 255#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12 256#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13 257 258/* We need to increase PHY switch and agc settling time 259 * on turbo mode */ 260#define AR5K_SWITCH_SETTLING 5760 261#define AR5K_SWITCH_SETTLING_TURBO 7168 262 263#define AR5K_AGC_SETTLING 28 264/* 38 on 5210 but shouldn't matter */ 265#define AR5K_AGC_SETTLING_TURBO 37 266 267 268/* GENERIC CHIPSET DEFINITIONS */ 269 270/* MAC Chips */ 271enum ath5k_version { 272 AR5K_AR5210 = 0, 273 AR5K_AR5211 = 1, 274 AR5K_AR5212 = 2, 275}; 276 277/* PHY Chips */ 278enum ath5k_radio { 279 AR5K_RF5110 = 0, 280 AR5K_RF5111 = 1, 281 AR5K_RF5112 = 2, 282 AR5K_RF2413 = 3, 283 AR5K_RF5413 = 4, 284 AR5K_RF2316 = 5, 285 AR5K_RF2317 = 6, 286 AR5K_RF2425 = 7, 287}; 288 289/* 290 * Common silicon revision/version values 291 */ 292 293enum ath5k_srev_type { 294 AR5K_VERSION_MAC, 295 AR5K_VERSION_RAD, 296}; 297 298struct ath5k_srev_name { 299 const char *sr_name; 300 enum ath5k_srev_type sr_type; 301 u_int sr_val; 302}; 303 304#define AR5K_SREV_UNKNOWN 0xffff 305 306#define AR5K_SREV_AR5210 0x00 /* Crete */ 307#define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 308#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 309#define AR5K_SREV_AR5311B 0x30 /* Spirit */ 310#define AR5K_SREV_AR5211 0x40 /* Oahu */ 311#define AR5K_SREV_AR5212 0x50 /* Venice */ 312#define AR5K_SREV_AR5312_R2 0x52 /* AP31 */ 313#define AR5K_SREV_AR5212_V4 0x54 /* ??? */ 314#define AR5K_SREV_AR5213 0x55 /* ??? */ 315#define AR5K_SREV_AR5312_R7 0x57 /* AP30 */ 316#define AR5K_SREV_AR2313_R8 0x58 /* AP43 */ 317#define AR5K_SREV_AR5213A 0x59 /* Hainan */ 318#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 319#define AR5K_SREV_AR2414 0x70 /* Griffin */ 320#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */ 321#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */ 322#define AR5K_SREV_AR5424 0x90 /* Condor */ 323#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */ 324#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */ 325#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 326#define AR5K_SREV_AR5414 0xa0 /* Eagle */ 327#define AR5K_SREV_AR2415 0xb0 /* Talon */ 328#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 329#define AR5K_SREV_AR5418 0xca /* PCI-E */ 330#define AR5K_SREV_AR2425 0xe0 /* Swan */ 331#define AR5K_SREV_AR2417 0xf0 /* Nala */ 332 333#define AR5K_SREV_RAD_5110 0x00 334#define AR5K_SREV_RAD_5111 0x10 335#define AR5K_SREV_RAD_5111A 0x15 336#define AR5K_SREV_RAD_2111 0x20 337#define AR5K_SREV_RAD_5112 0x30 338#define AR5K_SREV_RAD_5112A 0x35 339#define AR5K_SREV_RAD_5112B 0x36 340#define AR5K_SREV_RAD_2112 0x40 341#define AR5K_SREV_RAD_2112A 0x45 342#define AR5K_SREV_RAD_2112B 0x46 343#define AR5K_SREV_RAD_2413 0x50 344#define AR5K_SREV_RAD_5413 0x60 345#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 346#define AR5K_SREV_RAD_2317 0x80 347#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 348#define AR5K_SREV_RAD_2425 0xa2 349#define AR5K_SREV_RAD_5133 0xc0 350 351#define AR5K_SREV_PHY_5211 0x30 352#define AR5K_SREV_PHY_5212 0x41 353#define AR5K_SREV_PHY_5212A 0x42 354#define AR5K_SREV_PHY_5212B 0x43 355#define AR5K_SREV_PHY_2413 0x45 356#define AR5K_SREV_PHY_5413 0x61 357#define AR5K_SREV_PHY_2425 0x70 358 359/* TODO add support to mac80211 for vendor-specific rates and modes */ 360 361/* 362 * Some of this information is based on Documentation from: 363 * 364 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 365 * 366 * Modulation for Atheros' eXtended Range - range enhancing extension that is 367 * supposed to double the distance an Atheros client device can keep a 368 * connection with an Atheros access point. This is achieved by increasing 369 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 370 * the 802.11 specifications demand. In addition, new (proprietary) data rates 371 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 372 * 373 * Please note that can you either use XR or TURBO but you cannot use both, 374 * they are exclusive. 375 * 376 */ 377#define MODULATION_XR 0x00000200 378/* 379 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 380 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 381 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 382 * channels. To use this feature your Access Point must also suport it. 383 * There is also a distinction between "static" and "dynamic" turbo modes: 384 * 385 * - Static: is the dumb version: devices set to this mode stick to it until 386 * the mode is turned off. 387 * - Dynamic: is the intelligent version, the network decides itself if it 388 * is ok to use turbo. As soon as traffic is detected on adjacent channels 389 * (which would get used in turbo mode), or when a non-turbo station joins 390 * the network, turbo mode won't be used until the situation changes again. 391 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 392 * monitors the used radio band in order to decide whether turbo mode may 393 * be used or not. 394 * 395 * This article claims Super G sticks to bonding of channels 5 and 6 for 396 * USA: 397 * 398 * http://www.pcworld.com/article/id,113428-page,1/article.html 399 * 400 * The channel bonding seems to be driver specific though. In addition to 401 * deciding what channels will be used, these "Turbo" modes are accomplished 402 * by also enabling the following features: 403 * 404 * - Bursting: allows multiple frames to be sent at once, rather than pausing 405 * after each frame. Bursting is a standards-compliant feature that can be 406 * used with any Access Point. 407 * - Fast frames: increases the amount of information that can be sent per 408 * frame, also resulting in a reduction of transmission overhead. It is a 409 * proprietary feature that needs to be supported by the Access Point. 410 * - Compression: data frames are compressed in real time using a Lempel Ziv 411 * algorithm. This is done transparently. Once this feature is enabled, 412 * compression and decompression takes place inside the chipset, without 413 * putting additional load on the host CPU. 414 * 415 */ 416#define MODULATION_TURBO 0x00000080 417 418enum ath5k_driver_mode { 419 AR5K_MODE_11A = 0, 420 AR5K_MODE_11B = 1, 421 AR5K_MODE_11G = 2, 422 AR5K_MODE_XR = 0, 423 AR5K_MODE_MAX = 3 424}; 425 426enum ath5k_ant_mode { 427 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 428 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 429 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 430 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 431 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 432 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 433 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 434 AR5K_ANTMODE_MAX, 435}; 436 437enum ath5k_bw_mode { 438 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ 439 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ 440 AR5K_BWMODE_10MHZ = 2, /* Half rate */ 441 AR5K_BWMODE_40MHZ = 3 /* Turbo */ 442}; 443 444/****************\ 445 TX DEFINITIONS 446\****************/ 447 448/* 449 * TX Status descriptor 450 */ 451struct ath5k_tx_status { 452 u16 ts_seqnum; 453 u16 ts_tstamp; 454 u8 ts_status; 455 u8 ts_rate[4]; 456 u8 ts_retry[4]; 457 u8 ts_final_idx; 458 s8 ts_rssi; 459 u8 ts_shortretry; 460 u8 ts_longretry; 461 u8 ts_virtcol; 462 u8 ts_antenna; 463}; 464 465#define AR5K_TXSTAT_ALTRATE 0x80 466#define AR5K_TXERR_XRETRY 0x01 467#define AR5K_TXERR_FILT 0x02 468#define AR5K_TXERR_FIFO 0x04 469 470/** 471 * enum ath5k_tx_queue - Queue types used to classify tx queues. 472 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 473 * @AR5K_TX_QUEUE_DATA: A normal data queue 474 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 475 * @AR5K_TX_QUEUE_BEACON: The beacon queue 476 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 477 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 478 */ 479enum ath5k_tx_queue { 480 AR5K_TX_QUEUE_INACTIVE = 0, 481 AR5K_TX_QUEUE_DATA, 482 AR5K_TX_QUEUE_XR_DATA, 483 AR5K_TX_QUEUE_BEACON, 484 AR5K_TX_QUEUE_CAB, 485 AR5K_TX_QUEUE_UAPSD, 486}; 487 488#define AR5K_NUM_TX_QUEUES 10 489#define AR5K_NUM_TX_QUEUES_NOQCU 2 490 491/* 492 * Queue syb-types to classify normal data queues. 493 * These are the 4 Access Categories as defined in 494 * WME spec. 0 is the lowest priority and 4 is the 495 * highest. Normal data that hasn't been classified 496 * goes to the Best Effort AC. 497 */ 498enum ath5k_tx_queue_subtype { 499 AR5K_WME_AC_BK = 0, /*Background traffic*/ 500 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 501 AR5K_WME_AC_VI, /*Video traffic*/ 502 AR5K_WME_AC_VO, /*Voice traffic*/ 503}; 504 505/* 506 * Queue ID numbers as returned by the hw functions, each number 507 * represents a hw queue. If hw does not support hw queues 508 * (eg 5210) all data goes in one queue. These match 509 * d80211 definitions (net80211/MadWiFi don't use them). 510 */ 511enum ath5k_tx_queue_id { 512 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 513 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 514 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 515 AR5K_TX_QUEUE_ID_DATA_MAX = 3, /*IEEE80211_TX_QUEUE_DATA3*/ 516 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 517 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 518 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 519 AR5K_TX_QUEUE_ID_UAPSD = 8, 520 AR5K_TX_QUEUE_ID_XR_DATA = 9, 521}; 522 523/* 524 * Flags to set hw queue's parameters... 525 */ 526#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 527#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 528#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 529#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 530#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 531#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 532#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 533#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 534#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 535#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 536#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 537#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 538#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 539#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 540 541/* 542 * A struct to hold tx queue's parameters 543 */ 544struct ath5k_txq_info { 545 enum ath5k_tx_queue tqi_type; 546 enum ath5k_tx_queue_subtype tqi_subtype; 547 u16 tqi_flags; /* Tx queue flags (see above) */ 548 u8 tqi_aifs; /* Arbitrated Interframe Space */ 549 u16 tqi_cw_min; /* Minimum Contention Window */ 550 u16 tqi_cw_max; /* Maximum Contention Window */ 551 u32 tqi_cbr_period; /* Constant bit rate period */ 552 u32 tqi_cbr_overflow_limit; 553 u32 tqi_burst_time; 554 u32 tqi_ready_time; /* Time queue waits after an event */ 555}; 556 557/* 558 * Transmit packet types. 559 * used on tx control descriptor 560 */ 561enum ath5k_pkt_type { 562 AR5K_PKT_TYPE_NORMAL = 0, 563 AR5K_PKT_TYPE_ATIM = 1, 564 AR5K_PKT_TYPE_PSPOLL = 2, 565 AR5K_PKT_TYPE_BEACON = 3, 566 AR5K_PKT_TYPE_PROBE_RESP = 4, 567 AR5K_PKT_TYPE_PIFS = 5, 568}; 569 570/* 571 * TX power and TPC settings 572 */ 573#define AR5K_TXPOWER_OFDM(_r, _v) ( \ 574 ((0 & 1) << ((_v) + 6)) | \ 575 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 576) 577 578#define AR5K_TXPOWER_CCK(_r, _v) ( \ 579 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 580) 581 582/* 583 * DMA size definitions (2^(n+2)) 584 */ 585enum ath5k_dmasize { 586 AR5K_DMASIZE_4B = 0, 587 AR5K_DMASIZE_8B, 588 AR5K_DMASIZE_16B, 589 AR5K_DMASIZE_32B, 590 AR5K_DMASIZE_64B, 591 AR5K_DMASIZE_128B, 592 AR5K_DMASIZE_256B, 593 AR5K_DMASIZE_512B 594}; 595 596 597/****************\ 598 RX DEFINITIONS 599\****************/ 600 601/* 602 * RX Status descriptor 603 */ 604struct ath5k_rx_status { 605 u16 rs_datalen; 606 u16 rs_tstamp; 607 u8 rs_status; 608 u8 rs_phyerr; 609 s8 rs_rssi; 610 u8 rs_keyix; 611 u8 rs_rate; 612 u8 rs_antenna; 613 u8 rs_more; 614}; 615 616#define AR5K_RXERR_CRC 0x01 617#define AR5K_RXERR_PHY 0x02 618#define AR5K_RXERR_FIFO 0x04 619#define AR5K_RXERR_DECRYPT 0x08 620#define AR5K_RXERR_MIC 0x10 621#define AR5K_RXKEYIX_INVALID ((u8) - 1) 622#define AR5K_TXKEYIX_INVALID ((u32) - 1) 623 624 625/**************************\ 626 BEACON TIMERS DEFINITIONS 627\**************************/ 628 629#define AR5K_BEACON_PERIOD 0x0000ffff 630#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 631#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 632 633 634/* 635 * TSF to TU conversion: 636 * 637 * TSF is a 64bit value in usec (microseconds). 638 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 639 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 640 */ 641#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 642 643 644/*******************************\ 645 GAIN OPTIMIZATION DEFINITIONS 646\*******************************/ 647 648enum ath5k_rfgain { 649 AR5K_RFGAIN_INACTIVE = 0, 650 AR5K_RFGAIN_ACTIVE, 651 AR5K_RFGAIN_READ_REQUESTED, 652 AR5K_RFGAIN_NEED_CHANGE, 653}; 654 655struct ath5k_gain { 656 u8 g_step_idx; 657 u8 g_current; 658 u8 g_target; 659 u8 g_low; 660 u8 g_high; 661 u8 g_f_corr; 662 u8 g_state; 663}; 664 665/********************\ 666 COMMON DEFINITIONS 667\********************/ 668 669#define AR5K_SLOT_TIME_9 396 670#define AR5K_SLOT_TIME_20 880 671#define AR5K_SLOT_TIME_MAX 0xffff 672 673/* channel_flags */ 674#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 675#define CHANNEL_CCK 0x0020 /* CCK channel */ 676#define CHANNEL_OFDM 0x0040 /* OFDM channel */ 677#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 678#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 679#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 680#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 681#define CHANNEL_XR 0x0800 /* XR channel */ 682 683#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 684#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 685#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 686#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 687 688#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ) 689 690#define CHANNEL_MODES CHANNEL_ALL 691 692/* 693 * Used internaly for reset_tx_queue). 694 * Also see struct struct ieee80211_channel. 695 */ 696#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 697#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) 698 699/* 700 * The following structure is used to map 2GHz channels to 701 * 5GHz Atheros channels. 702 * TODO: Clean up 703 */ 704struct ath5k_athchan_2ghz { 705 u32 a2_flags; 706 u16 a2_athchan; 707}; 708 709 710/******************\ 711 RATE DEFINITIONS 712\******************/ 713 714/** 715 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 716 * 717 * The rate code is used to get the RX rate or set the TX rate on the 718 * hardware descriptors. It is also used for internal modulation control 719 * and settings. 720 * 721 * This is the hardware rate map we are aware of: 722 * 723 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 724 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 725 * 726 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 727 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 728 * 729 * rate_code 17 18 19 20 21 22 23 24 730 * rate_kbps ? ? ? ? ? ? ? 11000 731 * 732 * rate_code 25 26 27 28 29 30 31 32 733 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 734 * 735 * "S" indicates CCK rates with short preamble. 736 * 737 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 738 * lowest 4 bits, so they are the same as below with a 0xF mask. 739 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 740 * We handle this in ath5k_setup_bands(). 741 */ 742#define AR5K_MAX_RATES 32 743 744/* B */ 745#define ATH5K_RATE_CODE_1M 0x1B 746#define ATH5K_RATE_CODE_2M 0x1A 747#define ATH5K_RATE_CODE_5_5M 0x19 748#define ATH5K_RATE_CODE_11M 0x18 749/* A and G */ 750#define ATH5K_RATE_CODE_6M 0x0B 751#define ATH5K_RATE_CODE_9M 0x0F 752#define ATH5K_RATE_CODE_12M 0x0A 753#define ATH5K_RATE_CODE_18M 0x0E 754#define ATH5K_RATE_CODE_24M 0x09 755#define ATH5K_RATE_CODE_36M 0x0D 756#define ATH5K_RATE_CODE_48M 0x08 757#define ATH5K_RATE_CODE_54M 0x0C 758/* XR */ 759#define ATH5K_RATE_CODE_XR_500K 0x07 760#define ATH5K_RATE_CODE_XR_1M 0x02 761#define ATH5K_RATE_CODE_XR_2M 0x06 762#define ATH5K_RATE_CODE_XR_3M 0x01 763 764/* adding this flag to rate_code enables short preamble */ 765#define AR5K_SET_SHORT_PREAMBLE 0x04 766 767/* 768 * Crypto definitions 769 */ 770 771#define AR5K_KEYCACHE_SIZE 8 772 773/***********************\ 774 HW RELATED DEFINITIONS 775\***********************/ 776 777/* 778 * Misc definitions 779 */ 780#define AR5K_RSSI_EP_MULTIPLIER (1<<7) 781 782#define AR5K_ASSERT_ENTRY(_e, _s) do { \ 783 if (_e >= _s) \ 784 return (false); \ 785} while (0) 786 787/* 788 * Hardware interrupt abstraction 789 */ 790 791/** 792 * enum ath5k_int - Hardware interrupt masks helpers 793 * 794 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 795 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 796 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 797 * @AR5K_INT_RXNOFRM: No frame received (?) 798 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 799 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 800 * LinkPtr is NULL. For more details, refer to: 801 * http://www.freepatentsonline.com/20030225739.html 802 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 803 * Note that Rx overrun is not always fatal, on some chips we can continue 804 * operation without reseting the card, that's why int_fatal is not 805 * common for all chips. 806 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 807 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 808 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 809 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 810 * We currently do increments on interrupt by 811 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 812 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 813 * one of the PHY error counters reached the maximum value and should be 814 * read and cleared. 815 * @AR5K_INT_RXPHY: RX PHY Error 816 * @AR5K_INT_RXKCM: RX Key cache miss 817 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 818 * beacon that must be handled in software. The alternative is if you 819 * have VEOL support, in that case you let the hardware deal with things. 820 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 821 * beacons from the AP have associated with, we should probably try to 822 * reassociate. When in IBSS mode this might mean we have not received 823 * any beacons from any local stations. Note that every station in an 824 * IBSS schedules to send beacons at the Target Beacon Transmission Time 825 * (TBTT) with a random backoff. 826 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 827 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 828 * until properly handled 829 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 830 * errors. These types of errors we can enable seem to be of type 831 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 832 * @AR5K_INT_GLOBAL: Used to clear and set the IER 833 * @AR5K_INT_NOCARD: signals the card has been removed 834 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 835 * bit value 836 * 837 * These are mapped to take advantage of some common bits 838 * between the MACs, to be able to set intr properties 839 * easier. Some of them are not used yet inside hw.c. Most map 840 * to the respective hw interrupt value as they are common amogst different 841 * MACs. 842 */ 843enum ath5k_int { 844 AR5K_INT_RXOK = 0x00000001, 845 AR5K_INT_RXDESC = 0x00000002, 846 AR5K_INT_RXERR = 0x00000004, 847 AR5K_INT_RXNOFRM = 0x00000008, 848 AR5K_INT_RXEOL = 0x00000010, 849 AR5K_INT_RXORN = 0x00000020, 850 AR5K_INT_TXOK = 0x00000040, 851 AR5K_INT_TXDESC = 0x00000080, 852 AR5K_INT_TXERR = 0x00000100, 853 AR5K_INT_TXNOFRM = 0x00000200, 854 AR5K_INT_TXEOL = 0x00000400, 855 AR5K_INT_TXURN = 0x00000800, 856 AR5K_INT_MIB = 0x00001000, 857 AR5K_INT_SWI = 0x00002000, 858 AR5K_INT_RXPHY = 0x00004000, 859 AR5K_INT_RXKCM = 0x00008000, 860 AR5K_INT_SWBA = 0x00010000, 861 AR5K_INT_BRSSI = 0x00020000, 862 AR5K_INT_BMISS = 0x00040000, 863 AR5K_INT_FATAL = 0x00080000, /* Non common */ 864 AR5K_INT_BNR = 0x00100000, /* Non common */ 865 AR5K_INT_TIM = 0x00200000, /* Non common */ 866 AR5K_INT_DTIM = 0x00400000, /* Non common */ 867 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 868 AR5K_INT_GPIO = 0x01000000, 869 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 870 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 871 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 872 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 873 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 874 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 875 AR5K_INT_GLOBAL = 0x80000000, 876 877 AR5K_INT_COMMON = AR5K_INT_RXOK 878 | AR5K_INT_RXDESC 879 | AR5K_INT_RXERR 880 | AR5K_INT_RXNOFRM 881 | AR5K_INT_RXEOL 882 | AR5K_INT_RXORN 883 | AR5K_INT_TXOK 884 | AR5K_INT_TXDESC 885 | AR5K_INT_TXERR 886 | AR5K_INT_TXNOFRM 887 | AR5K_INT_TXEOL 888 | AR5K_INT_TXURN 889 | AR5K_INT_MIB 890 | AR5K_INT_SWI 891 | AR5K_INT_RXPHY 892 | AR5K_INT_RXKCM 893 | AR5K_INT_SWBA 894 | AR5K_INT_BRSSI 895 | AR5K_INT_BMISS 896 | AR5K_INT_GPIO 897 | AR5K_INT_GLOBAL, 898 899 AR5K_INT_NOCARD = 0xffffffff 900}; 901 902/* mask which calibration is active at the moment */ 903enum ath5k_calibration_mask { 904 AR5K_CALIBRATION_FULL = 0x01, 905 AR5K_CALIBRATION_SHORT = 0x02, 906 AR5K_CALIBRATION_ANI = 0x04, 907}; 908 909/* 910 * Power management 911 */ 912enum ath5k_power_mode { 913 AR5K_PM_UNDEFINED = 0, 914 AR5K_PM_AUTO, 915 AR5K_PM_AWAKE, 916 AR5K_PM_FULL_SLEEP, 917 AR5K_PM_NETWORK_SLEEP, 918}; 919 920/* 921 * These match net80211 definitions (not used in 922 * mac80211). 923 * TODO: Clean this up 924 */ 925#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 926#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 927#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 928#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 929#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 930 931/* GPIO-controlled software LED */ 932#define AR5K_SOFTLED_PIN 0 933#define AR5K_SOFTLED_ON 0 934#define AR5K_SOFTLED_OFF 1 935 936/* 937 * Chipset capabilities -see ath5k_hw_get_capability- 938 * get_capability function is not yet fully implemented 939 * in ath5k so most of these don't work yet... 940 * TODO: Implement these & merge with _TUNE_ stuff above 941 */ 942enum ath5k_capability_type { 943 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 944 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 945 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 946 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 947 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 948 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 949 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 950 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 951 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 952 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 953 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 954 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 955 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 956 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 957 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 958 AR5K_CAP_XR = 16, /* Supports XR mode */ 959 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 960 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 961 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 962 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 963}; 964 965 966/* XXX: we *may* move cap_range stuff to struct wiphy */ 967struct ath5k_capabilities { 968 /* 969 * Supported PHY modes 970 * (ie. CHANNEL_A, CHANNEL_B, ...) 971 */ 972 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 973 974 /* 975 * Frequency range (without regulation restrictions) 976 */ 977 struct { 978 u16 range_2ghz_min; 979 u16 range_2ghz_max; 980 u16 range_5ghz_min; 981 u16 range_5ghz_max; 982 } cap_range; 983 984 /* 985 * Values stored in the EEPROM (some of them...) 986 */ 987 struct ath5k_eeprom_info cap_eeprom; 988 989 /* 990 * Queue information 991 */ 992 struct { 993 u8 q_tx_num; 994 } cap_queues; 995 996 bool cap_has_phyerr_counters; 997}; 998 999/* size of noise floor history (keep it a power of two) */ 1000#define ATH5K_NF_CAL_HIST_MAX 8 1001struct ath5k_nfcal_hist 1002{ 1003 s16 index; /* current index into nfval */ 1004 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 1005}; 1006 1007/** 1008 * struct avg_val - Helper structure for average calculation 1009 * @avg: contains the actual average value 1010 * @avg_weight: is used internally during calculation to prevent rounding errors 1011 */ 1012struct ath5k_avg_val { 1013 int avg; 1014 int avg_weight; 1015}; 1016 1017/***************************************\ 1018 HARDWARE ABSTRACTION LAYER STRUCTURE 1019\***************************************/ 1020 1021/* 1022 * Misc defines 1023 */ 1024 1025#define AR5K_MAX_GPIO 10 1026#define AR5K_MAX_RF_BANKS 8 1027 1028/* TODO: Clean up and merge with ath5k_softc */ 1029struct ath5k_hw { 1030 struct ath_common common; 1031 1032 struct ath5k_softc *ah_sc; 1033 void __iomem *ah_iobase; 1034 1035 enum ath5k_int ah_imr; 1036 1037 struct ieee80211_channel *ah_current_channel; 1038 bool ah_calibration; 1039 bool ah_single_chip; 1040 1041 enum ath5k_version ah_version; 1042 enum ath5k_radio ah_radio; 1043 u32 ah_phy; 1044 u32 ah_mac_srev; 1045 u16 ah_mac_version; 1046 u16 ah_mac_revision; 1047 u16 ah_phy_revision; 1048 u16 ah_radio_5ghz_revision; 1049 u16 ah_radio_2ghz_revision; 1050 1051#define ah_modes ah_capabilities.cap_mode 1052#define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1053 1054 u8 ah_retry_long; 1055 u8 ah_retry_short; 1056 1057 u8 ah_coverage_class; 1058 bool ah_ack_bitrate_high; 1059 u8 ah_bwmode; 1060 1061 /* Antenna Control */ 1062 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1063 u8 ah_ant_mode; 1064 u8 ah_tx_ant; 1065 u8 ah_def_ant; 1066 1067 struct ath5k_capabilities ah_capabilities; 1068 1069 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1070 u32 ah_txq_status; 1071 u32 ah_txq_imr_txok; 1072 u32 ah_txq_imr_txerr; 1073 u32 ah_txq_imr_txurn; 1074 u32 ah_txq_imr_txdesc; 1075 u32 ah_txq_imr_txeol; 1076 u32 ah_txq_imr_cbrorn; 1077 u32 ah_txq_imr_cbrurn; 1078 u32 ah_txq_imr_qtrig; 1079 u32 ah_txq_imr_nofrm; 1080 u32 ah_txq_isr; 1081 u32 *ah_rf_banks; 1082 size_t ah_rf_banks_size; 1083 size_t ah_rf_regs_count; 1084 struct ath5k_gain ah_gain; 1085 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1086 1087 1088 struct { 1089 /* Temporary tables used for interpolation */ 1090 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1091 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1092 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1093 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1094 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1095 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1096 u8 txp_min_idx; 1097 bool txp_tpc; 1098 /* Values in 0.25dB units */ 1099 s16 txp_min_pwr; 1100 s16 txp_max_pwr; 1101 s16 txp_cur_pwr; 1102 /* Values in 0.5dB units */ 1103 s16 txp_offset; 1104 s16 txp_ofdm; 1105 s16 txp_cck_ofdm_gainf_delta; 1106 /* Value in dB units */ 1107 s16 txp_cck_ofdm_pwr_delta; 1108 bool txp_setup; 1109 } ah_txpower; 1110 1111 struct { 1112 bool r_enabled; 1113 int r_last_alert; 1114 struct ieee80211_channel r_last_channel; 1115 } ah_radar; 1116 1117 struct ath5k_nfcal_hist ah_nfcal_hist; 1118 1119 /* average beacon RSSI in our BSS (used by ANI) */ 1120 struct ewma ah_beacon_rssi_avg; 1121 1122 /* noise floor from last periodic calibration */ 1123 s32 ah_noise_floor; 1124 1125 /* Calibration timestamp */ 1126 unsigned long ah_cal_next_full; 1127 unsigned long ah_cal_next_ani; 1128 unsigned long ah_cal_next_nf; 1129 1130 /* Calibration mask */ 1131 u8 ah_cal_mask; 1132 1133 /* 1134 * Function pointers 1135 */ 1136 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1137 unsigned int, unsigned int, int, enum ath5k_pkt_type, 1138 unsigned int, unsigned int, unsigned int, unsigned int, 1139 unsigned int, unsigned int, unsigned int, unsigned int); 1140 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1141 struct ath5k_tx_status *); 1142 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1143 struct ath5k_rx_status *); 1144}; 1145 1146/* 1147 * Prototypes 1148 */ 1149extern const struct ieee80211_ops ath5k_hw_ops; 1150 1151/* Initialization and detach functions */ 1152int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops); 1153void ath5k_deinit_softc(struct ath5k_softc *sc); 1154int ath5k_hw_init(struct ath5k_softc *sc); 1155void ath5k_hw_deinit(struct ath5k_hw *ah); 1156 1157int ath5k_sysfs_register(struct ath5k_softc *sc); 1158void ath5k_sysfs_unregister(struct ath5k_softc *sc); 1159 1160/* base.c */ 1161struct ath5k_buf; 1162struct ath5k_txq; 1163 1164void set_beacon_filter(struct ieee80211_hw *hw, bool enable); 1165bool ath_any_vif_assoc(struct ath5k_softc *sc); 1166void ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1167 struct ath5k_txq *txq); 1168int ath5k_init_hw(struct ath5k_softc *sc); 1169int ath5k_stop_hw(struct ath5k_softc *sc); 1170void ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif); 1171void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, 1172 struct ieee80211_vif *vif); 1173int ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan); 1174void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 1175int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 1176void ath5k_beacon_config(struct ath5k_softc *sc); 1177void ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf); 1178void ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf); 1179 1180/*Chip id helper functions */ 1181const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val); 1182int ath5k_hw_read_srev(struct ath5k_hw *ah); 1183 1184/* LED functions */ 1185int ath5k_init_leds(struct ath5k_softc *sc); 1186void ath5k_led_enable(struct ath5k_softc *sc); 1187void ath5k_led_off(struct ath5k_softc *sc); 1188void ath5k_unregister_leds(struct ath5k_softc *sc); 1189 1190 1191/* Reset Functions */ 1192int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1193int ath5k_hw_on_hold(struct ath5k_hw *ah); 1194int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1195 struct ieee80211_channel *channel, bool fast, bool skip_pcu); 1196int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 1197 bool is_set); 1198/* Power management functions */ 1199 1200 1201/* Clock rate related functions */ 1202unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1203unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1204void ath5k_hw_set_clockrate(struct ath5k_hw *ah); 1205 1206 1207/* DMA Related Functions */ 1208void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1209u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1210int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1211int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1212int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue); 1213u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1214int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1215 u32 phys_addr); 1216int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1217/* Interrupt handling */ 1218bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1219int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1220enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1221void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); 1222/* Init/Stop functions */ 1223void ath5k_hw_dma_init(struct ath5k_hw *ah); 1224int ath5k_hw_dma_stop(struct ath5k_hw *ah); 1225 1226/* EEPROM access functions */ 1227int ath5k_eeprom_init(struct ath5k_hw *ah); 1228void ath5k_eeprom_detach(struct ath5k_hw *ah); 1229int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1230 1231 1232/* Protocol Control Unit Functions */ 1233/* Helpers */ 1234int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 1235 int len, struct ieee80211_rate *rate, bool shortpre); 1236unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah); 1237unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah); 1238extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1239void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1240/* RX filter control*/ 1241int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1242void ath5k_hw_set_bssid(struct ath5k_hw *ah); 1243void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1244void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1245u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1246void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1247/* Receive (DRU) start/stop functions */ 1248void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1249void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1250/* Beacon control functions */ 1251u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1252void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1253void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1254void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1255bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); 1256/* Init function */ 1257void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1258 u8 mode); 1259 1260/* Queue Control Unit, DFS Control Unit Functions */ 1261int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1262 struct ath5k_txq_info *queue_info); 1263int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1264 const struct ath5k_txq_info *queue_info); 1265int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1266 enum ath5k_tx_queue queue_type, 1267 struct ath5k_txq_info *queue_info); 1268void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah, 1269 unsigned int queue); 1270u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1271void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1272int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1273int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time); 1274/* Init function */ 1275int ath5k_hw_init_queues(struct ath5k_hw *ah); 1276 1277/* Hardware Descriptor Functions */ 1278int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1279int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1280 u32 size, unsigned int flags); 1281int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1282 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 1283 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); 1284 1285 1286/* GPIO Functions */ 1287void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1288int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1289int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1290u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1291int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1292void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 1293 u32 interrupt_level); 1294 1295 1296/* RFkill Functions */ 1297void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1298void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1299 1300 1301/* Misc functions TODO: Cleanup */ 1302int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1303int ath5k_hw_get_capability(struct ath5k_hw *ah, 1304 enum ath5k_capability_type cap_type, u32 capability, 1305 u32 *result); 1306int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1307int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1308 1309 1310/* Initial register settings functions */ 1311int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1312 1313 1314/* PHY functions */ 1315/* Misc PHY functions */ 1316u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1317int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1318/* Gain_F optimization */ 1319enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1320int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1321/* PHY/RF channel functions */ 1322bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1323/* PHY calibration */ 1324void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1325int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1326 struct ieee80211_channel *channel); 1327void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); 1328/* Spur mitigation */ 1329bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1330 struct ieee80211_channel *channel); 1331/* Antenna control */ 1332void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1333void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); 1334/* TX power setup */ 1335int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1336/* Init function */ 1337int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 1338 u8 mode, bool fast); 1339 1340/* 1341 * Functions used internaly 1342 */ 1343 1344static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1345{ 1346 return &ah->common; 1347} 1348 1349static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1350{ 1351 return &(ath5k_hw_common(ah)->regulatory); 1352} 1353 1354#ifdef CONFIG_ATHEROS_AR231X 1355#define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000) 1356 1357static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg) 1358{ 1359 /* On AR2315 and AR2317 the PCI clock domain registers 1360 * are outside of the WMAC register space */ 1361 if (unlikely((reg >= 0x4000) && (reg < 0x5000) && 1362 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6))) 1363 return AR5K_AR2315_PCI_BASE + reg; 1364 1365 return ah->ah_iobase + reg; 1366} 1367 1368static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1369{ 1370 return __raw_readl(ath5k_ahb_reg(ah, reg)); 1371} 1372 1373static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1374{ 1375 __raw_writel(val, ath5k_ahb_reg(ah, reg)); 1376} 1377 1378#else 1379 1380static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1381{ 1382 return ioread32(ah->ah_iobase + reg); 1383} 1384 1385static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1386{ 1387 iowrite32(val, ah->ah_iobase + reg); 1388} 1389 1390#endif 1391 1392static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah) 1393{ 1394 return ath5k_hw_common(ah)->bus_ops->ath_bus_type; 1395} 1396 1397static inline void ath5k_read_cachesize(struct ath_common *common, int *csz) 1398{ 1399 common->bus_ops->read_cachesize(common, csz); 1400} 1401 1402static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data) 1403{ 1404 struct ath_common *common = ath5k_hw_common(ah); 1405 return common->bus_ops->eeprom_read(common, off, data); 1406} 1407 1408static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1409{ 1410 u32 retval = 0, bit, i; 1411 1412 for (i = 0; i < bits; i++) { 1413 bit = (val >> i) & 1; 1414 retval = (retval << 1) | bit; 1415 } 1416 1417 return retval; 1418} 1419 1420#endif 1421