ath5k.h revision 608b88cb34b0e70a538ee1fc334cc833ef691836
1/* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _ATH5K_H 19#define _ATH5K_H 20 21/* TODO: Clean up channel debuging -doesn't work anyway- and start 22 * working on reg. control code using all available eeprom information 23 * -rev. engineering needed- */ 24#define CHAN_DEBUG 0 25 26#include <linux/io.h> 27#include <linux/types.h> 28#include <net/mac80211.h> 29 30/* RX/TX descriptor hw structs 31 * TODO: Driver part should only see sw structs */ 32#include "desc.h" 33 34/* EEPROM structs/offsets 35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 36 * and clean up common bits, then introduce set/get functions in eeprom.c */ 37#include "eeprom.h" 38 39/* PCI IDs */ 40#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 41#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 42#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 43#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 44#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 45#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 46#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 47#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 48#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 49#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 50#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 51#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 52#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 53#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 54#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 55#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 57#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 58#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 59#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 60#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 61#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 62#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 63#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 64#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 65#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 66#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 67#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 68 69/****************************\ 70 GENERIC DRIVER DEFINITIONS 71\****************************/ 72 73#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 74 75#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 76 printk(_level "ath5k %s: " _fmt, \ 77 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 78 ##__VA_ARGS__) 79 80#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 81 if (net_ratelimit()) \ 82 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 83 } while (0) 84 85#define ATH5K_INFO(_sc, _fmt, ...) \ 86 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 87 88#define ATH5K_WARN(_sc, _fmt, ...) \ 89 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 90 91#define ATH5K_ERR(_sc, _fmt, ...) \ 92 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 93 94/* 95 * AR5K REGISTER ACCESS 96 */ 97 98/* Some macros to read/write fields */ 99 100/* First shift, then mask */ 101#define AR5K_REG_SM(_val, _flags) \ 102 (((_val) << _flags##_S) & (_flags)) 103 104/* First mask, then shift */ 105#define AR5K_REG_MS(_val, _flags) \ 106 (((_val) & (_flags)) >> _flags##_S) 107 108/* Some registers can hold multiple values of interest. For this 109 * reason when we want to write to these registers we must first 110 * retrieve the values which we do not want to clear (lets call this 111 * old_data) and then set the register with this and our new_value: 112 * ( old_data | new_value) */ 113#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 114 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 115 (((_val) << _flags##_S) & (_flags)), _reg) 116 117#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 118 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 119 (_mask)) | (_flags), _reg) 120 121#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 122 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 123 124#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 125 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 126 127/* Access to PHY registers */ 128#define AR5K_PHY_READ(ah, _reg) \ 129 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 130 131#define AR5K_PHY_WRITE(ah, _reg, _val) \ 132 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 133 134/* Access QCU registers per queue */ 135#define AR5K_REG_READ_Q(ah, _reg, _queue) \ 136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 137 138#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 139 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 140 141#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 142 _reg |= 1 << _queue; \ 143} while (0) 144 145#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 146 _reg &= ~(1 << _queue); \ 147} while (0) 148 149/* Used while writing initvals */ 150#define AR5K_REG_WAIT(_i) do { \ 151 if (_i % 64) \ 152 udelay(1); \ 153} while (0) 154 155/* Register dumps are done per operation mode */ 156#define AR5K_INI_RFGAIN_5GHZ 0 157#define AR5K_INI_RFGAIN_2GHZ 1 158 159/* TODO: Clean this up */ 160#define AR5K_INI_VAL_11A 0 161#define AR5K_INI_VAL_11A_TURBO 1 162#define AR5K_INI_VAL_11B 2 163#define AR5K_INI_VAL_11G 3 164#define AR5K_INI_VAL_11G_TURBO 4 165#define AR5K_INI_VAL_XR 0 166#define AR5K_INI_VAL_MAX 5 167 168/* Used for BSSID etc manipulation */ 169#define AR5K_LOW_ID(_a)( \ 170(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ 171) 172 173#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) 174 175/* 176 * Some tuneable values (these should be changeable by the user) 177 * TODO: Make use of them and add more options OR use debug/configfs 178 */ 179#define AR5K_TUNE_DMA_BEACON_RESP 2 180#define AR5K_TUNE_SW_BEACON_RESP 10 181#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 182#define AR5K_TUNE_RADAR_ALERT false 183#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 184#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) 185#define AR5K_TUNE_REGISTER_TIMEOUT 20000 186/* Register for RSSI threshold has a mask of 0xff, so 255 seems to 187 * be the max value. */ 188#define AR5K_TUNE_RSSI_THRES 129 189/* This must be set when setting the RSSI threshold otherwise it can 190 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 191 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 192 * track of it. Max value depends on harware. For AR5210 this is just 7. 193 * For AR5211+ this seems to be up to 255. */ 194#define AR5K_TUNE_BMISS_THRES 7 195#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 196#define AR5K_TUNE_BEACON_INTERVAL 100 197#define AR5K_TUNE_AIFS 2 198#define AR5K_TUNE_AIFS_11B 2 199#define AR5K_TUNE_AIFS_XR 0 200#define AR5K_TUNE_CWMIN 15 201#define AR5K_TUNE_CWMIN_11B 31 202#define AR5K_TUNE_CWMIN_XR 3 203#define AR5K_TUNE_CWMAX 1023 204#define AR5K_TUNE_CWMAX_11B 1023 205#define AR5K_TUNE_CWMAX_XR 7 206#define AR5K_TUNE_NOISE_FLOOR -72 207#define AR5K_TUNE_MAX_TXPOWER 63 208#define AR5K_TUNE_DEFAULT_TXPOWER 25 209#define AR5K_TUNE_TPC_TXPOWER false 210#define AR5K_TUNE_HWTXTRIES 4 211 212#define AR5K_INIT_CARR_SENSE_EN 1 213 214/*Swap RX/TX Descriptor for big endian archs*/ 215#if defined(__BIG_ENDIAN) 216#define AR5K_INIT_CFG ( \ 217 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 218) 219#else 220#define AR5K_INIT_CFG 0x00000000 221#endif 222 223/* Initial values */ 224#define AR5K_INIT_CYCRSSI_THR1 2 225#define AR5K_INIT_TX_LATENCY 502 226#define AR5K_INIT_USEC 39 227#define AR5K_INIT_USEC_TURBO 79 228#define AR5K_INIT_USEC_32 31 229#define AR5K_INIT_SLOT_TIME 396 230#define AR5K_INIT_SLOT_TIME_TURBO 480 231#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 232#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 233#define AR5K_INIT_PROG_IFS 920 234#define AR5K_INIT_PROG_IFS_TURBO 960 235#define AR5K_INIT_EIFS 3440 236#define AR5K_INIT_EIFS_TURBO 6880 237#define AR5K_INIT_SIFS 560 238#define AR5K_INIT_SIFS_TURBO 480 239#define AR5K_INIT_SH_RETRY 10 240#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY 241#define AR5K_INIT_SSH_RETRY 32 242#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY 243#define AR5K_INIT_TX_RETRY 10 244 245#define AR5K_INIT_TRANSMIT_LATENCY ( \ 246 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 247 (AR5K_INIT_USEC) \ 248) 249#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ 250 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 251 (AR5K_INIT_USEC_TURBO) \ 252) 253#define AR5K_INIT_PROTO_TIME_CNTRL ( \ 254 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ 255 (AR5K_INIT_PROG_IFS) \ 256) 257#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ 258 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ 259 (AR5K_INIT_PROG_IFS_TURBO) \ 260) 261 262/* token to use for aifs, cwmin, cwmax in MadWiFi */ 263#define AR5K_TXQ_USEDEFAULT ((u32) -1) 264 265/* GENERIC CHIPSET DEFINITIONS */ 266 267/* MAC Chips */ 268enum ath5k_version { 269 AR5K_AR5210 = 0, 270 AR5K_AR5211 = 1, 271 AR5K_AR5212 = 2, 272}; 273 274/* PHY Chips */ 275enum ath5k_radio { 276 AR5K_RF5110 = 0, 277 AR5K_RF5111 = 1, 278 AR5K_RF5112 = 2, 279 AR5K_RF2413 = 3, 280 AR5K_RF5413 = 4, 281 AR5K_RF2316 = 5, 282 AR5K_RF2317 = 6, 283 AR5K_RF2425 = 7, 284}; 285 286/* 287 * Common silicon revision/version values 288 */ 289 290enum ath5k_srev_type { 291 AR5K_VERSION_MAC, 292 AR5K_VERSION_RAD, 293}; 294 295struct ath5k_srev_name { 296 const char *sr_name; 297 enum ath5k_srev_type sr_type; 298 u_int sr_val; 299}; 300 301#define AR5K_SREV_UNKNOWN 0xffff 302 303#define AR5K_SREV_AR5210 0x00 /* Crete */ 304#define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 305#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 306#define AR5K_SREV_AR5311B 0x30 /* Spirit */ 307#define AR5K_SREV_AR5211 0x40 /* Oahu */ 308#define AR5K_SREV_AR5212 0x50 /* Venice */ 309#define AR5K_SREV_AR5213 0x55 /* ??? */ 310#define AR5K_SREV_AR5213A 0x59 /* Hainan */ 311#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 312#define AR5K_SREV_AR2414 0x70 /* Griffin */ 313#define AR5K_SREV_AR5424 0x90 /* Condor */ 314#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 315#define AR5K_SREV_AR5414 0xa0 /* Eagle */ 316#define AR5K_SREV_AR2415 0xb0 /* Talon */ 317#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 318#define AR5K_SREV_AR5418 0xca /* PCI-E */ 319#define AR5K_SREV_AR2425 0xe0 /* Swan */ 320#define AR5K_SREV_AR2417 0xf0 /* Nala */ 321 322#define AR5K_SREV_RAD_5110 0x00 323#define AR5K_SREV_RAD_5111 0x10 324#define AR5K_SREV_RAD_5111A 0x15 325#define AR5K_SREV_RAD_2111 0x20 326#define AR5K_SREV_RAD_5112 0x30 327#define AR5K_SREV_RAD_5112A 0x35 328#define AR5K_SREV_RAD_5112B 0x36 329#define AR5K_SREV_RAD_2112 0x40 330#define AR5K_SREV_RAD_2112A 0x45 331#define AR5K_SREV_RAD_2112B 0x46 332#define AR5K_SREV_RAD_2413 0x50 333#define AR5K_SREV_RAD_5413 0x60 334#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 335#define AR5K_SREV_RAD_2317 0x80 336#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 337#define AR5K_SREV_RAD_2425 0xa2 338#define AR5K_SREV_RAD_5133 0xc0 339 340#define AR5K_SREV_PHY_5211 0x30 341#define AR5K_SREV_PHY_5212 0x41 342#define AR5K_SREV_PHY_5212A 0x42 343#define AR5K_SREV_PHY_5212B 0x43 344#define AR5K_SREV_PHY_2413 0x45 345#define AR5K_SREV_PHY_5413 0x61 346#define AR5K_SREV_PHY_2425 0x70 347 348/* IEEE defs */ 349#define IEEE80211_MAX_LEN 2500 350 351/* TODO add support to mac80211 for vendor-specific rates and modes */ 352 353/* 354 * Some of this information is based on Documentation from: 355 * 356 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG 357 * 358 * Modulation for Atheros' eXtended Range - range enhancing extension that is 359 * supposed to double the distance an Atheros client device can keep a 360 * connection with an Atheros access point. This is achieved by increasing 361 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 362 * the 802.11 specifications demand. In addition, new (proprietary) data rates 363 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 364 * 365 * Please note that can you either use XR or TURBO but you cannot use both, 366 * they are exclusive. 367 * 368 */ 369#define MODULATION_XR 0x00000200 370/* 371 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 372 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 373 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 374 * channels. To use this feature your Access Point must also suport it. 375 * There is also a distinction between "static" and "dynamic" turbo modes: 376 * 377 * - Static: is the dumb version: devices set to this mode stick to it until 378 * the mode is turned off. 379 * - Dynamic: is the intelligent version, the network decides itself if it 380 * is ok to use turbo. As soon as traffic is detected on adjacent channels 381 * (which would get used in turbo mode), or when a non-turbo station joins 382 * the network, turbo mode won't be used until the situation changes again. 383 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 384 * monitors the used radio band in order to decide whether turbo mode may 385 * be used or not. 386 * 387 * This article claims Super G sticks to bonding of channels 5 and 6 for 388 * USA: 389 * 390 * http://www.pcworld.com/article/id,113428-page,1/article.html 391 * 392 * The channel bonding seems to be driver specific though. In addition to 393 * deciding what channels will be used, these "Turbo" modes are accomplished 394 * by also enabling the following features: 395 * 396 * - Bursting: allows multiple frames to be sent at once, rather than pausing 397 * after each frame. Bursting is a standards-compliant feature that can be 398 * used with any Access Point. 399 * - Fast frames: increases the amount of information that can be sent per 400 * frame, also resulting in a reduction of transmission overhead. It is a 401 * proprietary feature that needs to be supported by the Access Point. 402 * - Compression: data frames are compressed in real time using a Lempel Ziv 403 * algorithm. This is done transparently. Once this feature is enabled, 404 * compression and decompression takes place inside the chipset, without 405 * putting additional load on the host CPU. 406 * 407 */ 408#define MODULATION_TURBO 0x00000080 409 410enum ath5k_driver_mode { 411 AR5K_MODE_11A = 0, 412 AR5K_MODE_11A_TURBO = 1, 413 AR5K_MODE_11B = 2, 414 AR5K_MODE_11G = 3, 415 AR5K_MODE_11G_TURBO = 4, 416 AR5K_MODE_XR = 0, 417 AR5K_MODE_MAX = 5 418}; 419 420enum ath5k_ant_mode { 421 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 422 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 423 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 424 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 425 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 426 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 427 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 428 AR5K_ANTMODE_MAX, 429}; 430 431 432/****************\ 433 TX DEFINITIONS 434\****************/ 435 436/* 437 * TX Status descriptor 438 */ 439struct ath5k_tx_status { 440 u16 ts_seqnum; 441 u16 ts_tstamp; 442 u8 ts_status; 443 u8 ts_rate[4]; 444 u8 ts_retry[4]; 445 u8 ts_final_idx; 446 s8 ts_rssi; 447 u8 ts_shortretry; 448 u8 ts_longretry; 449 u8 ts_virtcol; 450 u8 ts_antenna; 451}; 452 453#define AR5K_TXSTAT_ALTRATE 0x80 454#define AR5K_TXERR_XRETRY 0x01 455#define AR5K_TXERR_FILT 0x02 456#define AR5K_TXERR_FIFO 0x04 457 458/** 459 * enum ath5k_tx_queue - Queue types used to classify tx queues. 460 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 461 * @AR5K_TX_QUEUE_DATA: A normal data queue 462 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 463 * @AR5K_TX_QUEUE_BEACON: The beacon queue 464 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 465 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 466 */ 467enum ath5k_tx_queue { 468 AR5K_TX_QUEUE_INACTIVE = 0, 469 AR5K_TX_QUEUE_DATA, 470 AR5K_TX_QUEUE_XR_DATA, 471 AR5K_TX_QUEUE_BEACON, 472 AR5K_TX_QUEUE_CAB, 473 AR5K_TX_QUEUE_UAPSD, 474}; 475 476#define AR5K_NUM_TX_QUEUES 10 477#define AR5K_NUM_TX_QUEUES_NOQCU 2 478 479/* 480 * Queue syb-types to classify normal data queues. 481 * These are the 4 Access Categories as defined in 482 * WME spec. 0 is the lowest priority and 4 is the 483 * highest. Normal data that hasn't been classified 484 * goes to the Best Effort AC. 485 */ 486enum ath5k_tx_queue_subtype { 487 AR5K_WME_AC_BK = 0, /*Background traffic*/ 488 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 489 AR5K_WME_AC_VI, /*Video traffic*/ 490 AR5K_WME_AC_VO, /*Voice traffic*/ 491}; 492 493/* 494 * Queue ID numbers as returned by the hw functions, each number 495 * represents a hw queue. If hw does not support hw queues 496 * (eg 5210) all data goes in one queue. These match 497 * d80211 definitions (net80211/MadWiFi don't use them). 498 */ 499enum ath5k_tx_queue_id { 500 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 501 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 502 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 503 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ 504 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 505 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 506 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 507 AR5K_TX_QUEUE_ID_UAPSD = 8, 508 AR5K_TX_QUEUE_ID_XR_DATA = 9, 509}; 510 511/* 512 * Flags to set hw queue's parameters... 513 */ 514#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 515#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 516#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 517#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 518#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 519#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 520#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 521#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 522#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 523#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 524#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 525#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 526#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 527#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 528 529/* 530 * A struct to hold tx queue's parameters 531 */ 532struct ath5k_txq_info { 533 enum ath5k_tx_queue tqi_type; 534 enum ath5k_tx_queue_subtype tqi_subtype; 535 u16 tqi_flags; /* Tx queue flags (see above) */ 536 u32 tqi_aifs; /* Arbitrated Interframe Space */ 537 s32 tqi_cw_min; /* Minimum Contention Window */ 538 s32 tqi_cw_max; /* Maximum Contention Window */ 539 u32 tqi_cbr_period; /* Constant bit rate period */ 540 u32 tqi_cbr_overflow_limit; 541 u32 tqi_burst_time; 542 u32 tqi_ready_time; /* Not used */ 543}; 544 545/* 546 * Transmit packet types. 547 * used on tx control descriptor 548 * TODO: Use them inside base.c corectly 549 */ 550enum ath5k_pkt_type { 551 AR5K_PKT_TYPE_NORMAL = 0, 552 AR5K_PKT_TYPE_ATIM = 1, 553 AR5K_PKT_TYPE_PSPOLL = 2, 554 AR5K_PKT_TYPE_BEACON = 3, 555 AR5K_PKT_TYPE_PROBE_RESP = 4, 556 AR5K_PKT_TYPE_PIFS = 5, 557}; 558 559/* 560 * TX power and TPC settings 561 */ 562#define AR5K_TXPOWER_OFDM(_r, _v) ( \ 563 ((0 & 1) << ((_v) + 6)) | \ 564 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 565) 566 567#define AR5K_TXPOWER_CCK(_r, _v) ( \ 568 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 569) 570 571/* 572 * DMA size definitions (2^n+2) 573 */ 574enum ath5k_dmasize { 575 AR5K_DMASIZE_4B = 0, 576 AR5K_DMASIZE_8B, 577 AR5K_DMASIZE_16B, 578 AR5K_DMASIZE_32B, 579 AR5K_DMASIZE_64B, 580 AR5K_DMASIZE_128B, 581 AR5K_DMASIZE_256B, 582 AR5K_DMASIZE_512B 583}; 584 585 586/****************\ 587 RX DEFINITIONS 588\****************/ 589 590/* 591 * RX Status descriptor 592 */ 593struct ath5k_rx_status { 594 u16 rs_datalen; 595 u16 rs_tstamp; 596 u8 rs_status; 597 u8 rs_phyerr; 598 s8 rs_rssi; 599 u8 rs_keyix; 600 u8 rs_rate; 601 u8 rs_antenna; 602 u8 rs_more; 603}; 604 605#define AR5K_RXERR_CRC 0x01 606#define AR5K_RXERR_PHY 0x02 607#define AR5K_RXERR_FIFO 0x04 608#define AR5K_RXERR_DECRYPT 0x08 609#define AR5K_RXERR_MIC 0x10 610#define AR5K_RXKEYIX_INVALID ((u8) - 1) 611#define AR5K_TXKEYIX_INVALID ((u32) - 1) 612 613 614/**************************\ 615 BEACON TIMERS DEFINITIONS 616\**************************/ 617 618#define AR5K_BEACON_PERIOD 0x0000ffff 619#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 620#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 621 622#if 0 623/** 624 * struct ath5k_beacon_state - Per-station beacon timer state. 625 * @bs_interval: in TU's, can also include the above flags 626 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a 627 * Point Coordination Function capable AP 628 */ 629struct ath5k_beacon_state { 630 u32 bs_next_beacon; 631 u32 bs_next_dtim; 632 u32 bs_interval; 633 u8 bs_dtim_period; 634 u8 bs_cfp_period; 635 u16 bs_cfp_max_duration; 636 u16 bs_cfp_du_remain; 637 u16 bs_tim_offset; 638 u16 bs_sleep_duration; 639 u16 bs_bmiss_threshold; 640 u32 bs_cfp_next; 641}; 642#endif 643 644 645/* 646 * TSF to TU conversion: 647 * 648 * TSF is a 64bit value in usec (microseconds). 649 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 650 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 651 */ 652#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 653 654 655/*******************************\ 656 GAIN OPTIMIZATION DEFINITIONS 657\*******************************/ 658 659enum ath5k_rfgain { 660 AR5K_RFGAIN_INACTIVE = 0, 661 AR5K_RFGAIN_ACTIVE, 662 AR5K_RFGAIN_READ_REQUESTED, 663 AR5K_RFGAIN_NEED_CHANGE, 664}; 665 666struct ath5k_gain { 667 u8 g_step_idx; 668 u8 g_current; 669 u8 g_target; 670 u8 g_low; 671 u8 g_high; 672 u8 g_f_corr; 673 u8 g_state; 674}; 675 676/********************\ 677 COMMON DEFINITIONS 678\********************/ 679 680#define AR5K_SLOT_TIME_9 396 681#define AR5K_SLOT_TIME_20 880 682#define AR5K_SLOT_TIME_MAX 0xffff 683 684/* channel_flags */ 685#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 686#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ 687#define CHANNEL_CCK 0x0020 /* CCK channel */ 688#define CHANNEL_OFDM 0x0040 /* OFDM channel */ 689#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 690#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 691#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 692#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 693#define CHANNEL_XR 0x0800 /* XR channel */ 694 695#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 696#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 697#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 698#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 699#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 700#define CHANNEL_108A CHANNEL_T 701#define CHANNEL_108G CHANNEL_TG 702#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 703 704#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ 705 CHANNEL_TURBO) 706 707#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) 708#define CHANNEL_MODES CHANNEL_ALL 709 710/* 711 * Used internaly for reset_tx_queue). 712 * Also see struct struct ieee80211_channel. 713 */ 714#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 715#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) 716 717/* 718 * The following structure is used to map 2GHz channels to 719 * 5GHz Atheros channels. 720 * TODO: Clean up 721 */ 722struct ath5k_athchan_2ghz { 723 u32 a2_flags; 724 u16 a2_athchan; 725}; 726 727 728/******************\ 729 RATE DEFINITIONS 730\******************/ 731 732/** 733 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 734 * 735 * The rate code is used to get the RX rate or set the TX rate on the 736 * hardware descriptors. It is also used for internal modulation control 737 * and settings. 738 * 739 * This is the hardware rate map we are aware of: 740 * 741 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 742 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 743 * 744 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 745 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 746 * 747 * rate_code 17 18 19 20 21 22 23 24 748 * rate_kbps ? ? ? ? ? ? ? 11000 749 * 750 * rate_code 25 26 27 28 29 30 31 32 751 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 752 * 753 * "S" indicates CCK rates with short preamble. 754 * 755 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 756 * lowest 4 bits, so they are the same as below with a 0xF mask. 757 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 758 * We handle this in ath5k_setup_bands(). 759 */ 760#define AR5K_MAX_RATES 32 761 762/* B */ 763#define ATH5K_RATE_CODE_1M 0x1B 764#define ATH5K_RATE_CODE_2M 0x1A 765#define ATH5K_RATE_CODE_5_5M 0x19 766#define ATH5K_RATE_CODE_11M 0x18 767/* A and G */ 768#define ATH5K_RATE_CODE_6M 0x0B 769#define ATH5K_RATE_CODE_9M 0x0F 770#define ATH5K_RATE_CODE_12M 0x0A 771#define ATH5K_RATE_CODE_18M 0x0E 772#define ATH5K_RATE_CODE_24M 0x09 773#define ATH5K_RATE_CODE_36M 0x0D 774#define ATH5K_RATE_CODE_48M 0x08 775#define ATH5K_RATE_CODE_54M 0x0C 776/* XR */ 777#define ATH5K_RATE_CODE_XR_500K 0x07 778#define ATH5K_RATE_CODE_XR_1M 0x02 779#define ATH5K_RATE_CODE_XR_2M 0x06 780#define ATH5K_RATE_CODE_XR_3M 0x01 781 782/* adding this flag to rate_code enables short preamble */ 783#define AR5K_SET_SHORT_PREAMBLE 0x04 784 785/* 786 * Crypto definitions 787 */ 788 789#define AR5K_KEYCACHE_SIZE 8 790 791/***********************\ 792 HW RELATED DEFINITIONS 793\***********************/ 794 795/* 796 * Misc definitions 797 */ 798#define AR5K_RSSI_EP_MULTIPLIER (1<<7) 799 800#define AR5K_ASSERT_ENTRY(_e, _s) do { \ 801 if (_e >= _s) \ 802 return (false); \ 803} while (0) 804 805/* 806 * Hardware interrupt abstraction 807 */ 808 809/** 810 * enum ath5k_int - Hardware interrupt masks helpers 811 * 812 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 813 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 814 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 815 * @AR5K_INT_RXNOFRM: No frame received (?) 816 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 817 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 818 * LinkPtr is NULL. For more details, refer to: 819 * http://www.freepatentsonline.com/20030225739.html 820 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 821 * Note that Rx overrun is not always fatal, on some chips we can continue 822 * operation without reseting the card, that's why int_fatal is not 823 * common for all chips. 824 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 825 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 826 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 827 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 828 * We currently do increments on interrupt by 829 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 830 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be 831 * checked. We should do this with ath5k_hw_update_mib_counters() but 832 * it seems we should also then do some noise immunity work. 833 * @AR5K_INT_RXPHY: RX PHY Error 834 * @AR5K_INT_RXKCM: RX Key cache miss 835 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 836 * beacon that must be handled in software. The alternative is if you 837 * have VEOL support, in that case you let the hardware deal with things. 838 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 839 * beacons from the AP have associated with, we should probably try to 840 * reassociate. When in IBSS mode this might mean we have not received 841 * any beacons from any local stations. Note that every station in an 842 * IBSS schedules to send beacons at the Target Beacon Transmission Time 843 * (TBTT) with a random backoff. 844 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 845 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 846 * until properly handled 847 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 848 * errors. These types of errors we can enable seem to be of type 849 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 850 * @AR5K_INT_GLOBAL: Used to clear and set the IER 851 * @AR5K_INT_NOCARD: signals the card has been removed 852 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 853 * bit value 854 * 855 * These are mapped to take advantage of some common bits 856 * between the MACs, to be able to set intr properties 857 * easier. Some of them are not used yet inside hw.c. Most map 858 * to the respective hw interrupt value as they are common amogst different 859 * MACs. 860 */ 861enum ath5k_int { 862 AR5K_INT_RXOK = 0x00000001, 863 AR5K_INT_RXDESC = 0x00000002, 864 AR5K_INT_RXERR = 0x00000004, 865 AR5K_INT_RXNOFRM = 0x00000008, 866 AR5K_INT_RXEOL = 0x00000010, 867 AR5K_INT_RXORN = 0x00000020, 868 AR5K_INT_TXOK = 0x00000040, 869 AR5K_INT_TXDESC = 0x00000080, 870 AR5K_INT_TXERR = 0x00000100, 871 AR5K_INT_TXNOFRM = 0x00000200, 872 AR5K_INT_TXEOL = 0x00000400, 873 AR5K_INT_TXURN = 0x00000800, 874 AR5K_INT_MIB = 0x00001000, 875 AR5K_INT_SWI = 0x00002000, 876 AR5K_INT_RXPHY = 0x00004000, 877 AR5K_INT_RXKCM = 0x00008000, 878 AR5K_INT_SWBA = 0x00010000, 879 AR5K_INT_BRSSI = 0x00020000, 880 AR5K_INT_BMISS = 0x00040000, 881 AR5K_INT_FATAL = 0x00080000, /* Non common */ 882 AR5K_INT_BNR = 0x00100000, /* Non common */ 883 AR5K_INT_TIM = 0x00200000, /* Non common */ 884 AR5K_INT_DTIM = 0x00400000, /* Non common */ 885 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 886 AR5K_INT_GPIO = 0x01000000, 887 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 888 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 889 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 890 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 891 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 892 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 893 AR5K_INT_GLOBAL = 0x80000000, 894 895 AR5K_INT_COMMON = AR5K_INT_RXOK 896 | AR5K_INT_RXDESC 897 | AR5K_INT_RXERR 898 | AR5K_INT_RXNOFRM 899 | AR5K_INT_RXEOL 900 | AR5K_INT_RXORN 901 | AR5K_INT_TXOK 902 | AR5K_INT_TXDESC 903 | AR5K_INT_TXERR 904 | AR5K_INT_TXNOFRM 905 | AR5K_INT_TXEOL 906 | AR5K_INT_TXURN 907 | AR5K_INT_MIB 908 | AR5K_INT_SWI 909 | AR5K_INT_RXPHY 910 | AR5K_INT_RXKCM 911 | AR5K_INT_SWBA 912 | AR5K_INT_BRSSI 913 | AR5K_INT_BMISS 914 | AR5K_INT_GPIO 915 | AR5K_INT_GLOBAL, 916 917 AR5K_INT_NOCARD = 0xffffffff 918}; 919 920/* Software interrupts used for calibration */ 921enum ath5k_software_interrupt { 922 AR5K_SWI_FULL_CALIBRATION = 0x01, 923 AR5K_SWI_SHORT_CALIBRATION = 0x02, 924}; 925 926/* 927 * Power management 928 */ 929enum ath5k_power_mode { 930 AR5K_PM_UNDEFINED = 0, 931 AR5K_PM_AUTO, 932 AR5K_PM_AWAKE, 933 AR5K_PM_FULL_SLEEP, 934 AR5K_PM_NETWORK_SLEEP, 935}; 936 937/* 938 * These match net80211 definitions (not used in 939 * mac80211). 940 * TODO: Clean this up 941 */ 942#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 943#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 944#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 945#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 946#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 947 948/* GPIO-controlled software LED */ 949#define AR5K_SOFTLED_PIN 0 950#define AR5K_SOFTLED_ON 0 951#define AR5K_SOFTLED_OFF 1 952 953/* 954 * Chipset capabilities -see ath5k_hw_get_capability- 955 * get_capability function is not yet fully implemented 956 * in ath5k so most of these don't work yet... 957 * TODO: Implement these & merge with _TUNE_ stuff above 958 */ 959enum ath5k_capability_type { 960 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 961 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 962 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 963 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 964 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 965 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 966 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 967 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 968 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 969 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 970 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 971 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 972 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 973 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 974 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 975 AR5K_CAP_XR = 16, /* Supports XR mode */ 976 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 977 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 978 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 979 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 980}; 981 982 983/* XXX: we *may* move cap_range stuff to struct wiphy */ 984struct ath5k_capabilities { 985 /* 986 * Supported PHY modes 987 * (ie. CHANNEL_A, CHANNEL_B, ...) 988 */ 989 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 990 991 /* 992 * Frequency range (without regulation restrictions) 993 */ 994 struct { 995 u16 range_2ghz_min; 996 u16 range_2ghz_max; 997 u16 range_5ghz_min; 998 u16 range_5ghz_max; 999 } cap_range; 1000 1001 /* 1002 * Values stored in the EEPROM (some of them...) 1003 */ 1004 struct ath5k_eeprom_info cap_eeprom; 1005 1006 /* 1007 * Queue information 1008 */ 1009 struct { 1010 u8 q_tx_num; 1011 } cap_queues; 1012}; 1013 1014 1015/***************************************\ 1016 HARDWARE ABSTRACTION LAYER STRUCTURE 1017\***************************************/ 1018 1019/* 1020 * Misc defines 1021 */ 1022 1023#define AR5K_MAX_GPIO 10 1024#define AR5K_MAX_RF_BANKS 8 1025 1026/* TODO: Clean up and merge with ath5k_softc */ 1027struct ath5k_hw { 1028 u32 ah_magic; 1029 1030 struct ath5k_softc *ah_sc; 1031 void __iomem *ah_iobase; 1032 1033 enum ath5k_int ah_imr; 1034 1035 enum nl80211_iftype ah_op_mode; 1036 struct ieee80211_channel *ah_current_channel; 1037 bool ah_turbo; 1038 bool ah_calibration; 1039 bool ah_single_chip; 1040 bool ah_combined_mic; 1041 1042 enum ath5k_version ah_version; 1043 enum ath5k_radio ah_radio; 1044 u32 ah_phy; 1045 u32 ah_mac_srev; 1046 u16 ah_mac_version; 1047 u16 ah_mac_revision; 1048 u16 ah_phy_revision; 1049 u16 ah_radio_5ghz_revision; 1050 u16 ah_radio_2ghz_revision; 1051 1052#define ah_modes ah_capabilities.cap_mode 1053#define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1054 1055 u32 ah_atim_window; 1056 u32 ah_aifs; 1057 u32 ah_cw_min; 1058 u32 ah_cw_max; 1059 u32 ah_limit_tx_retries; 1060 1061 /* Antenna Control */ 1062 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1063 u8 ah_ant_mode; 1064 u8 ah_tx_ant; 1065 u8 ah_def_ant; 1066 bool ah_software_retry; 1067 1068 u8 ah_sta_id[ETH_ALEN]; 1069 1070 /* Current BSSID we are trying to assoc to / create. 1071 * This is passed by mac80211 on config_interface() and cached here for 1072 * use in resets */ 1073 u8 ah_bssid[ETH_ALEN]; 1074 u8 ah_bssid_mask[ETH_ALEN]; 1075 1076 int ah_gpio_npins; 1077 1078 struct ath5k_capabilities ah_capabilities; 1079 1080 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1081 u32 ah_txq_status; 1082 u32 ah_txq_imr_txok; 1083 u32 ah_txq_imr_txerr; 1084 u32 ah_txq_imr_txurn; 1085 u32 ah_txq_imr_txdesc; 1086 u32 ah_txq_imr_txeol; 1087 u32 ah_txq_imr_cbrorn; 1088 u32 ah_txq_imr_cbrurn; 1089 u32 ah_txq_imr_qtrig; 1090 u32 ah_txq_imr_nofrm; 1091 u32 ah_txq_isr; 1092 u32 *ah_rf_banks; 1093 size_t ah_rf_banks_size; 1094 size_t ah_rf_regs_count; 1095 struct ath5k_gain ah_gain; 1096 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1097 1098 1099 struct { 1100 /* Temporary tables used for interpolation */ 1101 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1102 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1103 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1104 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1105 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1106 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1107 u8 txp_min_idx; 1108 bool txp_tpc; 1109 /* Values in 0.25dB units */ 1110 s16 txp_min_pwr; 1111 s16 txp_max_pwr; 1112 /* Values in 0.5dB units */ 1113 s16 txp_offset; 1114 s16 txp_ofdm; 1115 s16 txp_cck_ofdm_gainf_delta; 1116 /* Value in dB units */ 1117 s16 txp_cck_ofdm_pwr_delta; 1118 } ah_txpower; 1119 1120 struct { 1121 bool r_enabled; 1122 int r_last_alert; 1123 struct ieee80211_channel r_last_channel; 1124 } ah_radar; 1125 1126 /* noise floor from last periodic calibration */ 1127 s32 ah_noise_floor; 1128 1129 /* Calibration timestamp */ 1130 unsigned long ah_cal_tstamp; 1131 1132 /* Calibration interval (secs) */ 1133 u8 ah_cal_intval; 1134 1135 /* Software interrupt mask */ 1136 u8 ah_swi_mask; 1137 1138 /* 1139 * Function pointers 1140 */ 1141 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc, 1142 u32 size, unsigned int flags); 1143 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1144 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, 1145 unsigned int, unsigned int, unsigned int, unsigned int, 1146 unsigned int, unsigned int, unsigned int); 1147 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1148 unsigned int, unsigned int, unsigned int, unsigned int, 1149 unsigned int, unsigned int); 1150 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1151 struct ath5k_tx_status *); 1152 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1153 struct ath5k_rx_status *); 1154}; 1155 1156/* 1157 * Prototypes 1158 */ 1159 1160/* Attach/Detach Functions */ 1161extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version); 1162extern void ath5k_hw_detach(struct ath5k_hw *ah); 1163 1164/* LED functions */ 1165extern int ath5k_init_leds(struct ath5k_softc *sc); 1166extern void ath5k_led_enable(struct ath5k_softc *sc); 1167extern void ath5k_led_off(struct ath5k_softc *sc); 1168extern void ath5k_unregister_leds(struct ath5k_softc *sc); 1169 1170/* Reset Functions */ 1171extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1172extern int ath5k_hw_on_hold(struct ath5k_hw *ah); 1173extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel); 1174/* Power management functions */ 1175extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); 1176 1177/* DMA Related Functions */ 1178extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1179extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah); 1180extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1181extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1182extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1183extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1184extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1185extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1186 u32 phys_addr); 1187extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1188/* Interrupt handling */ 1189extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1190extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1191extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum 1192ath5k_int new_mask); 1193extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats); 1194 1195/* EEPROM access functions */ 1196extern int ath5k_eeprom_init(struct ath5k_hw *ah); 1197extern void ath5k_eeprom_detach(struct ath5k_hw *ah); 1198extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1199extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah); 1200 1201/* Protocol Control Unit Functions */ 1202extern int ath5k_hw_set_opmode(struct ath5k_hw *ah); 1203/* BSSID Functions */ 1204extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac); 1205extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1206extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id); 1207extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1208/* Receive start/stop functions */ 1209extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1210extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1211/* RX Filter functions */ 1212extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1213extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index); 1214extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index); 1215extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1216extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1217/* Beacon control functions */ 1218extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah); 1219extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1220extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1221extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1222extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1223#if 0 1224extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state); 1225extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah); 1226extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr); 1227#endif 1228/* ACK bit rate */ 1229void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high); 1230/* ACK/CTS Timeouts */ 1231extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout); 1232extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah); 1233extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout); 1234extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah); 1235/* Key table (WEP) functions */ 1236extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry); 1237extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry); 1238extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); 1239extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac); 1240 1241/* Queue Control Unit, DFS Control Unit Functions */ 1242extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info); 1243extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1244 const struct ath5k_txq_info *queue_info); 1245extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1246 enum ath5k_tx_queue queue_type, 1247 struct ath5k_txq_info *queue_info); 1248extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1249extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1250extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1251extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah); 1252extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time); 1253 1254/* Hardware Descriptor Functions */ 1255extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1256 1257/* GPIO Functions */ 1258extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1259extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1260extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1261extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1262extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1263extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level); 1264 1265/* rfkill Functions */ 1266extern void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1267extern void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1268 1269/* Misc functions */ 1270int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1271extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result); 1272extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1273extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1274 1275/* Initial register settings functions */ 1276extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1277 1278/* Initialize RF */ 1279extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 1280 struct ieee80211_channel *channel, 1281 unsigned int mode); 1282extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq); 1283extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1284extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1285/* PHY/RF channel functions */ 1286extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1287extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1288/* PHY calibration */ 1289extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1290extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq); 1291extern void ath5k_hw_calibration_poll(struct ath5k_hw *ah); 1292/* Spur mitigation */ 1293bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1294 struct ieee80211_channel *channel); 1295void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1296 struct ieee80211_channel *channel); 1297/* Misc PHY functions */ 1298extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1299extern int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1300/* Antenna control */ 1301extern void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1302extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant); 1303extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah); 1304/* TX power setup */ 1305extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower); 1306extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1307 1308/* 1309 * Functions used internaly 1310 */ 1311 1312/* 1313 * Translate usec to hw clock units 1314 * TODO: Half/quarter rate 1315 */ 1316static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) 1317{ 1318 return turbo ? (usec * 80) : (usec * 40); 1319} 1320 1321/* 1322 * Translate hw clock units to usec 1323 * TODO: Half/quarter rate 1324 */ 1325static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) 1326{ 1327 return turbo ? (clock / 80) : (clock / 40); 1328} 1329 1330/* 1331 * Read from a register 1332 */ 1333static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1334{ 1335 return ioread32(ah->ah_iobase + reg); 1336} 1337 1338/* 1339 * Write to a register 1340 */ 1341static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1342{ 1343 iowrite32(val, ah->ah_iobase + reg); 1344} 1345 1346#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY) 1347/* 1348 * Check if a register write has been completed 1349 */ 1350static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, 1351 u32 val, bool is_set) 1352{ 1353 int i; 1354 u32 data; 1355 1356 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 1357 data = ath5k_hw_reg_read(ah, reg); 1358 if (is_set && (data & flag)) 1359 break; 1360 else if ((data & flag) == val) 1361 break; 1362 udelay(15); 1363 } 1364 1365 return (i <= 0) ? -EAGAIN : 0; 1366} 1367#endif 1368 1369static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1370{ 1371 u32 retval = 0, bit, i; 1372 1373 for (i = 0; i < bits; i++) { 1374 bit = (val >> i) & 1; 1375 retval = (retval << 1) | bit; 1376 } 1377 1378 return retval; 1379} 1380 1381static inline int ath5k_pad_size(int hdrlen) 1382{ 1383 return (hdrlen < 24) ? 0 : hdrlen & 3; 1384} 1385 1386#endif 1387