ath5k.h revision 61cde037234c4b8e6497a23f5f236c64cbf9d41d
1/* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _ATH5K_H 19#define _ATH5K_H 20 21/* TODO: Clean up channel debuging -doesn't work anyway- and start 22 * working on reg. control code using all available eeprom information 23 * -rev. engineering needed- */ 24#define CHAN_DEBUG 0 25 26#include <linux/io.h> 27#include <linux/types.h> 28#include <linux/average.h> 29#include <net/mac80211.h> 30 31/* RX/TX descriptor hw structs 32 * TODO: Driver part should only see sw structs */ 33#include "desc.h" 34 35/* EEPROM structs/offsets 36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 37 * and clean up common bits, then introduce set/get functions in eeprom.c */ 38#include "eeprom.h" 39#include "../ath.h" 40 41/* PCI IDs */ 42#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 43#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 44#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 45#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 46#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 47#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 48#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 49#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 50#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 51#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 52#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 53#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 54#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 55#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 58#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 59#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 60#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 61#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 62#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 63#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 64#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 65#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 66#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 67#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 68#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 69#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 70 71/****************************\ 72 GENERIC DRIVER DEFINITIONS 73\****************************/ 74 75#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 76 77#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 78 printk(_level "ath5k %s: " _fmt, \ 79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 80 ##__VA_ARGS__) 81 82#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 83 if (net_ratelimit()) \ 84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 85 } while (0) 86 87#define ATH5K_INFO(_sc, _fmt, ...) \ 88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 89 90#define ATH5K_WARN(_sc, _fmt, ...) \ 91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 92 93#define ATH5K_ERR(_sc, _fmt, ...) \ 94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 95 96/* 97 * AR5K REGISTER ACCESS 98 */ 99 100/* Some macros to read/write fields */ 101 102/* First shift, then mask */ 103#define AR5K_REG_SM(_val, _flags) \ 104 (((_val) << _flags##_S) & (_flags)) 105 106/* First mask, then shift */ 107#define AR5K_REG_MS(_val, _flags) \ 108 (((_val) & (_flags)) >> _flags##_S) 109 110/* Some registers can hold multiple values of interest. For this 111 * reason when we want to write to these registers we must first 112 * retrieve the values which we do not want to clear (lets call this 113 * old_data) and then set the register with this and our new_value: 114 * ( old_data | new_value) */ 115#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 117 (((_val) << _flags##_S) & (_flags)), _reg) 118 119#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 121 (_mask)) | (_flags), _reg) 122 123#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 125 126#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 128 129/* Access to PHY registers */ 130#define AR5K_PHY_READ(ah, _reg) \ 131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 132 133#define AR5K_PHY_WRITE(ah, _reg, _val) \ 134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 135 136/* Access QCU registers per queue */ 137#define AR5K_REG_READ_Q(ah, _reg, _queue) \ 138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 139 140#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 141 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 142 143#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 144 _reg |= 1 << _queue; \ 145} while (0) 146 147#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 148 _reg &= ~(1 << _queue); \ 149} while (0) 150 151/* Used while writing initvals */ 152#define AR5K_REG_WAIT(_i) do { \ 153 if (_i % 64) \ 154 udelay(1); \ 155} while (0) 156 157/* Register dumps are done per operation mode */ 158#define AR5K_INI_RFGAIN_5GHZ 0 159#define AR5K_INI_RFGAIN_2GHZ 1 160 161/* TODO: Clean this up */ 162#define AR5K_INI_VAL_11A 0 163#define AR5K_INI_VAL_11A_TURBO 1 164#define AR5K_INI_VAL_11B 2 165#define AR5K_INI_VAL_11G 3 166#define AR5K_INI_VAL_11G_TURBO 4 167#define AR5K_INI_VAL_XR 0 168#define AR5K_INI_VAL_MAX 5 169 170/* 171 * Some tuneable values (these should be changeable by the user) 172 * TODO: Make use of them and add more options OR use debug/configfs 173 */ 174#define AR5K_TUNE_DMA_BEACON_RESP 2 175#define AR5K_TUNE_SW_BEACON_RESP 10 176#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 177#define AR5K_TUNE_RADAR_ALERT false 178#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 179#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1) 180#define AR5K_TUNE_REGISTER_TIMEOUT 20000 181/* Register for RSSI threshold has a mask of 0xff, so 255 seems to 182 * be the max value. */ 183#define AR5K_TUNE_RSSI_THRES 129 184/* This must be set when setting the RSSI threshold otherwise it can 185 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 186 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 187 * track of it. Max value depends on harware. For AR5210 this is just 7. 188 * For AR5211+ this seems to be up to 255. */ 189#define AR5K_TUNE_BMISS_THRES 7 190#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 191#define AR5K_TUNE_BEACON_INTERVAL 100 192#define AR5K_TUNE_AIFS 2 193#define AR5K_TUNE_AIFS_11B 2 194#define AR5K_TUNE_AIFS_XR 0 195#define AR5K_TUNE_CWMIN 15 196#define AR5K_TUNE_CWMIN_11B 31 197#define AR5K_TUNE_CWMIN_XR 3 198#define AR5K_TUNE_CWMAX 1023 199#define AR5K_TUNE_CWMAX_11B 1023 200#define AR5K_TUNE_CWMAX_XR 7 201#define AR5K_TUNE_NOISE_FLOOR -72 202#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 203#define AR5K_TUNE_MAX_TXPOWER 63 204#define AR5K_TUNE_DEFAULT_TXPOWER 25 205#define AR5K_TUNE_TPC_TXPOWER false 206#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ 207#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ 208#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ 209 210#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */ 211 212#define AR5K_INIT_CARR_SENSE_EN 1 213 214/*Swap RX/TX Descriptor for big endian archs*/ 215#if defined(__BIG_ENDIAN) 216#define AR5K_INIT_CFG ( \ 217 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 218) 219#else 220#define AR5K_INIT_CFG 0x00000000 221#endif 222 223/* Initial values */ 224#define AR5K_INIT_CYCRSSI_THR1 2 225#define AR5K_INIT_TX_LATENCY 502 226#define AR5K_INIT_USEC 39 227#define AR5K_INIT_USEC_TURBO 79 228#define AR5K_INIT_USEC_32 31 229#define AR5K_INIT_SLOT_TIME_CLOCK 396 230#define AR5K_INIT_SLOT_TIME_TURBO_CLOCK 480 231#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 232#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 233#define AR5K_INIT_PROG_IFS 920 234#define AR5K_INIT_PROG_IFS_TURBO 960 235#define AR5K_INIT_EIFS 3440 236#define AR5K_INIT_EIFS_TURBO 6880 237#define AR5K_INIT_SIFS_CLOCK 560 238#define AR5K_INIT_SIFS_TURBO_CLOCK 480 239#define AR5K_INIT_SH_RETRY 10 240#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY 241#define AR5K_INIT_SSH_RETRY 32 242#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY 243#define AR5K_INIT_TX_RETRY 10 244 245#define AR5K_INIT_PROTO_TIME_CNTRL ( \ 246 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ 247 (AR5K_INIT_PROG_IFS) \ 248) 249#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ 250 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ 251 (AR5K_INIT_PROG_IFS_TURBO) \ 252) 253 254/* Slot time */ 255#define AR5K_INIT_SLOT_TIME_TURBO 6 256#define AR5K_INIT_SLOT_TIME_DEFAULT 9 257#define AR5K_INIT_SLOT_TIME_HALF_RATE 13 258#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21 259#define AR5K_INIT_SLOT_TIME_B 20 260#define AR5K_SLOT_TIME_MAX 0xffff 261 262/* SIFS */ 263#define AR5K_INIT_SIFS_TURBO 6 264/* XXX: 8 from initvals 10 from standard */ 265#define AR5K_INIT_SIFS_DEFAULT_BG 8 266#define AR5K_INIT_SIFS_DEFAULT_A 16 267#define AR5K_INIT_SIFS_HALF_RATE 32 268#define AR5K_INIT_SIFS_QUARTER_RATE 64 269 270/* Used to calculate tx time for non 5/10/40MHz 271 * operation */ 272/* It's preamble time + signal time (16 + 4) */ 273#define AR5K_INIT_OFDM_PREAMPLE_TIME 20 274/* Preamble time for 40MHz (turbo) operation (min ?) */ 275#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14 276#define AR5K_INIT_OFDM_SYMBOL_TIME 4 277#define AR5K_INIT_OFDM_PLCP_BITS 22 278 279/* Rx latency for 5 and 10MHz operation (max ?) */ 280#define AR5K_INIT_RX_LAT_MAX 63 281/* Tx latencies from initvals (5212 only but no problem 282 * because we only tweak them on 5212) */ 283#define AR5K_INIT_TX_LAT_A 54 284#define AR5K_INIT_TX_LAT_BG 384 285/* Tx latency for 40MHz (turbo) operation (min ?) */ 286#define AR5K_INIT_TX_LAT_MIN 32 287/* Default Tx/Rx latencies (same for 5211)*/ 288#define AR5K_INIT_TX_LATENCY_5210 54 289#define AR5K_INIT_RX_LATENCY_5210 29 290 291/* Tx frame to Tx data start delay */ 292#define AR5K_INIT_TXF2TXD_START_DEFAULT 14 293#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12 294#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13 295 296/* We need to increase PHY switch and agc settling time 297 * on turbo mode */ 298#define AR5K_SWITCH_SETTLING 5760 299#define AR5K_SWITCH_SETTLING_TURBO 7168 300 301#define AR5K_AGC_SETTLING 28 302/* 38 on 5210 but shouldn't matter */ 303#define AR5K_AGC_SETTLING_TURBO 37 304 305 306/* GENERIC CHIPSET DEFINITIONS */ 307 308/* MAC Chips */ 309enum ath5k_version { 310 AR5K_AR5210 = 0, 311 AR5K_AR5211 = 1, 312 AR5K_AR5212 = 2, 313}; 314 315/* PHY Chips */ 316enum ath5k_radio { 317 AR5K_RF5110 = 0, 318 AR5K_RF5111 = 1, 319 AR5K_RF5112 = 2, 320 AR5K_RF2413 = 3, 321 AR5K_RF5413 = 4, 322 AR5K_RF2316 = 5, 323 AR5K_RF2317 = 6, 324 AR5K_RF2425 = 7, 325}; 326 327/* 328 * Common silicon revision/version values 329 */ 330 331enum ath5k_srev_type { 332 AR5K_VERSION_MAC, 333 AR5K_VERSION_RAD, 334}; 335 336struct ath5k_srev_name { 337 const char *sr_name; 338 enum ath5k_srev_type sr_type; 339 u_int sr_val; 340}; 341 342#define AR5K_SREV_UNKNOWN 0xffff 343 344#define AR5K_SREV_AR5210 0x00 /* Crete */ 345#define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 346#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 347#define AR5K_SREV_AR5311B 0x30 /* Spirit */ 348#define AR5K_SREV_AR5211 0x40 /* Oahu */ 349#define AR5K_SREV_AR5212 0x50 /* Venice */ 350#define AR5K_SREV_AR5212_V4 0x54 /* ??? */ 351#define AR5K_SREV_AR5213 0x55 /* ??? */ 352#define AR5K_SREV_AR5213A 0x59 /* Hainan */ 353#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 354#define AR5K_SREV_AR2414 0x70 /* Griffin */ 355#define AR5K_SREV_AR5424 0x90 /* Condor */ 356#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 357#define AR5K_SREV_AR5414 0xa0 /* Eagle */ 358#define AR5K_SREV_AR2415 0xb0 /* Talon */ 359#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 360#define AR5K_SREV_AR5418 0xca /* PCI-E */ 361#define AR5K_SREV_AR2425 0xe0 /* Swan */ 362#define AR5K_SREV_AR2417 0xf0 /* Nala */ 363 364#define AR5K_SREV_RAD_5110 0x00 365#define AR5K_SREV_RAD_5111 0x10 366#define AR5K_SREV_RAD_5111A 0x15 367#define AR5K_SREV_RAD_2111 0x20 368#define AR5K_SREV_RAD_5112 0x30 369#define AR5K_SREV_RAD_5112A 0x35 370#define AR5K_SREV_RAD_5112B 0x36 371#define AR5K_SREV_RAD_2112 0x40 372#define AR5K_SREV_RAD_2112A 0x45 373#define AR5K_SREV_RAD_2112B 0x46 374#define AR5K_SREV_RAD_2413 0x50 375#define AR5K_SREV_RAD_5413 0x60 376#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 377#define AR5K_SREV_RAD_2317 0x80 378#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 379#define AR5K_SREV_RAD_2425 0xa2 380#define AR5K_SREV_RAD_5133 0xc0 381 382#define AR5K_SREV_PHY_5211 0x30 383#define AR5K_SREV_PHY_5212 0x41 384#define AR5K_SREV_PHY_5212A 0x42 385#define AR5K_SREV_PHY_5212B 0x43 386#define AR5K_SREV_PHY_2413 0x45 387#define AR5K_SREV_PHY_5413 0x61 388#define AR5K_SREV_PHY_2425 0x70 389 390/* TODO add support to mac80211 for vendor-specific rates and modes */ 391 392/* 393 * Some of this information is based on Documentation from: 394 * 395 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 396 * 397 * Modulation for Atheros' eXtended Range - range enhancing extension that is 398 * supposed to double the distance an Atheros client device can keep a 399 * connection with an Atheros access point. This is achieved by increasing 400 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 401 * the 802.11 specifications demand. In addition, new (proprietary) data rates 402 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 403 * 404 * Please note that can you either use XR or TURBO but you cannot use both, 405 * they are exclusive. 406 * 407 */ 408#define MODULATION_XR 0x00000200 409/* 410 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 411 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 412 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 413 * channels. To use this feature your Access Point must also suport it. 414 * There is also a distinction between "static" and "dynamic" turbo modes: 415 * 416 * - Static: is the dumb version: devices set to this mode stick to it until 417 * the mode is turned off. 418 * - Dynamic: is the intelligent version, the network decides itself if it 419 * is ok to use turbo. As soon as traffic is detected on adjacent channels 420 * (which would get used in turbo mode), or when a non-turbo station joins 421 * the network, turbo mode won't be used until the situation changes again. 422 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 423 * monitors the used radio band in order to decide whether turbo mode may 424 * be used or not. 425 * 426 * This article claims Super G sticks to bonding of channels 5 and 6 for 427 * USA: 428 * 429 * http://www.pcworld.com/article/id,113428-page,1/article.html 430 * 431 * The channel bonding seems to be driver specific though. In addition to 432 * deciding what channels will be used, these "Turbo" modes are accomplished 433 * by also enabling the following features: 434 * 435 * - Bursting: allows multiple frames to be sent at once, rather than pausing 436 * after each frame. Bursting is a standards-compliant feature that can be 437 * used with any Access Point. 438 * - Fast frames: increases the amount of information that can be sent per 439 * frame, also resulting in a reduction of transmission overhead. It is a 440 * proprietary feature that needs to be supported by the Access Point. 441 * - Compression: data frames are compressed in real time using a Lempel Ziv 442 * algorithm. This is done transparently. Once this feature is enabled, 443 * compression and decompression takes place inside the chipset, without 444 * putting additional load on the host CPU. 445 * 446 */ 447#define MODULATION_TURBO 0x00000080 448 449enum ath5k_driver_mode { 450 AR5K_MODE_11A = 0, 451 AR5K_MODE_11A_TURBO = 1, 452 AR5K_MODE_11B = 2, 453 AR5K_MODE_11G = 3, 454 AR5K_MODE_11G_TURBO = 4, 455 AR5K_MODE_XR = 0, 456 AR5K_MODE_MAX = 5 457}; 458 459enum ath5k_ant_mode { 460 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 461 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 462 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 463 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 464 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 465 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 466 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 467 AR5K_ANTMODE_MAX, 468}; 469 470enum ath5k_bw_mode { 471 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ 472 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ 473 AR5K_BWMODE_10MHZ = 2, /* Half rate */ 474 AR5K_BWMODE_40MHZ = 3 /* Turbo */ 475}; 476 477/****************\ 478 TX DEFINITIONS 479\****************/ 480 481/* 482 * TX Status descriptor 483 */ 484struct ath5k_tx_status { 485 u16 ts_seqnum; 486 u16 ts_tstamp; 487 u8 ts_status; 488 u8 ts_rate[4]; 489 u8 ts_retry[4]; 490 u8 ts_final_idx; 491 s8 ts_rssi; 492 u8 ts_shortretry; 493 u8 ts_longretry; 494 u8 ts_virtcol; 495 u8 ts_antenna; 496}; 497 498#define AR5K_TXSTAT_ALTRATE 0x80 499#define AR5K_TXERR_XRETRY 0x01 500#define AR5K_TXERR_FILT 0x02 501#define AR5K_TXERR_FIFO 0x04 502 503/** 504 * enum ath5k_tx_queue - Queue types used to classify tx queues. 505 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 506 * @AR5K_TX_QUEUE_DATA: A normal data queue 507 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 508 * @AR5K_TX_QUEUE_BEACON: The beacon queue 509 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 510 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 511 */ 512enum ath5k_tx_queue { 513 AR5K_TX_QUEUE_INACTIVE = 0, 514 AR5K_TX_QUEUE_DATA, 515 AR5K_TX_QUEUE_XR_DATA, 516 AR5K_TX_QUEUE_BEACON, 517 AR5K_TX_QUEUE_CAB, 518 AR5K_TX_QUEUE_UAPSD, 519}; 520 521#define AR5K_NUM_TX_QUEUES 10 522#define AR5K_NUM_TX_QUEUES_NOQCU 2 523 524/* 525 * Queue syb-types to classify normal data queues. 526 * These are the 4 Access Categories as defined in 527 * WME spec. 0 is the lowest priority and 4 is the 528 * highest. Normal data that hasn't been classified 529 * goes to the Best Effort AC. 530 */ 531enum ath5k_tx_queue_subtype { 532 AR5K_WME_AC_BK = 0, /*Background traffic*/ 533 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 534 AR5K_WME_AC_VI, /*Video traffic*/ 535 AR5K_WME_AC_VO, /*Voice traffic*/ 536}; 537 538/* 539 * Queue ID numbers as returned by the hw functions, each number 540 * represents a hw queue. If hw does not support hw queues 541 * (eg 5210) all data goes in one queue. These match 542 * d80211 definitions (net80211/MadWiFi don't use them). 543 */ 544enum ath5k_tx_queue_id { 545 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 546 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 547 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 548 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ 549 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 550 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 551 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 552 AR5K_TX_QUEUE_ID_UAPSD = 8, 553 AR5K_TX_QUEUE_ID_XR_DATA = 9, 554}; 555 556/* 557 * Flags to set hw queue's parameters... 558 */ 559#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 560#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 561#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 562#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 563#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 564#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 565#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 566#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 567#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 568#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 569#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 570#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 571#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 572#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 573 574/* 575 * A struct to hold tx queue's parameters 576 */ 577struct ath5k_txq_info { 578 enum ath5k_tx_queue tqi_type; 579 enum ath5k_tx_queue_subtype tqi_subtype; 580 u16 tqi_flags; /* Tx queue flags (see above) */ 581 u8 tqi_aifs; /* Arbitrated Interframe Space */ 582 u16 tqi_cw_min; /* Minimum Contention Window */ 583 u16 tqi_cw_max; /* Maximum Contention Window */ 584 u32 tqi_cbr_period; /* Constant bit rate period */ 585 u32 tqi_cbr_overflow_limit; 586 u32 tqi_burst_time; 587 u32 tqi_ready_time; /* Time queue waits after an event */ 588}; 589 590/* 591 * Transmit packet types. 592 * used on tx control descriptor 593 */ 594enum ath5k_pkt_type { 595 AR5K_PKT_TYPE_NORMAL = 0, 596 AR5K_PKT_TYPE_ATIM = 1, 597 AR5K_PKT_TYPE_PSPOLL = 2, 598 AR5K_PKT_TYPE_BEACON = 3, 599 AR5K_PKT_TYPE_PROBE_RESP = 4, 600 AR5K_PKT_TYPE_PIFS = 5, 601}; 602 603/* 604 * TX power and TPC settings 605 */ 606#define AR5K_TXPOWER_OFDM(_r, _v) ( \ 607 ((0 & 1) << ((_v) + 6)) | \ 608 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 609) 610 611#define AR5K_TXPOWER_CCK(_r, _v) ( \ 612 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 613) 614 615/* 616 * DMA size definitions (2^(n+2)) 617 */ 618enum ath5k_dmasize { 619 AR5K_DMASIZE_4B = 0, 620 AR5K_DMASIZE_8B, 621 AR5K_DMASIZE_16B, 622 AR5K_DMASIZE_32B, 623 AR5K_DMASIZE_64B, 624 AR5K_DMASIZE_128B, 625 AR5K_DMASIZE_256B, 626 AR5K_DMASIZE_512B 627}; 628 629 630/****************\ 631 RX DEFINITIONS 632\****************/ 633 634/* 635 * RX Status descriptor 636 */ 637struct ath5k_rx_status { 638 u16 rs_datalen; 639 u16 rs_tstamp; 640 u8 rs_status; 641 u8 rs_phyerr; 642 s8 rs_rssi; 643 u8 rs_keyix; 644 u8 rs_rate; 645 u8 rs_antenna; 646 u8 rs_more; 647}; 648 649#define AR5K_RXERR_CRC 0x01 650#define AR5K_RXERR_PHY 0x02 651#define AR5K_RXERR_FIFO 0x04 652#define AR5K_RXERR_DECRYPT 0x08 653#define AR5K_RXERR_MIC 0x10 654#define AR5K_RXKEYIX_INVALID ((u8) - 1) 655#define AR5K_TXKEYIX_INVALID ((u32) - 1) 656 657 658/**************************\ 659 BEACON TIMERS DEFINITIONS 660\**************************/ 661 662#define AR5K_BEACON_PERIOD 0x0000ffff 663#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 664#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 665 666 667/* 668 * TSF to TU conversion: 669 * 670 * TSF is a 64bit value in usec (microseconds). 671 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 672 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 673 */ 674#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 675 676 677/*******************************\ 678 GAIN OPTIMIZATION DEFINITIONS 679\*******************************/ 680 681enum ath5k_rfgain { 682 AR5K_RFGAIN_INACTIVE = 0, 683 AR5K_RFGAIN_ACTIVE, 684 AR5K_RFGAIN_READ_REQUESTED, 685 AR5K_RFGAIN_NEED_CHANGE, 686}; 687 688struct ath5k_gain { 689 u8 g_step_idx; 690 u8 g_current; 691 u8 g_target; 692 u8 g_low; 693 u8 g_high; 694 u8 g_f_corr; 695 u8 g_state; 696}; 697 698/********************\ 699 COMMON DEFINITIONS 700\********************/ 701 702#define AR5K_SLOT_TIME_9 396 703#define AR5K_SLOT_TIME_20 880 704#define AR5K_SLOT_TIME_MAX 0xffff 705 706/* channel_flags */ 707#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 708#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ 709#define CHANNEL_CCK 0x0020 /* CCK channel */ 710#define CHANNEL_OFDM 0x0040 /* OFDM channel */ 711#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 712#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 713#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 714#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 715#define CHANNEL_XR 0x0800 /* XR channel */ 716 717#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 718#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 719#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 720#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 721#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 722#define CHANNEL_108A CHANNEL_T 723#define CHANNEL_108G CHANNEL_TG 724#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 725 726#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ 727 CHANNEL_TURBO) 728 729#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) 730#define CHANNEL_MODES CHANNEL_ALL 731 732/* 733 * Used internaly for reset_tx_queue). 734 * Also see struct struct ieee80211_channel. 735 */ 736#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 737#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) 738 739/* 740 * The following structure is used to map 2GHz channels to 741 * 5GHz Atheros channels. 742 * TODO: Clean up 743 */ 744struct ath5k_athchan_2ghz { 745 u32 a2_flags; 746 u16 a2_athchan; 747}; 748 749 750/******************\ 751 RATE DEFINITIONS 752\******************/ 753 754/** 755 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 756 * 757 * The rate code is used to get the RX rate or set the TX rate on the 758 * hardware descriptors. It is also used for internal modulation control 759 * and settings. 760 * 761 * This is the hardware rate map we are aware of: 762 * 763 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 764 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 765 * 766 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 767 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 768 * 769 * rate_code 17 18 19 20 21 22 23 24 770 * rate_kbps ? ? ? ? ? ? ? 11000 771 * 772 * rate_code 25 26 27 28 29 30 31 32 773 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 774 * 775 * "S" indicates CCK rates with short preamble. 776 * 777 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 778 * lowest 4 bits, so they are the same as below with a 0xF mask. 779 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 780 * We handle this in ath5k_setup_bands(). 781 */ 782#define AR5K_MAX_RATES 32 783 784/* B */ 785#define ATH5K_RATE_CODE_1M 0x1B 786#define ATH5K_RATE_CODE_2M 0x1A 787#define ATH5K_RATE_CODE_5_5M 0x19 788#define ATH5K_RATE_CODE_11M 0x18 789/* A and G */ 790#define ATH5K_RATE_CODE_6M 0x0B 791#define ATH5K_RATE_CODE_9M 0x0F 792#define ATH5K_RATE_CODE_12M 0x0A 793#define ATH5K_RATE_CODE_18M 0x0E 794#define ATH5K_RATE_CODE_24M 0x09 795#define ATH5K_RATE_CODE_36M 0x0D 796#define ATH5K_RATE_CODE_48M 0x08 797#define ATH5K_RATE_CODE_54M 0x0C 798/* XR */ 799#define ATH5K_RATE_CODE_XR_500K 0x07 800#define ATH5K_RATE_CODE_XR_1M 0x02 801#define ATH5K_RATE_CODE_XR_2M 0x06 802#define ATH5K_RATE_CODE_XR_3M 0x01 803 804/* adding this flag to rate_code enables short preamble */ 805#define AR5K_SET_SHORT_PREAMBLE 0x04 806 807/* 808 * Crypto definitions 809 */ 810 811#define AR5K_KEYCACHE_SIZE 8 812 813/***********************\ 814 HW RELATED DEFINITIONS 815\***********************/ 816 817/* 818 * Misc definitions 819 */ 820#define AR5K_RSSI_EP_MULTIPLIER (1<<7) 821 822#define AR5K_ASSERT_ENTRY(_e, _s) do { \ 823 if (_e >= _s) \ 824 return (false); \ 825} while (0) 826 827/* 828 * Hardware interrupt abstraction 829 */ 830 831/** 832 * enum ath5k_int - Hardware interrupt masks helpers 833 * 834 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 835 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 836 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 837 * @AR5K_INT_RXNOFRM: No frame received (?) 838 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 839 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 840 * LinkPtr is NULL. For more details, refer to: 841 * http://www.freepatentsonline.com/20030225739.html 842 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 843 * Note that Rx overrun is not always fatal, on some chips we can continue 844 * operation without reseting the card, that's why int_fatal is not 845 * common for all chips. 846 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 847 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 848 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 849 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 850 * We currently do increments on interrupt by 851 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 852 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 853 * one of the PHY error counters reached the maximum value and should be 854 * read and cleared. 855 * @AR5K_INT_RXPHY: RX PHY Error 856 * @AR5K_INT_RXKCM: RX Key cache miss 857 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 858 * beacon that must be handled in software. The alternative is if you 859 * have VEOL support, in that case you let the hardware deal with things. 860 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 861 * beacons from the AP have associated with, we should probably try to 862 * reassociate. When in IBSS mode this might mean we have not received 863 * any beacons from any local stations. Note that every station in an 864 * IBSS schedules to send beacons at the Target Beacon Transmission Time 865 * (TBTT) with a random backoff. 866 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 867 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 868 * until properly handled 869 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 870 * errors. These types of errors we can enable seem to be of type 871 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 872 * @AR5K_INT_GLOBAL: Used to clear and set the IER 873 * @AR5K_INT_NOCARD: signals the card has been removed 874 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 875 * bit value 876 * 877 * These are mapped to take advantage of some common bits 878 * between the MACs, to be able to set intr properties 879 * easier. Some of them are not used yet inside hw.c. Most map 880 * to the respective hw interrupt value as they are common amogst different 881 * MACs. 882 */ 883enum ath5k_int { 884 AR5K_INT_RXOK = 0x00000001, 885 AR5K_INT_RXDESC = 0x00000002, 886 AR5K_INT_RXERR = 0x00000004, 887 AR5K_INT_RXNOFRM = 0x00000008, 888 AR5K_INT_RXEOL = 0x00000010, 889 AR5K_INT_RXORN = 0x00000020, 890 AR5K_INT_TXOK = 0x00000040, 891 AR5K_INT_TXDESC = 0x00000080, 892 AR5K_INT_TXERR = 0x00000100, 893 AR5K_INT_TXNOFRM = 0x00000200, 894 AR5K_INT_TXEOL = 0x00000400, 895 AR5K_INT_TXURN = 0x00000800, 896 AR5K_INT_MIB = 0x00001000, 897 AR5K_INT_SWI = 0x00002000, 898 AR5K_INT_RXPHY = 0x00004000, 899 AR5K_INT_RXKCM = 0x00008000, 900 AR5K_INT_SWBA = 0x00010000, 901 AR5K_INT_BRSSI = 0x00020000, 902 AR5K_INT_BMISS = 0x00040000, 903 AR5K_INT_FATAL = 0x00080000, /* Non common */ 904 AR5K_INT_BNR = 0x00100000, /* Non common */ 905 AR5K_INT_TIM = 0x00200000, /* Non common */ 906 AR5K_INT_DTIM = 0x00400000, /* Non common */ 907 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 908 AR5K_INT_GPIO = 0x01000000, 909 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 910 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 911 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 912 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 913 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 914 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 915 AR5K_INT_GLOBAL = 0x80000000, 916 917 AR5K_INT_COMMON = AR5K_INT_RXOK 918 | AR5K_INT_RXDESC 919 | AR5K_INT_RXERR 920 | AR5K_INT_RXNOFRM 921 | AR5K_INT_RXEOL 922 | AR5K_INT_RXORN 923 | AR5K_INT_TXOK 924 | AR5K_INT_TXDESC 925 | AR5K_INT_TXERR 926 | AR5K_INT_TXNOFRM 927 | AR5K_INT_TXEOL 928 | AR5K_INT_TXURN 929 | AR5K_INT_MIB 930 | AR5K_INT_SWI 931 | AR5K_INT_RXPHY 932 | AR5K_INT_RXKCM 933 | AR5K_INT_SWBA 934 | AR5K_INT_BRSSI 935 | AR5K_INT_BMISS 936 | AR5K_INT_GPIO 937 | AR5K_INT_GLOBAL, 938 939 AR5K_INT_NOCARD = 0xffffffff 940}; 941 942/* mask which calibration is active at the moment */ 943enum ath5k_calibration_mask { 944 AR5K_CALIBRATION_FULL = 0x01, 945 AR5K_CALIBRATION_SHORT = 0x02, 946 AR5K_CALIBRATION_ANI = 0x04, 947}; 948 949/* 950 * Power management 951 */ 952enum ath5k_power_mode { 953 AR5K_PM_UNDEFINED = 0, 954 AR5K_PM_AUTO, 955 AR5K_PM_AWAKE, 956 AR5K_PM_FULL_SLEEP, 957 AR5K_PM_NETWORK_SLEEP, 958}; 959 960/* 961 * These match net80211 definitions (not used in 962 * mac80211). 963 * TODO: Clean this up 964 */ 965#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 966#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 967#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 968#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 969#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 970 971/* GPIO-controlled software LED */ 972#define AR5K_SOFTLED_PIN 0 973#define AR5K_SOFTLED_ON 0 974#define AR5K_SOFTLED_OFF 1 975 976/* 977 * Chipset capabilities -see ath5k_hw_get_capability- 978 * get_capability function is not yet fully implemented 979 * in ath5k so most of these don't work yet... 980 * TODO: Implement these & merge with _TUNE_ stuff above 981 */ 982enum ath5k_capability_type { 983 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 984 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 985 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 986 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 987 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 988 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 989 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 990 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 991 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 992 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 993 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 994 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 995 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 996 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 997 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 998 AR5K_CAP_XR = 16, /* Supports XR mode */ 999 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 1000 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 1001 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 1002 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 1003}; 1004 1005 1006/* XXX: we *may* move cap_range stuff to struct wiphy */ 1007struct ath5k_capabilities { 1008 /* 1009 * Supported PHY modes 1010 * (ie. CHANNEL_A, CHANNEL_B, ...) 1011 */ 1012 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 1013 1014 /* 1015 * Frequency range (without regulation restrictions) 1016 */ 1017 struct { 1018 u16 range_2ghz_min; 1019 u16 range_2ghz_max; 1020 u16 range_5ghz_min; 1021 u16 range_5ghz_max; 1022 } cap_range; 1023 1024 /* 1025 * Values stored in the EEPROM (some of them...) 1026 */ 1027 struct ath5k_eeprom_info cap_eeprom; 1028 1029 /* 1030 * Queue information 1031 */ 1032 struct { 1033 u8 q_tx_num; 1034 } cap_queues; 1035 1036 bool cap_has_phyerr_counters; 1037}; 1038 1039/* size of noise floor history (keep it a power of two) */ 1040#define ATH5K_NF_CAL_HIST_MAX 8 1041struct ath5k_nfcal_hist 1042{ 1043 s16 index; /* current index into nfval */ 1044 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 1045}; 1046 1047/** 1048 * struct avg_val - Helper structure for average calculation 1049 * @avg: contains the actual average value 1050 * @avg_weight: is used internally during calculation to prevent rounding errors 1051 */ 1052struct ath5k_avg_val { 1053 int avg; 1054 int avg_weight; 1055}; 1056 1057/***************************************\ 1058 HARDWARE ABSTRACTION LAYER STRUCTURE 1059\***************************************/ 1060 1061/* 1062 * Misc defines 1063 */ 1064 1065#define AR5K_MAX_GPIO 10 1066#define AR5K_MAX_RF_BANKS 8 1067 1068/* TODO: Clean up and merge with ath5k_softc */ 1069struct ath5k_hw { 1070 struct ath_common common; 1071 1072 struct ath5k_softc *ah_sc; 1073 void __iomem *ah_iobase; 1074 1075 enum ath5k_int ah_imr; 1076 1077 struct ieee80211_channel *ah_current_channel; 1078 bool ah_calibration; 1079 bool ah_single_chip; 1080 1081 enum ath5k_version ah_version; 1082 enum ath5k_radio ah_radio; 1083 u32 ah_phy; 1084 u32 ah_mac_srev; 1085 u16 ah_mac_version; 1086 u16 ah_phy_revision; 1087 u16 ah_radio_5ghz_revision; 1088 u16 ah_radio_2ghz_revision; 1089 1090#define ah_modes ah_capabilities.cap_mode 1091#define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1092 1093 u32 ah_limit_tx_retries; 1094 u8 ah_coverage_class; 1095 bool ah_ack_bitrate_high; 1096 u8 ah_bwmode; 1097 1098 /* Antenna Control */ 1099 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1100 u8 ah_ant_mode; 1101 u8 ah_tx_ant; 1102 u8 ah_def_ant; 1103 bool ah_software_retry; 1104 1105 struct ath5k_capabilities ah_capabilities; 1106 1107 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1108 u32 ah_txq_status; 1109 u32 ah_txq_imr_txok; 1110 u32 ah_txq_imr_txerr; 1111 u32 ah_txq_imr_txurn; 1112 u32 ah_txq_imr_txdesc; 1113 u32 ah_txq_imr_txeol; 1114 u32 ah_txq_imr_cbrorn; 1115 u32 ah_txq_imr_cbrurn; 1116 u32 ah_txq_imr_qtrig; 1117 u32 ah_txq_imr_nofrm; 1118 u32 ah_txq_isr; 1119 u32 *ah_rf_banks; 1120 size_t ah_rf_banks_size; 1121 size_t ah_rf_regs_count; 1122 struct ath5k_gain ah_gain; 1123 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1124 1125 1126 struct { 1127 /* Temporary tables used for interpolation */ 1128 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1129 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1130 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1131 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1132 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1133 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1134 u8 txp_min_idx; 1135 bool txp_tpc; 1136 /* Values in 0.25dB units */ 1137 s16 txp_min_pwr; 1138 s16 txp_max_pwr; 1139 /* Values in 0.5dB units */ 1140 s16 txp_offset; 1141 s16 txp_ofdm; 1142 s16 txp_cck_ofdm_gainf_delta; 1143 /* Value in dB units */ 1144 s16 txp_cck_ofdm_pwr_delta; 1145 } ah_txpower; 1146 1147 struct { 1148 bool r_enabled; 1149 int r_last_alert; 1150 struct ieee80211_channel r_last_channel; 1151 } ah_radar; 1152 1153 struct ath5k_nfcal_hist ah_nfcal_hist; 1154 1155 /* average beacon RSSI in our BSS (used by ANI) */ 1156 struct ewma ah_beacon_rssi_avg; 1157 1158 /* noise floor from last periodic calibration */ 1159 s32 ah_noise_floor; 1160 1161 /* Calibration timestamp */ 1162 unsigned long ah_cal_next_full; 1163 unsigned long ah_cal_next_ani; 1164 unsigned long ah_cal_next_nf; 1165 1166 /* Calibration mask */ 1167 u8 ah_cal_mask; 1168 1169 /* 1170 * Function pointers 1171 */ 1172 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1173 unsigned int, unsigned int, int, enum ath5k_pkt_type, 1174 unsigned int, unsigned int, unsigned int, unsigned int, 1175 unsigned int, unsigned int, unsigned int, unsigned int); 1176 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1177 struct ath5k_tx_status *); 1178 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1179 struct ath5k_rx_status *); 1180}; 1181 1182/* 1183 * Prototypes 1184 */ 1185 1186/* Attach/Detach Functions */ 1187int ath5k_hw_attach(struct ath5k_softc *sc); 1188void ath5k_hw_detach(struct ath5k_hw *ah); 1189 1190int ath5k_sysfs_register(struct ath5k_softc *sc); 1191void ath5k_sysfs_unregister(struct ath5k_softc *sc); 1192 1193 1194/* LED functions */ 1195int ath5k_init_leds(struct ath5k_softc *sc); 1196void ath5k_led_enable(struct ath5k_softc *sc); 1197void ath5k_led_off(struct ath5k_softc *sc); 1198void ath5k_unregister_leds(struct ath5k_softc *sc); 1199 1200 1201/* Reset Functions */ 1202int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1203int ath5k_hw_on_hold(struct ath5k_hw *ah); 1204int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1205 struct ieee80211_channel *channel, bool change_channel); 1206int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 1207 bool is_set); 1208/* Power management functions */ 1209 1210 1211/* Clock rate related functions */ 1212unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1213unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1214void ath5k_hw_set_clockrate(struct ath5k_hw *ah); 1215 1216 1217/* DMA Related Functions */ 1218void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1219u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1220int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1221int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1222int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue); 1223u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1224int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1225 u32 phys_addr); 1226int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1227/* Interrupt handling */ 1228bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1229int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1230enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1231void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); 1232/* Init/Stop functions */ 1233void ath5k_hw_dma_init(struct ath5k_hw *ah); 1234int ath5k_hw_dma_stop(struct ath5k_hw *ah); 1235 1236/* EEPROM access functions */ 1237int ath5k_eeprom_init(struct ath5k_hw *ah); 1238void ath5k_eeprom_detach(struct ath5k_hw *ah); 1239int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1240 1241 1242/* Protocol Control Unit Functions */ 1243extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1244void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1245/* RX filter control*/ 1246int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1247void ath5k_hw_set_bssid(struct ath5k_hw *ah); 1248void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1249void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1250u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1251void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1252/* Receive (DRU) start/stop functions */ 1253void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1254void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1255/* Beacon control functions */ 1256u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1257void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1258void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1259void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1260bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); 1261/* Init function */ 1262void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1263 u8 mode); 1264 1265/* Queue Control Unit, DFS Control Unit Functions */ 1266int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1267 struct ath5k_txq_info *queue_info); 1268int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1269 const struct ath5k_txq_info *queue_info); 1270int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1271 enum ath5k_tx_queue queue_type, 1272 struct ath5k_txq_info *queue_info); 1273u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1274void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1275int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1276int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time); 1277/* Init function */ 1278int ath5k_hw_init_queues(struct ath5k_hw *ah); 1279 1280/* Hardware Descriptor Functions */ 1281int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1282int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1283 u32 size, unsigned int flags); 1284int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1285 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 1286 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); 1287 1288 1289/* GPIO Functions */ 1290void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1291int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1292int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1293u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1294int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1295void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 1296 u32 interrupt_level); 1297 1298 1299/* RFkill Functions */ 1300void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1301void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1302 1303 1304/* Misc functions TODO: Cleanup */ 1305int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1306int ath5k_hw_get_capability(struct ath5k_hw *ah, 1307 enum ath5k_capability_type cap_type, u32 capability, 1308 u32 *result); 1309int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1310int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1311 1312 1313/* Initial register settings functions */ 1314int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1315 1316 1317/* PHY functions */ 1318/* Misc PHY functions */ 1319u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1320int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1321/* Gain_F optimization */ 1322enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1323int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1324/* PHY/RF channel functions */ 1325bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1326/* PHY calibration */ 1327void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1328int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1329 struct ieee80211_channel *channel); 1330void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); 1331/* Spur mitigation */ 1332bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1333 struct ieee80211_channel *channel); 1334/* Antenna control */ 1335void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1336void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); 1337/* TX power setup */ 1338int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1339/* Init function */ 1340int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 1341 u8 mode, u8 ee_mode, u8 freq); 1342 1343/* 1344 * Functions used internaly 1345 */ 1346 1347static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1348{ 1349 return &ah->common; 1350} 1351 1352static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1353{ 1354 return &(ath5k_hw_common(ah)->regulatory); 1355} 1356 1357static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1358{ 1359 return ioread32(ah->ah_iobase + reg); 1360} 1361 1362static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1363{ 1364 iowrite32(val, ah->ah_iobase + reg); 1365} 1366 1367static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1368{ 1369 u32 retval = 0, bit, i; 1370 1371 for (i = 0; i < bits; i++) { 1372 bit = (val >> i) & 1; 1373 retval = (retval << 1) | bit; 1374 } 1375 1376 return retval; 1377} 1378 1379#endif 1380