ath5k.h revision 631dd1a885b6d7e9f6f51b4e5b311c2bb04c323c
1/* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _ATH5K_H 19#define _ATH5K_H 20 21/* TODO: Clean up channel debuging -doesn't work anyway- and start 22 * working on reg. control code using all available eeprom information 23 * -rev. engineering needed- */ 24#define CHAN_DEBUG 0 25 26#include <linux/io.h> 27#include <linux/types.h> 28#include <net/mac80211.h> 29 30/* RX/TX descriptor hw structs 31 * TODO: Driver part should only see sw structs */ 32#include "desc.h" 33 34/* EEPROM structs/offsets 35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 36 * and clean up common bits, then introduce set/get functions in eeprom.c */ 37#include "eeprom.h" 38#include "../ath.h" 39 40/* PCI IDs */ 41#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 42#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 43#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 44#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 45#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 46#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 47#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 48#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 49#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 50#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 51#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 52#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 53#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 54#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 55#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 58#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 59#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 60#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 61#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 62#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 63#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 64#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 65#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 66#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 67#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 68#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 69 70/****************************\ 71 GENERIC DRIVER DEFINITIONS 72\****************************/ 73 74#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 75 76#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 77 printk(_level "ath5k %s: " _fmt, \ 78 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 79 ##__VA_ARGS__) 80 81#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 82 if (net_ratelimit()) \ 83 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 84 } while (0) 85 86#define ATH5K_INFO(_sc, _fmt, ...) \ 87 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 88 89#define ATH5K_WARN(_sc, _fmt, ...) \ 90 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 91 92#define ATH5K_ERR(_sc, _fmt, ...) \ 93 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 94 95/* 96 * AR5K REGISTER ACCESS 97 */ 98 99/* Some macros to read/write fields */ 100 101/* First shift, then mask */ 102#define AR5K_REG_SM(_val, _flags) \ 103 (((_val) << _flags##_S) & (_flags)) 104 105/* First mask, then shift */ 106#define AR5K_REG_MS(_val, _flags) \ 107 (((_val) & (_flags)) >> _flags##_S) 108 109/* Some registers can hold multiple values of interest. For this 110 * reason when we want to write to these registers we must first 111 * retrieve the values which we do not want to clear (lets call this 112 * old_data) and then set the register with this and our new_value: 113 * ( old_data | new_value) */ 114#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 115 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 116 (((_val) << _flags##_S) & (_flags)), _reg) 117 118#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 119 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 120 (_mask)) | (_flags), _reg) 121 122#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 123 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 124 125#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 126 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 127 128/* Access to PHY registers */ 129#define AR5K_PHY_READ(ah, _reg) \ 130 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 131 132#define AR5K_PHY_WRITE(ah, _reg, _val) \ 133 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 134 135/* Access QCU registers per queue */ 136#define AR5K_REG_READ_Q(ah, _reg, _queue) \ 137 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 138 139#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 140 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 141 142#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 143 _reg |= 1 << _queue; \ 144} while (0) 145 146#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 147 _reg &= ~(1 << _queue); \ 148} while (0) 149 150/* Used while writing initvals */ 151#define AR5K_REG_WAIT(_i) do { \ 152 if (_i % 64) \ 153 udelay(1); \ 154} while (0) 155 156/* Register dumps are done per operation mode */ 157#define AR5K_INI_RFGAIN_5GHZ 0 158#define AR5K_INI_RFGAIN_2GHZ 1 159 160/* TODO: Clean this up */ 161#define AR5K_INI_VAL_11A 0 162#define AR5K_INI_VAL_11A_TURBO 1 163#define AR5K_INI_VAL_11B 2 164#define AR5K_INI_VAL_11G 3 165#define AR5K_INI_VAL_11G_TURBO 4 166#define AR5K_INI_VAL_XR 0 167#define AR5K_INI_VAL_MAX 5 168 169/* 170 * Some tuneable values (these should be changeable by the user) 171 * TODO: Make use of them and add more options OR use debug/configfs 172 */ 173#define AR5K_TUNE_DMA_BEACON_RESP 2 174#define AR5K_TUNE_SW_BEACON_RESP 10 175#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 176#define AR5K_TUNE_RADAR_ALERT false 177#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 178#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) 179#define AR5K_TUNE_REGISTER_TIMEOUT 20000 180/* Register for RSSI threshold has a mask of 0xff, so 255 seems to 181 * be the max value. */ 182#define AR5K_TUNE_RSSI_THRES 129 183/* This must be set when setting the RSSI threshold otherwise it can 184 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 185 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 186 * track of it. Max value depends on harware. For AR5210 this is just 7. 187 * For AR5211+ this seems to be up to 255. */ 188#define AR5K_TUNE_BMISS_THRES 7 189#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 190#define AR5K_TUNE_BEACON_INTERVAL 100 191#define AR5K_TUNE_AIFS 2 192#define AR5K_TUNE_AIFS_11B 2 193#define AR5K_TUNE_AIFS_XR 0 194#define AR5K_TUNE_CWMIN 15 195#define AR5K_TUNE_CWMIN_11B 31 196#define AR5K_TUNE_CWMIN_XR 3 197#define AR5K_TUNE_CWMAX 1023 198#define AR5K_TUNE_CWMAX_11B 1023 199#define AR5K_TUNE_CWMAX_XR 7 200#define AR5K_TUNE_NOISE_FLOOR -72 201#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 202#define AR5K_TUNE_MAX_TXPOWER 63 203#define AR5K_TUNE_DEFAULT_TXPOWER 25 204#define AR5K_TUNE_TPC_TXPOWER false 205#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ 206#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ 207#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ 208 209#define AR5K_INIT_CARR_SENSE_EN 1 210 211/*Swap RX/TX Descriptor for big endian archs*/ 212#if defined(__BIG_ENDIAN) 213#define AR5K_INIT_CFG ( \ 214 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 215) 216#else 217#define AR5K_INIT_CFG 0x00000000 218#endif 219 220/* Initial values */ 221#define AR5K_INIT_CYCRSSI_THR1 2 222#define AR5K_INIT_TX_LATENCY 502 223#define AR5K_INIT_USEC 39 224#define AR5K_INIT_USEC_TURBO 79 225#define AR5K_INIT_USEC_32 31 226#define AR5K_INIT_SLOT_TIME 396 227#define AR5K_INIT_SLOT_TIME_TURBO 480 228#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 229#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 230#define AR5K_INIT_PROG_IFS 920 231#define AR5K_INIT_PROG_IFS_TURBO 960 232#define AR5K_INIT_EIFS 3440 233#define AR5K_INIT_EIFS_TURBO 6880 234#define AR5K_INIT_SIFS 560 235#define AR5K_INIT_SIFS_TURBO 480 236#define AR5K_INIT_SH_RETRY 10 237#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY 238#define AR5K_INIT_SSH_RETRY 32 239#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY 240#define AR5K_INIT_TX_RETRY 10 241 242#define AR5K_INIT_TRANSMIT_LATENCY ( \ 243 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 244 (AR5K_INIT_USEC) \ 245) 246#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ 247 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 248 (AR5K_INIT_USEC_TURBO) \ 249) 250#define AR5K_INIT_PROTO_TIME_CNTRL ( \ 251 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ 252 (AR5K_INIT_PROG_IFS) \ 253) 254#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ 255 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ 256 (AR5K_INIT_PROG_IFS_TURBO) \ 257) 258 259/* token to use for aifs, cwmin, cwmax in MadWiFi */ 260#define AR5K_TXQ_USEDEFAULT ((u32) -1) 261 262/* GENERIC CHIPSET DEFINITIONS */ 263 264/* MAC Chips */ 265enum ath5k_version { 266 AR5K_AR5210 = 0, 267 AR5K_AR5211 = 1, 268 AR5K_AR5212 = 2, 269}; 270 271/* PHY Chips */ 272enum ath5k_radio { 273 AR5K_RF5110 = 0, 274 AR5K_RF5111 = 1, 275 AR5K_RF5112 = 2, 276 AR5K_RF2413 = 3, 277 AR5K_RF5413 = 4, 278 AR5K_RF2316 = 5, 279 AR5K_RF2317 = 6, 280 AR5K_RF2425 = 7, 281}; 282 283/* 284 * Common silicon revision/version values 285 */ 286 287enum ath5k_srev_type { 288 AR5K_VERSION_MAC, 289 AR5K_VERSION_RAD, 290}; 291 292struct ath5k_srev_name { 293 const char *sr_name; 294 enum ath5k_srev_type sr_type; 295 u_int sr_val; 296}; 297 298#define AR5K_SREV_UNKNOWN 0xffff 299 300#define AR5K_SREV_AR5210 0x00 /* Crete */ 301#define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 302#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 303#define AR5K_SREV_AR5311B 0x30 /* Spirit */ 304#define AR5K_SREV_AR5211 0x40 /* Oahu */ 305#define AR5K_SREV_AR5212 0x50 /* Venice */ 306#define AR5K_SREV_AR5212_V4 0x54 /* ??? */ 307#define AR5K_SREV_AR5213 0x55 /* ??? */ 308#define AR5K_SREV_AR5213A 0x59 /* Hainan */ 309#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 310#define AR5K_SREV_AR2414 0x70 /* Griffin */ 311#define AR5K_SREV_AR5424 0x90 /* Condor */ 312#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 313#define AR5K_SREV_AR5414 0xa0 /* Eagle */ 314#define AR5K_SREV_AR2415 0xb0 /* Talon */ 315#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 316#define AR5K_SREV_AR5418 0xca /* PCI-E */ 317#define AR5K_SREV_AR2425 0xe0 /* Swan */ 318#define AR5K_SREV_AR2417 0xf0 /* Nala */ 319 320#define AR5K_SREV_RAD_5110 0x00 321#define AR5K_SREV_RAD_5111 0x10 322#define AR5K_SREV_RAD_5111A 0x15 323#define AR5K_SREV_RAD_2111 0x20 324#define AR5K_SREV_RAD_5112 0x30 325#define AR5K_SREV_RAD_5112A 0x35 326#define AR5K_SREV_RAD_5112B 0x36 327#define AR5K_SREV_RAD_2112 0x40 328#define AR5K_SREV_RAD_2112A 0x45 329#define AR5K_SREV_RAD_2112B 0x46 330#define AR5K_SREV_RAD_2413 0x50 331#define AR5K_SREV_RAD_5413 0x60 332#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 333#define AR5K_SREV_RAD_2317 0x80 334#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 335#define AR5K_SREV_RAD_2425 0xa2 336#define AR5K_SREV_RAD_5133 0xc0 337 338#define AR5K_SREV_PHY_5211 0x30 339#define AR5K_SREV_PHY_5212 0x41 340#define AR5K_SREV_PHY_5212A 0x42 341#define AR5K_SREV_PHY_5212B 0x43 342#define AR5K_SREV_PHY_2413 0x45 343#define AR5K_SREV_PHY_5413 0x61 344#define AR5K_SREV_PHY_2425 0x70 345 346/* IEEE defs */ 347#define IEEE80211_MAX_LEN 2500 348 349/* TODO add support to mac80211 for vendor-specific rates and modes */ 350 351/* 352 * Some of this information is based on Documentation from: 353 * 354 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 355 * 356 * Modulation for Atheros' eXtended Range - range enhancing extension that is 357 * supposed to double the distance an Atheros client device can keep a 358 * connection with an Atheros access point. This is achieved by increasing 359 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 360 * the 802.11 specifications demand. In addition, new (proprietary) data rates 361 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 362 * 363 * Please note that can you either use XR or TURBO but you cannot use both, 364 * they are exclusive. 365 * 366 */ 367#define MODULATION_XR 0x00000200 368/* 369 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 370 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 371 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 372 * channels. To use this feature your Access Point must also suport it. 373 * There is also a distinction between "static" and "dynamic" turbo modes: 374 * 375 * - Static: is the dumb version: devices set to this mode stick to it until 376 * the mode is turned off. 377 * - Dynamic: is the intelligent version, the network decides itself if it 378 * is ok to use turbo. As soon as traffic is detected on adjacent channels 379 * (which would get used in turbo mode), or when a non-turbo station joins 380 * the network, turbo mode won't be used until the situation changes again. 381 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 382 * monitors the used radio band in order to decide whether turbo mode may 383 * be used or not. 384 * 385 * This article claims Super G sticks to bonding of channels 5 and 6 for 386 * USA: 387 * 388 * http://www.pcworld.com/article/id,113428-page,1/article.html 389 * 390 * The channel bonding seems to be driver specific though. In addition to 391 * deciding what channels will be used, these "Turbo" modes are accomplished 392 * by also enabling the following features: 393 * 394 * - Bursting: allows multiple frames to be sent at once, rather than pausing 395 * after each frame. Bursting is a standards-compliant feature that can be 396 * used with any Access Point. 397 * - Fast frames: increases the amount of information that can be sent per 398 * frame, also resulting in a reduction of transmission overhead. It is a 399 * proprietary feature that needs to be supported by the Access Point. 400 * - Compression: data frames are compressed in real time using a Lempel Ziv 401 * algorithm. This is done transparently. Once this feature is enabled, 402 * compression and decompression takes place inside the chipset, without 403 * putting additional load on the host CPU. 404 * 405 */ 406#define MODULATION_TURBO 0x00000080 407 408enum ath5k_driver_mode { 409 AR5K_MODE_11A = 0, 410 AR5K_MODE_11A_TURBO = 1, 411 AR5K_MODE_11B = 2, 412 AR5K_MODE_11G = 3, 413 AR5K_MODE_11G_TURBO = 4, 414 AR5K_MODE_XR = 0, 415 AR5K_MODE_MAX = 5 416}; 417 418enum ath5k_ant_mode { 419 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 420 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 421 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 422 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 423 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 424 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 425 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 426 AR5K_ANTMODE_MAX, 427}; 428 429 430/****************\ 431 TX DEFINITIONS 432\****************/ 433 434/* 435 * TX Status descriptor 436 */ 437struct ath5k_tx_status { 438 u16 ts_seqnum; 439 u16 ts_tstamp; 440 u8 ts_status; 441 u8 ts_rate[4]; 442 u8 ts_retry[4]; 443 u8 ts_final_idx; 444 s8 ts_rssi; 445 u8 ts_shortretry; 446 u8 ts_longretry; 447 u8 ts_virtcol; 448 u8 ts_antenna; 449}; 450 451#define AR5K_TXSTAT_ALTRATE 0x80 452#define AR5K_TXERR_XRETRY 0x01 453#define AR5K_TXERR_FILT 0x02 454#define AR5K_TXERR_FIFO 0x04 455 456/** 457 * enum ath5k_tx_queue - Queue types used to classify tx queues. 458 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 459 * @AR5K_TX_QUEUE_DATA: A normal data queue 460 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 461 * @AR5K_TX_QUEUE_BEACON: The beacon queue 462 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 463 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 464 */ 465enum ath5k_tx_queue { 466 AR5K_TX_QUEUE_INACTIVE = 0, 467 AR5K_TX_QUEUE_DATA, 468 AR5K_TX_QUEUE_XR_DATA, 469 AR5K_TX_QUEUE_BEACON, 470 AR5K_TX_QUEUE_CAB, 471 AR5K_TX_QUEUE_UAPSD, 472}; 473 474#define AR5K_NUM_TX_QUEUES 10 475#define AR5K_NUM_TX_QUEUES_NOQCU 2 476 477/* 478 * Queue syb-types to classify normal data queues. 479 * These are the 4 Access Categories as defined in 480 * WME spec. 0 is the lowest priority and 4 is the 481 * highest. Normal data that hasn't been classified 482 * goes to the Best Effort AC. 483 */ 484enum ath5k_tx_queue_subtype { 485 AR5K_WME_AC_BK = 0, /*Background traffic*/ 486 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 487 AR5K_WME_AC_VI, /*Video traffic*/ 488 AR5K_WME_AC_VO, /*Voice traffic*/ 489}; 490 491/* 492 * Queue ID numbers as returned by the hw functions, each number 493 * represents a hw queue. If hw does not support hw queues 494 * (eg 5210) all data goes in one queue. These match 495 * d80211 definitions (net80211/MadWiFi don't use them). 496 */ 497enum ath5k_tx_queue_id { 498 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 499 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 500 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 501 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ 502 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 503 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 504 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 505 AR5K_TX_QUEUE_ID_UAPSD = 8, 506 AR5K_TX_QUEUE_ID_XR_DATA = 9, 507}; 508 509/* 510 * Flags to set hw queue's parameters... 511 */ 512#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 513#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 514#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 515#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 516#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 517#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 518#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 519#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 520#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 521#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 522#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 523#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 524#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 525#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 526 527/* 528 * A struct to hold tx queue's parameters 529 */ 530struct ath5k_txq_info { 531 enum ath5k_tx_queue tqi_type; 532 enum ath5k_tx_queue_subtype tqi_subtype; 533 u16 tqi_flags; /* Tx queue flags (see above) */ 534 u32 tqi_aifs; /* Arbitrated Interframe Space */ 535 s32 tqi_cw_min; /* Minimum Contention Window */ 536 s32 tqi_cw_max; /* Maximum Contention Window */ 537 u32 tqi_cbr_period; /* Constant bit rate period */ 538 u32 tqi_cbr_overflow_limit; 539 u32 tqi_burst_time; 540 u32 tqi_ready_time; /* Time queue waits after an event */ 541}; 542 543/* 544 * Transmit packet types. 545 * used on tx control descriptor 546 */ 547enum ath5k_pkt_type { 548 AR5K_PKT_TYPE_NORMAL = 0, 549 AR5K_PKT_TYPE_ATIM = 1, 550 AR5K_PKT_TYPE_PSPOLL = 2, 551 AR5K_PKT_TYPE_BEACON = 3, 552 AR5K_PKT_TYPE_PROBE_RESP = 4, 553 AR5K_PKT_TYPE_PIFS = 5, 554}; 555 556/* 557 * TX power and TPC settings 558 */ 559#define AR5K_TXPOWER_OFDM(_r, _v) ( \ 560 ((0 & 1) << ((_v) + 6)) | \ 561 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 562) 563 564#define AR5K_TXPOWER_CCK(_r, _v) ( \ 565 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 566) 567 568/* 569 * DMA size definitions (2^(n+2)) 570 */ 571enum ath5k_dmasize { 572 AR5K_DMASIZE_4B = 0, 573 AR5K_DMASIZE_8B, 574 AR5K_DMASIZE_16B, 575 AR5K_DMASIZE_32B, 576 AR5K_DMASIZE_64B, 577 AR5K_DMASIZE_128B, 578 AR5K_DMASIZE_256B, 579 AR5K_DMASIZE_512B 580}; 581 582 583/****************\ 584 RX DEFINITIONS 585\****************/ 586 587/* 588 * RX Status descriptor 589 */ 590struct ath5k_rx_status { 591 u16 rs_datalen; 592 u16 rs_tstamp; 593 u8 rs_status; 594 u8 rs_phyerr; 595 s8 rs_rssi; 596 u8 rs_keyix; 597 u8 rs_rate; 598 u8 rs_antenna; 599 u8 rs_more; 600}; 601 602#define AR5K_RXERR_CRC 0x01 603#define AR5K_RXERR_PHY 0x02 604#define AR5K_RXERR_FIFO 0x04 605#define AR5K_RXERR_DECRYPT 0x08 606#define AR5K_RXERR_MIC 0x10 607#define AR5K_RXKEYIX_INVALID ((u8) - 1) 608#define AR5K_TXKEYIX_INVALID ((u32) - 1) 609 610 611/**************************\ 612 BEACON TIMERS DEFINITIONS 613\**************************/ 614 615#define AR5K_BEACON_PERIOD 0x0000ffff 616#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 617#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 618 619 620/* 621 * TSF to TU conversion: 622 * 623 * TSF is a 64bit value in usec (microseconds). 624 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 625 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 626 */ 627#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 628 629 630/*******************************\ 631 GAIN OPTIMIZATION DEFINITIONS 632\*******************************/ 633 634enum ath5k_rfgain { 635 AR5K_RFGAIN_INACTIVE = 0, 636 AR5K_RFGAIN_ACTIVE, 637 AR5K_RFGAIN_READ_REQUESTED, 638 AR5K_RFGAIN_NEED_CHANGE, 639}; 640 641struct ath5k_gain { 642 u8 g_step_idx; 643 u8 g_current; 644 u8 g_target; 645 u8 g_low; 646 u8 g_high; 647 u8 g_f_corr; 648 u8 g_state; 649}; 650 651/********************\ 652 COMMON DEFINITIONS 653\********************/ 654 655#define AR5K_SLOT_TIME_9 396 656#define AR5K_SLOT_TIME_20 880 657#define AR5K_SLOT_TIME_MAX 0xffff 658 659/* channel_flags */ 660#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 661#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ 662#define CHANNEL_CCK 0x0020 /* CCK channel */ 663#define CHANNEL_OFDM 0x0040 /* OFDM channel */ 664#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 665#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 666#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 667#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 668#define CHANNEL_XR 0x0800 /* XR channel */ 669 670#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 671#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 672#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 673#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 674#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 675#define CHANNEL_108A CHANNEL_T 676#define CHANNEL_108G CHANNEL_TG 677#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 678 679#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ 680 CHANNEL_TURBO) 681 682#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) 683#define CHANNEL_MODES CHANNEL_ALL 684 685/* 686 * Used internaly for reset_tx_queue). 687 * Also see struct struct ieee80211_channel. 688 */ 689#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 690#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) 691 692/* 693 * The following structure is used to map 2GHz channels to 694 * 5GHz Atheros channels. 695 * TODO: Clean up 696 */ 697struct ath5k_athchan_2ghz { 698 u32 a2_flags; 699 u16 a2_athchan; 700}; 701 702 703/******************\ 704 RATE DEFINITIONS 705\******************/ 706 707/** 708 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 709 * 710 * The rate code is used to get the RX rate or set the TX rate on the 711 * hardware descriptors. It is also used for internal modulation control 712 * and settings. 713 * 714 * This is the hardware rate map we are aware of: 715 * 716 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 717 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 718 * 719 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 720 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 721 * 722 * rate_code 17 18 19 20 21 22 23 24 723 * rate_kbps ? ? ? ? ? ? ? 11000 724 * 725 * rate_code 25 26 27 28 29 30 31 32 726 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 727 * 728 * "S" indicates CCK rates with short preamble. 729 * 730 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 731 * lowest 4 bits, so they are the same as below with a 0xF mask. 732 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 733 * We handle this in ath5k_setup_bands(). 734 */ 735#define AR5K_MAX_RATES 32 736 737/* B */ 738#define ATH5K_RATE_CODE_1M 0x1B 739#define ATH5K_RATE_CODE_2M 0x1A 740#define ATH5K_RATE_CODE_5_5M 0x19 741#define ATH5K_RATE_CODE_11M 0x18 742/* A and G */ 743#define ATH5K_RATE_CODE_6M 0x0B 744#define ATH5K_RATE_CODE_9M 0x0F 745#define ATH5K_RATE_CODE_12M 0x0A 746#define ATH5K_RATE_CODE_18M 0x0E 747#define ATH5K_RATE_CODE_24M 0x09 748#define ATH5K_RATE_CODE_36M 0x0D 749#define ATH5K_RATE_CODE_48M 0x08 750#define ATH5K_RATE_CODE_54M 0x0C 751/* XR */ 752#define ATH5K_RATE_CODE_XR_500K 0x07 753#define ATH5K_RATE_CODE_XR_1M 0x02 754#define ATH5K_RATE_CODE_XR_2M 0x06 755#define ATH5K_RATE_CODE_XR_3M 0x01 756 757/* adding this flag to rate_code enables short preamble */ 758#define AR5K_SET_SHORT_PREAMBLE 0x04 759 760/* 761 * Crypto definitions 762 */ 763 764#define AR5K_KEYCACHE_SIZE 8 765 766/***********************\ 767 HW RELATED DEFINITIONS 768\***********************/ 769 770/* 771 * Misc definitions 772 */ 773#define AR5K_RSSI_EP_MULTIPLIER (1<<7) 774 775#define AR5K_ASSERT_ENTRY(_e, _s) do { \ 776 if (_e >= _s) \ 777 return (false); \ 778} while (0) 779 780/* 781 * Hardware interrupt abstraction 782 */ 783 784/** 785 * enum ath5k_int - Hardware interrupt masks helpers 786 * 787 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 788 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 789 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 790 * @AR5K_INT_RXNOFRM: No frame received (?) 791 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 792 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 793 * LinkPtr is NULL. For more details, refer to: 794 * http://www.freepatentsonline.com/20030225739.html 795 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 796 * Note that Rx overrun is not always fatal, on some chips we can continue 797 * operation without reseting the card, that's why int_fatal is not 798 * common for all chips. 799 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 800 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 801 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 802 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 803 * We currently do increments on interrupt by 804 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 805 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 806 * one of the PHY error counters reached the maximum value and should be 807 * read and cleared. 808 * @AR5K_INT_RXPHY: RX PHY Error 809 * @AR5K_INT_RXKCM: RX Key cache miss 810 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 811 * beacon that must be handled in software. The alternative is if you 812 * have VEOL support, in that case you let the hardware deal with things. 813 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 814 * beacons from the AP have associated with, we should probably try to 815 * reassociate. When in IBSS mode this might mean we have not received 816 * any beacons from any local stations. Note that every station in an 817 * IBSS schedules to send beacons at the Target Beacon Transmission Time 818 * (TBTT) with a random backoff. 819 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 820 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 821 * until properly handled 822 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 823 * errors. These types of errors we can enable seem to be of type 824 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 825 * @AR5K_INT_GLOBAL: Used to clear and set the IER 826 * @AR5K_INT_NOCARD: signals the card has been removed 827 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 828 * bit value 829 * 830 * These are mapped to take advantage of some common bits 831 * between the MACs, to be able to set intr properties 832 * easier. Some of them are not used yet inside hw.c. Most map 833 * to the respective hw interrupt value as they are common amogst different 834 * MACs. 835 */ 836enum ath5k_int { 837 AR5K_INT_RXOK = 0x00000001, 838 AR5K_INT_RXDESC = 0x00000002, 839 AR5K_INT_RXERR = 0x00000004, 840 AR5K_INT_RXNOFRM = 0x00000008, 841 AR5K_INT_RXEOL = 0x00000010, 842 AR5K_INT_RXORN = 0x00000020, 843 AR5K_INT_TXOK = 0x00000040, 844 AR5K_INT_TXDESC = 0x00000080, 845 AR5K_INT_TXERR = 0x00000100, 846 AR5K_INT_TXNOFRM = 0x00000200, 847 AR5K_INT_TXEOL = 0x00000400, 848 AR5K_INT_TXURN = 0x00000800, 849 AR5K_INT_MIB = 0x00001000, 850 AR5K_INT_SWI = 0x00002000, 851 AR5K_INT_RXPHY = 0x00004000, 852 AR5K_INT_RXKCM = 0x00008000, 853 AR5K_INT_SWBA = 0x00010000, 854 AR5K_INT_BRSSI = 0x00020000, 855 AR5K_INT_BMISS = 0x00040000, 856 AR5K_INT_FATAL = 0x00080000, /* Non common */ 857 AR5K_INT_BNR = 0x00100000, /* Non common */ 858 AR5K_INT_TIM = 0x00200000, /* Non common */ 859 AR5K_INT_DTIM = 0x00400000, /* Non common */ 860 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 861 AR5K_INT_GPIO = 0x01000000, 862 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 863 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 864 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 865 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 866 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 867 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 868 AR5K_INT_GLOBAL = 0x80000000, 869 870 AR5K_INT_COMMON = AR5K_INT_RXOK 871 | AR5K_INT_RXDESC 872 | AR5K_INT_RXERR 873 | AR5K_INT_RXNOFRM 874 | AR5K_INT_RXEOL 875 | AR5K_INT_RXORN 876 | AR5K_INT_TXOK 877 | AR5K_INT_TXDESC 878 | AR5K_INT_TXERR 879 | AR5K_INT_TXNOFRM 880 | AR5K_INT_TXEOL 881 | AR5K_INT_TXURN 882 | AR5K_INT_MIB 883 | AR5K_INT_SWI 884 | AR5K_INT_RXPHY 885 | AR5K_INT_RXKCM 886 | AR5K_INT_SWBA 887 | AR5K_INT_BRSSI 888 | AR5K_INT_BMISS 889 | AR5K_INT_GPIO 890 | AR5K_INT_GLOBAL, 891 892 AR5K_INT_NOCARD = 0xffffffff 893}; 894 895/* mask which calibration is active at the moment */ 896enum ath5k_calibration_mask { 897 AR5K_CALIBRATION_FULL = 0x01, 898 AR5K_CALIBRATION_SHORT = 0x02, 899 AR5K_CALIBRATION_ANI = 0x04, 900}; 901 902/* 903 * Power management 904 */ 905enum ath5k_power_mode { 906 AR5K_PM_UNDEFINED = 0, 907 AR5K_PM_AUTO, 908 AR5K_PM_AWAKE, 909 AR5K_PM_FULL_SLEEP, 910 AR5K_PM_NETWORK_SLEEP, 911}; 912 913/* 914 * These match net80211 definitions (not used in 915 * mac80211). 916 * TODO: Clean this up 917 */ 918#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 919#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 920#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 921#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 922#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 923 924/* GPIO-controlled software LED */ 925#define AR5K_SOFTLED_PIN 0 926#define AR5K_SOFTLED_ON 0 927#define AR5K_SOFTLED_OFF 1 928 929/* 930 * Chipset capabilities -see ath5k_hw_get_capability- 931 * get_capability function is not yet fully implemented 932 * in ath5k so most of these don't work yet... 933 * TODO: Implement these & merge with _TUNE_ stuff above 934 */ 935enum ath5k_capability_type { 936 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 937 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 938 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 939 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 940 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 941 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 942 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 943 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 944 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 945 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 946 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 947 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 948 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 949 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 950 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 951 AR5K_CAP_XR = 16, /* Supports XR mode */ 952 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 953 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 954 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 955 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 956}; 957 958 959/* XXX: we *may* move cap_range stuff to struct wiphy */ 960struct ath5k_capabilities { 961 /* 962 * Supported PHY modes 963 * (ie. CHANNEL_A, CHANNEL_B, ...) 964 */ 965 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 966 967 /* 968 * Frequency range (without regulation restrictions) 969 */ 970 struct { 971 u16 range_2ghz_min; 972 u16 range_2ghz_max; 973 u16 range_5ghz_min; 974 u16 range_5ghz_max; 975 } cap_range; 976 977 /* 978 * Values stored in the EEPROM (some of them...) 979 */ 980 struct ath5k_eeprom_info cap_eeprom; 981 982 /* 983 * Queue information 984 */ 985 struct { 986 u8 q_tx_num; 987 } cap_queues; 988 989 bool cap_has_phyerr_counters; 990}; 991 992/* size of noise floor history (keep it a power of two) */ 993#define ATH5K_NF_CAL_HIST_MAX 8 994struct ath5k_nfcal_hist 995{ 996 s16 index; /* current index into nfval */ 997 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 998}; 999 1000/** 1001 * struct avg_val - Helper structure for average calculation 1002 * @avg: contains the actual average value 1003 * @avg_weight: is used internally during calculation to prevent rounding errors 1004 */ 1005struct ath5k_avg_val { 1006 int avg; 1007 int avg_weight; 1008}; 1009 1010/***************************************\ 1011 HARDWARE ABSTRACTION LAYER STRUCTURE 1012\***************************************/ 1013 1014/* 1015 * Misc defines 1016 */ 1017 1018#define AR5K_MAX_GPIO 10 1019#define AR5K_MAX_RF_BANKS 8 1020 1021/* TODO: Clean up and merge with ath5k_softc */ 1022struct ath5k_hw { 1023 struct ath_common common; 1024 1025 struct ath5k_softc *ah_sc; 1026 void __iomem *ah_iobase; 1027 1028 enum ath5k_int ah_imr; 1029 1030 struct ieee80211_channel *ah_current_channel; 1031 bool ah_turbo; 1032 bool ah_calibration; 1033 bool ah_single_chip; 1034 bool ah_aes_support; 1035 bool ah_combined_mic; 1036 1037 enum ath5k_version ah_version; 1038 enum ath5k_radio ah_radio; 1039 u32 ah_phy; 1040 u32 ah_mac_srev; 1041 u16 ah_mac_version; 1042 u16 ah_phy_revision; 1043 u16 ah_radio_5ghz_revision; 1044 u16 ah_radio_2ghz_revision; 1045 1046#define ah_modes ah_capabilities.cap_mode 1047#define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1048 1049 u32 ah_atim_window; 1050 u32 ah_aifs; 1051 u32 ah_cw_min; 1052 u32 ah_cw_max; 1053 u32 ah_limit_tx_retries; 1054 u8 ah_coverage_class; 1055 1056 /* Antenna Control */ 1057 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1058 u8 ah_ant_mode; 1059 u8 ah_tx_ant; 1060 u8 ah_def_ant; 1061 bool ah_software_retry; 1062 1063 struct ath5k_capabilities ah_capabilities; 1064 1065 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1066 u32 ah_txq_status; 1067 u32 ah_txq_imr_txok; 1068 u32 ah_txq_imr_txerr; 1069 u32 ah_txq_imr_txurn; 1070 u32 ah_txq_imr_txdesc; 1071 u32 ah_txq_imr_txeol; 1072 u32 ah_txq_imr_cbrorn; 1073 u32 ah_txq_imr_cbrurn; 1074 u32 ah_txq_imr_qtrig; 1075 u32 ah_txq_imr_nofrm; 1076 u32 ah_txq_isr; 1077 u32 *ah_rf_banks; 1078 size_t ah_rf_banks_size; 1079 size_t ah_rf_regs_count; 1080 struct ath5k_gain ah_gain; 1081 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1082 1083 1084 struct { 1085 /* Temporary tables used for interpolation */ 1086 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1087 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1088 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1089 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1090 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1091 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1092 u8 txp_min_idx; 1093 bool txp_tpc; 1094 /* Values in 0.25dB units */ 1095 s16 txp_min_pwr; 1096 s16 txp_max_pwr; 1097 /* Values in 0.5dB units */ 1098 s16 txp_offset; 1099 s16 txp_ofdm; 1100 s16 txp_cck_ofdm_gainf_delta; 1101 /* Value in dB units */ 1102 s16 txp_cck_ofdm_pwr_delta; 1103 } ah_txpower; 1104 1105 struct { 1106 bool r_enabled; 1107 int r_last_alert; 1108 struct ieee80211_channel r_last_channel; 1109 } ah_radar; 1110 1111 struct ath5k_nfcal_hist ah_nfcal_hist; 1112 1113 /* average beacon RSSI in our BSS (used by ANI) */ 1114 struct ath5k_avg_val ah_beacon_rssi_avg; 1115 1116 /* noise floor from last periodic calibration */ 1117 s32 ah_noise_floor; 1118 1119 /* Calibration timestamp */ 1120 unsigned long ah_cal_next_full; 1121 unsigned long ah_cal_next_ani; 1122 unsigned long ah_cal_next_nf; 1123 1124 /* Calibration mask */ 1125 u8 ah_cal_mask; 1126 1127 /* 1128 * Function pointers 1129 */ 1130 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1131 unsigned int, unsigned int, int, enum ath5k_pkt_type, 1132 unsigned int, unsigned int, unsigned int, unsigned int, 1133 unsigned int, unsigned int, unsigned int, unsigned int); 1134 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1135 struct ath5k_tx_status *); 1136 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1137 struct ath5k_rx_status *); 1138}; 1139 1140/* 1141 * Prototypes 1142 */ 1143 1144/* Attach/Detach Functions */ 1145int ath5k_hw_attach(struct ath5k_softc *sc); 1146void ath5k_hw_detach(struct ath5k_hw *ah); 1147 1148int ath5k_sysfs_register(struct ath5k_softc *sc); 1149void ath5k_sysfs_unregister(struct ath5k_softc *sc); 1150 1151/* LED functions */ 1152int ath5k_init_leds(struct ath5k_softc *sc); 1153void ath5k_led_enable(struct ath5k_softc *sc); 1154void ath5k_led_off(struct ath5k_softc *sc); 1155void ath5k_unregister_leds(struct ath5k_softc *sc); 1156 1157/* Reset Functions */ 1158int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1159int ath5k_hw_on_hold(struct ath5k_hw *ah); 1160int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1161 struct ieee80211_channel *channel, bool change_channel); 1162int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 1163 bool is_set); 1164/* Power management functions */ 1165 1166/* DMA Related Functions */ 1167void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1168int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah); 1169u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1170void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1171int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1172int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1173u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1174int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1175 u32 phys_addr); 1176int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1177/* Interrupt handling */ 1178bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1179int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1180enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1181void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); 1182 1183/* EEPROM access functions */ 1184int ath5k_eeprom_init(struct ath5k_hw *ah); 1185void ath5k_eeprom_detach(struct ath5k_hw *ah); 1186int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1187 1188/* Protocol Control Unit Functions */ 1189extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1190void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1191/* BSSID Functions */ 1192int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1193void ath5k_hw_set_associd(struct ath5k_hw *ah); 1194void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1195/* Receive start/stop functions */ 1196void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1197void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1198/* RX Filter functions */ 1199void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1200u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1201void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1202/* Beacon control functions */ 1203u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1204void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1205void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1206void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1207/* ACK bit rate */ 1208void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high); 1209/* Clock rate related functions */ 1210unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1211unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1212unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah); 1213/* Key table (WEP) functions */ 1214int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry); 1215int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, 1216 const struct ieee80211_key_conf *key, const u8 *mac); 1217int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac); 1218 1219/* Queue Control Unit, DFS Control Unit Functions */ 1220int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1221 struct ath5k_txq_info *queue_info); 1222int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1223 const struct ath5k_txq_info *queue_info); 1224int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1225 enum ath5k_tx_queue queue_type, 1226 struct ath5k_txq_info *queue_info); 1227u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1228void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1229int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1230int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time); 1231 1232/* Hardware Descriptor Functions */ 1233int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1234int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1235 u32 size, unsigned int flags); 1236int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1237 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 1238 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); 1239 1240/* GPIO Functions */ 1241void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1242int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1243int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1244u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1245int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1246void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 1247 u32 interrupt_level); 1248 1249/* rfkill Functions */ 1250void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1251void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1252 1253/* Misc functions */ 1254int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1255int ath5k_hw_get_capability(struct ath5k_hw *ah, 1256 enum ath5k_capability_type cap_type, u32 capability, 1257 u32 *result); 1258int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1259int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1260 1261/* Initial register settings functions */ 1262int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1263 1264/* Initialize RF */ 1265int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 1266 struct ieee80211_channel *channel, 1267 unsigned int mode); 1268int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq); 1269enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1270int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1271/* PHY/RF channel functions */ 1272bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1273int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1274/* PHY calibration */ 1275void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1276int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1277 struct ieee80211_channel *channel); 1278void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); 1279/* Spur mitigation */ 1280bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1281 struct ieee80211_channel *channel); 1282void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1283 struct ieee80211_channel *channel); 1284/* Misc PHY functions */ 1285u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1286int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1287/* Antenna control */ 1288void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1289void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); 1290/* TX power setup */ 1291int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 1292 u8 ee_mode, u8 txpower); 1293int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1294 1295/* 1296 * Functions used internaly 1297 */ 1298 1299static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1300{ 1301 return &ah->common; 1302} 1303 1304static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1305{ 1306 return &(ath5k_hw_common(ah)->regulatory); 1307} 1308 1309static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1310{ 1311 return ioread32(ah->ah_iobase + reg); 1312} 1313 1314static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1315{ 1316 iowrite32(val, ah->ah_iobase + reg); 1317} 1318 1319static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1320{ 1321 u32 retval = 0, bit, i; 1322 1323 for (i = 0; i < bits; i++) { 1324 bit = (val >> i) & 1; 1325 retval = (retval << 1) | bit; 1326 } 1327 1328 return retval; 1329} 1330 1331#define AVG_SAMPLES 8 1332#define AVG_FACTOR 1000 1333 1334/** 1335 * ath5k_moving_average - Exponentially weighted moving average 1336 * @avg: average structure 1337 * @val: current value 1338 * 1339 * This implementation make use of a struct ath5k_avg_val to prevent rounding 1340 * errors. 1341 */ 1342static inline struct ath5k_avg_val 1343ath5k_moving_average(const struct ath5k_avg_val avg, const int val) 1344{ 1345 struct ath5k_avg_val new; 1346 new.avg_weight = avg.avg_weight ? 1347 (((avg.avg_weight * ((AVG_SAMPLES) - 1)) + 1348 (val * (AVG_FACTOR))) / (AVG_SAMPLES)) : 1349 (val * (AVG_FACTOR)); 1350 new.avg = new.avg_weight / (AVG_FACTOR); 1351 return new; 1352} 1353 1354#endif 1355