ath5k.h revision 6a2a0e738225fc9ec063f84b79f0adf5c0ed176c
1/* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _ATH5K_H 19#define _ATH5K_H 20 21/* TODO: Clean up channel debugging (doesn't work anyway) and start 22 * working on reg. control code using all available eeprom information 23 * (rev. engineering needed) */ 24#define CHAN_DEBUG 0 25 26#include <linux/io.h> 27#include <linux/types.h> 28#include <linux/average.h> 29#include <net/mac80211.h> 30 31/* RX/TX descriptor hw structs 32 * TODO: Driver part should only see sw structs */ 33#include "desc.h" 34 35/* EEPROM structs/offsets 36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 37 * and clean up common bits, then introduce set/get functions in eeprom.c */ 38#include "eeprom.h" 39#include "../ath.h" 40 41/* PCI IDs */ 42#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 43#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 44#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 45#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 46#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 47#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 48#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 49#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 50#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 51#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 52#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 53#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 54#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 55#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 58#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 59#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 60#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 61#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 62#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 63#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 64#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 65#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 66#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 67#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 68#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 69#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 70 71/****************************\ 72 GENERIC DRIVER DEFINITIONS 73\****************************/ 74 75#define ATH5K_PRINTF(fmt, ...) \ 76 printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__) 77 78#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 79 printk(_level "ath5k %s: " _fmt, \ 80 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 81 ##__VA_ARGS__) 82 83#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 84 if (net_ratelimit()) \ 85 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 86 } while (0) 87 88#define ATH5K_INFO(_sc, _fmt, ...) \ 89 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 90 91#define ATH5K_WARN(_sc, _fmt, ...) \ 92 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 93 94#define ATH5K_ERR(_sc, _fmt, ...) \ 95 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 96 97/* 98 * AR5K REGISTER ACCESS 99 */ 100 101/* Some macros to read/write fields */ 102 103/* First shift, then mask */ 104#define AR5K_REG_SM(_val, _flags) \ 105 (((_val) << _flags##_S) & (_flags)) 106 107/* First mask, then shift */ 108#define AR5K_REG_MS(_val, _flags) \ 109 (((_val) & (_flags)) >> _flags##_S) 110 111/* Some registers can hold multiple values of interest. For this 112 * reason when we want to write to these registers we must first 113 * retrieve the values which we do not want to clear (lets call this 114 * old_data) and then set the register with this and our new_value: 115 * ( old_data | new_value) */ 116#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 117 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 118 (((_val) << _flags##_S) & (_flags)), _reg) 119 120#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 121 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 122 (_mask)) | (_flags), _reg) 123 124#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 125 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 126 127#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 128 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 129 130/* Access to PHY registers */ 131#define AR5K_PHY_READ(ah, _reg) \ 132 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 133 134#define AR5K_PHY_WRITE(ah, _reg, _val) \ 135 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 136 137/* Access QCU registers per queue */ 138#define AR5K_REG_READ_Q(ah, _reg, _queue) \ 139 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 140 141#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 142 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 143 144#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 145 _reg |= 1 << _queue; \ 146} while (0) 147 148#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 149 _reg &= ~(1 << _queue); \ 150} while (0) 151 152/* Used while writing initvals */ 153#define AR5K_REG_WAIT(_i) do { \ 154 if (_i % 64) \ 155 udelay(1); \ 156} while (0) 157 158/* 159 * Some tunable values (these should be changeable by the user) 160 * TODO: Make use of them and add more options OR use debug/configfs 161 */ 162#define AR5K_TUNE_DMA_BEACON_RESP 2 163#define AR5K_TUNE_SW_BEACON_RESP 10 164#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 165#define AR5K_TUNE_RADAR_ALERT false 166#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 167#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1) 168#define AR5K_TUNE_REGISTER_TIMEOUT 20000 169/* Register for RSSI threshold has a mask of 0xff, so 255 seems to 170 * be the max value. */ 171#define AR5K_TUNE_RSSI_THRES 129 172/* This must be set when setting the RSSI threshold otherwise it can 173 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 174 * the BMISS_THRES will be seen as 0, seems hardware doesn't keep 175 * track of it. Max value depends on hardware. For AR5210 this is just 7. 176 * For AR5211+ this seems to be up to 255. */ 177#define AR5K_TUNE_BMISS_THRES 7 178#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 179#define AR5K_TUNE_BEACON_INTERVAL 100 180#define AR5K_TUNE_AIFS 2 181#define AR5K_TUNE_AIFS_11B 2 182#define AR5K_TUNE_AIFS_XR 0 183#define AR5K_TUNE_CWMIN 15 184#define AR5K_TUNE_CWMIN_11B 31 185#define AR5K_TUNE_CWMIN_XR 3 186#define AR5K_TUNE_CWMAX 1023 187#define AR5K_TUNE_CWMAX_11B 1023 188#define AR5K_TUNE_CWMAX_XR 7 189#define AR5K_TUNE_NOISE_FLOOR -72 190#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 191#define AR5K_TUNE_MAX_TXPOWER 63 192#define AR5K_TUNE_DEFAULT_TXPOWER 25 193#define AR5K_TUNE_TPC_TXPOWER false 194#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ 195#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ 196#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ 197 198#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */ 199 200#define AR5K_INIT_CARR_SENSE_EN 1 201 202/*Swap RX/TX Descriptor for big endian archs*/ 203#if defined(__BIG_ENDIAN) 204#define AR5K_INIT_CFG ( \ 205 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 206) 207#else 208#define AR5K_INIT_CFG 0x00000000 209#endif 210 211/* Initial values */ 212#define AR5K_INIT_CYCRSSI_THR1 2 213 214/* Tx retry limit defaults from standard */ 215#define AR5K_INIT_RETRY_SHORT 7 216#define AR5K_INIT_RETRY_LONG 4 217 218/* Slot time */ 219#define AR5K_INIT_SLOT_TIME_TURBO 6 220#define AR5K_INIT_SLOT_TIME_DEFAULT 9 221#define AR5K_INIT_SLOT_TIME_HALF_RATE 13 222#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21 223#define AR5K_INIT_SLOT_TIME_B 20 224#define AR5K_SLOT_TIME_MAX 0xffff 225 226/* SIFS */ 227#define AR5K_INIT_SIFS_TURBO 6 228#define AR5K_INIT_SIFS_DEFAULT_BG 10 229#define AR5K_INIT_SIFS_DEFAULT_A 16 230#define AR5K_INIT_SIFS_HALF_RATE 32 231#define AR5K_INIT_SIFS_QUARTER_RATE 64 232 233/* Used to calculate tx time for non 5/10/40MHz 234 * operation */ 235/* It's preamble time + signal time (16 + 4) */ 236#define AR5K_INIT_OFDM_PREAMPLE_TIME 20 237/* Preamble time for 40MHz (turbo) operation (min ?) */ 238#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14 239#define AR5K_INIT_OFDM_SYMBOL_TIME 4 240#define AR5K_INIT_OFDM_PLCP_BITS 22 241 242/* Rx latency for 5 and 10MHz operation (max ?) */ 243#define AR5K_INIT_RX_LAT_MAX 63 244/* Tx latencies from initvals (5212 only but no problem 245 * because we only tweak them on 5212) */ 246#define AR5K_INIT_TX_LAT_A 54 247#define AR5K_INIT_TX_LAT_BG 384 248/* Tx latency for 40MHz (turbo) operation (min ?) */ 249#define AR5K_INIT_TX_LAT_MIN 32 250/* Default Tx/Rx latencies (same for 5211)*/ 251#define AR5K_INIT_TX_LATENCY_5210 54 252#define AR5K_INIT_RX_LATENCY_5210 29 253 254/* Tx frame to Tx data start delay */ 255#define AR5K_INIT_TXF2TXD_START_DEFAULT 14 256#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12 257#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13 258 259/* We need to increase PHY switch and agc settling time 260 * on turbo mode */ 261#define AR5K_SWITCH_SETTLING 5760 262#define AR5K_SWITCH_SETTLING_TURBO 7168 263 264#define AR5K_AGC_SETTLING 28 265/* 38 on 5210 but shouldn't matter */ 266#define AR5K_AGC_SETTLING_TURBO 37 267 268 269/* GENERIC CHIPSET DEFINITIONS */ 270 271/* MAC Chips */ 272enum ath5k_version { 273 AR5K_AR5210 = 0, 274 AR5K_AR5211 = 1, 275 AR5K_AR5212 = 2, 276}; 277 278/* PHY Chips */ 279enum ath5k_radio { 280 AR5K_RF5110 = 0, 281 AR5K_RF5111 = 1, 282 AR5K_RF5112 = 2, 283 AR5K_RF2413 = 3, 284 AR5K_RF5413 = 4, 285 AR5K_RF2316 = 5, 286 AR5K_RF2317 = 6, 287 AR5K_RF2425 = 7, 288}; 289 290/* 291 * Common silicon revision/version values 292 */ 293 294enum ath5k_srev_type { 295 AR5K_VERSION_MAC, 296 AR5K_VERSION_RAD, 297}; 298 299struct ath5k_srev_name { 300 const char *sr_name; 301 enum ath5k_srev_type sr_type; 302 u_int sr_val; 303}; 304 305#define AR5K_SREV_UNKNOWN 0xffff 306 307#define AR5K_SREV_AR5210 0x00 /* Crete */ 308#define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 309#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 310#define AR5K_SREV_AR5311B 0x30 /* Spirit */ 311#define AR5K_SREV_AR5211 0x40 /* Oahu */ 312#define AR5K_SREV_AR5212 0x50 /* Venice */ 313#define AR5K_SREV_AR5312_R2 0x52 /* AP31 */ 314#define AR5K_SREV_AR5212_V4 0x54 /* ??? */ 315#define AR5K_SREV_AR5213 0x55 /* ??? */ 316#define AR5K_SREV_AR5312_R7 0x57 /* AP30 */ 317#define AR5K_SREV_AR2313_R8 0x58 /* AP43 */ 318#define AR5K_SREV_AR5213A 0x59 /* Hainan */ 319#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 320#define AR5K_SREV_AR2414 0x70 /* Griffin */ 321#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */ 322#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */ 323#define AR5K_SREV_AR5424 0x90 /* Condor */ 324#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */ 325#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */ 326#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 327#define AR5K_SREV_AR5414 0xa0 /* Eagle */ 328#define AR5K_SREV_AR2415 0xb0 /* Talon */ 329#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 330#define AR5K_SREV_AR5418 0xca /* PCI-E */ 331#define AR5K_SREV_AR2425 0xe0 /* Swan */ 332#define AR5K_SREV_AR2417 0xf0 /* Nala */ 333 334#define AR5K_SREV_RAD_5110 0x00 335#define AR5K_SREV_RAD_5111 0x10 336#define AR5K_SREV_RAD_5111A 0x15 337#define AR5K_SREV_RAD_2111 0x20 338#define AR5K_SREV_RAD_5112 0x30 339#define AR5K_SREV_RAD_5112A 0x35 340#define AR5K_SREV_RAD_5112B 0x36 341#define AR5K_SREV_RAD_2112 0x40 342#define AR5K_SREV_RAD_2112A 0x45 343#define AR5K_SREV_RAD_2112B 0x46 344#define AR5K_SREV_RAD_2413 0x50 345#define AR5K_SREV_RAD_5413 0x60 346#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 347#define AR5K_SREV_RAD_2317 0x80 348#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 349#define AR5K_SREV_RAD_2425 0xa2 350#define AR5K_SREV_RAD_5133 0xc0 351 352#define AR5K_SREV_PHY_5211 0x30 353#define AR5K_SREV_PHY_5212 0x41 354#define AR5K_SREV_PHY_5212A 0x42 355#define AR5K_SREV_PHY_5212B 0x43 356#define AR5K_SREV_PHY_2413 0x45 357#define AR5K_SREV_PHY_5413 0x61 358#define AR5K_SREV_PHY_2425 0x70 359 360/* TODO add support to mac80211 for vendor-specific rates and modes */ 361 362/* 363 * Some of this information is based on Documentation from: 364 * 365 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 366 * 367 * Modulation for Atheros' eXtended Range - range enhancing extension that is 368 * supposed to double the distance an Atheros client device can keep a 369 * connection with an Atheros access point. This is achieved by increasing 370 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 371 * the 802.11 specifications demand. In addition, new (proprietary) data rates 372 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 373 * 374 * Please note that can you either use XR or TURBO but you cannot use both, 375 * they are exclusive. 376 * 377 */ 378#define MODULATION_XR 0x00000200 379/* 380 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 381 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 382 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 383 * channels. To use this feature your Access Point must also support it. 384 * There is also a distinction between "static" and "dynamic" turbo modes: 385 * 386 * - Static: is the dumb version: devices set to this mode stick to it until 387 * the mode is turned off. 388 * - Dynamic: is the intelligent version, the network decides itself if it 389 * is ok to use turbo. As soon as traffic is detected on adjacent channels 390 * (which would get used in turbo mode), or when a non-turbo station joins 391 * the network, turbo mode won't be used until the situation changes again. 392 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 393 * monitors the used radio band in order to decide whether turbo mode may 394 * be used or not. 395 * 396 * This article claims Super G sticks to bonding of channels 5 and 6 for 397 * USA: 398 * 399 * http://www.pcworld.com/article/id,113428-page,1/article.html 400 * 401 * The channel bonding seems to be driver specific though. In addition to 402 * deciding what channels will be used, these "Turbo" modes are accomplished 403 * by also enabling the following features: 404 * 405 * - Bursting: allows multiple frames to be sent at once, rather than pausing 406 * after each frame. Bursting is a standards-compliant feature that can be 407 * used with any Access Point. 408 * - Fast frames: increases the amount of information that can be sent per 409 * frame, also resulting in a reduction of transmission overhead. It is a 410 * proprietary feature that needs to be supported by the Access Point. 411 * - Compression: data frames are compressed in real time using a Lempel Ziv 412 * algorithm. This is done transparently. Once this feature is enabled, 413 * compression and decompression takes place inside the chipset, without 414 * putting additional load on the host CPU. 415 * 416 */ 417#define MODULATION_TURBO 0x00000080 418 419enum ath5k_driver_mode { 420 AR5K_MODE_11A = 0, 421 AR5K_MODE_11B = 1, 422 AR5K_MODE_11G = 2, 423 AR5K_MODE_XR = 0, 424 AR5K_MODE_MAX = 3 425}; 426 427enum ath5k_ant_mode { 428 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 429 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 430 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 431 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 432 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 433 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 434 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 435 AR5K_ANTMODE_MAX, 436}; 437 438enum ath5k_bw_mode { 439 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ 440 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ 441 AR5K_BWMODE_10MHZ = 2, /* Half rate */ 442 AR5K_BWMODE_40MHZ = 3 /* Turbo */ 443}; 444 445/****************\ 446 TX DEFINITIONS 447\****************/ 448 449/* 450 * TX Status descriptor 451 */ 452struct ath5k_tx_status { 453 u16 ts_seqnum; 454 u16 ts_tstamp; 455 u8 ts_status; 456 u8 ts_final_idx; 457 u8 ts_final_retry; 458 s8 ts_rssi; 459 u8 ts_shortretry; 460 u8 ts_virtcol; 461 u8 ts_antenna; 462}; 463 464#define AR5K_TXSTAT_ALTRATE 0x80 465#define AR5K_TXERR_XRETRY 0x01 466#define AR5K_TXERR_FILT 0x02 467#define AR5K_TXERR_FIFO 0x04 468 469/** 470 * enum ath5k_tx_queue - Queue types used to classify tx queues. 471 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 472 * @AR5K_TX_QUEUE_DATA: A normal data queue 473 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 474 * @AR5K_TX_QUEUE_BEACON: The beacon queue 475 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 476 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 477 */ 478enum ath5k_tx_queue { 479 AR5K_TX_QUEUE_INACTIVE = 0, 480 AR5K_TX_QUEUE_DATA, 481 AR5K_TX_QUEUE_XR_DATA, 482 AR5K_TX_QUEUE_BEACON, 483 AR5K_TX_QUEUE_CAB, 484 AR5K_TX_QUEUE_UAPSD, 485}; 486 487#define AR5K_NUM_TX_QUEUES 10 488#define AR5K_NUM_TX_QUEUES_NOQCU 2 489 490/* 491 * Queue syb-types to classify normal data queues. 492 * These are the 4 Access Categories as defined in 493 * WME spec. 0 is the lowest priority and 4 is the 494 * highest. Normal data that hasn't been classified 495 * goes to the Best Effort AC. 496 */ 497enum ath5k_tx_queue_subtype { 498 AR5K_WME_AC_BK = 0, /*Background traffic*/ 499 AR5K_WME_AC_BE, /*Best-effort (normal) traffic*/ 500 AR5K_WME_AC_VI, /*Video traffic*/ 501 AR5K_WME_AC_VO, /*Voice traffic*/ 502}; 503 504/* 505 * Queue ID numbers as returned by the hw functions, each number 506 * represents a hw queue. If hw does not support hw queues 507 * (eg 5210) all data goes in one queue. These match 508 * d80211 definitions (net80211/MadWiFi don't use them). 509 */ 510enum ath5k_tx_queue_id { 511 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 512 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 513 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 514 AR5K_TX_QUEUE_ID_DATA_MAX = 3, /*IEEE80211_TX_QUEUE_DATA3*/ 515 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 516 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 517 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 518 AR5K_TX_QUEUE_ID_UAPSD = 8, 519 AR5K_TX_QUEUE_ID_XR_DATA = 9, 520}; 521 522/* 523 * Flags to set hw queue's parameters... 524 */ 525#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 526#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 527#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 528#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 529#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 530#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 531#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 532#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 533#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 534#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 535#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 536#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 537#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 538#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 539 540/* 541 * A struct to hold tx queue's parameters 542 */ 543struct ath5k_txq_info { 544 enum ath5k_tx_queue tqi_type; 545 enum ath5k_tx_queue_subtype tqi_subtype; 546 u16 tqi_flags; /* Tx queue flags (see above) */ 547 u8 tqi_aifs; /* Arbitrated Interframe Space */ 548 u16 tqi_cw_min; /* Minimum Contention Window */ 549 u16 tqi_cw_max; /* Maximum Contention Window */ 550 u32 tqi_cbr_period; /* Constant bit rate period */ 551 u32 tqi_cbr_overflow_limit; 552 u32 tqi_burst_time; 553 u32 tqi_ready_time; /* Time queue waits after an event */ 554}; 555 556/* 557 * Transmit packet types. 558 * used on tx control descriptor 559 */ 560enum ath5k_pkt_type { 561 AR5K_PKT_TYPE_NORMAL = 0, 562 AR5K_PKT_TYPE_ATIM = 1, 563 AR5K_PKT_TYPE_PSPOLL = 2, 564 AR5K_PKT_TYPE_BEACON = 3, 565 AR5K_PKT_TYPE_PROBE_RESP = 4, 566 AR5K_PKT_TYPE_PIFS = 5, 567}; 568 569/* 570 * TX power and TPC settings 571 */ 572#define AR5K_TXPOWER_OFDM(_r, _v) ( \ 573 ((0 & 1) << ((_v) + 6)) | \ 574 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 575) 576 577#define AR5K_TXPOWER_CCK(_r, _v) ( \ 578 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 579) 580 581/* 582 * DMA size definitions (2^(n+2)) 583 */ 584enum ath5k_dmasize { 585 AR5K_DMASIZE_4B = 0, 586 AR5K_DMASIZE_8B, 587 AR5K_DMASIZE_16B, 588 AR5K_DMASIZE_32B, 589 AR5K_DMASIZE_64B, 590 AR5K_DMASIZE_128B, 591 AR5K_DMASIZE_256B, 592 AR5K_DMASIZE_512B 593}; 594 595 596/****************\ 597 RX DEFINITIONS 598\****************/ 599 600/* 601 * RX Status descriptor 602 */ 603struct ath5k_rx_status { 604 u16 rs_datalen; 605 u16 rs_tstamp; 606 u8 rs_status; 607 u8 rs_phyerr; 608 s8 rs_rssi; 609 u8 rs_keyix; 610 u8 rs_rate; 611 u8 rs_antenna; 612 u8 rs_more; 613}; 614 615#define AR5K_RXERR_CRC 0x01 616#define AR5K_RXERR_PHY 0x02 617#define AR5K_RXERR_FIFO 0x04 618#define AR5K_RXERR_DECRYPT 0x08 619#define AR5K_RXERR_MIC 0x10 620#define AR5K_RXKEYIX_INVALID ((u8) -1) 621#define AR5K_TXKEYIX_INVALID ((u32) -1) 622 623 624/**************************\ 625 BEACON TIMERS DEFINITIONS 626\**************************/ 627 628#define AR5K_BEACON_PERIOD 0x0000ffff 629#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 630#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 631 632 633/* 634 * TSF to TU conversion: 635 * 636 * TSF is a 64bit value in usec (microseconds). 637 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 638 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 639 */ 640#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 641 642 643/*******************************\ 644 GAIN OPTIMIZATION DEFINITIONS 645\*******************************/ 646 647enum ath5k_rfgain { 648 AR5K_RFGAIN_INACTIVE = 0, 649 AR5K_RFGAIN_ACTIVE, 650 AR5K_RFGAIN_READ_REQUESTED, 651 AR5K_RFGAIN_NEED_CHANGE, 652}; 653 654struct ath5k_gain { 655 u8 g_step_idx; 656 u8 g_current; 657 u8 g_target; 658 u8 g_low; 659 u8 g_high; 660 u8 g_f_corr; 661 u8 g_state; 662}; 663 664/********************\ 665 COMMON DEFINITIONS 666\********************/ 667 668#define AR5K_SLOT_TIME_9 396 669#define AR5K_SLOT_TIME_20 880 670#define AR5K_SLOT_TIME_MAX 0xffff 671 672/* channel_flags */ 673#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 674#define CHANNEL_CCK 0x0020 /* CCK channel */ 675#define CHANNEL_OFDM 0x0040 /* OFDM channel */ 676#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 677#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 678#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 679#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 680#define CHANNEL_XR 0x0800 /* XR channel */ 681 682#define CHANNEL_A (CHANNEL_5GHZ | CHANNEL_OFDM) 683#define CHANNEL_B (CHANNEL_2GHZ | CHANNEL_CCK) 684#define CHANNEL_G (CHANNEL_2GHZ | CHANNEL_OFDM) 685#define CHANNEL_X (CHANNEL_5GHZ | CHANNEL_OFDM | CHANNEL_XR) 686 687#define CHANNEL_ALL (CHANNEL_OFDM | CHANNEL_CCK | \ 688 CHANNEL_2GHZ | CHANNEL_5GHZ) 689 690#define CHANNEL_MODES CHANNEL_ALL 691 692/* 693 * Used internally for ath5k_hw_reset_tx_queue(). 694 * Also see struct struct ieee80211_channel. 695 */ 696#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 697#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) 698 699/* 700 * The following structure is used to map 2GHz channels to 701 * 5GHz Atheros channels. 702 * TODO: Clean up 703 */ 704struct ath5k_athchan_2ghz { 705 u32 a2_flags; 706 u16 a2_athchan; 707}; 708 709 710/******************\ 711 RATE DEFINITIONS 712\******************/ 713 714/** 715 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32. 716 * 717 * The rate code is used to get the RX rate or set the TX rate on the 718 * hardware descriptors. It is also used for internal modulation control 719 * and settings. 720 * 721 * This is the hardware rate map we are aware of: 722 * 723 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 724 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 725 * 726 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 727 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 728 * 729 * rate_code 17 18 19 20 21 22 23 24 730 * rate_kbps ? ? ? ? ? ? ? 11000 731 * 732 * rate_code 25 26 27 28 29 30 31 32 733 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 734 * 735 * "S" indicates CCK rates with short preamble. 736 * 737 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 738 * lowest 4 bits, so they are the same as below with a 0xF mask. 739 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 740 * We handle this in ath5k_setup_bands(). 741 */ 742#define AR5K_MAX_RATES 32 743 744/* B */ 745#define ATH5K_RATE_CODE_1M 0x1B 746#define ATH5K_RATE_CODE_2M 0x1A 747#define ATH5K_RATE_CODE_5_5M 0x19 748#define ATH5K_RATE_CODE_11M 0x18 749/* A and G */ 750#define ATH5K_RATE_CODE_6M 0x0B 751#define ATH5K_RATE_CODE_9M 0x0F 752#define ATH5K_RATE_CODE_12M 0x0A 753#define ATH5K_RATE_CODE_18M 0x0E 754#define ATH5K_RATE_CODE_24M 0x09 755#define ATH5K_RATE_CODE_36M 0x0D 756#define ATH5K_RATE_CODE_48M 0x08 757#define ATH5K_RATE_CODE_54M 0x0C 758/* XR */ 759#define ATH5K_RATE_CODE_XR_500K 0x07 760#define ATH5K_RATE_CODE_XR_1M 0x02 761#define ATH5K_RATE_CODE_XR_2M 0x06 762#define ATH5K_RATE_CODE_XR_3M 0x01 763 764/* adding this flag to rate_code enables short preamble */ 765#define AR5K_SET_SHORT_PREAMBLE 0x04 766 767/* 768 * Crypto definitions 769 */ 770 771#define AR5K_KEYCACHE_SIZE 8 772extern int ath5k_modparam_nohwcrypt; 773 774/***********************\ 775 HW RELATED DEFINITIONS 776\***********************/ 777 778/* 779 * Misc definitions 780 */ 781#define AR5K_RSSI_EP_MULTIPLIER (1 << 7) 782 783#define AR5K_ASSERT_ENTRY(_e, _s) do { \ 784 if (_e >= _s) \ 785 return false; \ 786} while (0) 787 788/* 789 * Hardware interrupt abstraction 790 */ 791 792/** 793 * enum ath5k_int - Hardware interrupt masks helpers 794 * 795 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 796 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 797 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 798 * @AR5K_INT_RXNOFRM: No frame received (?) 799 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 800 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 801 * LinkPtr is NULL. For more details, refer to: 802 * http://www.freepatentsonline.com/20030225739.html 803 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 804 * Note that Rx overrun is not always fatal, on some chips we can continue 805 * operation without resetting the card, that's why int_fatal is not 806 * common for all chips. 807 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 808 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 809 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 810 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 811 * We currently do increments on interrupt by 812 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 813 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 814 * one of the PHY error counters reached the maximum value and should be 815 * read and cleared. 816 * @AR5K_INT_RXPHY: RX PHY Error 817 * @AR5K_INT_RXKCM: RX Key cache miss 818 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 819 * beacon that must be handled in software. The alternative is if you 820 * have VEOL support, in that case you let the hardware deal with things. 821 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 822 * beacons from the AP have associated with, we should probably try to 823 * reassociate. When in IBSS mode this might mean we have not received 824 * any beacons from any local stations. Note that every station in an 825 * IBSS schedules to send beacons at the Target Beacon Transmission Time 826 * (TBTT) with a random backoff. 827 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 828 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 829 * until properly handled 830 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 831 * errors. These types of errors we can enable seem to be of type 832 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 833 * @AR5K_INT_GLOBAL: Used to clear and set the IER 834 * @AR5K_INT_NOCARD: signals the card has been removed 835 * @AR5K_INT_COMMON: common interrupts shared among MACs with the same 836 * bit value 837 * 838 * These are mapped to take advantage of some common bits 839 * between the MACs, to be able to set intr properties 840 * easier. Some of them are not used yet inside hw.c. Most map 841 * to the respective hw interrupt value as they are common among different 842 * MACs. 843 */ 844enum ath5k_int { 845 AR5K_INT_RXOK = 0x00000001, 846 AR5K_INT_RXDESC = 0x00000002, 847 AR5K_INT_RXERR = 0x00000004, 848 AR5K_INT_RXNOFRM = 0x00000008, 849 AR5K_INT_RXEOL = 0x00000010, 850 AR5K_INT_RXORN = 0x00000020, 851 AR5K_INT_TXOK = 0x00000040, 852 AR5K_INT_TXDESC = 0x00000080, 853 AR5K_INT_TXERR = 0x00000100, 854 AR5K_INT_TXNOFRM = 0x00000200, 855 AR5K_INT_TXEOL = 0x00000400, 856 AR5K_INT_TXURN = 0x00000800, 857 AR5K_INT_MIB = 0x00001000, 858 AR5K_INT_SWI = 0x00002000, 859 AR5K_INT_RXPHY = 0x00004000, 860 AR5K_INT_RXKCM = 0x00008000, 861 AR5K_INT_SWBA = 0x00010000, 862 AR5K_INT_BRSSI = 0x00020000, 863 AR5K_INT_BMISS = 0x00040000, 864 AR5K_INT_FATAL = 0x00080000, /* Non common */ 865 AR5K_INT_BNR = 0x00100000, /* Non common */ 866 AR5K_INT_TIM = 0x00200000, /* Non common */ 867 AR5K_INT_DTIM = 0x00400000, /* Non common */ 868 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 869 AR5K_INT_GPIO = 0x01000000, 870 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 871 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 872 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 873 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 874 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 875 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 876 AR5K_INT_GLOBAL = 0x80000000, 877 878 AR5K_INT_TX_ALL = AR5K_INT_TXOK 879 | AR5K_INT_TXDESC 880 | AR5K_INT_TXERR 881 | AR5K_INT_TXEOL 882 | AR5K_INT_TXURN, 883 884 AR5K_INT_RX_ALL = AR5K_INT_RXOK 885 | AR5K_INT_RXDESC 886 | AR5K_INT_RXERR 887 | AR5K_INT_RXNOFRM 888 | AR5K_INT_RXEOL 889 | AR5K_INT_RXORN, 890 891 AR5K_INT_COMMON = AR5K_INT_RXOK 892 | AR5K_INT_RXDESC 893 | AR5K_INT_RXERR 894 | AR5K_INT_RXNOFRM 895 | AR5K_INT_RXEOL 896 | AR5K_INT_RXORN 897 | AR5K_INT_TXOK 898 | AR5K_INT_TXDESC 899 | AR5K_INT_TXERR 900 | AR5K_INT_TXNOFRM 901 | AR5K_INT_TXEOL 902 | AR5K_INT_TXURN 903 | AR5K_INT_MIB 904 | AR5K_INT_SWI 905 | AR5K_INT_RXPHY 906 | AR5K_INT_RXKCM 907 | AR5K_INT_SWBA 908 | AR5K_INT_BRSSI 909 | AR5K_INT_BMISS 910 | AR5K_INT_GPIO 911 | AR5K_INT_GLOBAL, 912 913 AR5K_INT_NOCARD = 0xffffffff 914}; 915 916/* mask which calibration is active at the moment */ 917enum ath5k_calibration_mask { 918 AR5K_CALIBRATION_FULL = 0x01, 919 AR5K_CALIBRATION_SHORT = 0x02, 920 AR5K_CALIBRATION_ANI = 0x04, 921}; 922 923/* 924 * Power management 925 */ 926enum ath5k_power_mode { 927 AR5K_PM_UNDEFINED = 0, 928 AR5K_PM_AUTO, 929 AR5K_PM_AWAKE, 930 AR5K_PM_FULL_SLEEP, 931 AR5K_PM_NETWORK_SLEEP, 932}; 933 934/* 935 * These match net80211 definitions (not used in 936 * mac80211). 937 * TODO: Clean this up 938 */ 939#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 940#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 941#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 942#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 943#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 944 945/* GPIO-controlled software LED */ 946#define AR5K_SOFTLED_PIN 0 947#define AR5K_SOFTLED_ON 0 948#define AR5K_SOFTLED_OFF 1 949 950/* 951 * Chipset capabilities -see ath5k_hw_get_capability- 952 * get_capability function is not yet fully implemented 953 * in ath5k so most of these don't work yet... 954 * TODO: Implement these & merge with _TUNE_ stuff above 955 */ 956enum ath5k_capability_type { 957 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 958 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 959 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 960 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 961 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 962 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 963 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 964 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 965 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 966 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 967 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 968 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 969 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 970 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 971 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 972 AR5K_CAP_XR = 16, /* Supports XR mode */ 973 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 974 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 975 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 976 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 977}; 978 979 980/* XXX: we *may* move cap_range stuff to struct wiphy */ 981struct ath5k_capabilities { 982 /* 983 * Supported PHY modes 984 * (ie. CHANNEL_A, CHANNEL_B, ...) 985 */ 986 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 987 988 /* 989 * Frequency range (without regulation restrictions) 990 */ 991 struct { 992 u16 range_2ghz_min; 993 u16 range_2ghz_max; 994 u16 range_5ghz_min; 995 u16 range_5ghz_max; 996 } cap_range; 997 998 /* 999 * Values stored in the EEPROM (some of them...) 1000 */ 1001 struct ath5k_eeprom_info cap_eeprom; 1002 1003 /* 1004 * Queue information 1005 */ 1006 struct { 1007 u8 q_tx_num; 1008 } cap_queues; 1009 1010 bool cap_has_phyerr_counters; 1011}; 1012 1013/* size of noise floor history (keep it a power of two) */ 1014#define ATH5K_NF_CAL_HIST_MAX 8 1015struct ath5k_nfcal_hist { 1016 s16 index; /* current index into nfval */ 1017 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 1018}; 1019 1020/** 1021 * struct avg_val - Helper structure for average calculation 1022 * @avg: contains the actual average value 1023 * @avg_weight: is used internally during calculation to prevent rounding errors 1024 */ 1025struct ath5k_avg_val { 1026 int avg; 1027 int avg_weight; 1028}; 1029 1030/***************************************\ 1031 HARDWARE ABSTRACTION LAYER STRUCTURE 1032\***************************************/ 1033 1034/* 1035 * Misc defines 1036 */ 1037 1038#define AR5K_MAX_GPIO 10 1039#define AR5K_MAX_RF_BANKS 8 1040 1041/* TODO: Clean up and merge with ath5k_softc */ 1042struct ath5k_hw { 1043 struct ath_common common; 1044 1045 struct ath5k_softc *ah_sc; 1046 void __iomem *ah_iobase; 1047 1048 enum ath5k_int ah_imr; 1049 1050 struct ieee80211_channel *ah_current_channel; 1051 bool ah_calibration; 1052 bool ah_single_chip; 1053 1054 enum ath5k_version ah_version; 1055 enum ath5k_radio ah_radio; 1056 u32 ah_phy; 1057 u32 ah_mac_srev; 1058 u16 ah_mac_version; 1059 u16 ah_mac_revision; 1060 u16 ah_phy_revision; 1061 u16 ah_radio_5ghz_revision; 1062 u16 ah_radio_2ghz_revision; 1063 1064#define ah_modes ah_capabilities.cap_mode 1065#define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1066 1067 u8 ah_retry_long; 1068 u8 ah_retry_short; 1069 1070 u8 ah_coverage_class; 1071 bool ah_ack_bitrate_high; 1072 u8 ah_bwmode; 1073 bool ah_short_slot; 1074 1075 /* Antenna Control */ 1076 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1077 u8 ah_ant_mode; 1078 u8 ah_tx_ant; 1079 u8 ah_def_ant; 1080 1081 struct ath5k_capabilities ah_capabilities; 1082 1083 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1084 u32 ah_txq_status; 1085 u32 ah_txq_imr_txok; 1086 u32 ah_txq_imr_txerr; 1087 u32 ah_txq_imr_txurn; 1088 u32 ah_txq_imr_txdesc; 1089 u32 ah_txq_imr_txeol; 1090 u32 ah_txq_imr_cbrorn; 1091 u32 ah_txq_imr_cbrurn; 1092 u32 ah_txq_imr_qtrig; 1093 u32 ah_txq_imr_nofrm; 1094 u32 ah_txq_isr; 1095 u32 *ah_rf_banks; 1096 size_t ah_rf_banks_size; 1097 size_t ah_rf_regs_count; 1098 struct ath5k_gain ah_gain; 1099 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1100 1101 1102 struct { 1103 /* Temporary tables used for interpolation */ 1104 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1105 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1106 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1107 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1108 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1109 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1110 u8 txp_min_idx; 1111 bool txp_tpc; 1112 /* Values in 0.25dB units */ 1113 s16 txp_min_pwr; 1114 s16 txp_max_pwr; 1115 s16 txp_cur_pwr; 1116 /* Values in 0.5dB units */ 1117 s16 txp_offset; 1118 s16 txp_ofdm; 1119 s16 txp_cck_ofdm_gainf_delta; 1120 /* Value in dB units */ 1121 s16 txp_cck_ofdm_pwr_delta; 1122 bool txp_setup; 1123 } ah_txpower; 1124 1125 struct { 1126 bool r_enabled; 1127 int r_last_alert; 1128 struct ieee80211_channel r_last_channel; 1129 } ah_radar; 1130 1131 struct ath5k_nfcal_hist ah_nfcal_hist; 1132 1133 /* average beacon RSSI in our BSS (used by ANI) */ 1134 struct ewma ah_beacon_rssi_avg; 1135 1136 /* noise floor from last periodic calibration */ 1137 s32 ah_noise_floor; 1138 1139 /* Calibration timestamp */ 1140 unsigned long ah_cal_next_full; 1141 unsigned long ah_cal_next_ani; 1142 unsigned long ah_cal_next_nf; 1143 1144 /* Calibration mask */ 1145 u8 ah_cal_mask; 1146 1147 /* 1148 * Function pointers 1149 */ 1150 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1151 unsigned int, unsigned int, int, enum ath5k_pkt_type, 1152 unsigned int, unsigned int, unsigned int, unsigned int, 1153 unsigned int, unsigned int, unsigned int, unsigned int); 1154 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1155 struct ath5k_tx_status *); 1156 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1157 struct ath5k_rx_status *); 1158}; 1159 1160struct ath_bus_ops { 1161 enum ath_bus_type ath_bus_type; 1162 void (*read_cachesize)(struct ath_common *common, int *csz); 1163 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 1164 int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac); 1165}; 1166 1167/* 1168 * Prototypes 1169 */ 1170extern const struct ieee80211_ops ath5k_hw_ops; 1171 1172/* Initialization and detach functions */ 1173int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops); 1174void ath5k_deinit_softc(struct ath5k_softc *sc); 1175int ath5k_hw_init(struct ath5k_softc *sc); 1176void ath5k_hw_deinit(struct ath5k_hw *ah); 1177 1178int ath5k_sysfs_register(struct ath5k_softc *sc); 1179void ath5k_sysfs_unregister(struct ath5k_softc *sc); 1180 1181/* base.c */ 1182struct ath5k_buf; 1183struct ath5k_txq; 1184 1185void ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable); 1186bool ath5k_any_vif_assoc(struct ath5k_softc *sc); 1187void ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1188 struct ath5k_txq *txq); 1189int ath5k_init_hw(struct ath5k_softc *sc); 1190int ath5k_stop_hw(struct ath5k_softc *sc); 1191void ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif); 1192void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, 1193 struct ieee80211_vif *vif); 1194int ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan); 1195void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 1196int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 1197void ath5k_beacon_config(struct ath5k_softc *sc); 1198void ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf); 1199void ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf); 1200 1201/*Chip id helper functions */ 1202const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val); 1203int ath5k_hw_read_srev(struct ath5k_hw *ah); 1204 1205/* LED functions */ 1206int ath5k_init_leds(struct ath5k_softc *sc); 1207void ath5k_led_enable(struct ath5k_softc *sc); 1208void ath5k_led_off(struct ath5k_softc *sc); 1209void ath5k_unregister_leds(struct ath5k_softc *sc); 1210 1211 1212/* Reset Functions */ 1213int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1214int ath5k_hw_on_hold(struct ath5k_hw *ah); 1215int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1216 struct ieee80211_channel *channel, bool fast, bool skip_pcu); 1217int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 1218 bool is_set); 1219/* Power management functions */ 1220 1221 1222/* Clock rate related functions */ 1223unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1224unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1225void ath5k_hw_set_clockrate(struct ath5k_hw *ah); 1226 1227 1228/* DMA Related Functions */ 1229void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1230u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1231int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1232int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1233int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue); 1234u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1235int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1236 u32 phys_addr); 1237int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1238/* Interrupt handling */ 1239bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1240int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1241enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1242void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); 1243/* Init/Stop functions */ 1244void ath5k_hw_dma_init(struct ath5k_hw *ah); 1245int ath5k_hw_dma_stop(struct ath5k_hw *ah); 1246 1247/* EEPROM access functions */ 1248int ath5k_eeprom_init(struct ath5k_hw *ah); 1249void ath5k_eeprom_detach(struct ath5k_hw *ah); 1250 1251 1252/* Protocol Control Unit Functions */ 1253/* Helpers */ 1254int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 1255 int len, struct ieee80211_rate *rate, bool shortpre); 1256unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah); 1257unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah); 1258int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1259void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1260/* RX filter control*/ 1261int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1262void ath5k_hw_set_bssid(struct ath5k_hw *ah); 1263void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1264void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1265u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1266void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1267/* Receive (DRU) start/stop functions */ 1268void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1269void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1270/* Beacon control functions */ 1271u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1272void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1273void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1274void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1275bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); 1276/* Init function */ 1277void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1278 u8 mode); 1279 1280/* Queue Control Unit, DFS Control Unit Functions */ 1281int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1282 struct ath5k_txq_info *queue_info); 1283int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1284 const struct ath5k_txq_info *queue_info); 1285int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1286 enum ath5k_tx_queue queue_type, 1287 struct ath5k_txq_info *queue_info); 1288void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah, 1289 unsigned int queue); 1290u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1291void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1292int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1293int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time); 1294/* Init function */ 1295int ath5k_hw_init_queues(struct ath5k_hw *ah); 1296 1297/* Hardware Descriptor Functions */ 1298int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1299int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1300 u32 size, unsigned int flags); 1301int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1302 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 1303 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); 1304 1305 1306/* GPIO Functions */ 1307void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1308int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1309int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1310u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1311int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1312void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 1313 u32 interrupt_level); 1314 1315 1316/* RFkill Functions */ 1317void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1318void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1319 1320 1321/* Misc functions TODO: Cleanup */ 1322int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1323int ath5k_hw_get_capability(struct ath5k_hw *ah, 1324 enum ath5k_capability_type cap_type, u32 capability, 1325 u32 *result); 1326int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1327int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1328 1329 1330/* Initial register settings functions */ 1331int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1332 1333 1334/* PHY functions */ 1335/* Misc PHY functions */ 1336u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1337int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1338/* Gain_F optimization */ 1339enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1340int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1341/* PHY/RF channel functions */ 1342bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1343/* PHY calibration */ 1344void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1345int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1346 struct ieee80211_channel *channel); 1347void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); 1348/* Spur mitigation */ 1349bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1350 struct ieee80211_channel *channel); 1351/* Antenna control */ 1352void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1353void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); 1354/* TX power setup */ 1355int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1356/* Init function */ 1357int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 1358 u8 mode, bool fast); 1359 1360/* 1361 * Functions used internally 1362 */ 1363 1364static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1365{ 1366 return &ah->common; 1367} 1368 1369static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1370{ 1371 return &(ath5k_hw_common(ah)->regulatory); 1372} 1373 1374#ifdef CONFIG_ATHEROS_AR231X 1375#define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000) 1376 1377static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg) 1378{ 1379 /* On AR2315 and AR2317 the PCI clock domain registers 1380 * are outside of the WMAC register space */ 1381 if (unlikely((reg >= 0x4000) && (reg < 0x5000) && 1382 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6))) 1383 return AR5K_AR2315_PCI_BASE + reg; 1384 1385 return ah->ah_iobase + reg; 1386} 1387 1388static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1389{ 1390 return __raw_readl(ath5k_ahb_reg(ah, reg)); 1391} 1392 1393static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1394{ 1395 __raw_writel(val, ath5k_ahb_reg(ah, reg)); 1396} 1397 1398#else 1399 1400static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1401{ 1402 return ioread32(ah->ah_iobase + reg); 1403} 1404 1405static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1406{ 1407 iowrite32(val, ah->ah_iobase + reg); 1408} 1409 1410#endif 1411 1412static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah) 1413{ 1414 return ath5k_hw_common(ah)->bus_ops->ath_bus_type; 1415} 1416 1417static inline void ath5k_read_cachesize(struct ath_common *common, int *csz) 1418{ 1419 common->bus_ops->read_cachesize(common, csz); 1420} 1421 1422static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data) 1423{ 1424 struct ath_common *common = ath5k_hw_common(ah); 1425 return common->bus_ops->eeprom_read(common, off, data); 1426} 1427 1428static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1429{ 1430 u32 retval = 0, bit, i; 1431 1432 for (i = 0; i < bits; i++) { 1433 bit = (val >> i) & 1; 1434 retval = (retval << 1) | bit; 1435 } 1436 1437 return retval; 1438} 1439 1440#endif 1441