ath5k.h revision a082381044ce026e83dbd17f8837722b028fc07d
1/* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _ATH5K_H 19#define _ATH5K_H 20 21/* TODO: Clean up channel debuging -doesn't work anyway- and start 22 * working on reg. control code using all available eeprom information 23 * -rev. engineering needed- */ 24#define CHAN_DEBUG 0 25 26#include <linux/io.h> 27#include <linux/types.h> 28#include <net/mac80211.h> 29 30#include "../regd.h" 31 32/* RX/TX descriptor hw structs 33 * TODO: Driver part should only see sw structs */ 34#include "desc.h" 35 36/* EEPROM structs/offsets 37 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 38 * and clean up common bits, then introduce set/get functions in eeprom.c */ 39#include "eeprom.h" 40 41/* PCI IDs */ 42#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 43#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 44#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 45#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 46#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 47#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 48#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 49#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 50#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 51#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 52#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 53#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 54#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 55#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 58#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 59#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 60#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 61#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 62#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 63#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 64#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 65#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 66#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 67#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 68#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 69#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 70 71/****************************\ 72 GENERIC DRIVER DEFINITIONS 73\****************************/ 74 75#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 76 77#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 78 printk(_level "ath5k %s: " _fmt, \ 79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 80 ##__VA_ARGS__) 81 82#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 83 if (net_ratelimit()) \ 84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 85 } while (0) 86 87#define ATH5K_INFO(_sc, _fmt, ...) \ 88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 89 90#define ATH5K_WARN(_sc, _fmt, ...) \ 91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 92 93#define ATH5K_ERR(_sc, _fmt, ...) \ 94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 95 96/* 97 * AR5K REGISTER ACCESS 98 */ 99 100/* Some macros to read/write fields */ 101 102/* First shift, then mask */ 103#define AR5K_REG_SM(_val, _flags) \ 104 (((_val) << _flags##_S) & (_flags)) 105 106/* First mask, then shift */ 107#define AR5K_REG_MS(_val, _flags) \ 108 (((_val) & (_flags)) >> _flags##_S) 109 110/* Some registers can hold multiple values of interest. For this 111 * reason when we want to write to these registers we must first 112 * retrieve the values which we do not want to clear (lets call this 113 * old_data) and then set the register with this and our new_value: 114 * ( old_data | new_value) */ 115#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 117 (((_val) << _flags##_S) & (_flags)), _reg) 118 119#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 121 (_mask)) | (_flags), _reg) 122 123#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 125 126#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 128 129/* Access to PHY registers */ 130#define AR5K_PHY_READ(ah, _reg) \ 131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 132 133#define AR5K_PHY_WRITE(ah, _reg, _val) \ 134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 135 136/* Access QCU registers per queue */ 137#define AR5K_REG_READ_Q(ah, _reg, _queue) \ 138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 139 140#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 141 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 142 143#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 144 _reg |= 1 << _queue; \ 145} while (0) 146 147#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 148 _reg &= ~(1 << _queue); \ 149} while (0) 150 151/* Used while writing initvals */ 152#define AR5K_REG_WAIT(_i) do { \ 153 if (_i % 64) \ 154 udelay(1); \ 155} while (0) 156 157/* Register dumps are done per operation mode */ 158#define AR5K_INI_RFGAIN_5GHZ 0 159#define AR5K_INI_RFGAIN_2GHZ 1 160 161/* TODO: Clean this up */ 162#define AR5K_INI_VAL_11A 0 163#define AR5K_INI_VAL_11A_TURBO 1 164#define AR5K_INI_VAL_11B 2 165#define AR5K_INI_VAL_11G 3 166#define AR5K_INI_VAL_11G_TURBO 4 167#define AR5K_INI_VAL_XR 0 168#define AR5K_INI_VAL_MAX 5 169 170/* Used for BSSID etc manipulation */ 171#define AR5K_LOW_ID(_a)( \ 172(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ 173) 174 175#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) 176 177/* 178 * Some tuneable values (these should be changeable by the user) 179 * TODO: Make use of them and add more options OR use debug/configfs 180 */ 181#define AR5K_TUNE_DMA_BEACON_RESP 2 182#define AR5K_TUNE_SW_BEACON_RESP 10 183#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 184#define AR5K_TUNE_RADAR_ALERT false 185#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 186#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) 187#define AR5K_TUNE_REGISTER_TIMEOUT 20000 188/* Register for RSSI threshold has a mask of 0xff, so 255 seems to 189 * be the max value. */ 190#define AR5K_TUNE_RSSI_THRES 129 191/* This must be set when setting the RSSI threshold otherwise it can 192 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 193 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 194 * track of it. Max value depends on harware. For AR5210 this is just 7. 195 * For AR5211+ this seems to be up to 255. */ 196#define AR5K_TUNE_BMISS_THRES 7 197#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 198#define AR5K_TUNE_BEACON_INTERVAL 100 199#define AR5K_TUNE_AIFS 2 200#define AR5K_TUNE_AIFS_11B 2 201#define AR5K_TUNE_AIFS_XR 0 202#define AR5K_TUNE_CWMIN 15 203#define AR5K_TUNE_CWMIN_11B 31 204#define AR5K_TUNE_CWMIN_XR 3 205#define AR5K_TUNE_CWMAX 1023 206#define AR5K_TUNE_CWMAX_11B 1023 207#define AR5K_TUNE_CWMAX_XR 7 208#define AR5K_TUNE_NOISE_FLOOR -72 209#define AR5K_TUNE_MAX_TXPOWER 63 210#define AR5K_TUNE_DEFAULT_TXPOWER 25 211#define AR5K_TUNE_TPC_TXPOWER false 212#define AR5K_TUNE_ANT_DIVERSITY true 213#define AR5K_TUNE_HWTXTRIES 4 214 215#define AR5K_INIT_CARR_SENSE_EN 1 216 217/*Swap RX/TX Descriptor for big endian archs*/ 218#if defined(__BIG_ENDIAN) 219#define AR5K_INIT_CFG ( \ 220 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 221) 222#else 223#define AR5K_INIT_CFG 0x00000000 224#endif 225 226/* Initial values */ 227#define AR5K_INIT_CYCRSSI_THR1 2 228#define AR5K_INIT_TX_LATENCY 502 229#define AR5K_INIT_USEC 39 230#define AR5K_INIT_USEC_TURBO 79 231#define AR5K_INIT_USEC_32 31 232#define AR5K_INIT_SLOT_TIME 396 233#define AR5K_INIT_SLOT_TIME_TURBO 480 234#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 235#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 236#define AR5K_INIT_PROG_IFS 920 237#define AR5K_INIT_PROG_IFS_TURBO 960 238#define AR5K_INIT_EIFS 3440 239#define AR5K_INIT_EIFS_TURBO 6880 240#define AR5K_INIT_SIFS 560 241#define AR5K_INIT_SIFS_TURBO 480 242#define AR5K_INIT_SH_RETRY 10 243#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY 244#define AR5K_INIT_SSH_RETRY 32 245#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY 246#define AR5K_INIT_TX_RETRY 10 247 248#define AR5K_INIT_TRANSMIT_LATENCY ( \ 249 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 250 (AR5K_INIT_USEC) \ 251) 252#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ 253 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 254 (AR5K_INIT_USEC_TURBO) \ 255) 256#define AR5K_INIT_PROTO_TIME_CNTRL ( \ 257 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ 258 (AR5K_INIT_PROG_IFS) \ 259) 260#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ 261 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ 262 (AR5K_INIT_PROG_IFS_TURBO) \ 263) 264 265/* token to use for aifs, cwmin, cwmax in MadWiFi */ 266#define AR5K_TXQ_USEDEFAULT ((u32) -1) 267 268/* GENERIC CHIPSET DEFINITIONS */ 269 270/* MAC Chips */ 271enum ath5k_version { 272 AR5K_AR5210 = 0, 273 AR5K_AR5211 = 1, 274 AR5K_AR5212 = 2, 275}; 276 277/* PHY Chips */ 278enum ath5k_radio { 279 AR5K_RF5110 = 0, 280 AR5K_RF5111 = 1, 281 AR5K_RF5112 = 2, 282 AR5K_RF2413 = 3, 283 AR5K_RF5413 = 4, 284 AR5K_RF2316 = 5, 285 AR5K_RF2317 = 6, 286 AR5K_RF2425 = 7, 287}; 288 289/* 290 * Common silicon revision/version values 291 */ 292 293enum ath5k_srev_type { 294 AR5K_VERSION_MAC, 295 AR5K_VERSION_RAD, 296}; 297 298struct ath5k_srev_name { 299 const char *sr_name; 300 enum ath5k_srev_type sr_type; 301 u_int sr_val; 302}; 303 304#define AR5K_SREV_UNKNOWN 0xffff 305 306#define AR5K_SREV_AR5210 0x00 /* Crete */ 307#define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 308#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 309#define AR5K_SREV_AR5311B 0x30 /* Spirit */ 310#define AR5K_SREV_AR5211 0x40 /* Oahu */ 311#define AR5K_SREV_AR5212 0x50 /* Venice */ 312#define AR5K_SREV_AR5213 0x55 /* ??? */ 313#define AR5K_SREV_AR5213A 0x59 /* Hainan */ 314#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 315#define AR5K_SREV_AR2414 0x70 /* Griffin */ 316#define AR5K_SREV_AR5424 0x90 /* Condor */ 317#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 318#define AR5K_SREV_AR5414 0xa0 /* Eagle */ 319#define AR5K_SREV_AR2415 0xb0 /* Talon */ 320#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 321#define AR5K_SREV_AR5418 0xca /* PCI-E */ 322#define AR5K_SREV_AR2425 0xe0 /* Swan */ 323#define AR5K_SREV_AR2417 0xf0 /* Nala */ 324 325#define AR5K_SREV_RAD_5110 0x00 326#define AR5K_SREV_RAD_5111 0x10 327#define AR5K_SREV_RAD_5111A 0x15 328#define AR5K_SREV_RAD_2111 0x20 329#define AR5K_SREV_RAD_5112 0x30 330#define AR5K_SREV_RAD_5112A 0x35 331#define AR5K_SREV_RAD_5112B 0x36 332#define AR5K_SREV_RAD_2112 0x40 333#define AR5K_SREV_RAD_2112A 0x45 334#define AR5K_SREV_RAD_2112B 0x46 335#define AR5K_SREV_RAD_2413 0x50 336#define AR5K_SREV_RAD_5413 0x60 337#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 338#define AR5K_SREV_RAD_2317 0x80 339#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 340#define AR5K_SREV_RAD_2425 0xa2 341#define AR5K_SREV_RAD_5133 0xc0 342 343#define AR5K_SREV_PHY_5211 0x30 344#define AR5K_SREV_PHY_5212 0x41 345#define AR5K_SREV_PHY_5212A 0x42 346#define AR5K_SREV_PHY_5212B 0x43 347#define AR5K_SREV_PHY_2413 0x45 348#define AR5K_SREV_PHY_5413 0x61 349#define AR5K_SREV_PHY_2425 0x70 350 351/* IEEE defs */ 352#define IEEE80211_MAX_LEN 2500 353 354/* TODO add support to mac80211 for vendor-specific rates and modes */ 355 356/* 357 * Some of this information is based on Documentation from: 358 * 359 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG 360 * 361 * Modulation for Atheros' eXtended Range - range enhancing extension that is 362 * supposed to double the distance an Atheros client device can keep a 363 * connection with an Atheros access point. This is achieved by increasing 364 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 365 * the 802.11 specifications demand. In addition, new (proprietary) data rates 366 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 367 * 368 * Please note that can you either use XR or TURBO but you cannot use both, 369 * they are exclusive. 370 * 371 */ 372#define MODULATION_XR 0x00000200 373/* 374 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 375 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 376 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 377 * channels. To use this feature your Access Point must also suport it. 378 * There is also a distinction between "static" and "dynamic" turbo modes: 379 * 380 * - Static: is the dumb version: devices set to this mode stick to it until 381 * the mode is turned off. 382 * - Dynamic: is the intelligent version, the network decides itself if it 383 * is ok to use turbo. As soon as traffic is detected on adjacent channels 384 * (which would get used in turbo mode), or when a non-turbo station joins 385 * the network, turbo mode won't be used until the situation changes again. 386 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 387 * monitors the used radio band in order to decide whether turbo mode may 388 * be used or not. 389 * 390 * This article claims Super G sticks to bonding of channels 5 and 6 for 391 * USA: 392 * 393 * http://www.pcworld.com/article/id,113428-page,1/article.html 394 * 395 * The channel bonding seems to be driver specific though. In addition to 396 * deciding what channels will be used, these "Turbo" modes are accomplished 397 * by also enabling the following features: 398 * 399 * - Bursting: allows multiple frames to be sent at once, rather than pausing 400 * after each frame. Bursting is a standards-compliant feature that can be 401 * used with any Access Point. 402 * - Fast frames: increases the amount of information that can be sent per 403 * frame, also resulting in a reduction of transmission overhead. It is a 404 * proprietary feature that needs to be supported by the Access Point. 405 * - Compression: data frames are compressed in real time using a Lempel Ziv 406 * algorithm. This is done transparently. Once this feature is enabled, 407 * compression and decompression takes place inside the chipset, without 408 * putting additional load on the host CPU. 409 * 410 */ 411#define MODULATION_TURBO 0x00000080 412 413enum ath5k_driver_mode { 414 AR5K_MODE_11A = 0, 415 AR5K_MODE_11A_TURBO = 1, 416 AR5K_MODE_11B = 2, 417 AR5K_MODE_11G = 3, 418 AR5K_MODE_11G_TURBO = 4, 419 AR5K_MODE_XR = 0, 420 AR5K_MODE_MAX = 5 421}; 422 423 424/****************\ 425 TX DEFINITIONS 426\****************/ 427 428/* 429 * TX Status descriptor 430 */ 431struct ath5k_tx_status { 432 u16 ts_seqnum; 433 u16 ts_tstamp; 434 u8 ts_status; 435 u8 ts_rate[4]; 436 u8 ts_retry[4]; 437 u8 ts_final_idx; 438 s8 ts_rssi; 439 u8 ts_shortretry; 440 u8 ts_longretry; 441 u8 ts_virtcol; 442 u8 ts_antenna; 443}; 444 445#define AR5K_TXSTAT_ALTRATE 0x80 446#define AR5K_TXERR_XRETRY 0x01 447#define AR5K_TXERR_FILT 0x02 448#define AR5K_TXERR_FIFO 0x04 449 450/** 451 * enum ath5k_tx_queue - Queue types used to classify tx queues. 452 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 453 * @AR5K_TX_QUEUE_DATA: A normal data queue 454 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 455 * @AR5K_TX_QUEUE_BEACON: The beacon queue 456 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 457 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 458 */ 459enum ath5k_tx_queue { 460 AR5K_TX_QUEUE_INACTIVE = 0, 461 AR5K_TX_QUEUE_DATA, 462 AR5K_TX_QUEUE_XR_DATA, 463 AR5K_TX_QUEUE_BEACON, 464 AR5K_TX_QUEUE_CAB, 465 AR5K_TX_QUEUE_UAPSD, 466}; 467 468#define AR5K_NUM_TX_QUEUES 10 469#define AR5K_NUM_TX_QUEUES_NOQCU 2 470 471/* 472 * Queue syb-types to classify normal data queues. 473 * These are the 4 Access Categories as defined in 474 * WME spec. 0 is the lowest priority and 4 is the 475 * highest. Normal data that hasn't been classified 476 * goes to the Best Effort AC. 477 */ 478enum ath5k_tx_queue_subtype { 479 AR5K_WME_AC_BK = 0, /*Background traffic*/ 480 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 481 AR5K_WME_AC_VI, /*Video traffic*/ 482 AR5K_WME_AC_VO, /*Voice traffic*/ 483}; 484 485/* 486 * Queue ID numbers as returned by the hw functions, each number 487 * represents a hw queue. If hw does not support hw queues 488 * (eg 5210) all data goes in one queue. These match 489 * d80211 definitions (net80211/MadWiFi don't use them). 490 */ 491enum ath5k_tx_queue_id { 492 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 493 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 494 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 495 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ 496 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 497 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 498 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 499 AR5K_TX_QUEUE_ID_UAPSD = 8, 500 AR5K_TX_QUEUE_ID_XR_DATA = 9, 501}; 502 503/* 504 * Flags to set hw queue's parameters... 505 */ 506#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 507#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 508#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 509#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 510#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 511#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 512#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 513#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 514#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 515#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 516#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 517#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 518#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 519#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 520 521/* 522 * A struct to hold tx queue's parameters 523 */ 524struct ath5k_txq_info { 525 enum ath5k_tx_queue tqi_type; 526 enum ath5k_tx_queue_subtype tqi_subtype; 527 u16 tqi_flags; /* Tx queue flags (see above) */ 528 u32 tqi_aifs; /* Arbitrated Interframe Space */ 529 s32 tqi_cw_min; /* Minimum Contention Window */ 530 s32 tqi_cw_max; /* Maximum Contention Window */ 531 u32 tqi_cbr_period; /* Constant bit rate period */ 532 u32 tqi_cbr_overflow_limit; 533 u32 tqi_burst_time; 534 u32 tqi_ready_time; /* Not used */ 535}; 536 537/* 538 * Transmit packet types. 539 * used on tx control descriptor 540 * TODO: Use them inside base.c corectly 541 */ 542enum ath5k_pkt_type { 543 AR5K_PKT_TYPE_NORMAL = 0, 544 AR5K_PKT_TYPE_ATIM = 1, 545 AR5K_PKT_TYPE_PSPOLL = 2, 546 AR5K_PKT_TYPE_BEACON = 3, 547 AR5K_PKT_TYPE_PROBE_RESP = 4, 548 AR5K_PKT_TYPE_PIFS = 5, 549}; 550 551/* 552 * TX power and TPC settings 553 */ 554#define AR5K_TXPOWER_OFDM(_r, _v) ( \ 555 ((0 & 1) << ((_v) + 6)) | \ 556 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 557) 558 559#define AR5K_TXPOWER_CCK(_r, _v) ( \ 560 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 561) 562 563/* 564 * DMA size definitions (2^n+2) 565 */ 566enum ath5k_dmasize { 567 AR5K_DMASIZE_4B = 0, 568 AR5K_DMASIZE_8B, 569 AR5K_DMASIZE_16B, 570 AR5K_DMASIZE_32B, 571 AR5K_DMASIZE_64B, 572 AR5K_DMASIZE_128B, 573 AR5K_DMASIZE_256B, 574 AR5K_DMASIZE_512B 575}; 576 577 578/****************\ 579 RX DEFINITIONS 580\****************/ 581 582/* 583 * RX Status descriptor 584 */ 585struct ath5k_rx_status { 586 u16 rs_datalen; 587 u16 rs_tstamp; 588 u8 rs_status; 589 u8 rs_phyerr; 590 s8 rs_rssi; 591 u8 rs_keyix; 592 u8 rs_rate; 593 u8 rs_antenna; 594 u8 rs_more; 595}; 596 597#define AR5K_RXERR_CRC 0x01 598#define AR5K_RXERR_PHY 0x02 599#define AR5K_RXERR_FIFO 0x04 600#define AR5K_RXERR_DECRYPT 0x08 601#define AR5K_RXERR_MIC 0x10 602#define AR5K_RXKEYIX_INVALID ((u8) - 1) 603#define AR5K_TXKEYIX_INVALID ((u32) - 1) 604 605 606/**************************\ 607 BEACON TIMERS DEFINITIONS 608\**************************/ 609 610#define AR5K_BEACON_PERIOD 0x0000ffff 611#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 612#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 613 614#if 0 615/** 616 * struct ath5k_beacon_state - Per-station beacon timer state. 617 * @bs_interval: in TU's, can also include the above flags 618 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a 619 * Point Coordination Function capable AP 620 */ 621struct ath5k_beacon_state { 622 u32 bs_next_beacon; 623 u32 bs_next_dtim; 624 u32 bs_interval; 625 u8 bs_dtim_period; 626 u8 bs_cfp_period; 627 u16 bs_cfp_max_duration; 628 u16 bs_cfp_du_remain; 629 u16 bs_tim_offset; 630 u16 bs_sleep_duration; 631 u16 bs_bmiss_threshold; 632 u32 bs_cfp_next; 633}; 634#endif 635 636 637/* 638 * TSF to TU conversion: 639 * 640 * TSF is a 64bit value in usec (microseconds). 641 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 642 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 643 */ 644#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 645 646 647/*******************************\ 648 GAIN OPTIMIZATION DEFINITIONS 649\*******************************/ 650 651enum ath5k_rfgain { 652 AR5K_RFGAIN_INACTIVE = 0, 653 AR5K_RFGAIN_ACTIVE, 654 AR5K_RFGAIN_READ_REQUESTED, 655 AR5K_RFGAIN_NEED_CHANGE, 656}; 657 658struct ath5k_gain { 659 u8 g_step_idx; 660 u8 g_current; 661 u8 g_target; 662 u8 g_low; 663 u8 g_high; 664 u8 g_f_corr; 665 u8 g_state; 666}; 667 668/********************\ 669 COMMON DEFINITIONS 670\********************/ 671 672#define AR5K_SLOT_TIME_9 396 673#define AR5K_SLOT_TIME_20 880 674#define AR5K_SLOT_TIME_MAX 0xffff 675 676/* channel_flags */ 677#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 678#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ 679#define CHANNEL_CCK 0x0020 /* CCK channel */ 680#define CHANNEL_OFDM 0x0040 /* OFDM channel */ 681#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 682#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 683#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 684#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 685#define CHANNEL_XR 0x0800 /* XR channel */ 686 687#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 688#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 689#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 690#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 691#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 692#define CHANNEL_108A CHANNEL_T 693#define CHANNEL_108G CHANNEL_TG 694#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 695 696#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ 697 CHANNEL_TURBO) 698 699#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) 700#define CHANNEL_MODES CHANNEL_ALL 701 702/* 703 * Used internaly for reset_tx_queue). 704 * Also see struct struct ieee80211_channel. 705 */ 706#define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0) 707#define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0) 708 709/* 710 * The following structure is used to map 2GHz channels to 711 * 5GHz Atheros channels. 712 * TODO: Clean up 713 */ 714struct ath5k_athchan_2ghz { 715 u32 a2_flags; 716 u16 a2_athchan; 717}; 718 719 720/******************\ 721 RATE DEFINITIONS 722\******************/ 723 724/** 725 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 726 * 727 * The rate code is used to get the RX rate or set the TX rate on the 728 * hardware descriptors. It is also used for internal modulation control 729 * and settings. 730 * 731 * This is the hardware rate map we are aware of: 732 * 733 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 734 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 735 * 736 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 737 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 738 * 739 * rate_code 17 18 19 20 21 22 23 24 740 * rate_kbps ? ? ? ? ? ? ? 11000 741 * 742 * rate_code 25 26 27 28 29 30 31 32 743 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 744 * 745 * "S" indicates CCK rates with short preamble. 746 * 747 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 748 * lowest 4 bits, so they are the same as below with a 0xF mask. 749 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 750 * We handle this in ath5k_setup_bands(). 751 */ 752#define AR5K_MAX_RATES 32 753 754/* B */ 755#define ATH5K_RATE_CODE_1M 0x1B 756#define ATH5K_RATE_CODE_2M 0x1A 757#define ATH5K_RATE_CODE_5_5M 0x19 758#define ATH5K_RATE_CODE_11M 0x18 759/* A and G */ 760#define ATH5K_RATE_CODE_6M 0x0B 761#define ATH5K_RATE_CODE_9M 0x0F 762#define ATH5K_RATE_CODE_12M 0x0A 763#define ATH5K_RATE_CODE_18M 0x0E 764#define ATH5K_RATE_CODE_24M 0x09 765#define ATH5K_RATE_CODE_36M 0x0D 766#define ATH5K_RATE_CODE_48M 0x08 767#define ATH5K_RATE_CODE_54M 0x0C 768/* XR */ 769#define ATH5K_RATE_CODE_XR_500K 0x07 770#define ATH5K_RATE_CODE_XR_1M 0x02 771#define ATH5K_RATE_CODE_XR_2M 0x06 772#define ATH5K_RATE_CODE_XR_3M 0x01 773 774/* adding this flag to rate_code enables short preamble */ 775#define AR5K_SET_SHORT_PREAMBLE 0x04 776 777/* 778 * Crypto definitions 779 */ 780 781#define AR5K_KEYCACHE_SIZE 8 782 783/***********************\ 784 HW RELATED DEFINITIONS 785\***********************/ 786 787/* 788 * Misc definitions 789 */ 790#define AR5K_RSSI_EP_MULTIPLIER (1<<7) 791 792#define AR5K_ASSERT_ENTRY(_e, _s) do { \ 793 if (_e >= _s) \ 794 return (false); \ 795} while (0) 796 797/* 798 * Hardware interrupt abstraction 799 */ 800 801/** 802 * enum ath5k_int - Hardware interrupt masks helpers 803 * 804 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 805 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 806 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 807 * @AR5K_INT_RXNOFRM: No frame received (?) 808 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 809 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 810 * LinkPtr is NULL. For more details, refer to: 811 * http://www.freepatentsonline.com/20030225739.html 812 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 813 * Note that Rx overrun is not always fatal, on some chips we can continue 814 * operation without reseting the card, that's why int_fatal is not 815 * common for all chips. 816 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 817 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 818 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 819 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 820 * We currently do increments on interrupt by 821 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 822 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be 823 * checked. We should do this with ath5k_hw_update_mib_counters() but 824 * it seems we should also then do some noise immunity work. 825 * @AR5K_INT_RXPHY: RX PHY Error 826 * @AR5K_INT_RXKCM: RX Key cache miss 827 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 828 * beacon that must be handled in software. The alternative is if you 829 * have VEOL support, in that case you let the hardware deal with things. 830 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 831 * beacons from the AP have associated with, we should probably try to 832 * reassociate. When in IBSS mode this might mean we have not received 833 * any beacons from any local stations. Note that every station in an 834 * IBSS schedules to send beacons at the Target Beacon Transmission Time 835 * (TBTT) with a random backoff. 836 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 837 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 838 * until properly handled 839 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 840 * errors. These types of errors we can enable seem to be of type 841 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 842 * @AR5K_INT_GLOBAL: Used to clear and set the IER 843 * @AR5K_INT_NOCARD: signals the card has been removed 844 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 845 * bit value 846 * 847 * These are mapped to take advantage of some common bits 848 * between the MACs, to be able to set intr properties 849 * easier. Some of them are not used yet inside hw.c. Most map 850 * to the respective hw interrupt value as they are common amogst different 851 * MACs. 852 */ 853enum ath5k_int { 854 AR5K_INT_RXOK = 0x00000001, 855 AR5K_INT_RXDESC = 0x00000002, 856 AR5K_INT_RXERR = 0x00000004, 857 AR5K_INT_RXNOFRM = 0x00000008, 858 AR5K_INT_RXEOL = 0x00000010, 859 AR5K_INT_RXORN = 0x00000020, 860 AR5K_INT_TXOK = 0x00000040, 861 AR5K_INT_TXDESC = 0x00000080, 862 AR5K_INT_TXERR = 0x00000100, 863 AR5K_INT_TXNOFRM = 0x00000200, 864 AR5K_INT_TXEOL = 0x00000400, 865 AR5K_INT_TXURN = 0x00000800, 866 AR5K_INT_MIB = 0x00001000, 867 AR5K_INT_SWI = 0x00002000, 868 AR5K_INT_RXPHY = 0x00004000, 869 AR5K_INT_RXKCM = 0x00008000, 870 AR5K_INT_SWBA = 0x00010000, 871 AR5K_INT_BRSSI = 0x00020000, 872 AR5K_INT_BMISS = 0x00040000, 873 AR5K_INT_FATAL = 0x00080000, /* Non common */ 874 AR5K_INT_BNR = 0x00100000, /* Non common */ 875 AR5K_INT_TIM = 0x00200000, /* Non common */ 876 AR5K_INT_DTIM = 0x00400000, /* Non common */ 877 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 878 AR5K_INT_GPIO = 0x01000000, 879 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 880 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 881 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 882 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 883 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 884 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 885 AR5K_INT_GLOBAL = 0x80000000, 886 887 AR5K_INT_COMMON = AR5K_INT_RXOK 888 | AR5K_INT_RXDESC 889 | AR5K_INT_RXERR 890 | AR5K_INT_RXNOFRM 891 | AR5K_INT_RXEOL 892 | AR5K_INT_RXORN 893 | AR5K_INT_TXOK 894 | AR5K_INT_TXDESC 895 | AR5K_INT_TXERR 896 | AR5K_INT_TXNOFRM 897 | AR5K_INT_TXEOL 898 | AR5K_INT_TXURN 899 | AR5K_INT_MIB 900 | AR5K_INT_SWI 901 | AR5K_INT_RXPHY 902 | AR5K_INT_RXKCM 903 | AR5K_INT_SWBA 904 | AR5K_INT_BRSSI 905 | AR5K_INT_BMISS 906 | AR5K_INT_GPIO 907 | AR5K_INT_GLOBAL, 908 909 AR5K_INT_NOCARD = 0xffffffff 910}; 911 912/* 913 * Power management 914 */ 915enum ath5k_power_mode { 916 AR5K_PM_UNDEFINED = 0, 917 AR5K_PM_AUTO, 918 AR5K_PM_AWAKE, 919 AR5K_PM_FULL_SLEEP, 920 AR5K_PM_NETWORK_SLEEP, 921}; 922 923/* 924 * These match net80211 definitions (not used in 925 * mac80211). 926 * TODO: Clean this up 927 */ 928#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 929#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 930#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 931#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 932#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 933 934/* GPIO-controlled software LED */ 935#define AR5K_SOFTLED_PIN 0 936#define AR5K_SOFTLED_ON 0 937#define AR5K_SOFTLED_OFF 1 938 939/* 940 * Chipset capabilities -see ath5k_hw_get_capability- 941 * get_capability function is not yet fully implemented 942 * in ath5k so most of these don't work yet... 943 * TODO: Implement these & merge with _TUNE_ stuff above 944 */ 945enum ath5k_capability_type { 946 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 947 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 948 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 949 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 950 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 951 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 952 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 953 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 954 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 955 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 956 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 957 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 958 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 959 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 960 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 961 AR5K_CAP_XR = 16, /* Supports XR mode */ 962 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 963 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 964 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 965 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 966}; 967 968 969/* XXX: we *may* move cap_range stuff to struct wiphy */ 970struct ath5k_capabilities { 971 /* 972 * Supported PHY modes 973 * (ie. CHANNEL_A, CHANNEL_B, ...) 974 */ 975 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 976 977 /* 978 * Frequency range (without regulation restrictions) 979 */ 980 struct { 981 u16 range_2ghz_min; 982 u16 range_2ghz_max; 983 u16 range_5ghz_min; 984 u16 range_5ghz_max; 985 } cap_range; 986 987 /* 988 * Values stored in the EEPROM (some of them...) 989 */ 990 struct ath5k_eeprom_info cap_eeprom; 991 992 /* 993 * Queue information 994 */ 995 struct { 996 u8 q_tx_num; 997 } cap_queues; 998}; 999 1000 1001/***************************************\ 1002 HARDWARE ABSTRACTION LAYER STRUCTURE 1003\***************************************/ 1004 1005/* 1006 * Misc defines 1007 */ 1008 1009#define AR5K_MAX_GPIO 10 1010#define AR5K_MAX_RF_BANKS 8 1011 1012/* TODO: Clean up and merge with ath5k_softc */ 1013struct ath5k_hw { 1014 u32 ah_magic; 1015 1016 struct ath5k_softc *ah_sc; 1017 void __iomem *ah_iobase; 1018 1019 enum ath5k_int ah_imr; 1020 1021 enum nl80211_iftype ah_op_mode; 1022 enum ath5k_power_mode ah_power_mode; 1023 struct ieee80211_channel ah_current_channel; 1024 bool ah_turbo; 1025 bool ah_calibration; 1026 bool ah_running; 1027 bool ah_single_chip; 1028 bool ah_combined_mic; 1029 1030 u32 ah_mac_srev; 1031 u16 ah_mac_version; 1032 u16 ah_mac_revision; 1033 u16 ah_phy_revision; 1034 u16 ah_radio_5ghz_revision; 1035 u16 ah_radio_2ghz_revision; 1036 1037 enum ath5k_version ah_version; 1038 enum ath5k_radio ah_radio; 1039 u32 ah_phy; 1040 1041 bool ah_5ghz; 1042 bool ah_2ghz; 1043 1044#define ah_modes ah_capabilities.cap_mode 1045#define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1046 1047 u32 ah_atim_window; 1048 u32 ah_aifs; 1049 u32 ah_cw_min; 1050 u32 ah_cw_max; 1051 bool ah_software_retry; 1052 u32 ah_limit_tx_retries; 1053 1054 u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1055 bool ah_ant_diversity; 1056 1057 u8 ah_sta_id[ETH_ALEN]; 1058 1059 /* Current BSSID we are trying to assoc to / create. 1060 * This is passed by mac80211 on config_interface() and cached here for 1061 * use in resets */ 1062 u8 ah_bssid[ETH_ALEN]; 1063 u8 ah_bssid_mask[ETH_ALEN]; 1064 1065 u32 ah_gpio[AR5K_MAX_GPIO]; 1066 int ah_gpio_npins; 1067 1068 struct ath_regulatory ah_regulatory; 1069 struct ath5k_capabilities ah_capabilities; 1070 1071 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1072 u32 ah_txq_status; 1073 u32 ah_txq_imr_txok; 1074 u32 ah_txq_imr_txerr; 1075 u32 ah_txq_imr_txurn; 1076 u32 ah_txq_imr_txdesc; 1077 u32 ah_txq_imr_txeol; 1078 u32 ah_txq_imr_cbrorn; 1079 u32 ah_txq_imr_cbrurn; 1080 u32 ah_txq_imr_qtrig; 1081 u32 ah_txq_imr_nofrm; 1082 u32 ah_txq_isr; 1083 u32 *ah_rf_banks; 1084 size_t ah_rf_banks_size; 1085 size_t ah_rf_regs_count; 1086 struct ath5k_gain ah_gain; 1087 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1088 1089 1090 struct { 1091 /* Temporary tables used for interpolation */ 1092 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1093 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1094 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1095 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1096 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1097 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1098 u8 txp_min_idx; 1099 bool txp_tpc; 1100 /* Values in 0.25dB units */ 1101 s16 txp_min_pwr; 1102 s16 txp_max_pwr; 1103 /* Values in 0.5dB units */ 1104 s16 txp_offset; 1105 s16 txp_ofdm; 1106 s16 txp_cck_ofdm_gainf_delta; 1107 /* Value in dB units */ 1108 s16 txp_cck_ofdm_pwr_delta; 1109 } ah_txpower; 1110 1111 struct { 1112 bool r_enabled; 1113 int r_last_alert; 1114 struct ieee80211_channel r_last_channel; 1115 } ah_radar; 1116 1117 /* noise floor from last periodic calibration */ 1118 s32 ah_noise_floor; 1119 1120 /* 1121 * Function pointers 1122 */ 1123 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc, 1124 u32 size, unsigned int flags); 1125 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1126 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int, 1127 unsigned int, unsigned int, unsigned int, unsigned int, 1128 unsigned int, unsigned int, unsigned int); 1129 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1130 unsigned int, unsigned int, unsigned int, unsigned int, 1131 unsigned int, unsigned int); 1132 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1133 struct ath5k_tx_status *); 1134 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1135 struct ath5k_rx_status *); 1136}; 1137 1138/* 1139 * Prototypes 1140 */ 1141 1142/* Attach/Detach Functions */ 1143extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version); 1144extern void ath5k_hw_detach(struct ath5k_hw *ah); 1145 1146/* LED functions */ 1147extern int ath5k_init_leds(struct ath5k_softc *sc); 1148extern void ath5k_led_enable(struct ath5k_softc *sc); 1149extern void ath5k_led_off(struct ath5k_softc *sc); 1150extern void ath5k_unregister_leds(struct ath5k_softc *sc); 1151 1152/* Reset Functions */ 1153extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1154extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel); 1155/* Power management functions */ 1156extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration); 1157 1158/* DMA Related Functions */ 1159extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1160extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah); 1161extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1162extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1163extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1164extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1165extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1166extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1167 u32 phys_addr); 1168extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1169/* Interrupt handling */ 1170extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1171extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1172extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum 1173ath5k_int new_mask); 1174extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats); 1175 1176/* EEPROM access functions */ 1177extern int ath5k_eeprom_init(struct ath5k_hw *ah); 1178extern void ath5k_eeprom_detach(struct ath5k_hw *ah); 1179extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1180extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah); 1181 1182/* Protocol Control Unit Functions */ 1183extern int ath5k_hw_set_opmode(struct ath5k_hw *ah); 1184/* BSSID Functions */ 1185extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac); 1186extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1187extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id); 1188extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1189/* Receive start/stop functions */ 1190extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1191extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1192/* RX Filter functions */ 1193extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1194extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index); 1195extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index); 1196extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1197extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1198/* Beacon control functions */ 1199extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah); 1200extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1201extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1202extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1203extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1204#if 0 1205extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state); 1206extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah); 1207extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr); 1208#endif 1209/* ACK bit rate */ 1210void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high); 1211/* ACK/CTS Timeouts */ 1212extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout); 1213extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah); 1214extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout); 1215extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah); 1216/* Key table (WEP) functions */ 1217extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry); 1218extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry); 1219extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac); 1220extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac); 1221 1222/* Queue Control Unit, DFS Control Unit Functions */ 1223extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info); 1224extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1225 const struct ath5k_txq_info *queue_info); 1226extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1227 enum ath5k_tx_queue queue_type, 1228 struct ath5k_txq_info *queue_info); 1229extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1230extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1231extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1232extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah); 1233extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time); 1234 1235/* Hardware Descriptor Functions */ 1236extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1237 1238/* GPIO Functions */ 1239extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1240extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1241extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1242extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1243extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1244extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level); 1245 1246/* Misc functions */ 1247int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1248extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result); 1249extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1250extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1251 1252/* Initial register settings functions */ 1253extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1254 1255/* Initialize RF */ 1256extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 1257 struct ieee80211_channel *channel, 1258 unsigned int mode); 1259extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq); 1260extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1261extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1262/* PHY/RF channel functions */ 1263extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1264extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1265/* PHY calibration */ 1266extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1267extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq); 1268/* Misc PHY functions */ 1269extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1270extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant); 1271extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah); 1272extern int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1273/* TX power setup */ 1274extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower); 1275extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1276 1277/* 1278 * Functions used internaly 1279 */ 1280 1281/* 1282 * Translate usec to hw clock units 1283 * TODO: Half/quarter rate 1284 */ 1285static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) 1286{ 1287 return turbo ? (usec * 80) : (usec * 40); 1288} 1289 1290/* 1291 * Translate hw clock units to usec 1292 * TODO: Half/quarter rate 1293 */ 1294static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) 1295{ 1296 return turbo ? (clock / 80) : (clock / 40); 1297} 1298 1299/* 1300 * Read from a register 1301 */ 1302static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1303{ 1304 return ioread32(ah->ah_iobase + reg); 1305} 1306 1307/* 1308 * Write to a register 1309 */ 1310static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1311{ 1312 iowrite32(val, ah->ah_iobase + reg); 1313} 1314 1315#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY) 1316/* 1317 * Check if a register write has been completed 1318 */ 1319static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, 1320 u32 val, bool is_set) 1321{ 1322 int i; 1323 u32 data; 1324 1325 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 1326 data = ath5k_hw_reg_read(ah, reg); 1327 if (is_set && (data & flag)) 1328 break; 1329 else if ((data & flag) == val) 1330 break; 1331 udelay(15); 1332 } 1333 1334 return (i <= 0) ? -EAGAIN : 0; 1335} 1336#endif 1337 1338static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1339{ 1340 u32 retval = 0, bit, i; 1341 1342 for (i = 0; i < bits; i++) { 1343 bit = (val >> i) & 1; 1344 retval = (retval << 1) | bit; 1345 } 1346 1347 return retval; 1348} 1349 1350static inline int ath5k_pad_size(int hdrlen) 1351{ 1352 return (hdrlen < 24) ? 0 : hdrlen & 3; 1353} 1354 1355#endif 1356