ath5k.h revision eef39befaae2a1559efe197d795c376a317af2af
1/* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _ATH5K_H 19#define _ATH5K_H 20 21/* TODO: Clean up channel debuging -doesn't work anyway- and start 22 * working on reg. control code using all available eeprom information 23 * -rev. engineering needed- */ 24#define CHAN_DEBUG 0 25 26#include <linux/io.h> 27#include <linux/types.h> 28#include <linux/average.h> 29#include <net/mac80211.h> 30 31/* RX/TX descriptor hw structs 32 * TODO: Driver part should only see sw structs */ 33#include "desc.h" 34 35/* EEPROM structs/offsets 36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 37 * and clean up common bits, then introduce set/get functions in eeprom.c */ 38#include "eeprom.h" 39#include "../ath.h" 40 41/* PCI IDs */ 42#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 43#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 44#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 45#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 46#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 47#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 48#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 49#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 50#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 51#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 52#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 53#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 54#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 55#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 58#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 59#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 60#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 61#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 62#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 63#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 64#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 65#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 66#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 67#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 68#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 69#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 70 71/****************************\ 72 GENERIC DRIVER DEFINITIONS 73\****************************/ 74 75#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 76 77#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 78 printk(_level "ath5k %s: " _fmt, \ 79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 80 ##__VA_ARGS__) 81 82#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 83 if (net_ratelimit()) \ 84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 85 } while (0) 86 87#define ATH5K_INFO(_sc, _fmt, ...) \ 88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 89 90#define ATH5K_WARN(_sc, _fmt, ...) \ 91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 92 93#define ATH5K_ERR(_sc, _fmt, ...) \ 94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 95 96/* 97 * AR5K REGISTER ACCESS 98 */ 99 100/* Some macros to read/write fields */ 101 102/* First shift, then mask */ 103#define AR5K_REG_SM(_val, _flags) \ 104 (((_val) << _flags##_S) & (_flags)) 105 106/* First mask, then shift */ 107#define AR5K_REG_MS(_val, _flags) \ 108 (((_val) & (_flags)) >> _flags##_S) 109 110/* Some registers can hold multiple values of interest. For this 111 * reason when we want to write to these registers we must first 112 * retrieve the values which we do not want to clear (lets call this 113 * old_data) and then set the register with this and our new_value: 114 * ( old_data | new_value) */ 115#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 117 (((_val) << _flags##_S) & (_flags)), _reg) 118 119#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 121 (_mask)) | (_flags), _reg) 122 123#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 125 126#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 128 129/* Access to PHY registers */ 130#define AR5K_PHY_READ(ah, _reg) \ 131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 132 133#define AR5K_PHY_WRITE(ah, _reg, _val) \ 134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 135 136/* Access QCU registers per queue */ 137#define AR5K_REG_READ_Q(ah, _reg, _queue) \ 138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 139 140#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 141 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 142 143#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 144 _reg |= 1 << _queue; \ 145} while (0) 146 147#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 148 _reg &= ~(1 << _queue); \ 149} while (0) 150 151/* Used while writing initvals */ 152#define AR5K_REG_WAIT(_i) do { \ 153 if (_i % 64) \ 154 udelay(1); \ 155} while (0) 156 157/* Register dumps are done per operation mode */ 158#define AR5K_INI_RFGAIN_5GHZ 0 159#define AR5K_INI_RFGAIN_2GHZ 1 160 161/* TODO: Clean this up */ 162#define AR5K_INI_VAL_11A 0 163#define AR5K_INI_VAL_11A_TURBO 1 164#define AR5K_INI_VAL_11B 2 165#define AR5K_INI_VAL_11G 3 166#define AR5K_INI_VAL_11G_TURBO 4 167#define AR5K_INI_VAL_XR 0 168#define AR5K_INI_VAL_MAX 5 169 170/* 171 * Some tuneable values (these should be changeable by the user) 172 * TODO: Make use of them and add more options OR use debug/configfs 173 */ 174#define AR5K_TUNE_DMA_BEACON_RESP 2 175#define AR5K_TUNE_SW_BEACON_RESP 10 176#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 177#define AR5K_TUNE_RADAR_ALERT false 178#define AR5K_TUNE_MIN_TX_FIFO_THRES 1 179#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1) 180#define AR5K_TUNE_REGISTER_TIMEOUT 20000 181/* Register for RSSI threshold has a mask of 0xff, so 255 seems to 182 * be the max value. */ 183#define AR5K_TUNE_RSSI_THRES 129 184/* This must be set when setting the RSSI threshold otherwise it can 185 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 186 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 187 * track of it. Max value depends on harware. For AR5210 this is just 7. 188 * For AR5211+ this seems to be up to 255. */ 189#define AR5K_TUNE_BMISS_THRES 7 190#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 191#define AR5K_TUNE_BEACON_INTERVAL 100 192#define AR5K_TUNE_AIFS 2 193#define AR5K_TUNE_AIFS_11B 2 194#define AR5K_TUNE_AIFS_XR 0 195#define AR5K_TUNE_CWMIN 15 196#define AR5K_TUNE_CWMIN_11B 31 197#define AR5K_TUNE_CWMIN_XR 3 198#define AR5K_TUNE_CWMAX 1023 199#define AR5K_TUNE_CWMAX_11B 1023 200#define AR5K_TUNE_CWMAX_XR 7 201#define AR5K_TUNE_NOISE_FLOOR -72 202#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 203#define AR5K_TUNE_MAX_TXPOWER 63 204#define AR5K_TUNE_DEFAULT_TXPOWER 25 205#define AR5K_TUNE_TPC_TXPOWER false 206#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ 207#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ 208#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ 209 210#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */ 211 212#define AR5K_INIT_CARR_SENSE_EN 1 213 214/*Swap RX/TX Descriptor for big endian archs*/ 215#if defined(__BIG_ENDIAN) 216#define AR5K_INIT_CFG ( \ 217 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 218) 219#else 220#define AR5K_INIT_CFG 0x00000000 221#endif 222 223/* Initial values */ 224#define AR5K_INIT_CYCRSSI_THR1 2 225#define AR5K_INIT_TX_LATENCY 502 226#define AR5K_INIT_USEC 39 227#define AR5K_INIT_USEC_TURBO 79 228#define AR5K_INIT_USEC_32 31 229#define AR5K_INIT_SLOT_TIME 396 230#define AR5K_INIT_SLOT_TIME_TURBO 480 231#define AR5K_INIT_ACK_CTS_TIMEOUT 1024 232#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 233#define AR5K_INIT_PROG_IFS 920 234#define AR5K_INIT_PROG_IFS_TURBO 960 235#define AR5K_INIT_EIFS 3440 236#define AR5K_INIT_EIFS_TURBO 6880 237#define AR5K_INIT_SIFS 560 238#define AR5K_INIT_SIFS_TURBO 480 239#define AR5K_INIT_SH_RETRY 10 240#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY 241#define AR5K_INIT_SSH_RETRY 32 242#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY 243#define AR5K_INIT_TX_RETRY 10 244 245#define AR5K_INIT_TRANSMIT_LATENCY ( \ 246 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 247 (AR5K_INIT_USEC) \ 248) 249#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ 250 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 251 (AR5K_INIT_USEC_TURBO) \ 252) 253#define AR5K_INIT_PROTO_TIME_CNTRL ( \ 254 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ 255 (AR5K_INIT_PROG_IFS) \ 256) 257#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ 258 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ 259 (AR5K_INIT_PROG_IFS_TURBO) \ 260) 261 262 263/* GENERIC CHIPSET DEFINITIONS */ 264 265/* MAC Chips */ 266enum ath5k_version { 267 AR5K_AR5210 = 0, 268 AR5K_AR5211 = 1, 269 AR5K_AR5212 = 2, 270}; 271 272/* PHY Chips */ 273enum ath5k_radio { 274 AR5K_RF5110 = 0, 275 AR5K_RF5111 = 1, 276 AR5K_RF5112 = 2, 277 AR5K_RF2413 = 3, 278 AR5K_RF5413 = 4, 279 AR5K_RF2316 = 5, 280 AR5K_RF2317 = 6, 281 AR5K_RF2425 = 7, 282}; 283 284/* 285 * Common silicon revision/version values 286 */ 287 288enum ath5k_srev_type { 289 AR5K_VERSION_MAC, 290 AR5K_VERSION_RAD, 291}; 292 293struct ath5k_srev_name { 294 const char *sr_name; 295 enum ath5k_srev_type sr_type; 296 u_int sr_val; 297}; 298 299#define AR5K_SREV_UNKNOWN 0xffff 300 301#define AR5K_SREV_AR5210 0x00 /* Crete */ 302#define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 303#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 304#define AR5K_SREV_AR5311B 0x30 /* Spirit */ 305#define AR5K_SREV_AR5211 0x40 /* Oahu */ 306#define AR5K_SREV_AR5212 0x50 /* Venice */ 307#define AR5K_SREV_AR5212_V4 0x54 /* ??? */ 308#define AR5K_SREV_AR5213 0x55 /* ??? */ 309#define AR5K_SREV_AR5213A 0x59 /* Hainan */ 310#define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 311#define AR5K_SREV_AR2414 0x70 /* Griffin */ 312#define AR5K_SREV_AR5424 0x90 /* Condor */ 313#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 314#define AR5K_SREV_AR5414 0xa0 /* Eagle */ 315#define AR5K_SREV_AR2415 0xb0 /* Talon */ 316#define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 317#define AR5K_SREV_AR5418 0xca /* PCI-E */ 318#define AR5K_SREV_AR2425 0xe0 /* Swan */ 319#define AR5K_SREV_AR2417 0xf0 /* Nala */ 320 321#define AR5K_SREV_RAD_5110 0x00 322#define AR5K_SREV_RAD_5111 0x10 323#define AR5K_SREV_RAD_5111A 0x15 324#define AR5K_SREV_RAD_2111 0x20 325#define AR5K_SREV_RAD_5112 0x30 326#define AR5K_SREV_RAD_5112A 0x35 327#define AR5K_SREV_RAD_5112B 0x36 328#define AR5K_SREV_RAD_2112 0x40 329#define AR5K_SREV_RAD_2112A 0x45 330#define AR5K_SREV_RAD_2112B 0x46 331#define AR5K_SREV_RAD_2413 0x50 332#define AR5K_SREV_RAD_5413 0x60 333#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 334#define AR5K_SREV_RAD_2317 0x80 335#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 336#define AR5K_SREV_RAD_2425 0xa2 337#define AR5K_SREV_RAD_5133 0xc0 338 339#define AR5K_SREV_PHY_5211 0x30 340#define AR5K_SREV_PHY_5212 0x41 341#define AR5K_SREV_PHY_5212A 0x42 342#define AR5K_SREV_PHY_5212B 0x43 343#define AR5K_SREV_PHY_2413 0x45 344#define AR5K_SREV_PHY_5413 0x61 345#define AR5K_SREV_PHY_2425 0x70 346 347/* TODO add support to mac80211 for vendor-specific rates and modes */ 348 349/* 350 * Some of this information is based on Documentation from: 351 * 352 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 353 * 354 * Modulation for Atheros' eXtended Range - range enhancing extension that is 355 * supposed to double the distance an Atheros client device can keep a 356 * connection with an Atheros access point. This is achieved by increasing 357 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 358 * the 802.11 specifications demand. In addition, new (proprietary) data rates 359 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 360 * 361 * Please note that can you either use XR or TURBO but you cannot use both, 362 * they are exclusive. 363 * 364 */ 365#define MODULATION_XR 0x00000200 366/* 367 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 368 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 369 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 370 * channels. To use this feature your Access Point must also suport it. 371 * There is also a distinction between "static" and "dynamic" turbo modes: 372 * 373 * - Static: is the dumb version: devices set to this mode stick to it until 374 * the mode is turned off. 375 * - Dynamic: is the intelligent version, the network decides itself if it 376 * is ok to use turbo. As soon as traffic is detected on adjacent channels 377 * (which would get used in turbo mode), or when a non-turbo station joins 378 * the network, turbo mode won't be used until the situation changes again. 379 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 380 * monitors the used radio band in order to decide whether turbo mode may 381 * be used or not. 382 * 383 * This article claims Super G sticks to bonding of channels 5 and 6 for 384 * USA: 385 * 386 * http://www.pcworld.com/article/id,113428-page,1/article.html 387 * 388 * The channel bonding seems to be driver specific though. In addition to 389 * deciding what channels will be used, these "Turbo" modes are accomplished 390 * by also enabling the following features: 391 * 392 * - Bursting: allows multiple frames to be sent at once, rather than pausing 393 * after each frame. Bursting is a standards-compliant feature that can be 394 * used with any Access Point. 395 * - Fast frames: increases the amount of information that can be sent per 396 * frame, also resulting in a reduction of transmission overhead. It is a 397 * proprietary feature that needs to be supported by the Access Point. 398 * - Compression: data frames are compressed in real time using a Lempel Ziv 399 * algorithm. This is done transparently. Once this feature is enabled, 400 * compression and decompression takes place inside the chipset, without 401 * putting additional load on the host CPU. 402 * 403 */ 404#define MODULATION_TURBO 0x00000080 405 406enum ath5k_driver_mode { 407 AR5K_MODE_11A = 0, 408 AR5K_MODE_11A_TURBO = 1, 409 AR5K_MODE_11B = 2, 410 AR5K_MODE_11G = 3, 411 AR5K_MODE_11G_TURBO = 4, 412 AR5K_MODE_XR = 0, 413 AR5K_MODE_MAX = 5 414}; 415 416enum ath5k_ant_mode { 417 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 418 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 419 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 420 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 421 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 422 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 423 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 424 AR5K_ANTMODE_MAX, 425}; 426 427 428/****************\ 429 TX DEFINITIONS 430\****************/ 431 432/* 433 * TX Status descriptor 434 */ 435struct ath5k_tx_status { 436 u16 ts_seqnum; 437 u16 ts_tstamp; 438 u8 ts_status; 439 u8 ts_rate[4]; 440 u8 ts_retry[4]; 441 u8 ts_final_idx; 442 s8 ts_rssi; 443 u8 ts_shortretry; 444 u8 ts_longretry; 445 u8 ts_virtcol; 446 u8 ts_antenna; 447}; 448 449#define AR5K_TXSTAT_ALTRATE 0x80 450#define AR5K_TXERR_XRETRY 0x01 451#define AR5K_TXERR_FILT 0x02 452#define AR5K_TXERR_FIFO 0x04 453 454/** 455 * enum ath5k_tx_queue - Queue types used to classify tx queues. 456 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 457 * @AR5K_TX_QUEUE_DATA: A normal data queue 458 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 459 * @AR5K_TX_QUEUE_BEACON: The beacon queue 460 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 461 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 462 */ 463enum ath5k_tx_queue { 464 AR5K_TX_QUEUE_INACTIVE = 0, 465 AR5K_TX_QUEUE_DATA, 466 AR5K_TX_QUEUE_XR_DATA, 467 AR5K_TX_QUEUE_BEACON, 468 AR5K_TX_QUEUE_CAB, 469 AR5K_TX_QUEUE_UAPSD, 470}; 471 472#define AR5K_NUM_TX_QUEUES 10 473#define AR5K_NUM_TX_QUEUES_NOQCU 2 474 475/* 476 * Queue syb-types to classify normal data queues. 477 * These are the 4 Access Categories as defined in 478 * WME spec. 0 is the lowest priority and 4 is the 479 * highest. Normal data that hasn't been classified 480 * goes to the Best Effort AC. 481 */ 482enum ath5k_tx_queue_subtype { 483 AR5K_WME_AC_BK = 0, /*Background traffic*/ 484 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 485 AR5K_WME_AC_VI, /*Video traffic*/ 486 AR5K_WME_AC_VO, /*Voice traffic*/ 487}; 488 489/* 490 * Queue ID numbers as returned by the hw functions, each number 491 * represents a hw queue. If hw does not support hw queues 492 * (eg 5210) all data goes in one queue. These match 493 * d80211 definitions (net80211/MadWiFi don't use them). 494 */ 495enum ath5k_tx_queue_id { 496 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 497 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 498 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 499 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ 500 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 501 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 502 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 503 AR5K_TX_QUEUE_ID_UAPSD = 8, 504 AR5K_TX_QUEUE_ID_XR_DATA = 9, 505}; 506 507/* 508 * Flags to set hw queue's parameters... 509 */ 510#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 511#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 512#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 513#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 514#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 515#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 516#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 517#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 518#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 519#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 520#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 521#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 522#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 523#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 524 525/* 526 * A struct to hold tx queue's parameters 527 */ 528struct ath5k_txq_info { 529 enum ath5k_tx_queue tqi_type; 530 enum ath5k_tx_queue_subtype tqi_subtype; 531 u16 tqi_flags; /* Tx queue flags (see above) */ 532 u8 tqi_aifs; /* Arbitrated Interframe Space */ 533 u16 tqi_cw_min; /* Minimum Contention Window */ 534 u16 tqi_cw_max; /* Maximum Contention Window */ 535 u32 tqi_cbr_period; /* Constant bit rate period */ 536 u32 tqi_cbr_overflow_limit; 537 u32 tqi_burst_time; 538 u32 tqi_ready_time; /* Time queue waits after an event */ 539}; 540 541/* 542 * Transmit packet types. 543 * used on tx control descriptor 544 */ 545enum ath5k_pkt_type { 546 AR5K_PKT_TYPE_NORMAL = 0, 547 AR5K_PKT_TYPE_ATIM = 1, 548 AR5K_PKT_TYPE_PSPOLL = 2, 549 AR5K_PKT_TYPE_BEACON = 3, 550 AR5K_PKT_TYPE_PROBE_RESP = 4, 551 AR5K_PKT_TYPE_PIFS = 5, 552}; 553 554/* 555 * TX power and TPC settings 556 */ 557#define AR5K_TXPOWER_OFDM(_r, _v) ( \ 558 ((0 & 1) << ((_v) + 6)) | \ 559 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 560) 561 562#define AR5K_TXPOWER_CCK(_r, _v) ( \ 563 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 564) 565 566/* 567 * DMA size definitions (2^(n+2)) 568 */ 569enum ath5k_dmasize { 570 AR5K_DMASIZE_4B = 0, 571 AR5K_DMASIZE_8B, 572 AR5K_DMASIZE_16B, 573 AR5K_DMASIZE_32B, 574 AR5K_DMASIZE_64B, 575 AR5K_DMASIZE_128B, 576 AR5K_DMASIZE_256B, 577 AR5K_DMASIZE_512B 578}; 579 580 581/****************\ 582 RX DEFINITIONS 583\****************/ 584 585/* 586 * RX Status descriptor 587 */ 588struct ath5k_rx_status { 589 u16 rs_datalen; 590 u16 rs_tstamp; 591 u8 rs_status; 592 u8 rs_phyerr; 593 s8 rs_rssi; 594 u8 rs_keyix; 595 u8 rs_rate; 596 u8 rs_antenna; 597 u8 rs_more; 598}; 599 600#define AR5K_RXERR_CRC 0x01 601#define AR5K_RXERR_PHY 0x02 602#define AR5K_RXERR_FIFO 0x04 603#define AR5K_RXERR_DECRYPT 0x08 604#define AR5K_RXERR_MIC 0x10 605#define AR5K_RXKEYIX_INVALID ((u8) - 1) 606#define AR5K_TXKEYIX_INVALID ((u32) - 1) 607 608 609/**************************\ 610 BEACON TIMERS DEFINITIONS 611\**************************/ 612 613#define AR5K_BEACON_PERIOD 0x0000ffff 614#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 615#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 616 617 618/* 619 * TSF to TU conversion: 620 * 621 * TSF is a 64bit value in usec (microseconds). 622 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 623 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 624 */ 625#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 626 627 628/*******************************\ 629 GAIN OPTIMIZATION DEFINITIONS 630\*******************************/ 631 632enum ath5k_rfgain { 633 AR5K_RFGAIN_INACTIVE = 0, 634 AR5K_RFGAIN_ACTIVE, 635 AR5K_RFGAIN_READ_REQUESTED, 636 AR5K_RFGAIN_NEED_CHANGE, 637}; 638 639struct ath5k_gain { 640 u8 g_step_idx; 641 u8 g_current; 642 u8 g_target; 643 u8 g_low; 644 u8 g_high; 645 u8 g_f_corr; 646 u8 g_state; 647}; 648 649/********************\ 650 COMMON DEFINITIONS 651\********************/ 652 653#define AR5K_SLOT_TIME_9 396 654#define AR5K_SLOT_TIME_20 880 655#define AR5K_SLOT_TIME_MAX 0xffff 656 657/* channel_flags */ 658#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 659#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ 660#define CHANNEL_CCK 0x0020 /* CCK channel */ 661#define CHANNEL_OFDM 0x0040 /* OFDM channel */ 662#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 663#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 664#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 665#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 666#define CHANNEL_XR 0x0800 /* XR channel */ 667 668#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 669#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 670#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 671#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 672#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 673#define CHANNEL_108A CHANNEL_T 674#define CHANNEL_108G CHANNEL_TG 675#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 676 677#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ 678 CHANNEL_TURBO) 679 680#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) 681#define CHANNEL_MODES CHANNEL_ALL 682 683/* 684 * Used internaly for reset_tx_queue). 685 * Also see struct struct ieee80211_channel. 686 */ 687#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 688#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) 689 690/* 691 * The following structure is used to map 2GHz channels to 692 * 5GHz Atheros channels. 693 * TODO: Clean up 694 */ 695struct ath5k_athchan_2ghz { 696 u32 a2_flags; 697 u16 a2_athchan; 698}; 699 700 701/******************\ 702 RATE DEFINITIONS 703\******************/ 704 705/** 706 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 707 * 708 * The rate code is used to get the RX rate or set the TX rate on the 709 * hardware descriptors. It is also used for internal modulation control 710 * and settings. 711 * 712 * This is the hardware rate map we are aware of: 713 * 714 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 715 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 716 * 717 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 718 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 719 * 720 * rate_code 17 18 19 20 21 22 23 24 721 * rate_kbps ? ? ? ? ? ? ? 11000 722 * 723 * rate_code 25 26 27 28 29 30 31 32 724 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 725 * 726 * "S" indicates CCK rates with short preamble. 727 * 728 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 729 * lowest 4 bits, so they are the same as below with a 0xF mask. 730 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 731 * We handle this in ath5k_setup_bands(). 732 */ 733#define AR5K_MAX_RATES 32 734 735/* B */ 736#define ATH5K_RATE_CODE_1M 0x1B 737#define ATH5K_RATE_CODE_2M 0x1A 738#define ATH5K_RATE_CODE_5_5M 0x19 739#define ATH5K_RATE_CODE_11M 0x18 740/* A and G */ 741#define ATH5K_RATE_CODE_6M 0x0B 742#define ATH5K_RATE_CODE_9M 0x0F 743#define ATH5K_RATE_CODE_12M 0x0A 744#define ATH5K_RATE_CODE_18M 0x0E 745#define ATH5K_RATE_CODE_24M 0x09 746#define ATH5K_RATE_CODE_36M 0x0D 747#define ATH5K_RATE_CODE_48M 0x08 748#define ATH5K_RATE_CODE_54M 0x0C 749/* XR */ 750#define ATH5K_RATE_CODE_XR_500K 0x07 751#define ATH5K_RATE_CODE_XR_1M 0x02 752#define ATH5K_RATE_CODE_XR_2M 0x06 753#define ATH5K_RATE_CODE_XR_3M 0x01 754 755/* adding this flag to rate_code enables short preamble */ 756#define AR5K_SET_SHORT_PREAMBLE 0x04 757 758/* 759 * Crypto definitions 760 */ 761 762#define AR5K_KEYCACHE_SIZE 8 763 764/***********************\ 765 HW RELATED DEFINITIONS 766\***********************/ 767 768/* 769 * Misc definitions 770 */ 771#define AR5K_RSSI_EP_MULTIPLIER (1<<7) 772 773#define AR5K_ASSERT_ENTRY(_e, _s) do { \ 774 if (_e >= _s) \ 775 return (false); \ 776} while (0) 777 778/* 779 * Hardware interrupt abstraction 780 */ 781 782/** 783 * enum ath5k_int - Hardware interrupt masks helpers 784 * 785 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 786 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 787 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 788 * @AR5K_INT_RXNOFRM: No frame received (?) 789 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 790 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 791 * LinkPtr is NULL. For more details, refer to: 792 * http://www.freepatentsonline.com/20030225739.html 793 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 794 * Note that Rx overrun is not always fatal, on some chips we can continue 795 * operation without reseting the card, that's why int_fatal is not 796 * common for all chips. 797 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 798 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 799 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 800 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 801 * We currently do increments on interrupt by 802 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 803 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 804 * one of the PHY error counters reached the maximum value and should be 805 * read and cleared. 806 * @AR5K_INT_RXPHY: RX PHY Error 807 * @AR5K_INT_RXKCM: RX Key cache miss 808 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 809 * beacon that must be handled in software. The alternative is if you 810 * have VEOL support, in that case you let the hardware deal with things. 811 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 812 * beacons from the AP have associated with, we should probably try to 813 * reassociate. When in IBSS mode this might mean we have not received 814 * any beacons from any local stations. Note that every station in an 815 * IBSS schedules to send beacons at the Target Beacon Transmission Time 816 * (TBTT) with a random backoff. 817 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 818 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 819 * until properly handled 820 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 821 * errors. These types of errors we can enable seem to be of type 822 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 823 * @AR5K_INT_GLOBAL: Used to clear and set the IER 824 * @AR5K_INT_NOCARD: signals the card has been removed 825 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 826 * bit value 827 * 828 * These are mapped to take advantage of some common bits 829 * between the MACs, to be able to set intr properties 830 * easier. Some of them are not used yet inside hw.c. Most map 831 * to the respective hw interrupt value as they are common amogst different 832 * MACs. 833 */ 834enum ath5k_int { 835 AR5K_INT_RXOK = 0x00000001, 836 AR5K_INT_RXDESC = 0x00000002, 837 AR5K_INT_RXERR = 0x00000004, 838 AR5K_INT_RXNOFRM = 0x00000008, 839 AR5K_INT_RXEOL = 0x00000010, 840 AR5K_INT_RXORN = 0x00000020, 841 AR5K_INT_TXOK = 0x00000040, 842 AR5K_INT_TXDESC = 0x00000080, 843 AR5K_INT_TXERR = 0x00000100, 844 AR5K_INT_TXNOFRM = 0x00000200, 845 AR5K_INT_TXEOL = 0x00000400, 846 AR5K_INT_TXURN = 0x00000800, 847 AR5K_INT_MIB = 0x00001000, 848 AR5K_INT_SWI = 0x00002000, 849 AR5K_INT_RXPHY = 0x00004000, 850 AR5K_INT_RXKCM = 0x00008000, 851 AR5K_INT_SWBA = 0x00010000, 852 AR5K_INT_BRSSI = 0x00020000, 853 AR5K_INT_BMISS = 0x00040000, 854 AR5K_INT_FATAL = 0x00080000, /* Non common */ 855 AR5K_INT_BNR = 0x00100000, /* Non common */ 856 AR5K_INT_TIM = 0x00200000, /* Non common */ 857 AR5K_INT_DTIM = 0x00400000, /* Non common */ 858 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 859 AR5K_INT_GPIO = 0x01000000, 860 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 861 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 862 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 863 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 864 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 865 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 866 AR5K_INT_GLOBAL = 0x80000000, 867 868 AR5K_INT_COMMON = AR5K_INT_RXOK 869 | AR5K_INT_RXDESC 870 | AR5K_INT_RXERR 871 | AR5K_INT_RXNOFRM 872 | AR5K_INT_RXEOL 873 | AR5K_INT_RXORN 874 | AR5K_INT_TXOK 875 | AR5K_INT_TXDESC 876 | AR5K_INT_TXERR 877 | AR5K_INT_TXNOFRM 878 | AR5K_INT_TXEOL 879 | AR5K_INT_TXURN 880 | AR5K_INT_MIB 881 | AR5K_INT_SWI 882 | AR5K_INT_RXPHY 883 | AR5K_INT_RXKCM 884 | AR5K_INT_SWBA 885 | AR5K_INT_BRSSI 886 | AR5K_INT_BMISS 887 | AR5K_INT_GPIO 888 | AR5K_INT_GLOBAL, 889 890 AR5K_INT_NOCARD = 0xffffffff 891}; 892 893/* mask which calibration is active at the moment */ 894enum ath5k_calibration_mask { 895 AR5K_CALIBRATION_FULL = 0x01, 896 AR5K_CALIBRATION_SHORT = 0x02, 897 AR5K_CALIBRATION_ANI = 0x04, 898}; 899 900/* 901 * Power management 902 */ 903enum ath5k_power_mode { 904 AR5K_PM_UNDEFINED = 0, 905 AR5K_PM_AUTO, 906 AR5K_PM_AWAKE, 907 AR5K_PM_FULL_SLEEP, 908 AR5K_PM_NETWORK_SLEEP, 909}; 910 911/* 912 * These match net80211 definitions (not used in 913 * mac80211). 914 * TODO: Clean this up 915 */ 916#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 917#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 918#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 919#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 920#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 921 922/* GPIO-controlled software LED */ 923#define AR5K_SOFTLED_PIN 0 924#define AR5K_SOFTLED_ON 0 925#define AR5K_SOFTLED_OFF 1 926 927/* 928 * Chipset capabilities -see ath5k_hw_get_capability- 929 * get_capability function is not yet fully implemented 930 * in ath5k so most of these don't work yet... 931 * TODO: Implement these & merge with _TUNE_ stuff above 932 */ 933enum ath5k_capability_type { 934 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 935 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 936 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 937 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 938 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 939 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 940 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 941 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 942 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 943 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 944 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 945 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 946 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 947 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 948 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 949 AR5K_CAP_XR = 16, /* Supports XR mode */ 950 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 951 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 952 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 953 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 954}; 955 956 957/* XXX: we *may* move cap_range stuff to struct wiphy */ 958struct ath5k_capabilities { 959 /* 960 * Supported PHY modes 961 * (ie. CHANNEL_A, CHANNEL_B, ...) 962 */ 963 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 964 965 /* 966 * Frequency range (without regulation restrictions) 967 */ 968 struct { 969 u16 range_2ghz_min; 970 u16 range_2ghz_max; 971 u16 range_5ghz_min; 972 u16 range_5ghz_max; 973 } cap_range; 974 975 /* 976 * Values stored in the EEPROM (some of them...) 977 */ 978 struct ath5k_eeprom_info cap_eeprom; 979 980 /* 981 * Queue information 982 */ 983 struct { 984 u8 q_tx_num; 985 } cap_queues; 986 987 bool cap_has_phyerr_counters; 988}; 989 990/* size of noise floor history (keep it a power of two) */ 991#define ATH5K_NF_CAL_HIST_MAX 8 992struct ath5k_nfcal_hist 993{ 994 s16 index; /* current index into nfval */ 995 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 996}; 997 998/** 999 * struct avg_val - Helper structure for average calculation 1000 * @avg: contains the actual average value 1001 * @avg_weight: is used internally during calculation to prevent rounding errors 1002 */ 1003struct ath5k_avg_val { 1004 int avg; 1005 int avg_weight; 1006}; 1007 1008/***************************************\ 1009 HARDWARE ABSTRACTION LAYER STRUCTURE 1010\***************************************/ 1011 1012/* 1013 * Misc defines 1014 */ 1015 1016#define AR5K_MAX_GPIO 10 1017#define AR5K_MAX_RF_BANKS 8 1018 1019/* TODO: Clean up and merge with ath5k_softc */ 1020struct ath5k_hw { 1021 struct ath_common common; 1022 1023 struct ath5k_softc *ah_sc; 1024 void __iomem *ah_iobase; 1025 1026 enum ath5k_int ah_imr; 1027 1028 struct ieee80211_channel *ah_current_channel; 1029 bool ah_turbo; 1030 bool ah_calibration; 1031 bool ah_single_chip; 1032 1033 enum ath5k_version ah_version; 1034 enum ath5k_radio ah_radio; 1035 u32 ah_phy; 1036 u32 ah_mac_srev; 1037 u16 ah_mac_version; 1038 u16 ah_phy_revision; 1039 u16 ah_radio_5ghz_revision; 1040 u16 ah_radio_2ghz_revision; 1041 1042#define ah_modes ah_capabilities.cap_mode 1043#define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1044 1045 u32 ah_limit_tx_retries; 1046 u8 ah_coverage_class; 1047 1048 /* Antenna Control */ 1049 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1050 u8 ah_ant_mode; 1051 u8 ah_tx_ant; 1052 u8 ah_def_ant; 1053 bool ah_software_retry; 1054 1055 struct ath5k_capabilities ah_capabilities; 1056 1057 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1058 u32 ah_txq_status; 1059 u32 ah_txq_imr_txok; 1060 u32 ah_txq_imr_txerr; 1061 u32 ah_txq_imr_txurn; 1062 u32 ah_txq_imr_txdesc; 1063 u32 ah_txq_imr_txeol; 1064 u32 ah_txq_imr_cbrorn; 1065 u32 ah_txq_imr_cbrurn; 1066 u32 ah_txq_imr_qtrig; 1067 u32 ah_txq_imr_nofrm; 1068 u32 ah_txq_isr; 1069 u32 *ah_rf_banks; 1070 size_t ah_rf_banks_size; 1071 size_t ah_rf_regs_count; 1072 struct ath5k_gain ah_gain; 1073 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1074 1075 1076 struct { 1077 /* Temporary tables used for interpolation */ 1078 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1079 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1080 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1081 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1082 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1083 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1084 u8 txp_min_idx; 1085 bool txp_tpc; 1086 /* Values in 0.25dB units */ 1087 s16 txp_min_pwr; 1088 s16 txp_max_pwr; 1089 /* Values in 0.5dB units */ 1090 s16 txp_offset; 1091 s16 txp_ofdm; 1092 s16 txp_cck_ofdm_gainf_delta; 1093 /* Value in dB units */ 1094 s16 txp_cck_ofdm_pwr_delta; 1095 } ah_txpower; 1096 1097 struct { 1098 bool r_enabled; 1099 int r_last_alert; 1100 struct ieee80211_channel r_last_channel; 1101 } ah_radar; 1102 1103 struct ath5k_nfcal_hist ah_nfcal_hist; 1104 1105 /* average beacon RSSI in our BSS (used by ANI) */ 1106 struct ewma ah_beacon_rssi_avg; 1107 1108 /* noise floor from last periodic calibration */ 1109 s32 ah_noise_floor; 1110 1111 /* Calibration timestamp */ 1112 unsigned long ah_cal_next_full; 1113 unsigned long ah_cal_next_ani; 1114 unsigned long ah_cal_next_nf; 1115 1116 /* Calibration mask */ 1117 u8 ah_cal_mask; 1118 1119 /* 1120 * Function pointers 1121 */ 1122 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1123 unsigned int, unsigned int, int, enum ath5k_pkt_type, 1124 unsigned int, unsigned int, unsigned int, unsigned int, 1125 unsigned int, unsigned int, unsigned int, unsigned int); 1126 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1127 struct ath5k_tx_status *); 1128 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1129 struct ath5k_rx_status *); 1130}; 1131 1132/* 1133 * Prototypes 1134 */ 1135 1136/* Attach/Detach Functions */ 1137int ath5k_hw_attach(struct ath5k_softc *sc); 1138void ath5k_hw_detach(struct ath5k_hw *ah); 1139 1140int ath5k_sysfs_register(struct ath5k_softc *sc); 1141void ath5k_sysfs_unregister(struct ath5k_softc *sc); 1142 1143/* LED functions */ 1144int ath5k_init_leds(struct ath5k_softc *sc); 1145void ath5k_led_enable(struct ath5k_softc *sc); 1146void ath5k_led_off(struct ath5k_softc *sc); 1147void ath5k_unregister_leds(struct ath5k_softc *sc); 1148 1149/* Reset Functions */ 1150int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1151int ath5k_hw_on_hold(struct ath5k_hw *ah); 1152int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1153 struct ieee80211_channel *channel, bool change_channel); 1154int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 1155 bool is_set); 1156/* Power management functions */ 1157 1158/* DMA Related Functions */ 1159void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1160int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah); 1161u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1162void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1163int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1164int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1165u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1166int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1167 u32 phys_addr); 1168int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1169/* Interrupt handling */ 1170bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1171int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1172enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1173void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); 1174 1175/* EEPROM access functions */ 1176int ath5k_eeprom_init(struct ath5k_hw *ah); 1177void ath5k_eeprom_detach(struct ath5k_hw *ah); 1178int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1179 1180/* Protocol Control Unit Functions */ 1181extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1182void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1183/* BSSID Functions */ 1184int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1185void ath5k_hw_set_bssid(struct ath5k_hw *ah); 1186void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1187/* Receive start/stop functions */ 1188void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1189void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1190/* RX Filter functions */ 1191void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1192u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1193void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1194/* Beacon control functions */ 1195u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1196void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1197void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1198void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1199bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); 1200/* ACK bit rate */ 1201void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high); 1202/* Clock rate related functions */ 1203unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1204unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1205void ath5k_hw_set_clockrate(struct ath5k_hw *ah); 1206 1207/* Queue Control Unit, DFS Control Unit Functions */ 1208int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1209 struct ath5k_txq_info *queue_info); 1210int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1211 const struct ath5k_txq_info *queue_info); 1212int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1213 enum ath5k_tx_queue queue_type, 1214 struct ath5k_txq_info *queue_info); 1215u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1216void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1217int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1218int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time); 1219 1220/* Hardware Descriptor Functions */ 1221int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1222int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1223 u32 size, unsigned int flags); 1224int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1225 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 1226 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); 1227 1228/* GPIO Functions */ 1229void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1230int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1231int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1232u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1233int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1234void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 1235 u32 interrupt_level); 1236 1237/* rfkill Functions */ 1238void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1239void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1240 1241/* Misc functions */ 1242int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1243int ath5k_hw_get_capability(struct ath5k_hw *ah, 1244 enum ath5k_capability_type cap_type, u32 capability, 1245 u32 *result); 1246int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1247int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1248 1249/* Initial register settings functions */ 1250int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1251 1252/* Initialize RF */ 1253int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 1254 struct ieee80211_channel *channel, 1255 unsigned int mode); 1256int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq); 1257enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1258int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1259/* PHY/RF channel functions */ 1260bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1261int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel); 1262/* PHY calibration */ 1263void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1264int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1265 struct ieee80211_channel *channel); 1266void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); 1267/* Spur mitigation */ 1268bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1269 struct ieee80211_channel *channel); 1270void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1271 struct ieee80211_channel *channel); 1272/* Misc PHY functions */ 1273u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1274int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1275/* Antenna control */ 1276void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1277void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); 1278/* TX power setup */ 1279int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 1280 u8 ee_mode, u8 txpower); 1281int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1282 1283/* 1284 * Functions used internaly 1285 */ 1286 1287static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1288{ 1289 return &ah->common; 1290} 1291 1292static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1293{ 1294 return &(ath5k_hw_common(ah)->regulatory); 1295} 1296 1297static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1298{ 1299 return ioread32(ah->ah_iobase + reg); 1300} 1301 1302static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1303{ 1304 iowrite32(val, ah->ah_iobase + reg); 1305} 1306 1307static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1308{ 1309 u32 retval = 0, bit, i; 1310 1311 for (i = 0; i < bits; i++) { 1312 bit = (val >> i) & 1; 1313 retval = (retval << 1) | bit; 1314 } 1315 1316 return retval; 1317} 1318 1319#endif 1320