phy.c revision 28bec7b845e10b68e6ba1ade5de0fc566690fc61
1/* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23#include <linux/delay.h> 24#include <linux/slab.h> 25 26#include "ath5k.h" 27#include "reg.h" 28#include "base.h" 29#include "rfbuffer.h" 30#include "rfgain.h" 31 32 33/******************\ 34* Helper functions * 35\******************/ 36 37/* 38 * Get the PHY Chip revision 39 */ 40u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) 41{ 42 unsigned int i; 43 u32 srev; 44 u16 ret; 45 46 /* 47 * Set the radio chip access register 48 */ 49 switch (chan) { 50 case CHANNEL_2GHZ: 51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 52 break; 53 case CHANNEL_5GHZ: 54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 55 break; 56 default: 57 return 0; 58 } 59 60 mdelay(2); 61 62 /* ...wait until PHY is ready and read the selected radio revision */ 63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 64 65 for (i = 0; i < 8; i++) 66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 67 68 if (ah->ah_version == AR5K_AR5210) { 69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 71 } else { 72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 74 ((srev & 0x0f) << 4), 8); 75 } 76 77 /* Reset to the 5GHz mode */ 78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 79 80 return ret; 81} 82 83/* 84 * Check if a channel is supported 85 */ 86bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) 87{ 88 /* Check if the channel is in our supported range */ 89 if (flags & CHANNEL_2GHZ) { 90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 92 return true; 93 } else if (flags & CHANNEL_5GHZ) 94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 96 return true; 97 98 return false; 99} 100 101bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 102 struct ieee80211_channel *channel) 103{ 104 u8 refclk_freq; 105 106 if ((ah->ah_radio == AR5K_RF5112) || 107 (ah->ah_radio == AR5K_RF5413) || 108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 109 refclk_freq = 40; 110 else 111 refclk_freq = 32; 112 113 if ((channel->center_freq % refclk_freq != 0) && 114 ((channel->center_freq % refclk_freq < 10) || 115 (channel->center_freq % refclk_freq > 22))) 116 return true; 117 else 118 return false; 119} 120 121/* 122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 123 */ 124static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 125 const struct ath5k_rf_reg *rf_regs, 126 u32 val, u8 reg_id, bool set) 127{ 128 const struct ath5k_rf_reg *rfreg = NULL; 129 u8 offset, bank, num_bits, col, position; 130 u16 entry; 131 u32 mask, data, last_bit, bits_shifted, first_bit; 132 u32 *rfb; 133 s32 bits_left; 134 int i; 135 136 data = 0; 137 rfb = ah->ah_rf_banks; 138 139 for (i = 0; i < ah->ah_rf_regs_count; i++) { 140 if (rf_regs[i].index == reg_id) { 141 rfreg = &rf_regs[i]; 142 break; 143 } 144 } 145 146 if (rfb == NULL || rfreg == NULL) { 147 ATH5K_PRINTF("Rf register not found!\n"); 148 /* should not happen */ 149 return 0; 150 } 151 152 bank = rfreg->bank; 153 num_bits = rfreg->field.len; 154 first_bit = rfreg->field.pos; 155 col = rfreg->field.col; 156 157 /* first_bit is an offset from bank's 158 * start. Since we have all banks on 159 * the same array, we use this offset 160 * to mark each bank's start */ 161 offset = ah->ah_offset[bank]; 162 163 /* Boundary check */ 164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 165 ATH5K_PRINTF("invalid values at offset %u\n", offset); 166 return 0; 167 } 168 169 entry = ((first_bit - 1) / 8) + offset; 170 position = (first_bit - 1) % 8; 171 172 if (set) 173 data = ath5k_hw_bitswap(val, num_bits); 174 175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 176 position = 0, entry++) { 177 178 last_bit = (position + bits_left > 8) ? 8 : 179 position + bits_left; 180 181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 182 (col * 8); 183 184 if (set) { 185 rfb[entry] &= ~mask; 186 rfb[entry] |= ((data << position) << (col * 8)) & mask; 187 data >>= (8 - position); 188 } else { 189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 190 << bits_shifted; 191 bits_shifted += last_bit - position; 192 } 193 194 bits_left -= 8 - position; 195 } 196 197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 198 199 return data; 200} 201 202/** 203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 204 * 205 * @ah: the &struct ath5k_hw 206 * @channel: the currently set channel upon reset 207 * 208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init. 210 * 211 * Since delta slope is floating point we split it on its exponent and 212 * mantissa and provide these values on hw. 213 * 214 * For more infos i think this patent is related 215 * http://www.freepatentsonline.com/7184495.html 216 */ 217static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 218 struct ieee80211_channel *channel) 219{ 220 /* Get exponent and mantissa and set it */ 221 u32 coef_scaled, coef_exp, coef_man, 222 ds_coef_exp, ds_coef_man, clock; 223 224 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 225 !(channel->hw_value & CHANNEL_OFDM)); 226 227 /* Get coefficient 228 * ALGO: coef = (5 * clock / carrier_freq) / 2 229 * we scale coef by shifting clock value by 24 for 230 * better precision since we use integers */ 231 switch (ah->ah_bwmode) { 232 case AR5K_BWMODE_40MHZ: 233 clock = 40 * 2; 234 break; 235 case AR5K_BWMODE_10MHZ: 236 clock = 40 / 2; 237 break; 238 case AR5K_BWMODE_5MHZ: 239 clock = 40 / 4; 240 break; 241 default: 242 clock = 40; 243 break; 244 } 245 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 246 247 /* Get exponent 248 * ALGO: coef_exp = 14 - highest set bit position */ 249 coef_exp = ilog2(coef_scaled); 250 251 /* Doesn't make sense if it's zero*/ 252 if (!coef_scaled || !coef_exp) 253 return -EINVAL; 254 255 /* Note: we've shifted coef_scaled by 24 */ 256 coef_exp = 14 - (coef_exp - 24); 257 258 259 /* Get mantissa (significant digits) 260 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 261 coef_man = coef_scaled + 262 (1 << (24 - coef_exp - 1)); 263 264 /* Calculate delta slope coefficient exponent 265 * and mantissa (remove scaling) and set them on hw */ 266 ds_coef_man = coef_man >> (24 - coef_exp); 267 ds_coef_exp = coef_exp - 16; 268 269 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 270 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 271 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 272 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 273 274 return 0; 275} 276 277int ath5k_hw_phy_disable(struct ath5k_hw *ah) 278{ 279 /*Just a try M.F.*/ 280 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 281 282 return 0; 283} 284 285 286/**********************\ 287* RF Gain optimization * 288\**********************/ 289 290/* 291 * This code is used to optimize RF gain on different environments 292 * (temperature mostly) based on feedback from a power detector. 293 * 294 * It's only used on RF5111 and RF5112, later RF chips seem to have 295 * auto adjustment on hw -notice they have a much smaller BANK 7 and 296 * no gain optimization ladder-. 297 * 298 * For more infos check out this patent doc 299 * http://www.freepatentsonline.com/7400691.html 300 * 301 * This paper describes power drops as seen on the receiver due to 302 * probe packets 303 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 304 * %20of%20Power%20Control.pdf 305 * 306 * And this is the MadWiFi bug entry related to the above 307 * http://madwifi-project.org/ticket/1659 308 * with various measurements and diagrams 309 * 310 * TODO: Deal with power drops due to probes by setting an apropriate 311 * tx power on the probe packets ! Make this part of the calibration process. 312 */ 313 314/* Initialize ah_gain durring attach */ 315int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 316{ 317 /* Initialize the gain optimization values */ 318 switch (ah->ah_radio) { 319 case AR5K_RF5111: 320 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 321 ah->ah_gain.g_low = 20; 322 ah->ah_gain.g_high = 35; 323 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 324 break; 325 case AR5K_RF5112: 326 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 327 ah->ah_gain.g_low = 20; 328 ah->ah_gain.g_high = 85; 329 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 330 break; 331 default: 332 return -EINVAL; 333 } 334 335 return 0; 336} 337 338/* Schedule a gain probe check on the next transmited packet. 339 * That means our next packet is going to be sent with lower 340 * tx power and a Peak to Average Power Detector (PAPD) will try 341 * to measure the gain. 342 * 343 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 344 * just after we enable the probe so that we don't mess with 345 * standard traffic ? Maybe it's time to use sw interrupts and 346 * a probe tasklet !!! 347 */ 348static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 349{ 350 351 /* Skip if gain calibration is inactive or 352 * we already handle a probe request */ 353 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 354 return; 355 356 /* Send the packet with 2dB below max power as 357 * patent doc suggest */ 358 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 359 AR5K_PHY_PAPD_PROBE_TXPOWER) | 360 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 361 362 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 363 364} 365 366/* Calculate gain_F measurement correction 367 * based on the current step for RF5112 rev. 2 */ 368static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 369{ 370 u32 mix, step; 371 u32 *rf; 372 const struct ath5k_gain_opt *go; 373 const struct ath5k_gain_opt_step *g_step; 374 const struct ath5k_rf_reg *rf_regs; 375 376 /* Only RF5112 Rev. 2 supports it */ 377 if ((ah->ah_radio != AR5K_RF5112) || 378 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 379 return 0; 380 381 go = &rfgain_opt_5112; 382 rf_regs = rf_regs_5112a; 383 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 384 385 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 386 387 if (ah->ah_rf_banks == NULL) 388 return 0; 389 390 rf = ah->ah_rf_banks; 391 ah->ah_gain.g_f_corr = 0; 392 393 /* No VGA (Variable Gain Amplifier) override, skip */ 394 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 395 return 0; 396 397 /* Mix gain stepping */ 398 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 399 400 /* Mix gain override */ 401 mix = g_step->gos_param[0]; 402 403 switch (mix) { 404 case 3: 405 ah->ah_gain.g_f_corr = step * 2; 406 break; 407 case 2: 408 ah->ah_gain.g_f_corr = (step - 5) * 2; 409 break; 410 case 1: 411 ah->ah_gain.g_f_corr = step; 412 break; 413 default: 414 ah->ah_gain.g_f_corr = 0; 415 break; 416 } 417 418 return ah->ah_gain.g_f_corr; 419} 420 421/* Check if current gain_F measurement is in the range of our 422 * power detector windows. If we get a measurement outside range 423 * we know it's not accurate (detectors can't measure anything outside 424 * their detection window) so we must ignore it */ 425static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 426{ 427 const struct ath5k_rf_reg *rf_regs; 428 u32 step, mix_ovr, level[4]; 429 u32 *rf; 430 431 if (ah->ah_rf_banks == NULL) 432 return false; 433 434 rf = ah->ah_rf_banks; 435 436 if (ah->ah_radio == AR5K_RF5111) { 437 438 rf_regs = rf_regs_5111; 439 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 440 441 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 442 false); 443 444 level[0] = 0; 445 level[1] = (step == 63) ? 50 : step + 4; 446 level[2] = (step != 63) ? 64 : level[0]; 447 level[3] = level[2] + 50 ; 448 449 ah->ah_gain.g_high = level[3] - 450 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 451 ah->ah_gain.g_low = level[0] + 452 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 453 } else { 454 455 rf_regs = rf_regs_5112; 456 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 457 458 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 459 false); 460 461 level[0] = level[2] = 0; 462 463 if (mix_ovr == 1) { 464 level[1] = level[3] = 83; 465 } else { 466 level[1] = level[3] = 107; 467 ah->ah_gain.g_high = 55; 468 } 469 } 470 471 return (ah->ah_gain.g_current >= level[0] && 472 ah->ah_gain.g_current <= level[1]) || 473 (ah->ah_gain.g_current >= level[2] && 474 ah->ah_gain.g_current <= level[3]); 475} 476 477/* Perform gain_F adjustment by choosing the right set 478 * of parameters from RF gain optimization ladder */ 479static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 480{ 481 const struct ath5k_gain_opt *go; 482 const struct ath5k_gain_opt_step *g_step; 483 int ret = 0; 484 485 switch (ah->ah_radio) { 486 case AR5K_RF5111: 487 go = &rfgain_opt_5111; 488 break; 489 case AR5K_RF5112: 490 go = &rfgain_opt_5112; 491 break; 492 default: 493 return 0; 494 } 495 496 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 497 498 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 499 500 /* Reached maximum */ 501 if (ah->ah_gain.g_step_idx == 0) 502 return -1; 503 504 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 505 ah->ah_gain.g_target >= ah->ah_gain.g_high && 506 ah->ah_gain.g_step_idx > 0; 507 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 508 ah->ah_gain.g_target -= 2 * 509 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 510 g_step->gos_gain); 511 512 ret = 1; 513 goto done; 514 } 515 516 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 517 518 /* Reached minimum */ 519 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 520 return -2; 521 522 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 523 ah->ah_gain.g_target <= ah->ah_gain.g_low && 524 ah->ah_gain.g_step_idx < go->go_steps_count-1; 525 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 526 ah->ah_gain.g_target -= 2 * 527 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 528 g_step->gos_gain); 529 530 ret = 2; 531 goto done; 532 } 533 534done: 535 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 536 "ret %d, gain step %u, current gain %u, target gain %u\n", 537 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 538 ah->ah_gain.g_target); 539 540 return ret; 541} 542 543/* Main callback for thermal RF gain calibration engine 544 * Check for a new gain reading and schedule an adjustment 545 * if needed. 546 * 547 * TODO: Use sw interrupt to schedule reset if gain_F needs 548 * adjustment */ 549enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 550{ 551 u32 data, type; 552 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 553 554 if (ah->ah_rf_banks == NULL || 555 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 556 return AR5K_RFGAIN_INACTIVE; 557 558 /* No check requested, either engine is inactive 559 * or an adjustment is already requested */ 560 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 561 goto done; 562 563 /* Read the PAPD (Peak to Average Power Detector) 564 * register */ 565 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 566 567 /* No probe is scheduled, read gain_F measurement */ 568 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 569 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 570 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 571 572 /* If tx packet is CCK correct the gain_F measurement 573 * by cck ofdm gain delta */ 574 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 575 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 576 ah->ah_gain.g_current += 577 ee->ee_cck_ofdm_gain_delta; 578 else 579 ah->ah_gain.g_current += 580 AR5K_GAIN_CCK_PROBE_CORR; 581 } 582 583 /* Further correct gain_F measurement for 584 * RF5112A radios */ 585 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 586 ath5k_hw_rf_gainf_corr(ah); 587 ah->ah_gain.g_current = 588 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 589 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 590 0; 591 } 592 593 /* Check if measurement is ok and if we need 594 * to adjust gain, schedule a gain adjustment, 595 * else switch back to the acive state */ 596 if (ath5k_hw_rf_check_gainf_readback(ah) && 597 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 598 ath5k_hw_rf_gainf_adjust(ah)) { 599 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 600 } else { 601 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 602 } 603 } 604 605done: 606 return ah->ah_gain.g_state; 607} 608 609/* Write initial RF gain table to set the RF sensitivity 610 * this one works on all RF chips and has nothing to do 611 * with gain_F calibration */ 612static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band) 613{ 614 const struct ath5k_ini_rfgain *ath5k_rfg; 615 unsigned int i, size, index; 616 617 switch (ah->ah_radio) { 618 case AR5K_RF5111: 619 ath5k_rfg = rfgain_5111; 620 size = ARRAY_SIZE(rfgain_5111); 621 break; 622 case AR5K_RF5112: 623 ath5k_rfg = rfgain_5112; 624 size = ARRAY_SIZE(rfgain_5112); 625 break; 626 case AR5K_RF2413: 627 ath5k_rfg = rfgain_2413; 628 size = ARRAY_SIZE(rfgain_2413); 629 break; 630 case AR5K_RF2316: 631 ath5k_rfg = rfgain_2316; 632 size = ARRAY_SIZE(rfgain_2316); 633 break; 634 case AR5K_RF5413: 635 ath5k_rfg = rfgain_5413; 636 size = ARRAY_SIZE(rfgain_5413); 637 break; 638 case AR5K_RF2317: 639 case AR5K_RF2425: 640 ath5k_rfg = rfgain_2425; 641 size = ARRAY_SIZE(rfgain_2425); 642 break; 643 default: 644 return -EINVAL; 645 } 646 647 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0; 648 649 for (i = 0; i < size; i++) { 650 AR5K_REG_WAIT(i); 651 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], 652 (u32)ath5k_rfg[i].rfg_register); 653 } 654 655 return 0; 656} 657 658 659 660/********************\ 661* RF Registers setup * 662\********************/ 663 664/* 665 * Setup RF registers by writing RF buffer on hw 666 */ 667static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 668 struct ieee80211_channel *channel, unsigned int mode) 669{ 670 const struct ath5k_rf_reg *rf_regs; 671 const struct ath5k_ini_rfbuffer *ini_rfb; 672 const struct ath5k_gain_opt *go = NULL; 673 const struct ath5k_gain_opt_step *g_step; 674 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 675 u8 ee_mode = 0; 676 u32 *rfb; 677 int i, obdb = -1, bank = -1; 678 679 switch (ah->ah_radio) { 680 case AR5K_RF5111: 681 rf_regs = rf_regs_5111; 682 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 683 ini_rfb = rfb_5111; 684 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 685 go = &rfgain_opt_5111; 686 break; 687 case AR5K_RF5112: 688 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 689 rf_regs = rf_regs_5112a; 690 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 691 ini_rfb = rfb_5112a; 692 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 693 } else { 694 rf_regs = rf_regs_5112; 695 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 696 ini_rfb = rfb_5112; 697 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 698 } 699 go = &rfgain_opt_5112; 700 break; 701 case AR5K_RF2413: 702 rf_regs = rf_regs_2413; 703 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 704 ini_rfb = rfb_2413; 705 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 706 break; 707 case AR5K_RF2316: 708 rf_regs = rf_regs_2316; 709 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 710 ini_rfb = rfb_2316; 711 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 712 break; 713 case AR5K_RF5413: 714 rf_regs = rf_regs_5413; 715 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 716 ini_rfb = rfb_5413; 717 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 718 break; 719 case AR5K_RF2317: 720 rf_regs = rf_regs_2425; 721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 722 ini_rfb = rfb_2317; 723 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 724 break; 725 case AR5K_RF2425: 726 rf_regs = rf_regs_2425; 727 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 728 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 729 ini_rfb = rfb_2425; 730 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 731 } else { 732 ini_rfb = rfb_2417; 733 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 734 } 735 break; 736 default: 737 return -EINVAL; 738 } 739 740 /* If it's the first time we set RF buffer, allocate 741 * ah->ah_rf_banks based on ah->ah_rf_banks_size 742 * we set above */ 743 if (ah->ah_rf_banks == NULL) { 744 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 745 GFP_KERNEL); 746 if (ah->ah_rf_banks == NULL) { 747 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 748 return -ENOMEM; 749 } 750 } 751 752 /* Copy values to modify them */ 753 rfb = ah->ah_rf_banks; 754 755 for (i = 0; i < ah->ah_rf_banks_size; i++) { 756 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 757 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 758 return -EINVAL; 759 } 760 761 /* Bank changed, write down the offset */ 762 if (bank != ini_rfb[i].rfb_bank) { 763 bank = ini_rfb[i].rfb_bank; 764 ah->ah_offset[bank] = i; 765 } 766 767 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 768 } 769 770 /* Set Output and Driver bias current (OB/DB) */ 771 if (channel->hw_value & CHANNEL_2GHZ) { 772 773 if (channel->hw_value & CHANNEL_CCK) 774 ee_mode = AR5K_EEPROM_MODE_11B; 775 else 776 ee_mode = AR5K_EEPROM_MODE_11G; 777 778 /* For RF511X/RF211X combination we 779 * use b_OB and b_DB parameters stored 780 * in eeprom on ee->ee_ob[ee_mode][0] 781 * 782 * For all other chips we use OB/DB for 2Ghz 783 * stored in the b/g modal section just like 784 * 802.11a on ee->ee_ob[ee_mode][1] */ 785 if ((ah->ah_radio == AR5K_RF5111) || 786 (ah->ah_radio == AR5K_RF5112)) 787 obdb = 0; 788 else 789 obdb = 1; 790 791 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 792 AR5K_RF_OB_2GHZ, true); 793 794 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 795 AR5K_RF_DB_2GHZ, true); 796 797 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 798 } else if ((channel->hw_value & CHANNEL_5GHZ) || 799 (ah->ah_radio == AR5K_RF5111)) { 800 801 /* For 11a, Turbo and XR we need to choose 802 * OB/DB based on frequency range */ 803 ee_mode = AR5K_EEPROM_MODE_11A; 804 obdb = channel->center_freq >= 5725 ? 3 : 805 (channel->center_freq >= 5500 ? 2 : 806 (channel->center_freq >= 5260 ? 1 : 807 (channel->center_freq > 4000 ? 0 : -1))); 808 809 if (obdb < 0) 810 return -EINVAL; 811 812 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 813 AR5K_RF_OB_5GHZ, true); 814 815 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 816 AR5K_RF_DB_5GHZ, true); 817 } 818 819 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 820 821 /* Set turbo mode (N/A on RF5413) */ 822 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && 823 (ah->ah_radio != AR5K_RF5413)) 824 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); 825 826 /* Bank Modifications (chip-specific) */ 827 if (ah->ah_radio == AR5K_RF5111) { 828 829 /* Set gain_F settings according to current step */ 830 if (channel->hw_value & CHANNEL_OFDM) { 831 832 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 833 AR5K_PHY_FRAME_CTL_TX_CLIP, 834 g_step->gos_param[0]); 835 836 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 837 AR5K_RF_PWD_90, true); 838 839 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 840 AR5K_RF_PWD_84, true); 841 842 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 843 AR5K_RF_RFGAIN_SEL, true); 844 845 /* We programmed gain_F parameters, switch back 846 * to active state */ 847 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 848 849 } 850 851 /* Bank 6/7 setup */ 852 853 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 854 AR5K_RF_PWD_XPD, true); 855 856 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 857 AR5K_RF_XPD_GAIN, true); 858 859 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 860 AR5K_RF_GAIN_I, true); 861 862 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 863 AR5K_RF_PLO_SEL, true); 864 865 /* Tweak power detectors for half/quarter rate support */ 866 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 867 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 868 u8 wait_i; 869 870 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, 871 AR5K_RF_WAIT_S, true); 872 873 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 874 0x1f : 0x10; 875 876 ath5k_hw_rfb_op(ah, rf_regs, wait_i, 877 AR5K_RF_WAIT_I, true); 878 ath5k_hw_rfb_op(ah, rf_regs, 3, 879 AR5K_RF_MAX_TIME, true); 880 881 } 882 } 883 884 if (ah->ah_radio == AR5K_RF5112) { 885 886 /* Set gain_F settings according to current step */ 887 if (channel->hw_value & CHANNEL_OFDM) { 888 889 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 890 AR5K_RF_MIXGAIN_OVR, true); 891 892 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 893 AR5K_RF_PWD_138, true); 894 895 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 896 AR5K_RF_PWD_137, true); 897 898 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 899 AR5K_RF_PWD_136, true); 900 901 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 902 AR5K_RF_PWD_132, true); 903 904 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 905 AR5K_RF_PWD_131, true); 906 907 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 908 AR5K_RF_PWD_130, true); 909 910 /* We programmed gain_F parameters, switch back 911 * to active state */ 912 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 913 } 914 915 /* Bank 6/7 setup */ 916 917 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 918 AR5K_RF_XPD_SEL, true); 919 920 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 921 /* Rev. 1 supports only one xpd */ 922 ath5k_hw_rfb_op(ah, rf_regs, 923 ee->ee_x_gain[ee_mode], 924 AR5K_RF_XPD_GAIN, true); 925 926 } else { 927 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 928 if (ee->ee_pd_gains[ee_mode] > 1) { 929 ath5k_hw_rfb_op(ah, rf_regs, 930 pdg_curve_to_idx[0], 931 AR5K_RF_PD_GAIN_LO, true); 932 ath5k_hw_rfb_op(ah, rf_regs, 933 pdg_curve_to_idx[1], 934 AR5K_RF_PD_GAIN_HI, true); 935 } else { 936 ath5k_hw_rfb_op(ah, rf_regs, 937 pdg_curve_to_idx[0], 938 AR5K_RF_PD_GAIN_LO, true); 939 ath5k_hw_rfb_op(ah, rf_regs, 940 pdg_curve_to_idx[0], 941 AR5K_RF_PD_GAIN_HI, true); 942 } 943 944 /* Lower synth voltage on Rev 2 */ 945 ath5k_hw_rfb_op(ah, rf_regs, 2, 946 AR5K_RF_HIGH_VC_CP, true); 947 948 ath5k_hw_rfb_op(ah, rf_regs, 2, 949 AR5K_RF_MID_VC_CP, true); 950 951 ath5k_hw_rfb_op(ah, rf_regs, 2, 952 AR5K_RF_LOW_VC_CP, true); 953 954 ath5k_hw_rfb_op(ah, rf_regs, 2, 955 AR5K_RF_PUSH_UP, true); 956 957 /* Decrease power consumption on 5213+ BaseBand */ 958 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 959 ath5k_hw_rfb_op(ah, rf_regs, 1, 960 AR5K_RF_PAD2GND, true); 961 962 ath5k_hw_rfb_op(ah, rf_regs, 1, 963 AR5K_RF_XB2_LVL, true); 964 965 ath5k_hw_rfb_op(ah, rf_regs, 1, 966 AR5K_RF_XB5_LVL, true); 967 968 ath5k_hw_rfb_op(ah, rf_regs, 1, 969 AR5K_RF_PWD_167, true); 970 971 ath5k_hw_rfb_op(ah, rf_regs, 1, 972 AR5K_RF_PWD_166, true); 973 } 974 } 975 976 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 977 AR5K_RF_GAIN_I, true); 978 979 /* Tweak power detector for half/quarter rates */ 980 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 981 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 982 u8 pd_delay; 983 984 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 985 0xf : 0x8; 986 987 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, 988 AR5K_RF_PD_PERIOD_A, true); 989 ath5k_hw_rfb_op(ah, rf_regs, 0xf, 990 AR5K_RF_PD_DELAY_A, true); 991 992 } 993 } 994 995 if (ah->ah_radio == AR5K_RF5413 && 996 channel->hw_value & CHANNEL_2GHZ) { 997 998 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 999 true); 1000 1001 /* Set optimum value for early revisions (on pci-e chips) */ 1002 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1003 ah->ah_mac_srev < AR5K_SREV_AR5413) 1004 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 1005 AR5K_RF_PWD_ICLOBUF_2G, true); 1006 1007 } 1008 1009 /* Write RF banks on hw */ 1010 for (i = 0; i < ah->ah_rf_banks_size; i++) { 1011 AR5K_REG_WAIT(i); 1012 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 1013 } 1014 1015 return 0; 1016} 1017 1018 1019/**************************\ 1020 PHY/RF channel functions 1021\**************************/ 1022 1023/* 1024 * Convertion needed for RF5110 1025 */ 1026static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 1027{ 1028 u32 athchan; 1029 1030 /* 1031 * Convert IEEE channel/MHz to an internal channel value used 1032 * by the AR5210 chipset. This has not been verified with 1033 * newer chipsets like the AR5212A who have a completely 1034 * different RF/PHY part. 1035 */ 1036 athchan = (ath5k_hw_bitswap( 1037 (ieee80211_frequency_to_channel( 1038 channel->center_freq) - 24) / 2, 5) 1039 << 1) | (1 << 6) | 0x1; 1040 return athchan; 1041} 1042 1043/* 1044 * Set channel on RF5110 1045 */ 1046static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1047 struct ieee80211_channel *channel) 1048{ 1049 u32 data; 1050 1051 /* 1052 * Set the channel and wait 1053 */ 1054 data = ath5k_hw_rf5110_chan2athchan(channel); 1055 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 1056 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 1057 mdelay(1); 1058 1059 return 0; 1060} 1061 1062/* 1063 * Convertion needed for 5111 1064 */ 1065static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1066 struct ath5k_athchan_2ghz *athchan) 1067{ 1068 int channel; 1069 1070 /* Cast this value to catch negative channel numbers (>= -19) */ 1071 channel = (int)ieee; 1072 1073 /* 1074 * Map 2GHz IEEE channel to 5GHz Atheros channel 1075 */ 1076 if (channel <= 13) { 1077 athchan->a2_athchan = 115 + channel; 1078 athchan->a2_flags = 0x46; 1079 } else if (channel == 14) { 1080 athchan->a2_athchan = 124; 1081 athchan->a2_flags = 0x44; 1082 } else if (channel >= 15 && channel <= 26) { 1083 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1084 athchan->a2_flags = 0x46; 1085 } else 1086 return -EINVAL; 1087 1088 return 0; 1089} 1090 1091/* 1092 * Set channel on 5111 1093 */ 1094static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1095 struct ieee80211_channel *channel) 1096{ 1097 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1098 unsigned int ath5k_channel = 1099 ieee80211_frequency_to_channel(channel->center_freq); 1100 u32 data0, data1, clock; 1101 int ret; 1102 1103 /* 1104 * Set the channel on the RF5111 radio 1105 */ 1106 data0 = data1 = 0; 1107 1108 if (channel->hw_value & CHANNEL_2GHZ) { 1109 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1110 ret = ath5k_hw_rf5111_chan2athchan( 1111 ieee80211_frequency_to_channel(channel->center_freq), 1112 &ath5k_channel_2ghz); 1113 if (ret) 1114 return ret; 1115 1116 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 1117 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 1118 << 5) | (1 << 4); 1119 } 1120 1121 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 1122 clock = 1; 1123 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 1124 (clock << 1) | (1 << 10) | 1; 1125 } else { 1126 clock = 0; 1127 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 1128 << 2) | (clock << 1) | (1 << 10) | 1; 1129 } 1130 1131 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 1132 AR5K_RF_BUFFER); 1133 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 1134 AR5K_RF_BUFFER_CONTROL_3); 1135 1136 return 0; 1137} 1138 1139/* 1140 * Set channel on 5112 and newer 1141 */ 1142static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1143 struct ieee80211_channel *channel) 1144{ 1145 u32 data, data0, data1, data2; 1146 u16 c; 1147 1148 data = data0 = data1 = data2 = 0; 1149 c = channel->center_freq; 1150 1151 if (c < 4800) { 1152 if (!((c - 2224) % 5)) { 1153 data0 = ((2 * (c - 704)) - 3040) / 10; 1154 data1 = 1; 1155 } else if (!((c - 2192) % 5)) { 1156 data0 = ((2 * (c - 672)) - 3040) / 10; 1157 data1 = 0; 1158 } else 1159 return -EINVAL; 1160 1161 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1162 } else if ((c % 5) != 2 || c > 5435) { 1163 if (!(c % 20) && c >= 5120) { 1164 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1165 data2 = ath5k_hw_bitswap(3, 2); 1166 } else if (!(c % 10)) { 1167 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1168 data2 = ath5k_hw_bitswap(2, 2); 1169 } else if (!(c % 5)) { 1170 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1171 data2 = ath5k_hw_bitswap(1, 2); 1172 } else 1173 return -EINVAL; 1174 } else { 1175 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1176 data2 = ath5k_hw_bitswap(0, 2); 1177 } 1178 1179 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1180 1181 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1182 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1183 1184 return 0; 1185} 1186 1187/* 1188 * Set the channel on the RF2425 1189 */ 1190static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1191 struct ieee80211_channel *channel) 1192{ 1193 u32 data, data0, data2; 1194 u16 c; 1195 1196 data = data0 = data2 = 0; 1197 c = channel->center_freq; 1198 1199 if (c < 4800) { 1200 data0 = ath5k_hw_bitswap((c - 2272), 8); 1201 data2 = 0; 1202 /* ? 5GHz ? */ 1203 } else if ((c % 5) != 2 || c > 5435) { 1204 if (!(c % 20) && c < 5120) 1205 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1206 else if (!(c % 10)) 1207 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1208 else if (!(c % 5)) 1209 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1210 else 1211 return -EINVAL; 1212 data2 = ath5k_hw_bitswap(1, 2); 1213 } else { 1214 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1215 data2 = ath5k_hw_bitswap(0, 2); 1216 } 1217 1218 data = (data0 << 4) | data2 << 2 | 0x1001; 1219 1220 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1221 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1222 1223 return 0; 1224} 1225 1226/* 1227 * Set a channel on the radio chip 1228 */ 1229static int ath5k_hw_channel(struct ath5k_hw *ah, 1230 struct ieee80211_channel *channel) 1231{ 1232 int ret; 1233 /* 1234 * Check bounds supported by the PHY (we don't care about regultory 1235 * restrictions at this point). Note: hw_value already has the band 1236 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1237 * of the band by that */ 1238 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1239 ATH5K_ERR(ah->ah_sc, 1240 "channel frequency (%u MHz) out of supported " 1241 "band range\n", 1242 channel->center_freq); 1243 return -EINVAL; 1244 } 1245 1246 /* 1247 * Set the channel and wait 1248 */ 1249 switch (ah->ah_radio) { 1250 case AR5K_RF5110: 1251 ret = ath5k_hw_rf5110_channel(ah, channel); 1252 break; 1253 case AR5K_RF5111: 1254 ret = ath5k_hw_rf5111_channel(ah, channel); 1255 break; 1256 case AR5K_RF2317: 1257 case AR5K_RF2425: 1258 ret = ath5k_hw_rf2425_channel(ah, channel); 1259 break; 1260 default: 1261 ret = ath5k_hw_rf5112_channel(ah, channel); 1262 break; 1263 } 1264 1265 if (ret) 1266 return ret; 1267 1268 /* Set JAPAN setting for channel 14 */ 1269 if (channel->center_freq == 2484) { 1270 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1271 AR5K_PHY_CCKTXCTL_JAPAN); 1272 } else { 1273 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1274 AR5K_PHY_CCKTXCTL_WORLD); 1275 } 1276 1277 ah->ah_current_channel = channel; 1278 1279 return 0; 1280} 1281 1282/*****************\ 1283 PHY calibration 1284\*****************/ 1285 1286static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1287{ 1288 s32 val; 1289 1290 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1291 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1292} 1293 1294void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1295{ 1296 int i; 1297 1298 ah->ah_nfcal_hist.index = 0; 1299 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1300 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1301} 1302 1303static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1304{ 1305 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1306 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1); 1307 hist->nfval[hist->index] = noise_floor; 1308} 1309 1310static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1311{ 1312 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1313 s16 tmp; 1314 int i, j; 1315 1316 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1317 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1318 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1319 if (sort[j] > sort[j-1]) { 1320 tmp = sort[j]; 1321 sort[j] = sort[j-1]; 1322 sort[j-1] = tmp; 1323 } 1324 } 1325 } 1326 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1327 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1328 "cal %d:%d\n", i, sort[i]); 1329 } 1330 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2]; 1331} 1332 1333/* 1334 * When we tell the hardware to perform a noise floor calibration 1335 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1336 * sample-and-hold the minimum noise level seen at the antennas. 1337 * This value is then stored in a ring buffer of recently measured 1338 * noise floor values so we have a moving window of the last few 1339 * samples. 1340 * 1341 * The median of the values in the history is then loaded into the 1342 * hardware for its own use for RSSI and CCA measurements. 1343 */ 1344void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1345{ 1346 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1347 u32 val; 1348 s16 nf, threshold; 1349 u8 ee_mode; 1350 1351 /* keep last value if calibration hasn't completed */ 1352 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1353 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1354 "NF did not complete in calibration window\n"); 1355 1356 return; 1357 } 1358 1359 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel); 1360 1361 /* completed NF calibration, test threshold */ 1362 nf = ath5k_hw_read_measured_noise_floor(ah); 1363 threshold = ee->ee_noise_floor_thr[ee_mode]; 1364 1365 if (nf > threshold) { 1366 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1367 "noise floor failure detected; " 1368 "read %d, threshold %d\n", 1369 nf, threshold); 1370 1371 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1372 } 1373 1374 ath5k_hw_update_nfcal_hist(ah, nf); 1375 nf = ath5k_hw_get_median_noise_floor(ah); 1376 1377 /* load noise floor (in .5 dBm) so the hardware will use it */ 1378 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1379 val |= (nf * 2) & AR5K_PHY_NF_M; 1380 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1381 1382 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1383 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1384 1385 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1386 0, false); 1387 1388 /* 1389 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1390 * so that we're not capped by the median we just loaded. 1391 * This will be used as the initial value for the next noise 1392 * floor calibration. 1393 */ 1394 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1395 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1396 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1397 AR5K_PHY_AGCCTL_NF_EN | 1398 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1399 AR5K_PHY_AGCCTL_NF); 1400 1401 ah->ah_noise_floor = nf; 1402 1403 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1404 "noise floor calibrated: %d\n", nf); 1405} 1406 1407/* 1408 * Perform a PHY calibration on RF5110 1409 * -Fix BPSK/QAM Constellation (I/Q correction) 1410 */ 1411static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1412 struct ieee80211_channel *channel) 1413{ 1414 u32 phy_sig, phy_agc, phy_sat, beacon; 1415 int ret; 1416 1417 /* 1418 * Disable beacons and RX/TX queues, wait 1419 */ 1420 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1421 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1422 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1423 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1424 1425 mdelay(2); 1426 1427 /* 1428 * Set the channel (with AGC turned off) 1429 */ 1430 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1431 udelay(10); 1432 ret = ath5k_hw_channel(ah, channel); 1433 1434 /* 1435 * Activate PHY and wait 1436 */ 1437 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1438 mdelay(1); 1439 1440 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1441 1442 if (ret) 1443 return ret; 1444 1445 /* 1446 * Calibrate the radio chip 1447 */ 1448 1449 /* Remember normal state */ 1450 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1451 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1452 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1453 1454 /* Update radio registers */ 1455 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1456 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1457 1458 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1459 AR5K_PHY_AGCCOARSE_LO)) | 1460 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1461 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1462 1463 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1464 AR5K_PHY_ADCSAT_THR)) | 1465 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1466 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1467 1468 udelay(20); 1469 1470 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1471 udelay(10); 1472 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1473 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1474 1475 mdelay(1); 1476 1477 /* 1478 * Enable calibration and wait until completion 1479 */ 1480 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1481 1482 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1483 AR5K_PHY_AGCCTL_CAL, 0, false); 1484 1485 /* Reset to normal state */ 1486 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1487 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1488 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1489 1490 if (ret) { 1491 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1492 channel->center_freq); 1493 return ret; 1494 } 1495 1496 /* 1497 * Re-enable RX/TX and beacons 1498 */ 1499 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1500 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1501 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1502 1503 return 0; 1504} 1505 1506/* 1507 * Perform I/Q calibration on RF5111/5112 and newer chips 1508 */ 1509static int 1510ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1511{ 1512 u32 i_pwr, q_pwr; 1513 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1514 int i; 1515 1516 if (!ah->ah_calibration || 1517 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1518 return 0; 1519 1520 /* Calibration has finished, get the results and re-run */ 1521 /* work around empty results which can apparently happen on 5212 */ 1522 for (i = 0; i <= 10; i++) { 1523 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1524 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1525 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1526 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1527 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1528 if (i_pwr && q_pwr) 1529 break; 1530 } 1531 1532 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1533 1534 if (ah->ah_version == AR5K_AR5211) 1535 q_coffd = q_pwr >> 6; 1536 else 1537 q_coffd = q_pwr >> 7; 1538 1539 /* protect against divide by 0 and loss of sign bits */ 1540 if (i_coffd == 0 || q_coffd < 2) 1541 return 0; 1542 1543 i_coff = (-iq_corr) / i_coffd; 1544 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1545 1546 if (ah->ah_version == AR5K_AR5211) 1547 q_coff = (i_pwr / q_coffd) - 64; 1548 else 1549 q_coff = (i_pwr / q_coffd) - 128; 1550 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1551 1552 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1553 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1554 i_coff, q_coff, i_coffd, q_coffd); 1555 1556 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1557 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1558 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1559 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1560 1561 /* Re-enable calibration -if we don't we'll commit 1562 * the same values again and again */ 1563 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1564 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1565 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1566 1567 return 0; 1568} 1569 1570/* 1571 * Perform a PHY calibration 1572 */ 1573int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1574 struct ieee80211_channel *channel) 1575{ 1576 int ret; 1577 1578 if (ah->ah_radio == AR5K_RF5110) 1579 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1580 else { 1581 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1582 ath5k_hw_request_rfgain_probe(ah); 1583 } 1584 1585 return ret; 1586} 1587 1588 1589/***************************\ 1590* Spur mitigation functions * 1591\***************************/ 1592 1593static void 1594ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1595 struct ieee80211_channel *channel) 1596{ 1597 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1598 u32 mag_mask[4] = {0, 0, 0, 0}; 1599 u32 pilot_mask[2] = {0, 0}; 1600 /* Note: fbin values are scaled up by 2 */ 1601 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1602 s32 spur_delta_phase, spur_freq_sigma_delta; 1603 s32 spur_offset, num_symbols_x16; 1604 u8 num_symbol_offsets, i, freq_band; 1605 1606 /* Convert current frequency to fbin value (the same way channels 1607 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1608 * up by 2 so we can compare it later */ 1609 if (channel->hw_value & CHANNEL_2GHZ) { 1610 chan_fbin = (channel->center_freq - 2300) * 10; 1611 freq_band = AR5K_EEPROM_BAND_2GHZ; 1612 } else { 1613 chan_fbin = (channel->center_freq - 4900) * 10; 1614 freq_band = AR5K_EEPROM_BAND_5GHZ; 1615 } 1616 1617 /* Check if any spur_chan_fbin from EEPROM is 1618 * within our current channel's spur detection range */ 1619 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1620 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1621 /* XXX: Half/Quarter channels ?*/ 1622 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 1623 spur_detection_window *= 2; 1624 1625 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1626 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1627 1628 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1629 * so it's zero if we got nothing from EEPROM */ 1630 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1631 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1632 break; 1633 } 1634 1635 if ((chan_fbin - spur_detection_window <= 1636 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1637 (chan_fbin + spur_detection_window >= 1638 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1639 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1640 break; 1641 } 1642 } 1643 1644 /* We need to enable spur filter for this channel */ 1645 if (spur_chan_fbin) { 1646 spur_offset = spur_chan_fbin - chan_fbin; 1647 /* 1648 * Calculate deltas: 1649 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1650 * spur_delta_phase -> spur_offset / chip_freq << 11 1651 * Note: Both values have 100Hz resolution 1652 */ 1653 switch (ah->ah_bwmode) { 1654 case AR5K_BWMODE_40MHZ: 1655 /* Both sample_freq and chip_freq are 80MHz */ 1656 spur_delta_phase = (spur_offset << 16) / 25; 1657 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1658 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2; 1659 break; 1660 case AR5K_BWMODE_10MHZ: 1661 /* Both sample_freq and chip_freq are 20MHz (?) */ 1662 spur_delta_phase = (spur_offset << 18) / 25; 1663 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1664 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2; 1665 case AR5K_BWMODE_5MHZ: 1666 /* Both sample_freq and chip_freq are 10MHz (?) */ 1667 spur_delta_phase = (spur_offset << 19) / 25; 1668 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1669 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4; 1670 default: 1671 if (channel->hw_value == CHANNEL_A) { 1672 /* Both sample_freq and chip_freq are 40MHz */ 1673 spur_delta_phase = (spur_offset << 17) / 25; 1674 spur_freq_sigma_delta = 1675 (spur_delta_phase >> 10); 1676 symbol_width = 1677 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1678 } else { 1679 /* sample_freq -> 40MHz chip_freq -> 44MHz 1680 * (for b compatibility) */ 1681 spur_delta_phase = (spur_offset << 17) / 25; 1682 spur_freq_sigma_delta = 1683 (spur_offset << 8) / 55; 1684 symbol_width = 1685 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1686 } 1687 break; 1688 } 1689 1690 /* Calculate pilot and magnitude masks */ 1691 1692 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1693 * and divide by symbol_width to find how many symbols we have 1694 * Note: number of symbols is scaled up by 16 */ 1695 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1696 1697 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1698 if (!(num_symbols_x16 & 0xF)) 1699 /* _X_ */ 1700 num_symbol_offsets = 3; 1701 else 1702 /* _xx_ */ 1703 num_symbol_offsets = 4; 1704 1705 for (i = 0; i < num_symbol_offsets; i++) { 1706 1707 /* Calculate pilot mask */ 1708 s32 curr_sym_off = 1709 (num_symbols_x16 / 16) + i + 25; 1710 1711 /* Pilot magnitude mask seems to be a way to 1712 * declare the boundaries for our detection 1713 * window or something, it's 2 for the middle 1714 * value(s) where the symbol is expected to be 1715 * and 1 on the boundary values */ 1716 u8 plt_mag_map = 1717 (i == 0 || i == (num_symbol_offsets - 1)) 1718 ? 1 : 2; 1719 1720 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1721 if (curr_sym_off <= 25) 1722 pilot_mask[0] |= 1 << curr_sym_off; 1723 else if (curr_sym_off >= 27) 1724 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1725 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1726 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1727 1728 /* Calculate magnitude mask (for viterbi decoder) */ 1729 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1730 mag_mask[0] |= 1731 plt_mag_map << (curr_sym_off + 1) * 2; 1732 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1733 mag_mask[1] |= 1734 plt_mag_map << (curr_sym_off - 15) * 2; 1735 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1736 mag_mask[2] |= 1737 plt_mag_map << (curr_sym_off - 31) * 2; 1738 else if (curr_sym_off >= 47 && curr_sym_off <= 53) 1739 mag_mask[3] |= 1740 plt_mag_map << (curr_sym_off - 47) * 2; 1741 1742 } 1743 1744 /* Write settings on hw to enable spur filter */ 1745 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1746 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1747 /* XXX: Self correlator also ? */ 1748 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1749 AR5K_PHY_IQ_PILOT_MASK_EN | 1750 AR5K_PHY_IQ_CHAN_MASK_EN | 1751 AR5K_PHY_IQ_SPUR_FILT_EN); 1752 1753 /* Set delta phase and freq sigma delta */ 1754 ath5k_hw_reg_write(ah, 1755 AR5K_REG_SM(spur_delta_phase, 1756 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1757 AR5K_REG_SM(spur_freq_sigma_delta, 1758 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1759 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1760 AR5K_PHY_TIMING_11); 1761 1762 /* Write pilot masks */ 1763 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1764 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1765 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1766 pilot_mask[1]); 1767 1768 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1769 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1770 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1771 pilot_mask[1]); 1772 1773 /* Write magnitude masks */ 1774 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1775 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1776 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1777 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1778 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1779 mag_mask[3]); 1780 1781 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1782 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1783 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1784 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1785 AR5K_PHY_BIN_MASK2_4_MASK_4, 1786 mag_mask[3]); 1787 1788 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1789 AR5K_PHY_IQ_SPUR_FILT_EN) { 1790 /* Clean up spur mitigation settings and disable fliter */ 1791 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1792 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1793 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1794 AR5K_PHY_IQ_PILOT_MASK_EN | 1795 AR5K_PHY_IQ_CHAN_MASK_EN | 1796 AR5K_PHY_IQ_SPUR_FILT_EN); 1797 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1798 1799 /* Clear pilot masks */ 1800 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1801 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1802 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1803 0); 1804 1805 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1806 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1807 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1808 0); 1809 1810 /* Clear magnitude masks */ 1811 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1812 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1813 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1814 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1815 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1816 0); 1817 1818 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1819 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1820 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1821 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1822 AR5K_PHY_BIN_MASK2_4_MASK_4, 1823 0); 1824 } 1825} 1826 1827 1828/*****************\ 1829* Antenna control * 1830\*****************/ 1831 1832static void /*TODO:Boundary check*/ 1833ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1834{ 1835 if (ah->ah_version != AR5K_AR5210) 1836 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1837} 1838 1839/* 1840 * Enable/disable fast rx antenna diversity 1841 */ 1842static void 1843ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1844{ 1845 switch (ee_mode) { 1846 case AR5K_EEPROM_MODE_11G: 1847 /* XXX: This is set to 1848 * disabled on initvals !!! */ 1849 case AR5K_EEPROM_MODE_11A: 1850 if (enable) 1851 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1852 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1853 else 1854 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1855 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1856 break; 1857 case AR5K_EEPROM_MODE_11B: 1858 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1859 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1860 break; 1861 default: 1862 return; 1863 } 1864 1865 if (enable) { 1866 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1867 AR5K_PHY_RESTART_DIV_GC, 4); 1868 1869 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1870 AR5K_PHY_FAST_ANT_DIV_EN); 1871 } else { 1872 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1873 AR5K_PHY_RESTART_DIV_GC, 0); 1874 1875 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1876 AR5K_PHY_FAST_ANT_DIV_EN); 1877 } 1878} 1879 1880void 1881ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 1882{ 1883 u8 ant0, ant1; 1884 1885 /* 1886 * In case a fixed antenna was set as default 1887 * use the same switch table twice. 1888 */ 1889 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1890 ant0 = ant1 = AR5K_ANT_SWTABLE_A; 1891 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1892 ant0 = ant1 = AR5K_ANT_SWTABLE_B; 1893 else { 1894 ant0 = AR5K_ANT_SWTABLE_A; 1895 ant1 = AR5K_ANT_SWTABLE_B; 1896 } 1897 1898 /* Set antenna idle switch table */ 1899 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 1900 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 1901 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | 1902 AR5K_PHY_ANT_CTL_TXRX_EN)); 1903 1904 /* Set antenna switch tables */ 1905 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], 1906 AR5K_PHY_ANT_SWITCH_TABLE_0); 1907 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], 1908 AR5K_PHY_ANT_SWITCH_TABLE_1); 1909} 1910 1911/* 1912 * Set antenna operating mode 1913 */ 1914void 1915ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1916{ 1917 struct ieee80211_channel *channel = ah->ah_current_channel; 1918 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1919 bool use_def_for_sg; 1920 int ee_mode; 1921 u8 def_ant, tx_ant; 1922 u32 sta_id1 = 0; 1923 1924 /* if channel is not initialized yet we can't set the antennas 1925 * so just store the mode. it will be set on the next reset */ 1926 if (channel == NULL) { 1927 ah->ah_ant_mode = ant_mode; 1928 return; 1929 } 1930 1931 def_ant = ah->ah_def_ant; 1932 1933 ee_mode = ath5k_eeprom_mode_from_channel(channel); 1934 if (ee_mode < 0) { 1935 ATH5K_ERR(ah->ah_sc, 1936 "invalid channel: %d\n", channel->center_freq); 1937 return; 1938 } 1939 1940 switch (ant_mode) { 1941 case AR5K_ANTMODE_DEFAULT: 1942 tx_ant = 0; 1943 use_def_for_tx = false; 1944 update_def_on_tx = false; 1945 use_def_for_rts = false; 1946 use_def_for_sg = false; 1947 fast_div = true; 1948 break; 1949 case AR5K_ANTMODE_FIXED_A: 1950 def_ant = 1; 1951 tx_ant = 1; 1952 use_def_for_tx = true; 1953 update_def_on_tx = false; 1954 use_def_for_rts = true; 1955 use_def_for_sg = true; 1956 fast_div = false; 1957 break; 1958 case AR5K_ANTMODE_FIXED_B: 1959 def_ant = 2; 1960 tx_ant = 2; 1961 use_def_for_tx = true; 1962 update_def_on_tx = false; 1963 use_def_for_rts = true; 1964 use_def_for_sg = true; 1965 fast_div = false; 1966 break; 1967 case AR5K_ANTMODE_SINGLE_AP: 1968 def_ant = 1; /* updated on tx */ 1969 tx_ant = 0; 1970 use_def_for_tx = true; 1971 update_def_on_tx = true; 1972 use_def_for_rts = true; 1973 use_def_for_sg = true; 1974 fast_div = true; 1975 break; 1976 case AR5K_ANTMODE_SECTOR_AP: 1977 tx_ant = 1; /* variable */ 1978 use_def_for_tx = false; 1979 update_def_on_tx = false; 1980 use_def_for_rts = true; 1981 use_def_for_sg = false; 1982 fast_div = false; 1983 break; 1984 case AR5K_ANTMODE_SECTOR_STA: 1985 tx_ant = 1; /* variable */ 1986 use_def_for_tx = true; 1987 update_def_on_tx = false; 1988 use_def_for_rts = true; 1989 use_def_for_sg = false; 1990 fast_div = true; 1991 break; 1992 case AR5K_ANTMODE_DEBUG: 1993 def_ant = 1; 1994 tx_ant = 2; 1995 use_def_for_tx = false; 1996 update_def_on_tx = false; 1997 use_def_for_rts = false; 1998 use_def_for_sg = false; 1999 fast_div = false; 2000 break; 2001 default: 2002 return; 2003 } 2004 2005 ah->ah_tx_ant = tx_ant; 2006 ah->ah_ant_mode = ant_mode; 2007 ah->ah_def_ant = def_ant; 2008 2009 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 2010 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 2011 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 2012 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 2013 2014 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 2015 2016 if (sta_id1) 2017 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 2018 2019 ath5k_hw_set_antenna_switch(ah, ee_mode); 2020 /* Note: set diversity before default antenna 2021 * because it won't work correctly */ 2022 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 2023 ath5k_hw_set_def_antenna(ah, def_ant); 2024} 2025 2026 2027/****************\ 2028* TX power setup * 2029\****************/ 2030 2031/* 2032 * Helper functions 2033 */ 2034 2035/* 2036 * Do linear interpolation between two given (x, y) points 2037 */ 2038static s16 2039ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2040 s16 y_left, s16 y_right) 2041{ 2042 s16 ratio, result; 2043 2044 /* Avoid divide by zero and skip interpolation 2045 * if we have the same point */ 2046 if ((x_left == x_right) || (y_left == y_right)) 2047 return y_left; 2048 2049 /* 2050 * Since we use ints and not fps, we need to scale up in 2051 * order to get a sane ratio value (or else we 'll eg. get 2052 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2053 * to have some accuracy both for 0.5 and 0.25 steps. 2054 */ 2055 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 2056 2057 /* Now scale down to be in range */ 2058 result = y_left + (ratio * (target - x_left) / 100); 2059 2060 return result; 2061} 2062 2063/* 2064 * Find vertical boundary (min pwr) for the linear PCDAC curve. 2065 * 2066 * Since we have the top of the curve and we draw the line below 2067 * until we reach 1 (1 pcdac step) we need to know which point 2068 * (x value) that is so that we don't go below y axis and have negative 2069 * pcdac values when creating the curve, or fill the table with zeroes. 2070 */ 2071static s16 2072ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2073 const s16 *pwrL, const s16 *pwrR) 2074{ 2075 s8 tmp; 2076 s16 min_pwrL, min_pwrR; 2077 s16 pwr_i; 2078 2079 /* Some vendors write the same pcdac value twice !!! */ 2080 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 2081 return max(pwrL[0], pwrR[0]); 2082 2083 if (pwrL[0] == pwrL[1]) 2084 min_pwrL = pwrL[0]; 2085 else { 2086 pwr_i = pwrL[0]; 2087 do { 2088 pwr_i--; 2089 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2090 pwrL[0], pwrL[1], 2091 stepL[0], stepL[1]); 2092 } while (tmp > 1); 2093 2094 min_pwrL = pwr_i; 2095 } 2096 2097 if (pwrR[0] == pwrR[1]) 2098 min_pwrR = pwrR[0]; 2099 else { 2100 pwr_i = pwrR[0]; 2101 do { 2102 pwr_i--; 2103 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2104 pwrR[0], pwrR[1], 2105 stepR[0], stepR[1]); 2106 } while (tmp > 1); 2107 2108 min_pwrR = pwr_i; 2109 } 2110 2111 /* Keep the right boundary so that it works for both curves */ 2112 return max(min_pwrL, min_pwrR); 2113} 2114 2115/* 2116 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2117 * Power to PCDAC curve. 2118 * 2119 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2120 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2121 * PCDAC/PDADC step for each curve is 64 but we can write more than 2122 * one curves on hw so we can go up to 128 (which is the max step we 2123 * can write on the final table). 2124 * 2125 * We write y values (PCDAC/PDADC steps) on hw. 2126 */ 2127static void 2128ath5k_create_power_curve(s16 pmin, s16 pmax, 2129 const s16 *pwr, const u8 *vpd, 2130 u8 num_points, 2131 u8 *vpd_table, u8 type) 2132{ 2133 u8 idx[2] = { 0, 1 }; 2134 s16 pwr_i = 2*pmin; 2135 int i; 2136 2137 if (num_points < 2) 2138 return; 2139 2140 /* We want the whole line, so adjust boundaries 2141 * to cover the entire power range. Note that 2142 * power values are already 0.25dB so no need 2143 * to multiply pwr_i by 2 */ 2144 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2145 pwr_i = pmin; 2146 pmin = 0; 2147 pmax = 63; 2148 } 2149 2150 /* Find surrounding turning points (TPs) 2151 * and interpolate between them */ 2152 for (i = 0; (i <= (u16) (pmax - pmin)) && 2153 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2154 2155 /* We passed the right TP, move to the next set of TPs 2156 * if we pass the last TP, extrapolate above using the last 2157 * two TPs for ratio */ 2158 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2159 idx[0]++; 2160 idx[1]++; 2161 } 2162 2163 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2164 pwr[idx[0]], pwr[idx[1]], 2165 vpd[idx[0]], vpd[idx[1]]); 2166 2167 /* Increase by 0.5dB 2168 * (0.25 dB units) */ 2169 pwr_i += 2; 2170 } 2171} 2172 2173/* 2174 * Get the surrounding per-channel power calibration piers 2175 * for a given frequency so that we can interpolate between 2176 * them and come up with an apropriate dataset for our current 2177 * channel. 2178 */ 2179static void 2180ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2181 struct ieee80211_channel *channel, 2182 struct ath5k_chan_pcal_info **pcinfo_l, 2183 struct ath5k_chan_pcal_info **pcinfo_r) 2184{ 2185 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2186 struct ath5k_chan_pcal_info *pcinfo; 2187 u8 idx_l, idx_r; 2188 u8 mode, max, i; 2189 u32 target = channel->center_freq; 2190 2191 idx_l = 0; 2192 idx_r = 0; 2193 2194 if (!(channel->hw_value & CHANNEL_OFDM)) { 2195 pcinfo = ee->ee_pwr_cal_b; 2196 mode = AR5K_EEPROM_MODE_11B; 2197 } else if (channel->hw_value & CHANNEL_2GHZ) { 2198 pcinfo = ee->ee_pwr_cal_g; 2199 mode = AR5K_EEPROM_MODE_11G; 2200 } else { 2201 pcinfo = ee->ee_pwr_cal_a; 2202 mode = AR5K_EEPROM_MODE_11A; 2203 } 2204 max = ee->ee_n_piers[mode] - 1; 2205 2206 /* Frequency is below our calibrated 2207 * range. Use the lowest power curve 2208 * we have */ 2209 if (target < pcinfo[0].freq) { 2210 idx_l = idx_r = 0; 2211 goto done; 2212 } 2213 2214 /* Frequency is above our calibrated 2215 * range. Use the highest power curve 2216 * we have */ 2217 if (target > pcinfo[max].freq) { 2218 idx_l = idx_r = max; 2219 goto done; 2220 } 2221 2222 /* Frequency is inside our calibrated 2223 * channel range. Pick the surrounding 2224 * calibration piers so that we can 2225 * interpolate */ 2226 for (i = 0; i <= max; i++) { 2227 2228 /* Frequency matches one of our calibration 2229 * piers, no need to interpolate, just use 2230 * that calibration pier */ 2231 if (pcinfo[i].freq == target) { 2232 idx_l = idx_r = i; 2233 goto done; 2234 } 2235 2236 /* We found a calibration pier that's above 2237 * frequency, use this pier and the previous 2238 * one to interpolate */ 2239 if (target < pcinfo[i].freq) { 2240 idx_r = i; 2241 idx_l = idx_r - 1; 2242 goto done; 2243 } 2244 } 2245 2246done: 2247 *pcinfo_l = &pcinfo[idx_l]; 2248 *pcinfo_r = &pcinfo[idx_r]; 2249} 2250 2251/* 2252 * Get the surrounding per-rate power calibration data 2253 * for a given frequency and interpolate between power 2254 * values to set max target power supported by hw for 2255 * each rate. 2256 */ 2257static void 2258ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2259 struct ieee80211_channel *channel, 2260 struct ath5k_rate_pcal_info *rates) 2261{ 2262 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2263 struct ath5k_rate_pcal_info *rpinfo; 2264 u8 idx_l, idx_r; 2265 u8 mode, max, i; 2266 u32 target = channel->center_freq; 2267 2268 idx_l = 0; 2269 idx_r = 0; 2270 2271 if (!(channel->hw_value & CHANNEL_OFDM)) { 2272 rpinfo = ee->ee_rate_tpwr_b; 2273 mode = AR5K_EEPROM_MODE_11B; 2274 } else if (channel->hw_value & CHANNEL_2GHZ) { 2275 rpinfo = ee->ee_rate_tpwr_g; 2276 mode = AR5K_EEPROM_MODE_11G; 2277 } else { 2278 rpinfo = ee->ee_rate_tpwr_a; 2279 mode = AR5K_EEPROM_MODE_11A; 2280 } 2281 max = ee->ee_rate_target_pwr_num[mode] - 1; 2282 2283 /* Get the surrounding calibration 2284 * piers - same as above */ 2285 if (target < rpinfo[0].freq) { 2286 idx_l = idx_r = 0; 2287 goto done; 2288 } 2289 2290 if (target > rpinfo[max].freq) { 2291 idx_l = idx_r = max; 2292 goto done; 2293 } 2294 2295 for (i = 0; i <= max; i++) { 2296 2297 if (rpinfo[i].freq == target) { 2298 idx_l = idx_r = i; 2299 goto done; 2300 } 2301 2302 if (target < rpinfo[i].freq) { 2303 idx_r = i; 2304 idx_l = idx_r - 1; 2305 goto done; 2306 } 2307 } 2308 2309done: 2310 /* Now interpolate power value, based on the frequency */ 2311 rates->freq = target; 2312 2313 rates->target_power_6to24 = 2314 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2315 rpinfo[idx_r].freq, 2316 rpinfo[idx_l].target_power_6to24, 2317 rpinfo[idx_r].target_power_6to24); 2318 2319 rates->target_power_36 = 2320 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2321 rpinfo[idx_r].freq, 2322 rpinfo[idx_l].target_power_36, 2323 rpinfo[idx_r].target_power_36); 2324 2325 rates->target_power_48 = 2326 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2327 rpinfo[idx_r].freq, 2328 rpinfo[idx_l].target_power_48, 2329 rpinfo[idx_r].target_power_48); 2330 2331 rates->target_power_54 = 2332 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2333 rpinfo[idx_r].freq, 2334 rpinfo[idx_l].target_power_54, 2335 rpinfo[idx_r].target_power_54); 2336} 2337 2338/* 2339 * Get the max edge power for this channel if 2340 * we have such data from EEPROM's Conformance Test 2341 * Limits (CTL), and limit max power if needed. 2342 */ 2343static void 2344ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2345 struct ieee80211_channel *channel) 2346{ 2347 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2348 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2349 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2350 u8 *ctl_val = ee->ee_ctl; 2351 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2352 s16 edge_pwr = 0; 2353 u8 rep_idx; 2354 u8 i, ctl_mode; 2355 u8 ctl_idx = 0xFF; 2356 u32 target = channel->center_freq; 2357 2358 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2359 2360 switch (channel->hw_value & CHANNEL_MODES) { 2361 case CHANNEL_A: 2362 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2363 ctl_mode |= AR5K_CTL_TURBO; 2364 else 2365 ctl_mode |= AR5K_CTL_11A; 2366 break; 2367 case CHANNEL_G: 2368 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2369 ctl_mode |= AR5K_CTL_TURBOG; 2370 else 2371 ctl_mode |= AR5K_CTL_11G; 2372 break; 2373 case CHANNEL_B: 2374 ctl_mode |= AR5K_CTL_11B; 2375 break; 2376 case CHANNEL_XR: 2377 /* Fall through */ 2378 default: 2379 return; 2380 } 2381 2382 for (i = 0; i < ee->ee_ctls; i++) { 2383 if (ctl_val[i] == ctl_mode) { 2384 ctl_idx = i; 2385 break; 2386 } 2387 } 2388 2389 /* If we have a CTL dataset available grab it and find the 2390 * edge power for our frequency */ 2391 if (ctl_idx == 0xFF) 2392 return; 2393 2394 /* Edge powers are sorted by frequency from lower 2395 * to higher. Each CTL corresponds to 8 edge power 2396 * measurements. */ 2397 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2398 2399 /* Don't do boundaries check because we 2400 * might have more that one bands defined 2401 * for this mode */ 2402 2403 /* Get the edge power that's closer to our 2404 * frequency */ 2405 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2406 rep_idx += i; 2407 if (target <= rep[rep_idx].freq) 2408 edge_pwr = (s16) rep[rep_idx].edge; 2409 } 2410 2411 if (edge_pwr) 2412 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 2413} 2414 2415 2416/* 2417 * Power to PCDAC table functions 2418 */ 2419 2420/* 2421 * Fill Power to PCDAC table on RF5111 2422 * 2423 * No further processing is needed for RF5111, the only thing we have to 2424 * do is fill the values below and above calibration range since eeprom data 2425 * may not cover the entire PCDAC table. 2426 */ 2427static void 2428ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2429 s16 *table_max) 2430{ 2431 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2432 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2433 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2434 s16 min_pwr, max_pwr; 2435 2436 /* Get table boundaries */ 2437 min_pwr = table_min[0]; 2438 pcdac_0 = pcdac_tmp[0]; 2439 2440 max_pwr = table_max[0]; 2441 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2442 2443 /* Extrapolate below minimum using pcdac_0 */ 2444 pcdac_i = 0; 2445 for (i = 0; i < min_pwr; i++) 2446 pcdac_out[pcdac_i++] = pcdac_0; 2447 2448 /* Copy values from pcdac_tmp */ 2449 pwr_idx = min_pwr; 2450 for (i = 0 ; pwr_idx <= max_pwr && 2451 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2452 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2453 pwr_idx++; 2454 } 2455 2456 /* Extrapolate above maximum */ 2457 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2458 pcdac_out[pcdac_i++] = pcdac_n; 2459 2460} 2461 2462/* 2463 * Combine available XPD Curves and fill Linear Power to PCDAC table 2464 * on RF5112 2465 * 2466 * RFX112 can have up to 2 curves (one for low txpower range and one for 2467 * higher txpower range). We need to put them both on pcdac_out and place 2468 * them in the correct location. In case we only have one curve available 2469 * just fit it on pcdac_out (it's supposed to cover the entire range of 2470 * available pwr levels since it's always the higher power curve). Extrapolate 2471 * below and above final table if needed. 2472 */ 2473static void 2474ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2475 s16 *table_max, u8 pdcurves) 2476{ 2477 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2478 u8 *pcdac_low_pwr; 2479 u8 *pcdac_high_pwr; 2480 u8 *pcdac_tmp; 2481 u8 pwr; 2482 s16 max_pwr_idx; 2483 s16 min_pwr_idx; 2484 s16 mid_pwr_idx = 0; 2485 /* Edge flag turs on the 7nth bit on the PCDAC 2486 * to delcare the higher power curve (force values 2487 * to be greater than 64). If we only have one curve 2488 * we don't need to set this, if we have 2 curves and 2489 * fill the table backwards this can also be used to 2490 * switch from higher power curve to lower power curve */ 2491 u8 edge_flag; 2492 int i; 2493 2494 /* When we have only one curve available 2495 * that's the higher power curve. If we have 2496 * two curves the first is the high power curve 2497 * and the next is the low power curve. */ 2498 if (pdcurves > 1) { 2499 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2500 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2501 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2502 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2503 2504 /* If table size goes beyond 31.5dB, keep the 2505 * upper 31.5dB range when setting tx power. 2506 * Note: 126 = 31.5 dB in quarter dB steps */ 2507 if (table_max[0] - table_min[1] > 126) 2508 min_pwr_idx = table_max[0] - 126; 2509 else 2510 min_pwr_idx = table_min[1]; 2511 2512 /* Since we fill table backwards 2513 * start from high power curve */ 2514 pcdac_tmp = pcdac_high_pwr; 2515 2516 edge_flag = 0x40; 2517 } else { 2518 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2519 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2520 min_pwr_idx = table_min[0]; 2521 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2522 pcdac_tmp = pcdac_high_pwr; 2523 edge_flag = 0; 2524 } 2525 2526 /* This is used when setting tx power*/ 2527 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 2528 2529 /* Fill Power to PCDAC table backwards */ 2530 pwr = max_pwr_idx; 2531 for (i = 63; i >= 0; i--) { 2532 /* Entering lower power range, reset 2533 * edge flag and set pcdac_tmp to lower 2534 * power curve.*/ 2535 if (edge_flag == 0x40 && 2536 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2537 edge_flag = 0x00; 2538 pcdac_tmp = pcdac_low_pwr; 2539 pwr = mid_pwr_idx/2; 2540 } 2541 2542 /* Don't go below 1, extrapolate below if we have 2543 * already swithced to the lower power curve -or 2544 * we only have one curve and edge_flag is zero 2545 * anyway */ 2546 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2547 while (i >= 0) { 2548 pcdac_out[i] = pcdac_out[i + 1]; 2549 i--; 2550 } 2551 break; 2552 } 2553 2554 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2555 2556 /* Extrapolate above if pcdac is greater than 2557 * 126 -this can happen because we OR pcdac_out 2558 * value with edge_flag on high power curve */ 2559 if (pcdac_out[i] > 126) 2560 pcdac_out[i] = 126; 2561 2562 /* Decrease by a 0.5dB step */ 2563 pwr--; 2564 } 2565} 2566 2567/* Write PCDAC values on hw */ 2568static void 2569ath5k_write_pcdac_table(struct ath5k_hw *ah) 2570{ 2571 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2572 int i; 2573 2574 /* 2575 * Write TX power values 2576 */ 2577 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2578 ath5k_hw_reg_write(ah, 2579 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2580 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2581 AR5K_PHY_PCDAC_TXPOWER(i)); 2582 } 2583} 2584 2585 2586/* 2587 * Power to PDADC table functions 2588 */ 2589 2590/* 2591 * Set the gain boundaries and create final Power to PDADC table 2592 * 2593 * We can have up to 4 pd curves, we need to do a simmilar process 2594 * as we do for RF5112. This time we don't have an edge_flag but we 2595 * set the gain boundaries on a separate register. 2596 */ 2597static void 2598ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2599 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2600{ 2601 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2602 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2603 u8 *pdadc_tmp; 2604 s16 pdadc_0; 2605 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2606 u8 pd_gain_overlap; 2607 2608 /* Note: Register value is initialized on initvals 2609 * there is no feedback from hw. 2610 * XXX: What about pd_gain_overlap from EEPROM ? */ 2611 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2612 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2613 2614 /* Create final PDADC table */ 2615 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2616 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2617 2618 if (pdg == pdcurves - 1) 2619 /* 2 dB boundary stretch for last 2620 * (higher power) curve */ 2621 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2622 else 2623 /* Set gain boundary in the middle 2624 * between this curve and the next one */ 2625 gain_boundaries[pdg] = 2626 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2627 2628 /* Sanity check in case our 2 db stretch got out of 2629 * range. */ 2630 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2631 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2632 2633 /* For the first curve (lower power) 2634 * start from 0 dB */ 2635 if (pdg == 0) 2636 pdadc_0 = 0; 2637 else 2638 /* For the other curves use the gain overlap */ 2639 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2640 pd_gain_overlap; 2641 2642 /* Force each power step to be at least 0.5 dB */ 2643 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2644 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2645 else 2646 pwr_step = 1; 2647 2648 /* If pdadc_0 is negative, we need to extrapolate 2649 * below this pdgain by a number of pwr_steps */ 2650 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2651 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2652 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2653 pdadc_0++; 2654 } 2655 2656 /* Set last pwr level, using gain boundaries */ 2657 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2658 /* Limit it to be inside pwr range */ 2659 table_size = pwr_max[pdg] - pwr_min[pdg]; 2660 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2661 2662 /* Fill pdadc_out table */ 2663 while (pdadc_0 < max_idx && pdadc_i < 128) 2664 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2665 2666 /* Need to extrapolate above this pdgain? */ 2667 if (pdadc_n <= max_idx) 2668 continue; 2669 2670 /* Force each power step to be at least 0.5 dB */ 2671 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2672 pwr_step = pdadc_tmp[table_size - 1] - 2673 pdadc_tmp[table_size - 2]; 2674 else 2675 pwr_step = 1; 2676 2677 /* Extrapolate above */ 2678 while ((pdadc_0 < (s16) pdadc_n) && 2679 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2680 s16 tmp = pdadc_tmp[table_size - 1] + 2681 (pdadc_0 - max_idx) * pwr_step; 2682 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2683 pdadc_0++; 2684 } 2685 } 2686 2687 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2688 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2689 pdg++; 2690 } 2691 2692 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2693 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2694 pdadc_i++; 2695 } 2696 2697 /* Set gain boundaries */ 2698 ath5k_hw_reg_write(ah, 2699 AR5K_REG_SM(pd_gain_overlap, 2700 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2701 AR5K_REG_SM(gain_boundaries[0], 2702 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2703 AR5K_REG_SM(gain_boundaries[1], 2704 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2705 AR5K_REG_SM(gain_boundaries[2], 2706 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2707 AR5K_REG_SM(gain_boundaries[3], 2708 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2709 AR5K_PHY_TPC_RG5); 2710 2711 /* Used for setting rate power table */ 2712 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2713 2714} 2715 2716/* Write PDADC values on hw */ 2717static void 2718ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) 2719{ 2720 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2721 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2722 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2723 u8 pdcurves = ee->ee_pd_gains[ee_mode]; 2724 u32 reg; 2725 u8 i; 2726 2727 /* Select the right pdgain curves */ 2728 2729 /* Clear current settings */ 2730 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2731 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2732 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2733 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2734 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2735 2736 /* 2737 * Use pd_gains curve from eeprom 2738 * 2739 * This overrides the default setting from initvals 2740 * in case some vendors (e.g. Zcomax) don't use the default 2741 * curves. If we don't honor their settings we 'll get a 2742 * 5dB (1 * gain overlap ?) drop. 2743 */ 2744 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2745 2746 switch (pdcurves) { 2747 case 3: 2748 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2749 /* Fall through */ 2750 case 2: 2751 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2752 /* Fall through */ 2753 case 1: 2754 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2755 break; 2756 } 2757 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2758 2759 /* 2760 * Write TX power values 2761 */ 2762 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2763 ath5k_hw_reg_write(ah, 2764 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2765 ((pdadc_out[4*i + 1] & 0xff) << 8) | 2766 ((pdadc_out[4*i + 2] & 0xff) << 16) | 2767 ((pdadc_out[4*i + 3] & 0xff) << 24), 2768 AR5K_PHY_PDADC_TXPOWER(i)); 2769 } 2770} 2771 2772 2773/* 2774 * Common code for PCDAC/PDADC tables 2775 */ 2776 2777/* 2778 * This is the main function that uses all of the above 2779 * to set PCDAC/PDADC table on hw for the current channel. 2780 * This table is used for tx power calibration on the basband, 2781 * without it we get weird tx power levels and in some cases 2782 * distorted spectral mask 2783 */ 2784static int 2785ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2786 struct ieee80211_channel *channel, 2787 u8 ee_mode, u8 type) 2788{ 2789 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2790 struct ath5k_chan_pcal_info *pcinfo_L; 2791 struct ath5k_chan_pcal_info *pcinfo_R; 2792 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2793 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2794 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2795 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2796 u8 *tmpL; 2797 u8 *tmpR; 2798 u32 target = channel->center_freq; 2799 int pdg, i; 2800 2801 /* Get surounding freq piers for this channel */ 2802 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2803 &pcinfo_L, 2804 &pcinfo_R); 2805 2806 /* Loop over pd gain curves on 2807 * surounding freq piers by index */ 2808 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2809 2810 /* Fill curves in reverse order 2811 * from lower power (max gain) 2812 * to higher power. Use curve -> idx 2813 * backmapping we did on eeprom init */ 2814 u8 idx = pdg_curve_to_idx[pdg]; 2815 2816 /* Grab the needed curves by index */ 2817 pdg_L = &pcinfo_L->pd_curves[idx]; 2818 pdg_R = &pcinfo_R->pd_curves[idx]; 2819 2820 /* Initialize the temp tables */ 2821 tmpL = ah->ah_txpower.tmpL[pdg]; 2822 tmpR = ah->ah_txpower.tmpR[pdg]; 2823 2824 /* Set curve's x boundaries and create 2825 * curves so that they cover the same 2826 * range (if we don't do that one table 2827 * will have values on some range and the 2828 * other one won't have any so interpolation 2829 * will fail) */ 2830 table_min[pdg] = min(pdg_L->pd_pwr[0], 2831 pdg_R->pd_pwr[0]) / 2; 2832 2833 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2834 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2835 2836 /* Now create the curves on surrounding channels 2837 * and interpolate if needed to get the final 2838 * curve for this gain on this channel */ 2839 switch (type) { 2840 case AR5K_PWRTABLE_LINEAR_PCDAC: 2841 /* Override min/max so that we don't loose 2842 * accuracy (don't divide by 2) */ 2843 table_min[pdg] = min(pdg_L->pd_pwr[0], 2844 pdg_R->pd_pwr[0]); 2845 2846 table_max[pdg] = 2847 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2848 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2849 2850 /* Override minimum so that we don't get 2851 * out of bounds while extrapolating 2852 * below. Don't do this when we have 2 2853 * curves and we are on the high power curve 2854 * because table_min is ok in this case */ 2855 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2856 2857 table_min[pdg] = 2858 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2859 pdg_R->pd_step, 2860 pdg_L->pd_pwr, 2861 pdg_R->pd_pwr); 2862 2863 /* Don't go too low because we will 2864 * miss the upper part of the curve. 2865 * Note: 126 = 31.5dB (max power supported) 2866 * in 0.25dB units */ 2867 if (table_max[pdg] - table_min[pdg] > 126) 2868 table_min[pdg] = table_max[pdg] - 126; 2869 } 2870 2871 /* Fall through */ 2872 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2873 case AR5K_PWRTABLE_PWR_TO_PDADC: 2874 2875 ath5k_create_power_curve(table_min[pdg], 2876 table_max[pdg], 2877 pdg_L->pd_pwr, 2878 pdg_L->pd_step, 2879 pdg_L->pd_points, tmpL, type); 2880 2881 /* We are in a calibration 2882 * pier, no need to interpolate 2883 * between freq piers */ 2884 if (pcinfo_L == pcinfo_R) 2885 continue; 2886 2887 ath5k_create_power_curve(table_min[pdg], 2888 table_max[pdg], 2889 pdg_R->pd_pwr, 2890 pdg_R->pd_step, 2891 pdg_R->pd_points, tmpR, type); 2892 break; 2893 default: 2894 return -EINVAL; 2895 } 2896 2897 /* Interpolate between curves 2898 * of surounding freq piers to 2899 * get the final curve for this 2900 * pd gain. Re-use tmpL for interpolation 2901 * output */ 2902 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2903 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2904 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2905 (s16) pcinfo_L->freq, 2906 (s16) pcinfo_R->freq, 2907 (s16) tmpL[i], 2908 (s16) tmpR[i]); 2909 } 2910 } 2911 2912 /* Now we have a set of curves for this 2913 * channel on tmpL (x range is table_max - table_min 2914 * and y values are tmpL[pdg][]) sorted in the same 2915 * order as EEPROM (because we've used the backmapping). 2916 * So for RF5112 it's from higher power to lower power 2917 * and for RF2413 it's from lower power to higher power. 2918 * For RF5111 we only have one curve. */ 2919 2920 /* Fill min and max power levels for this 2921 * channel by interpolating the values on 2922 * surounding channels to complete the dataset */ 2923 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2924 (s16) pcinfo_L->freq, 2925 (s16) pcinfo_R->freq, 2926 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2927 2928 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2929 (s16) pcinfo_L->freq, 2930 (s16) pcinfo_R->freq, 2931 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2932 2933 /* Fill PCDAC/PDADC table */ 2934 switch (type) { 2935 case AR5K_PWRTABLE_LINEAR_PCDAC: 2936 /* For RF5112 we can have one or two curves 2937 * and each curve covers a certain power lvl 2938 * range so we need to do some more processing */ 2939 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2940 ee->ee_pd_gains[ee_mode]); 2941 2942 /* Set txp.offset so that we can 2943 * match max power value with max 2944 * table index */ 2945 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2946 break; 2947 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2948 /* We are done for RF5111 since it has only 2949 * one curve, just fit the curve on the table */ 2950 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2951 2952 /* No rate powertable adjustment for RF5111 */ 2953 ah->ah_txpower.txp_min_idx = 0; 2954 ah->ah_txpower.txp_offset = 0; 2955 break; 2956 case AR5K_PWRTABLE_PWR_TO_PDADC: 2957 /* Set PDADC boundaries and fill 2958 * final PDADC table */ 2959 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 2960 ee->ee_pd_gains[ee_mode]); 2961 2962 /* Set txp.offset, note that table_min 2963 * can be negative */ 2964 ah->ah_txpower.txp_offset = table_min[0]; 2965 break; 2966 default: 2967 return -EINVAL; 2968 } 2969 2970 ah->ah_txpower.txp_setup = true; 2971 2972 return 0; 2973} 2974 2975/* Write power table for current channel to hw */ 2976static void 2977ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) 2978{ 2979 if (type == AR5K_PWRTABLE_PWR_TO_PDADC) 2980 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); 2981 else 2982 ath5k_write_pcdac_table(ah); 2983} 2984 2985/* 2986 * Per-rate tx power setting 2987 * 2988 * This is the code that sets the desired tx power (below 2989 * maximum) on hw for each rate (we also have TPC that sets 2990 * power per packet). We do that by providing an index on the 2991 * PCDAC/PDADC table we set up. 2992 */ 2993 2994/* 2995 * Set rate power table 2996 * 2997 * For now we only limit txpower based on maximum tx power 2998 * supported by hw (what's inside rate_info). We need to limit 2999 * this even more, based on regulatory domain etc. 3000 * 3001 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 3002 * and is indexed as follows: 3003 * rates[0] - rates[7] -> OFDM rates 3004 * rates[8] - rates[14] -> CCK rates 3005 * rates[15] -> XR rates (they all have the same power) 3006 */ 3007static void 3008ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 3009 struct ath5k_rate_pcal_info *rate_info, 3010 u8 ee_mode) 3011{ 3012 unsigned int i; 3013 u16 *rates; 3014 3015 /* max_pwr is power level we got from driver/user in 0.5dB 3016 * units, switch to 0.25dB units so we can compare */ 3017 max_pwr *= 2; 3018 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 3019 3020 /* apply rate limits */ 3021 rates = ah->ah_txpower.txp_rates_power_table; 3022 3023 /* OFDM rates 6 to 24Mb/s */ 3024 for (i = 0; i < 5; i++) 3025 rates[i] = min(max_pwr, rate_info->target_power_6to24); 3026 3027 /* Rest OFDM rates */ 3028 rates[5] = min(rates[0], rate_info->target_power_36); 3029 rates[6] = min(rates[0], rate_info->target_power_48); 3030 rates[7] = min(rates[0], rate_info->target_power_54); 3031 3032 /* CCK rates */ 3033 /* 1L */ 3034 rates[8] = min(rates[0], rate_info->target_power_6to24); 3035 /* 2L */ 3036 rates[9] = min(rates[0], rate_info->target_power_36); 3037 /* 2S */ 3038 rates[10] = min(rates[0], rate_info->target_power_36); 3039 /* 5L */ 3040 rates[11] = min(rates[0], rate_info->target_power_48); 3041 /* 5S */ 3042 rates[12] = min(rates[0], rate_info->target_power_48); 3043 /* 11L */ 3044 rates[13] = min(rates[0], rate_info->target_power_54); 3045 /* 11S */ 3046 rates[14] = min(rates[0], rate_info->target_power_54); 3047 3048 /* XR rates */ 3049 rates[15] = min(rates[0], rate_info->target_power_6to24); 3050 3051 /* CCK rates have different peak to average ratio 3052 * so we have to tweak their power so that gainf 3053 * correction works ok. For this we use OFDM to 3054 * CCK delta from eeprom */ 3055 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 3056 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 3057 for (i = 8; i <= 15; i++) 3058 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 3059 3060 /* Now that we have all rates setup use table offset to 3061 * match the power range set by user with the power indices 3062 * on PCDAC/PDADC table */ 3063 for (i = 0; i < 16; i++) { 3064 rates[i] += ah->ah_txpower.txp_offset; 3065 /* Don't get out of bounds */ 3066 if (rates[i] > 63) 3067 rates[i] = 63; 3068 } 3069 3070 /* Min/max in 0.25dB units */ 3071 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 3072 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; 3073 ah->ah_txpower.txp_ofdm = rates[7]; 3074} 3075 3076 3077/* 3078 * Set transmission power 3079 */ 3080static int 3081ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3082 u8 txpower) 3083{ 3084 struct ath5k_rate_pcal_info rate_info; 3085 struct ieee80211_channel *curr_channel = ah->ah_current_channel; 3086 int ee_mode; 3087 u8 type; 3088 int ret; 3089 3090 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3091 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 3092 return -EINVAL; 3093 } 3094 3095 ee_mode = ath5k_eeprom_mode_from_channel(channel); 3096 if (ee_mode < 0) { 3097 ATH5K_ERR(ah->ah_sc, 3098 "invalid channel: %d\n", channel->center_freq); 3099 return -EINVAL; 3100 } 3101 3102 /* Initialize TX power table */ 3103 switch (ah->ah_radio) { 3104 case AR5K_RF5110: 3105 /* TODO */ 3106 return 0; 3107 case AR5K_RF5111: 3108 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3109 break; 3110 case AR5K_RF5112: 3111 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3112 break; 3113 case AR5K_RF2413: 3114 case AR5K_RF5413: 3115 case AR5K_RF2316: 3116 case AR5K_RF2317: 3117 case AR5K_RF2425: 3118 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3119 break; 3120 default: 3121 return -EINVAL; 3122 } 3123 3124 /* 3125 * If we don't change channel/mode skip tx powertable calculation 3126 * and use the cached one. 3127 */ 3128 if (!ah->ah_txpower.txp_setup || 3129 (channel->hw_value != curr_channel->hw_value) || 3130 (channel->center_freq != curr_channel->center_freq)) { 3131 /* Reset TX power values */ 3132 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 3133 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 3134 3135 /* Calculate the powertable */ 3136 ret = ath5k_setup_channel_powertable(ah, channel, 3137 ee_mode, type); 3138 if (ret) 3139 return ret; 3140 } 3141 3142 /* Write table on hw */ 3143 ath5k_write_channel_powertable(ah, ee_mode, type); 3144 3145 /* Limit max power if we have a CTL available */ 3146 ath5k_get_max_ctl_power(ah, channel); 3147 3148 /* FIXME: Antenna reduction stuff */ 3149 3150 /* FIXME: Limit power on turbo modes */ 3151 3152 /* FIXME: TPC scale reduction */ 3153 3154 /* Get surounding channels for per-rate power table 3155 * calibration */ 3156 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3157 3158 /* Setup rate power table */ 3159 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3160 3161 /* Write rate power table on hw */ 3162 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3163 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3164 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3165 3166 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3167 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3168 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3169 3170 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3171 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3172 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3173 3174 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3175 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3176 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3177 3178 /* FIXME: TPC support */ 3179 if (ah->ah_txpower.txp_tpc) { 3180 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3181 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3182 3183 ath5k_hw_reg_write(ah, 3184 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3185 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3186 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3187 AR5K_TPC); 3188 } else { 3189 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3190 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3191 } 3192 3193 return 0; 3194} 3195 3196int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3197{ 3198 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3199 "changing txpower to %d\n", txpower); 3200 3201 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); 3202} 3203 3204/*************\ 3205 Init function 3206\*************/ 3207 3208int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3209 u8 mode, bool fast) 3210{ 3211 struct ieee80211_channel *curr_channel; 3212 int ret, i; 3213 u32 phy_tst1; 3214 ret = 0; 3215 3216 /* 3217 * Sanity check for fast flag 3218 * Don't try fast channel change when changing modulation 3219 * mode/band. We check for chip compatibility on 3220 * ath5k_hw_reset. 3221 */ 3222 curr_channel = ah->ah_current_channel; 3223 if (fast && (channel->hw_value != curr_channel->hw_value)) 3224 return -EINVAL; 3225 3226 /* 3227 * On fast channel change we only set the synth parameters 3228 * while PHY is running, enable calibration and skip the rest. 3229 */ 3230 if (fast) { 3231 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3232 AR5K_PHY_RFBUS_REQ_REQUEST); 3233 for (i = 0; i < 100; i++) { 3234 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) 3235 break; 3236 udelay(5); 3237 } 3238 /* Failed */ 3239 if (i >= 100) 3240 return -EIO; 3241 } 3242 3243 /* 3244 * Set TX power 3245 * 3246 * Note: We need to do that before we set 3247 * RF buffer settings on 5211/5212+ so that we 3248 * properly set curve indices. 3249 */ 3250 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ? 3251 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER); 3252 if (ret) 3253 return ret; 3254 3255 /* 3256 * For 5210 we do all initialization using 3257 * initvals, so we don't have to modify 3258 * any settings (5210 also only supports 3259 * a/aturbo modes) 3260 */ 3261 if ((ah->ah_version != AR5K_AR5210) && !fast) { 3262 3263 /* 3264 * Write initial RF gain settings 3265 * This should work for both 5111/5112 3266 */ 3267 ret = ath5k_hw_rfgain_init(ah, channel->band); 3268 if (ret) 3269 return ret; 3270 3271 mdelay(1); 3272 3273 /* 3274 * Write RF buffer 3275 */ 3276 ret = ath5k_hw_rfregs_init(ah, channel, mode); 3277 if (ret) 3278 return ret; 3279 3280 /* Write OFDM timings on 5212*/ 3281 if (ah->ah_version == AR5K_AR5212 && 3282 channel->hw_value & CHANNEL_OFDM) { 3283 3284 ret = ath5k_hw_write_ofdm_timings(ah, channel); 3285 if (ret) 3286 return ret; 3287 3288 /* Spur info is available only from EEPROM versions 3289 * greater than 5.3, but the EEPROM routines will use 3290 * static values for older versions */ 3291 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 3292 ath5k_hw_set_spur_mitigation_filter(ah, 3293 channel); 3294 } 3295 3296 /*Enable/disable 802.11b mode on 5111 3297 (enable 2111 frequency converter + CCK)*/ 3298 if (ah->ah_radio == AR5K_RF5111) { 3299 if (mode == AR5K_MODE_11B) 3300 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 3301 AR5K_TXCFG_B_MODE); 3302 else 3303 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 3304 AR5K_TXCFG_B_MODE); 3305 } 3306 3307 } else if (ah->ah_version == AR5K_AR5210) { 3308 mdelay(1); 3309 /* Disable phy and wait */ 3310 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 3311 mdelay(1); 3312 } 3313 3314 /* Set channel on PHY */ 3315 ret = ath5k_hw_channel(ah, channel); 3316 if (ret) 3317 return ret; 3318 3319 /* 3320 * Enable the PHY and wait until completion 3321 * This includes BaseBand and Synthesizer 3322 * activation. 3323 */ 3324 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 3325 3326 /* 3327 * On 5211+ read activation -> rx delay 3328 * and use it. 3329 */ 3330 if (ah->ah_version != AR5K_AR5210) { 3331 u32 delay; 3332 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 3333 AR5K_PHY_RX_DELAY_M; 3334 delay = (channel->hw_value & CHANNEL_CCK) ? 3335 ((delay << 2) / 22) : (delay / 10); 3336 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) 3337 delay = delay << 1; 3338 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) 3339 delay = delay << 2; 3340 /* XXX: /2 on turbo ? Let's be safe 3341 * for now */ 3342 udelay(100 + delay); 3343 } else { 3344 mdelay(1); 3345 } 3346 3347 if (fast) 3348 /* 3349 * Release RF Bus grant 3350 */ 3351 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3352 AR5K_PHY_RFBUS_REQ_REQUEST); 3353 else { 3354 /* 3355 * Perform ADC test to see if baseband is ready 3356 * Set tx hold and check adc test register 3357 */ 3358 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 3359 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 3360 for (i = 0; i <= 20; i++) { 3361 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 3362 break; 3363 udelay(200); 3364 } 3365 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 3366 } 3367 3368 /* 3369 * Start automatic gain control calibration 3370 * 3371 * During AGC calibration RX path is re-routed to 3372 * a power detector so we don't receive anything. 3373 * 3374 * This method is used to calibrate some static offsets 3375 * used together with on-the fly I/Q calibration (the 3376 * one performed via ath5k_hw_phy_calibrate), which doesn't 3377 * interrupt rx path. 3378 * 3379 * While rx path is re-routed to the power detector we also 3380 * start a noise floor calibration to measure the 3381 * card's noise floor (the noise we measure when we are not 3382 * transmitting or receiving anything). 3383 * 3384 * If we are in a noisy environment, AGC calibration may time 3385 * out and/or noise floor calibration might timeout. 3386 */ 3387 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3388 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 3389 3390 /* At the same time start I/Q calibration for QAM constellation 3391 * -no need for CCK- */ 3392 ah->ah_calibration = false; 3393 if (!(mode == AR5K_MODE_11B)) { 3394 ah->ah_calibration = true; 3395 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 3396 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 3397 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 3398 AR5K_PHY_IQ_RUN); 3399 } 3400 3401 /* Wait for gain calibration to finish (we check for I/Q calibration 3402 * during ath5k_phy_calibrate) */ 3403 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3404 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3405 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 3406 channel->center_freq); 3407 } 3408 3409 /* Restore antenna mode */ 3410 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3411 3412 return ret; 3413} 3414