target.h revision bdf5396be177b689c00ae6ebed00d13fafaed36e
1bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* 2bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Copyright (c) 2004-2010 Atheros Communications Inc. 3bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 4bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 8bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 16bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 17bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#ifndef TARGET_H 18bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define TARGET_H 19bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 20bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_BOARD_DATA_SZ 1024 21bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_BOARD_EXT_DATA_SZ 768 22bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 2331024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6004_BOARD_DATA_SZ 7168 2431024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6004_BOARD_EXT_DATA_SZ 0 2531024d99003486c90c793dea58b55f7920f0488bKevin Fang 26bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RESET_CONTROL_ADDRESS 0x00000000 27bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RESET_CONTROL_COLD_RST 0x00000100 28bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RESET_CONTROL_MBOX_RST 0x00000004 29bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 30bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_CLOCK_STANDARD_S 0 31bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_CLOCK_STANDARD 0x00000003 32bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_CLOCK_ADDRESS 0x00000020 33bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 34bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CLOCK_CONTROL_ADDRESS 0x00000028 35bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CLOCK_CONTROL_LF_CLK32_S 2 36bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CLOCK_CONTROL_LF_CLK32 0x00000004 37bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 38bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define SYSTEM_SLEEP_ADDRESS 0x000000c4 39bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define SYSTEM_SLEEP_DISABLE_S 0 40bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define SYSTEM_SLEEP_DISABLE 0x00000001 41bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 42bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define LPO_CAL_ADDRESS 0x000000e0 43bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define LPO_CAL_ENABLE_S 20 44bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define LPO_CAL_ENABLE 0x00100000 45bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 46bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_PIN10_ADDRESS 0x00000050 47bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_PIN11_ADDRESS 0x00000054 48bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_PIN12_ADDRESS 0x00000058 49bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_PIN13_ADDRESS 0x0000005c 50bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 51bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_ADDRESS 0x00000400 52bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_ERROR_S 7 53bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_ERROR 0x00000080 54bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 55bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_CPU_S 6 56bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_CPU 0x00000040 57bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 58bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_COUNTER_S 4 59bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HOST_INT_STATUS_COUNTER 0x00000010 60bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 61bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_INT_STATUS_ADDRESS 0x00000401 62bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 63bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_ADDRESS 0x00000402 64bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_WAKEUP_S 2 65bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_WAKEUP 0x00000004 66bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 67bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_RX_UNDERFLOW_S 1 68bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_RX_UNDERFLOW 0x00000002 69bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 70bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_TX_OVERFLOW_S 0 71bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_INT_STATUS_TX_OVERFLOW 0x00000001 72bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 73bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_ADDRESS 0x00000403 74bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_COUNTER_S 0 75bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_COUNTER 0x000000ff 76bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 77bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 78bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 79bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_ADDRESS 0x00000418 80bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_ERROR_S 7 81bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_ERROR 0x00000080 82bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 83bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_CPU_S 6 84bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_CPU 0x00000040 85bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 86bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_INT_S 5 87bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_INT 0x00000020 88bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_COUNTER_S 4 89bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_COUNTER 0x00000010 90bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 91bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_MBOX_DATA_S 0 92bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define INT_STATUS_ENABLE_MBOX_DATA 0x0000000f 93bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 94bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 95bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_INT_STATUS_ENABLE_BIT_S 0 96bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_INT_STATUS_ENABLE_BIT 0x000000ff 97bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 98bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a 99bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S 1 100bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_RX_UNDERFLOW 0x00000002 101bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 102bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_TX_OVERFLOW_S 0 103bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ERROR_STATUS_ENABLE_TX_OVERFLOW 0x00000001 104bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 105bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b 106bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_ENABLE_BIT_S 0 107bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNTER_INT_STATUS_ENABLE_BIT 0x000000ff 108bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 109bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNT_ADDRESS 0x00000420 110bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 111bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define COUNT_DEC_ADDRESS 0x00000440 112bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 113bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define WINDOW_DATA_ADDRESS 0x00000474 114bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 115bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define WINDOW_READ_ADDR_ADDRESS 0x0000047c 116bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_DBG_SEL_ADDRESS 0x00000483 117bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define CPU_DBG_ADDRESS 0x00000484 118bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 119bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define LOCAL_SCRATCH_ADDRESS 0x000000c0 120bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ATH6KL_OPTION_SLEEP_DISABLE 0x08 121bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 122bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define RTC_BASE_ADDRESS 0x00004000 123bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define GPIO_BASE_ADDRESS 0x00014000 124bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define MBOX_BASE_ADDRESS 0x00018000 125bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ANALOG_INTF_BASE_ADDRESS 0x0001c000 126bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 127bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* real name of the register is unknown */ 128bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define ATH6KL_ANALOG_PLL_REGISTER (ANALOG_INTF_BASE_ADDRESS + 0x284) 129bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 130bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define SM(f, v) (((v) << f##_S) & f) 131bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define MS(f, v) (((v) & f) >> f##_S) 132bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 133bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* 134bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the 135bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * host_interest structure. 136bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 137bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Host Interest is shared between Host and Target in order to coordinate 138bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * between the two, and is intended to remain constant (with additions only 139bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * at the end). 140bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 14131024d99003486c90c793dea58b55f7920f0488bKevin Fang#define ATH6KL_AR6003_HI_START_ADDR 0x00540600 14231024d99003486c90c793dea58b55f7920f0488bKevin Fang#define ATH6KL_AR6004_HI_START_ADDR 0x00400800 143bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 144bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* 145bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * These are items that the Host may need to access 146bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * via BMI or via the Diagnostic Window. The position 147bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * of items in this structure must remain constant. 148bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * across firmware revisions! 149bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 150bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Types for each item must be fixed size across target and host platforms. 151bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * The structure is used only to calculate offset for each register with 152bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * HI_ITEM() macro, no values are stored to it. 153bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 154bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * More items may be added at the end. 155bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 156bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valostruct host_interest { 157bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 158bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Pointer to application-defined area, if any. 159bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Set by Target application during startup. 160bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 161bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_app_host_interest; /* 0x00 */ 162bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 163bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Pointer to register dump area, valid after Target crash. */ 164bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_failure_state; /* 0x04 */ 165bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 166bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Pointer to debug logging header */ 167bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dbglog_hdr; /* 0x08 */ 168bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 169bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_unused1; /* 0x0c */ 170bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 171bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 172bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * General-purpose flag bits, similar to ATH6KL_OPTION_* flags. 173bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Can be used by application rather than by OS. 174bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 175bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_option_flag; /* 0x10 */ 176bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 177bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 178bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Boolean that determines whether or not to 179bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * display messages on the serial port. 180bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 181bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_serial_enable; /* 0x14 */ 182bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 183bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Start address of DataSet index, if any */ 184bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dset_list_head; /* 0x18 */ 185bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 186bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Override Target application start address */ 187bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_app_start; /* 0x1c */ 188bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 189bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Clock and voltage tuning */ 190bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_skip_clock_init; /* 0x20 */ 191bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_core_clock_setting; /* 0x24 */ 192bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_cpu_clock_setting; /* 0x28 */ 193bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_system_sleep_setting; /* 0x2c */ 194bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_xtal_control_setting; /* 0x30 */ 195bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ 196bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ 197bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_ref_voltage_trim_setting; /* 0x3c */ 198bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_clock_info; /* 0x40 */ 199bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 200bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 201bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Flash configuration overrides, used only 202bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * when firmware is not executing from flash. 203bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * (When using flash, modify the global variables 204bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * with equivalent names.) 205bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 206bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_bank0_addr_value; /* 0x44 */ 207bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_bank0_read_value; /* 0x48 */ 208bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_bank0_write_value; /* 0x4c */ 209bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_bank0_config_value; /* 0x50 */ 210bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 211bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Pointer to Board Data */ 212bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_board_data; /* 0x54 */ 213bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_board_data_initialized; /* 0x58 */ 214bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 215bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dset_ram_index_tbl; /* 0x5c */ 216bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 217bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_desired_baud_rate; /* 0x60 */ 218bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dbglog_config; /* 0x64 */ 219bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_end_ram_reserve_sz; /* 0x68 */ 220bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_mbox_io_block_sz; /* 0x6c */ 221bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 222bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_num_bpatch_streams; /* 0x70 -- unused */ 223bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_mbox_isr_yield_limit; /* 0x74 */ 224bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 225bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_refclk_hz; /* 0x78 */ 226bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_ext_clk_detected; /* 0x7c */ 227bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dbg_uart_txpin; /* 0x80 */ 228bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_dbg_uart_rxpin; /* 0x84 */ 229bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_baud; /* 0x88 */ 230bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_pin_assignments; /* 0x8C */ 231bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 232bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts 233bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * pin 234bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 235bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_baud_scale_val; /* 0x90 */ 236bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_baud_step_val; /* 0x94 */ 237bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 238bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_allocram_start; /* 0x98 */ 239bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_allocram_sz; /* 0x9c */ 240bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_bridge_flags; /* 0xa0 */ 241bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_support_pins; /* 0xa4 */ 242bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 243bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * NOTE: byte [0] = RESET pin (bit 7 is polarity), 244bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * bytes[1]..bytes[3] are for future use 245bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 246bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ 247bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 248bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high 249bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * [31:16]: wakeup timeout in ms 250bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 251bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 252bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Pointer to extended board data */ 253bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_board_ext_data; /* 0xac */ 254bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_board_ext_data_config; /* 0xb0 */ 255bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 256bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 257bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Bit [0] : valid 258bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Bit[31:16: size 259bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 260bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 261bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * hi_reset_flag is used to do some stuff when target reset. 262bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * such as restore app_start after warm reset or 263bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * preserve host Interest area, or preserve ROM data, literals etc. 264bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 265bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_reset_flag; /* 0xb4 */ 266bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* indicate hi_reset_flag is valid */ 267bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_reset_flag_valid; /* 0xb8 */ 268bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ 269bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 270bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * 0xbc - [31:0]: idle timeout in ms 271bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 272bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* ACS flags */ 273bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_acs_flags; /* 0xc0 */ 274bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_console_flags; /* 0xc4 */ 275bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_nvram_state; /* 0xc8 */ 276bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_option_flag2; /* 0xcc */ 277bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 278bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* If non-zero, override values sent to Host in WMI_READY event. */ 279bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_sw_version_override; /* 0xd0 */ 280bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_abi_version_override; /* 0xd4 */ 281bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 282bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* 283bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * Percentage of high priority RX traffic to total expected RX traffic - 284bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo * applicable only to ar6004 285bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo */ 286bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ 287bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 288bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* test applications flags */ 289bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_test_apps_related ; /* 0xdc */ 290bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* location of test script */ 291bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_ota_testscript; /* 0xe0 */ 292bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* location of CAL data */ 293bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_cal_data; /* 0xe4 */ 294bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo /* Number of packet log buffers */ 295bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo u32 hi_pktlog_num_buffers; /* 0xe8 */ 296bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 297bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo} __packed; 298bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 299bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_ITEM(item) offsetof(struct host_interest, item) 300bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 301bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 302bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 303bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_MODE_IBSS 0x0 304bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_MODE_BSS_STA 0x1 305bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_MODE_AP 0x2 306bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 307bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_NUM_DEV_SHIFT 0x9 308bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 309bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_BRIDGE_SHIFT 0x04 310bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 311bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* Fw Mode/SubMode Mask 312bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo|------------------------------------------------------------------------------| 313bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo| SUB | SUB | SUB | SUB | | | | 314bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0| 315bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) 316bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo|------------------------------------------------------------------------------| 317bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo*/ 318bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define HI_OPTION_FW_MODE_SHIFT 0xC 319bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 320bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo/* Convert a Target virtual address into a Target physical address */ 32131024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) 32231024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6004_VTOP(vaddr) (vaddr) 32331024d99003486c90c793dea58b55f7920f0488bKevin Fang 32431024d99003486c90c793dea58b55f7920f0488bKevin Fang#define TARG_VTOP(target_type, vaddr) \ 32531024d99003486c90c793dea58b55f7920f0488bKevin Fang (((target_type) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \ 32631024d99003486c90c793dea58b55f7920f0488bKevin Fang (((target_type) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : 0)) 327bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 328bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV2_APP_START_OVERRIDE 0x944C00 329bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV2_APP_LOAD_ADDRESS 0x543180 330bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV2_BOARD_EXT_DATA_ADDRESS 0x57E500 331bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV2_DATASET_PATCH_ADDRESS 0x57e884 332bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV2_RAM_RESERVE_SIZE 6912 333bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 334bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV3_APP_START_OVERRIDE 0x945d00 335bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000 336bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330 337bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74 338bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#define AR6003_REV3_RAM_RESERVE_SIZE 512 339bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo 34031024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6004_REV1_BOARD_DATA_ADDRESS 0x435400 34131024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6004_REV1_BOARD_EXT_DATA_ADDRESS 0x437000 34231024d99003486c90c793dea58b55f7920f0488bKevin Fang#define AR6004_REV1_RAM_RESERVE_SIZE 11264 343bdf5396be177b689c00ae6ebed00d13fafaed36eKalle Valo 344bdf5396be177b689c00ae6ebed00d13fafaed36eKalle Valo#define ATH6KL_FWLOG_PAYLOAD_SIZE 1500 345bdf5396be177b689c00ae6ebed00d13fafaed36eKalle Valo 346bdcd81707973cf8aa9305337166f8ee842a050d4Kalle Valo#endif 347