ar9002_phy.c revision ae0c40314a86c5c942d32d9cbbc9f96d70839935
1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17/** 18 * DOC: Programming Atheros 802.11n analog front end radios 19 * 20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express 21 * devices have either an external AR2133 analog front end radio for single 22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual 23 * band 2.4 GHz / 5 GHz communication. 24 * 25 * All devices after the AR5416 and AR5418 family starting with the AR9280 26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded 27 * into a single-chip and require less programming. 28 * 29 * The following single-chips exist with a respective embedded radio: 30 * 31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe 32 * AR9281 - 11n single-band 1x2 MIMO for PCIe 33 * AR9285 - 11n single-band 1x1 for PCIe 34 * AR9287 - 11n single-band 2x2 MIMO for PCIe 35 * 36 * AR9220 - 11n dual-band 2x2 MIMO for PCI 37 * AR9223 - 11n single-band 2x2 MIMO for PCI 38 * 39 * AR9287 - 11n single-band 1x1 MIMO for USB 40 */ 41 42#include "hw.h" 43#include "ar9002_phy.h" 44 45/** 46 * ar9002_hw_set_channel - set channel on single-chip device 47 * @ah: atheros hardware structure 48 * @chan: 49 * 50 * This is the function to change channel on single-chip devices, that is 51 * all devices after ar9280. 52 * 53 * This function takes the channel value in MHz and sets 54 * hardware channel value. Assumes writes have been enabled to analog bus. 55 * 56 * Actual Expression, 57 * 58 * For 2GHz channel, 59 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 60 * (freq_ref = 40MHz) 61 * 62 * For 5GHz channel, 63 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) 64 * (freq_ref = 40MHz/(24>>amodeRefSel)) 65 */ 66static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 67{ 68 u16 bMode, fracMode, aModeRefSel = 0; 69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; 70 struct chan_centers centers; 71 u32 refDivA = 24; 72 73 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 74 freq = centers.synth_center; 75 76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); 77 reg32 &= 0xc0000000; 78 79 if (freq < 4800) { /* 2 GHz, fractional mode */ 80 u32 txctl; 81 int regWrites = 0; 82 83 bMode = 1; 84 fracMode = 1; 85 aModeRefSel = 0; 86 channelSel = CHANSEL_2G(freq); 87 88 if (AR_SREV_9287_11_OR_LATER(ah)) { 89 if (freq == 2484) { 90 /* Enable channel spreading for channel 14 */ 91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, 92 1, regWrites); 93 } else { 94 REG_WRITE_ARRAY(&ah->iniCckfirNormal, 95 1, regWrites); 96 } 97 } else { 98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 99 if (freq == 2484) { 100 /* Enable channel spreading for channel 14 */ 101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 102 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 103 } else { 104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 105 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 106 } 107 } 108 } else { 109 bMode = 0; 110 fracMode = 0; 111 112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { 113 case 0: 114 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) 115 aModeRefSel = 0; 116 else if ((freq % 20) == 0) 117 aModeRefSel = 3; 118 else if ((freq % 10) == 0) 119 aModeRefSel = 2; 120 if (aModeRefSel) 121 break; 122 case 1: 123 default: 124 aModeRefSel = 0; 125 /* 126 * Enable 2G (fractional) mode for channels 127 * which are 5MHz spaced. 128 */ 129 fracMode = 1; 130 refDivA = 1; 131 channelSel = CHANSEL_5G(freq); 132 133 /* RefDivA setting */ 134 ath9k_hw_analog_shift_rmw(ah, AR_AN_SYNTH9, 135 AR_AN_SYNTH9_REFDIVA, 136 AR_AN_SYNTH9_REFDIVA_S, refDivA); 137 138 } 139 140 if (!fracMode) { 141 ndiv = (freq * (refDivA >> aModeRefSel)) / 60; 142 channelSel = ndiv & 0x1ff; 143 channelFrac = (ndiv & 0xfffffe00) * 2; 144 channelSel = (channelSel << 17) | channelFrac; 145 } 146 } 147 148 reg32 = reg32 | 149 (bMode << 29) | 150 (fracMode << 28) | (aModeRefSel << 26) | (channelSel); 151 152 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 153 154 ah->curchan = chan; 155 156 return 0; 157} 158 159/** 160 * ar9002_hw_spur_mitigate - convert baseband spur frequency 161 * @ah: atheros hardware structure 162 * @chan: 163 * 164 * For single-chip solutions. Converts to baseband spur frequency given the 165 * input channel frequency and compute register settings below. 166 */ 167static void ar9002_hw_spur_mitigate(struct ath_hw *ah, 168 struct ath9k_channel *chan) 169{ 170 int bb_spur = AR_NO_SPUR; 171 int freq; 172 int bin, cur_bin; 173 int bb_spur_off, spur_subchannel_sd; 174 int spur_freq_sd; 175 int spur_delta_phase; 176 int denominator; 177 int upper, lower, cur_vit_mask; 178 int tmp, newVal; 179 int i; 180 static const int pilot_mask_reg[4] = { 181 AR_PHY_TIMING7, AR_PHY_TIMING8, 182 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 183 }; 184 static const int chan_mask_reg[4] = { 185 AR_PHY_TIMING9, AR_PHY_TIMING10, 186 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 187 }; 188 static const int inc[4] = { 0, 100, 0, 0 }; 189 struct chan_centers centers; 190 191 int8_t mask_m[123]; 192 int8_t mask_p[123]; 193 int8_t mask_amt; 194 int tmp_mask; 195 int cur_bb_spur; 196 bool is2GHz = IS_CHAN_2GHZ(chan); 197 198 memset(&mask_m, 0, sizeof(int8_t) * 123); 199 memset(&mask_p, 0, sizeof(int8_t) * 123); 200 201 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 202 freq = centers.synth_center; 203 204 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 205 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 206 207 if (AR_NO_SPUR == cur_bb_spur) 208 break; 209 210 if (is2GHz) 211 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 212 else 213 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 214 215 cur_bb_spur = cur_bb_spur - freq; 216 217 if (IS_CHAN_HT40(chan)) { 218 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 219 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 220 bb_spur = cur_bb_spur; 221 break; 222 } 223 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 224 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 225 bb_spur = cur_bb_spur; 226 break; 227 } 228 } 229 230 if (AR_NO_SPUR == bb_spur) { 231 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, 232 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 233 return; 234 } else { 235 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, 236 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 237 } 238 239 bin = bb_spur * 320; 240 241 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 242 243 ENABLE_REGWRITE_BUFFER(ah); 244 245 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 246 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 247 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 248 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 249 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); 250 251 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 252 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 253 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 254 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 255 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 256 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 257 258 if (IS_CHAN_HT40(chan)) { 259 if (bb_spur < 0) { 260 spur_subchannel_sd = 1; 261 bb_spur_off = bb_spur + 10; 262 } else { 263 spur_subchannel_sd = 0; 264 bb_spur_off = bb_spur - 10; 265 } 266 } else { 267 spur_subchannel_sd = 0; 268 bb_spur_off = bb_spur; 269 } 270 271 if (IS_CHAN_HT40(chan)) 272 spur_delta_phase = 273 ((bb_spur * 262144) / 274 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 275 else 276 spur_delta_phase = 277 ((bb_spur * 524288) / 278 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 279 280 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40; 281 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 282 283 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 284 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 285 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 286 REG_WRITE(ah, AR_PHY_TIMING11, newVal); 287 288 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 289 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 290 291 cur_bin = -6000; 292 upper = bin + 100; 293 lower = bin - 100; 294 295 for (i = 0; i < 4; i++) { 296 int pilot_mask = 0; 297 int chan_mask = 0; 298 int bp = 0; 299 for (bp = 0; bp < 30; bp++) { 300 if ((cur_bin > lower) && (cur_bin < upper)) { 301 pilot_mask = pilot_mask | 0x1 << bp; 302 chan_mask = chan_mask | 0x1 << bp; 303 } 304 cur_bin += 100; 305 } 306 cur_bin += inc[i]; 307 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 308 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 309 } 310 311 cur_vit_mask = 6100; 312 upper = bin + 120; 313 lower = bin - 120; 314 315 for (i = 0; i < 123; i++) { 316 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 317 318 /* workaround for gcc bug #37014 */ 319 volatile int tmp_v = abs(cur_vit_mask - bin); 320 321 if (tmp_v < 75) 322 mask_amt = 1; 323 else 324 mask_amt = 0; 325 if (cur_vit_mask < 0) 326 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 327 else 328 mask_p[cur_vit_mask / 100] = mask_amt; 329 } 330 cur_vit_mask -= 100; 331 } 332 333 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 334 | (mask_m[48] << 26) | (mask_m[49] << 24) 335 | (mask_m[50] << 22) | (mask_m[51] << 20) 336 | (mask_m[52] << 18) | (mask_m[53] << 16) 337 | (mask_m[54] << 14) | (mask_m[55] << 12) 338 | (mask_m[56] << 10) | (mask_m[57] << 8) 339 | (mask_m[58] << 6) | (mask_m[59] << 4) 340 | (mask_m[60] << 2) | (mask_m[61] << 0); 341 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 342 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 343 344 tmp_mask = (mask_m[31] << 28) 345 | (mask_m[32] << 26) | (mask_m[33] << 24) 346 | (mask_m[34] << 22) | (mask_m[35] << 20) 347 | (mask_m[36] << 18) | (mask_m[37] << 16) 348 | (mask_m[48] << 14) | (mask_m[39] << 12) 349 | (mask_m[40] << 10) | (mask_m[41] << 8) 350 | (mask_m[42] << 6) | (mask_m[43] << 4) 351 | (mask_m[44] << 2) | (mask_m[45] << 0); 352 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 353 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 354 355 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 356 | (mask_m[18] << 26) | (mask_m[18] << 24) 357 | (mask_m[20] << 22) | (mask_m[20] << 20) 358 | (mask_m[22] << 18) | (mask_m[22] << 16) 359 | (mask_m[24] << 14) | (mask_m[24] << 12) 360 | (mask_m[25] << 10) | (mask_m[26] << 8) 361 | (mask_m[27] << 6) | (mask_m[28] << 4) 362 | (mask_m[29] << 2) | (mask_m[30] << 0); 363 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 364 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 365 366 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 367 | (mask_m[2] << 26) | (mask_m[3] << 24) 368 | (mask_m[4] << 22) | (mask_m[5] << 20) 369 | (mask_m[6] << 18) | (mask_m[7] << 16) 370 | (mask_m[8] << 14) | (mask_m[9] << 12) 371 | (mask_m[10] << 10) | (mask_m[11] << 8) 372 | (mask_m[12] << 6) | (mask_m[13] << 4) 373 | (mask_m[14] << 2) | (mask_m[15] << 0); 374 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 375 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 376 377 tmp_mask = (mask_p[15] << 28) 378 | (mask_p[14] << 26) | (mask_p[13] << 24) 379 | (mask_p[12] << 22) | (mask_p[11] << 20) 380 | (mask_p[10] << 18) | (mask_p[9] << 16) 381 | (mask_p[8] << 14) | (mask_p[7] << 12) 382 | (mask_p[6] << 10) | (mask_p[5] << 8) 383 | (mask_p[4] << 6) | (mask_p[3] << 4) 384 | (mask_p[2] << 2) | (mask_p[1] << 0); 385 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 386 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 387 388 tmp_mask = (mask_p[30] << 28) 389 | (mask_p[29] << 26) | (mask_p[28] << 24) 390 | (mask_p[27] << 22) | (mask_p[26] << 20) 391 | (mask_p[25] << 18) | (mask_p[24] << 16) 392 | (mask_p[23] << 14) | (mask_p[22] << 12) 393 | (mask_p[21] << 10) | (mask_p[20] << 8) 394 | (mask_p[19] << 6) | (mask_p[18] << 4) 395 | (mask_p[17] << 2) | (mask_p[16] << 0); 396 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 397 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 398 399 tmp_mask = (mask_p[45] << 28) 400 | (mask_p[44] << 26) | (mask_p[43] << 24) 401 | (mask_p[42] << 22) | (mask_p[41] << 20) 402 | (mask_p[40] << 18) | (mask_p[39] << 16) 403 | (mask_p[38] << 14) | (mask_p[37] << 12) 404 | (mask_p[36] << 10) | (mask_p[35] << 8) 405 | (mask_p[34] << 6) | (mask_p[33] << 4) 406 | (mask_p[32] << 2) | (mask_p[31] << 0); 407 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 408 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 409 410 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 411 | (mask_p[59] << 26) | (mask_p[58] << 24) 412 | (mask_p[57] << 22) | (mask_p[56] << 20) 413 | (mask_p[55] << 18) | (mask_p[54] << 16) 414 | (mask_p[53] << 14) | (mask_p[52] << 12) 415 | (mask_p[51] << 10) | (mask_p[50] << 8) 416 | (mask_p[49] << 6) | (mask_p[48] << 4) 417 | (mask_p[47] << 2) | (mask_p[46] << 0); 418 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 419 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 420 421 REGWRITE_BUFFER_FLUSH(ah); 422} 423 424static void ar9002_olc_init(struct ath_hw *ah) 425{ 426 u32 i; 427 428 if (!OLC_FOR_AR9280_20_LATER) 429 return; 430 431 if (OLC_FOR_AR9287_10_LATER) { 432 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, 433 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); 434 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0, 435 AR9287_AN_TXPC0_TXPCMODE, 436 AR9287_AN_TXPC0_TXPCMODE_S, 437 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); 438 udelay(100); 439 } else { 440 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) 441 ah->originalGain[i] = 442 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), 443 AR_PHY_TX_GAIN); 444 ah->PDADCdelta = 0; 445 } 446} 447 448static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah, 449 struct ath9k_channel *chan) 450{ 451 int ref_div = 5; 452 int pll_div = 0x2c; 453 u32 pll; 454 455 if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) { 456 if (AR_SREV_9280_20(ah)) { 457 ref_div = 10; 458 pll_div = 0x50; 459 } else { 460 pll_div = 0x28; 461 } 462 } 463 464 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); 465 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); 466 467 if (chan && IS_CHAN_HALF_RATE(chan)) 468 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 469 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 470 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 471 472 return pll; 473} 474 475static void ar9002_hw_do_getnf(struct ath_hw *ah, 476 int16_t nfarray[NUM_NF_READINGS]) 477{ 478 int16_t nf; 479 480 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); 481 nfarray[0] = sign_extend32(nf, 8); 482 483 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); 484 if (IS_CHAN_HT40(ah->curchan)) 485 nfarray[3] = sign_extend32(nf, 8); 486 487 if (!(ah->rxchainmask & BIT(1))) 488 return; 489 490 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); 491 nfarray[1] = sign_extend32(nf, 8); 492 493 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); 494 if (IS_CHAN_HT40(ah->curchan)) 495 nfarray[4] = sign_extend32(nf, 8); 496} 497 498static void ar9002_hw_set_nf_limits(struct ath_hw *ah) 499{ 500 if (AR_SREV_9285(ah)) { 501 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ; 502 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ; 503 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ; 504 } else if (AR_SREV_9287(ah)) { 505 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ; 506 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ; 507 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ; 508 } else if (AR_SREV_9271(ah)) { 509 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ; 510 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ; 511 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ; 512 } else { 513 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 514 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 515 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 516 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 517 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 518 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 519 } 520} 521 522static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah, 523 struct ath_hw_antcomb_conf *antconf) 524{ 525 u32 regval; 526 527 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 528 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >> 529 AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S; 530 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >> 531 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S; 532 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >> 533 AR_PHY_9285_FAST_DIV_BIAS_S; 534 antconf->lna1_lna2_switch_delta = -1; 535 antconf->lna1_lna2_delta = -3; 536 antconf->div_group = 0; 537} 538 539static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah, 540 struct ath_hw_antcomb_conf *antconf) 541{ 542 u32 regval; 543 544 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 545 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | 546 AR_PHY_9285_ANT_DIV_ALT_LNACONF | 547 AR_PHY_9285_FAST_DIV_BIAS); 548 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S) 549 & AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 550 regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S) 551 & AR_PHY_9285_ANT_DIV_ALT_LNACONF); 552 regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S) 553 & AR_PHY_9285_FAST_DIV_BIAS); 554 555 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); 556} 557 558#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 559 560static void ar9002_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) 561{ 562 struct ath_btcoex_hw *btcoex = &ah->btcoex_hw; 563 u8 antdiv_ctrl1, antdiv_ctrl2; 564 u32 regval; 565 566 if (enable) { 567 antdiv_ctrl1 = ATH_BT_COEX_ANTDIV_CONTROL1_ENABLE; 568 antdiv_ctrl2 = ATH_BT_COEX_ANTDIV_CONTROL2_ENABLE; 569 570 /* 571 * Don't disable BT ant to allow BB to control SWCOM. 572 */ 573 btcoex->bt_coex_mode2 &= (~(AR_BT_DISABLE_BT_ANT)); 574 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); 575 576 REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM); 577 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); 578 } else { 579 /* 580 * Disable antenna diversity, use LNA1 only. 581 */ 582 antdiv_ctrl1 = ATH_BT_COEX_ANTDIV_CONTROL1_FIXED_A; 583 antdiv_ctrl2 = ATH_BT_COEX_ANTDIV_CONTROL2_FIXED_A; 584 585 /* 586 * Disable BT Ant. to allow concurrent BT and WLAN receive. 587 */ 588 btcoex->bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 589 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); 590 591 /* 592 * Program SWCOM table to make sure RF switch always parks 593 * at BT side. 594 */ 595 REG_WRITE(ah, AR_PHY_SWITCH_COM, 0); 596 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); 597 } 598 599 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 600 regval &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 601 /* 602 * Clear ant_fast_div_bias [14:9] since for WB195, 603 * the main LNA is always LNA1. 604 */ 605 regval &= (~(AR_PHY_9285_FAST_DIV_BIAS)); 606 regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL); 607 regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); 608 regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 609 regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); 610 regval |= SM((antdiv_ctrl1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 611 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); 612 613 regval = REG_READ(ah, AR_PHY_CCK_DETECT); 614 regval &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 615 regval |= SM((antdiv_ctrl1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 616 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); 617} 618 619#endif 620 621static void ar9002_hw_spectral_scan_config(struct ath_hw *ah, 622 struct ath_spec_scan *param) 623{ 624 u8 count; 625 626 if (!param->enabled) { 627 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, 628 AR_PHY_SPECTRAL_SCAN_ENABLE); 629 return; 630 } 631 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); 632 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); 633 634 if (param->short_repeat) 635 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, 636 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); 637 else 638 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, 639 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); 640 641 /* on AR92xx, the highest bit of count will make the the chip send 642 * spectral samples endlessly. Check if this really was intended, 643 * and fix otherwise. 644 */ 645 count = param->count; 646 if (param->endless) 647 count = 0x80; 648 else if (count & 0x80) 649 count = 0x7f; 650 651 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 652 AR_PHY_SPECTRAL_SCAN_COUNT, count); 653 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 654 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period); 655 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 656 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period); 657 658 return; 659} 660 661static void ar9002_hw_spectral_scan_trigger(struct ath_hw *ah) 662{ 663 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); 664 /* Activate spectral scan */ 665 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, 666 AR_PHY_SPECTRAL_SCAN_ACTIVE); 667} 668 669static void ar9002_hw_spectral_scan_wait(struct ath_hw *ah) 670{ 671 struct ath_common *common = ath9k_hw_common(ah); 672 673 /* Poll for spectral scan complete */ 674 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, 675 AR_PHY_SPECTRAL_SCAN_ACTIVE, 676 0, AH_WAIT_TIMEOUT)) { 677 ath_err(common, "spectral scan wait failed\n"); 678 return; 679 } 680} 681 682static void ar9002_hw_tx99_start(struct ath_hw *ah, u32 qnum) 683{ 684 REG_SET_BIT(ah, 0x9864, 0x7f000); 685 REG_SET_BIT(ah, 0x9924, 0x7f00fe); 686 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); 687 REG_WRITE(ah, AR_CR, AR_CR_RXD); 688 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 689 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); 690 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 691 REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum); 692 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 693 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 694 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); 695} 696 697static void ar9002_hw_tx99_stop(struct ath_hw *ah) 698{ 699 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); 700} 701 702void ar9002_hw_attach_phy_ops(struct ath_hw *ah) 703{ 704 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 705 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 706 707 priv_ops->set_rf_regs = NULL; 708 priv_ops->rf_set_freq = ar9002_hw_set_channel; 709 priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate; 710 priv_ops->olc_init = ar9002_olc_init; 711 priv_ops->compute_pll_control = ar9002_hw_compute_pll_control; 712 priv_ops->do_getnf = ar9002_hw_do_getnf; 713 714 ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get; 715 ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set; 716 ops->spectral_scan_config = ar9002_hw_spectral_scan_config; 717 ops->spectral_scan_trigger = ar9002_hw_spectral_scan_trigger; 718 ops->spectral_scan_wait = ar9002_hw_spectral_scan_wait; 719 720#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 721 ops->set_bt_ant_diversity = ar9002_hw_set_bt_ant_diversity; 722#endif 723 ops->tx99_start = ar9002_hw_tx99_start; 724 ops->tx99_stop = ar9002_hw_tx99_stop; 725 726 ar9002_hw_set_nf_limits(ah); 727} 728