hw.c revision 00e0003e0969517c5a447ac3173442dfbdb0613b
1/* 2 * Copyright (c) 2008-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <asm/unaligned.h> 20 21#include "hw.h" 22#include "hw-ops.h" 23#include "rc.h" 24#include "ar9003_mac.h" 25 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 27 28MODULE_AUTHOR("Atheros Communications"); 29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 31MODULE_LICENSE("Dual BSD/GPL"); 32 33static int __init ath9k_init(void) 34{ 35 return 0; 36} 37module_init(ath9k_init); 38 39static void __exit ath9k_exit(void) 40{ 41 return; 42} 43module_exit(ath9k_exit); 44 45/* Private hardware callbacks */ 46 47static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 48{ 49 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 50} 51 52static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 53{ 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 55} 56 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 58 struct ath9k_channel *chan) 59{ 60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 61} 62 63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 64{ 65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 66 return; 67 68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 69} 70 71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 72{ 73 /* You will not have this callback if using the old ANI */ 74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 75 return; 76 77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 78} 79 80/********************/ 81/* Helper Functions */ 82/********************/ 83 84static void ath9k_hw_set_clockrate(struct ath_hw *ah) 85{ 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 87 struct ath_common *common = ath9k_hw_common(ah); 88 unsigned int clockrate; 89 90 if (!ah->curchan) /* should really check for CCK instead */ 91 clockrate = ATH9K_CLOCK_RATE_CCK; 92 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 96 else 97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 98 99 if (conf_is_ht40(conf)) 100 clockrate *= 2; 101 102 common->clockrate = clockrate; 103} 104 105static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 106{ 107 struct ath_common *common = ath9k_hw_common(ah); 108 109 return usecs * common->clockrate; 110} 111 112bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 113{ 114 int i; 115 116 BUG_ON(timeout < AH_TIME_QUANTUM); 117 118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 119 if ((REG_READ(ah, reg) & mask) == val) 120 return true; 121 122 udelay(AH_TIME_QUANTUM); 123 } 124 125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, 126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 127 timeout, reg, REG_READ(ah, reg), mask, val); 128 129 return false; 130} 131EXPORT_SYMBOL(ath9k_hw_wait); 132 133u32 ath9k_hw_reverse_bits(u32 val, u32 n) 134{ 135 u32 retval; 136 int i; 137 138 for (i = 0, retval = 0; i < n; i++) { 139 retval = (retval << 1) | (val & 1); 140 val >>= 1; 141 } 142 return retval; 143} 144 145bool ath9k_get_channel_edges(struct ath_hw *ah, 146 u16 flags, u16 *low, 147 u16 *high) 148{ 149 struct ath9k_hw_capabilities *pCap = &ah->caps; 150 151 if (flags & CHANNEL_5GHZ) { 152 *low = pCap->low_5ghz_chan; 153 *high = pCap->high_5ghz_chan; 154 return true; 155 } 156 if ((flags & CHANNEL_2GHZ)) { 157 *low = pCap->low_2ghz_chan; 158 *high = pCap->high_2ghz_chan; 159 return true; 160 } 161 return false; 162} 163 164u16 ath9k_hw_computetxtime(struct ath_hw *ah, 165 u8 phy, int kbps, 166 u32 frameLen, u16 rateix, 167 bool shortPreamble) 168{ 169 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 170 171 if (kbps == 0) 172 return 0; 173 174 switch (phy) { 175 case WLAN_RC_PHY_CCK: 176 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 177 if (shortPreamble) 178 phyTime >>= 1; 179 numBits = frameLen << 3; 180 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 181 break; 182 case WLAN_RC_PHY_OFDM: 183 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 185 numBits = OFDM_PLCP_BITS + (frameLen << 3); 186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 187 txTime = OFDM_SIFS_TIME_QUARTER 188 + OFDM_PREAMBLE_TIME_QUARTER 189 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 190 } else if (ah->curchan && 191 IS_CHAN_HALF_RATE(ah->curchan)) { 192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 193 numBits = OFDM_PLCP_BITS + (frameLen << 3); 194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 195 txTime = OFDM_SIFS_TIME_HALF + 196 OFDM_PREAMBLE_TIME_HALF 197 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 198 } else { 199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 200 numBits = OFDM_PLCP_BITS + (frameLen << 3); 201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 202 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 203 + (numSymbols * OFDM_SYMBOL_TIME); 204 } 205 break; 206 default: 207 ath_err(ath9k_hw_common(ah), 208 "Unknown phy %u (rate ix %u)\n", phy, rateix); 209 txTime = 0; 210 break; 211 } 212 213 return txTime; 214} 215EXPORT_SYMBOL(ath9k_hw_computetxtime); 216 217void ath9k_hw_get_channel_centers(struct ath_hw *ah, 218 struct ath9k_channel *chan, 219 struct chan_centers *centers) 220{ 221 int8_t extoff; 222 223 if (!IS_CHAN_HT40(chan)) { 224 centers->ctl_center = centers->ext_center = 225 centers->synth_center = chan->channel; 226 return; 227 } 228 229 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 230 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 231 centers->synth_center = 232 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 233 extoff = 1; 234 } else { 235 centers->synth_center = 236 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 237 extoff = -1; 238 } 239 240 centers->ctl_center = 241 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 242 /* 25 MHz spacing is supported by hw but not on upper layers */ 243 centers->ext_center = 244 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 245} 246 247/******************/ 248/* Chip Revisions */ 249/******************/ 250 251static void ath9k_hw_read_revisions(struct ath_hw *ah) 252{ 253 u32 val; 254 255 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 256 257 if (val == 0xFF) { 258 val = REG_READ(ah, AR_SREV); 259 ah->hw_version.macVersion = 260 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 261 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 262 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 263 } else { 264 if (!AR_SREV_9100(ah)) 265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 266 267 ah->hw_version.macRev = val & AR_SREV_REVISION; 268 269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 270 ah->is_pciexpress = true; 271 } 272} 273 274/************************************/ 275/* HW Attach, Detach, Init Routines */ 276/************************************/ 277 278static void ath9k_hw_disablepcie(struct ath_hw *ah) 279{ 280 if (!AR_SREV_5416(ah)) 281 return; 282 283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 292 293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 294} 295 296/* This should work for all families including legacy */ 297static bool ath9k_hw_chip_test(struct ath_hw *ah) 298{ 299 struct ath_common *common = ath9k_hw_common(ah); 300 u32 regAddr[2] = { AR_STA_ID0 }; 301 u32 regHold[2]; 302 static const u32 patternData[4] = { 303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 304 }; 305 int i, j, loop_max; 306 307 if (!AR_SREV_9300_20_OR_LATER(ah)) { 308 loop_max = 2; 309 regAddr[1] = AR_PHY_BASE + (8 << 2); 310 } else 311 loop_max = 1; 312 313 for (i = 0; i < loop_max; i++) { 314 u32 addr = regAddr[i]; 315 u32 wrData, rdData; 316 317 regHold[i] = REG_READ(ah, addr); 318 for (j = 0; j < 0x100; j++) { 319 wrData = (j << 16) | j; 320 REG_WRITE(ah, addr, wrData); 321 rdData = REG_READ(ah, addr); 322 if (rdData != wrData) { 323 ath_err(common, 324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 325 addr, wrData, rdData); 326 return false; 327 } 328 } 329 for (j = 0; j < 4; j++) { 330 wrData = patternData[j]; 331 REG_WRITE(ah, addr, wrData); 332 rdData = REG_READ(ah, addr); 333 if (wrData != rdData) { 334 ath_err(common, 335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 336 addr, wrData, rdData); 337 return false; 338 } 339 } 340 REG_WRITE(ah, regAddr[i], regHold[i]); 341 } 342 udelay(100); 343 344 return true; 345} 346 347static void ath9k_hw_init_config(struct ath_hw *ah) 348{ 349 int i; 350 351 ah->config.dma_beacon_response_time = 2; 352 ah->config.sw_beacon_response_time = 10; 353 ah->config.additional_swba_backoff = 0; 354 ah->config.ack_6mb = 0x0; 355 ah->config.cwm_ignore_extcca = 0; 356 ah->config.pcie_powersave_enable = 0; 357 ah->config.pcie_clock_req = 0; 358 ah->config.pcie_waen = 0; 359 ah->config.analog_shiftreg = 1; 360 ah->config.enable_ani = true; 361 362 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 363 ah->config.spurchans[i][0] = AR_NO_SPUR; 364 ah->config.spurchans[i][1] = AR_NO_SPUR; 365 } 366 367 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 368 ah->config.ht_enable = 1; 369 else 370 ah->config.ht_enable = 0; 371 372 ah->config.rx_intr_mitigation = true; 373 ah->config.pcieSerDesWrite = true; 374 375 /* 376 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 377 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 378 * This means we use it for all AR5416 devices, and the few 379 * minor PCI AR9280 devices out there. 380 * 381 * Serialization is required because these devices do not handle 382 * well the case of two concurrent reads/writes due to the latency 383 * involved. During one read/write another read/write can be issued 384 * on another CPU while the previous read/write may still be working 385 * on our hardware, if we hit this case the hardware poops in a loop. 386 * We prevent this by serializing reads and writes. 387 * 388 * This issue is not present on PCI-Express devices or pre-AR5416 389 * devices (legacy, 802.11abg). 390 */ 391 if (num_possible_cpus() > 1) 392 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 393} 394 395static void ath9k_hw_init_defaults(struct ath_hw *ah) 396{ 397 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 398 399 regulatory->country_code = CTRY_DEFAULT; 400 regulatory->power_limit = MAX_RATE_POWER; 401 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 402 403 ah->hw_version.magic = AR5416_MAGIC; 404 ah->hw_version.subvendorid = 0; 405 406 ah->atim_window = 0; 407 ah->sta_id1_defaults = 408 AR_STA_ID1_CRPT_MIC_ENABLE | 409 AR_STA_ID1_MCAST_KSRCH; 410 ah->enable_32kHz_clock = DONT_USE_32KHZ; 411 ah->slottime = 20; 412 ah->globaltxtimeout = (u32) -1; 413 ah->power_mode = ATH9K_PM_UNDEFINED; 414} 415 416static int ath9k_hw_init_macaddr(struct ath_hw *ah) 417{ 418 struct ath_common *common = ath9k_hw_common(ah); 419 u32 sum; 420 int i; 421 u16 eeval; 422 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 423 424 sum = 0; 425 for (i = 0; i < 3; i++) { 426 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 427 sum += eeval; 428 common->macaddr[2 * i] = eeval >> 8; 429 common->macaddr[2 * i + 1] = eeval & 0xff; 430 } 431 if (sum == 0 || sum == 0xffff * 3) 432 return -EADDRNOTAVAIL; 433 434 return 0; 435} 436 437static int ath9k_hw_post_init(struct ath_hw *ah) 438{ 439 struct ath_common *common = ath9k_hw_common(ah); 440 int ecode; 441 442 if (common->bus_ops->ath_bus_type != ATH_USB) { 443 if (!ath9k_hw_chip_test(ah)) 444 return -ENODEV; 445 } 446 447 if (!AR_SREV_9300_20_OR_LATER(ah)) { 448 ecode = ar9002_hw_rf_claim(ah); 449 if (ecode != 0) 450 return ecode; 451 } 452 453 ecode = ath9k_hw_eeprom_init(ah); 454 if (ecode != 0) 455 return ecode; 456 457 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, 458 "Eeprom VER: %d, REV: %d\n", 459 ah->eep_ops->get_eeprom_ver(ah), 460 ah->eep_ops->get_eeprom_rev(ah)); 461 462 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 463 if (ecode) { 464 ath_err(ath9k_hw_common(ah), 465 "Failed allocating banks for external radio\n"); 466 ath9k_hw_rf_free_ext_banks(ah); 467 return ecode; 468 } 469 470 if (!AR_SREV_9100(ah)) { 471 ath9k_hw_ani_setup(ah); 472 ath9k_hw_ani_init(ah); 473 } 474 475 return 0; 476} 477 478static void ath9k_hw_attach_ops(struct ath_hw *ah) 479{ 480 if (AR_SREV_9300_20_OR_LATER(ah)) 481 ar9003_hw_attach_ops(ah); 482 else 483 ar9002_hw_attach_ops(ah); 484} 485 486/* Called for all hardware families */ 487static int __ath9k_hw_init(struct ath_hw *ah) 488{ 489 struct ath_common *common = ath9k_hw_common(ah); 490 int r = 0; 491 492 if (ah->hw_version.devid == AR5416_AR9100_DEVID) 493 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 494 495 ath9k_hw_read_revisions(ah); 496 497 /* 498 * Read back AR_WA into a permanent copy and set bits 14 and 17. 499 * We need to do this to avoid RMW of this register. We cannot 500 * read the reg when chip is asleep. 501 */ 502 ah->WARegVal = REG_READ(ah, AR_WA); 503 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 504 AR_WA_ASPM_TIMER_BASED_DISABLE); 505 506 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 507 ath_err(common, "Couldn't reset chip\n"); 508 return -EIO; 509 } 510 511 ath9k_hw_init_defaults(ah); 512 ath9k_hw_init_config(ah); 513 514 ath9k_hw_attach_ops(ah); 515 516 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 517 ath_err(common, "Couldn't wakeup chip\n"); 518 return -EIO; 519 } 520 521 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 522 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 523 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 524 !ah->is_pciexpress)) { 525 ah->config.serialize_regmode = 526 SER_REG_MODE_ON; 527 } else { 528 ah->config.serialize_regmode = 529 SER_REG_MODE_OFF; 530 } 531 } 532 533 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 534 ah->config.serialize_regmode); 535 536 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 537 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 538 else 539 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 540 541 switch (ah->hw_version.macVersion) { 542 case AR_SREV_VERSION_5416_PCI: 543 case AR_SREV_VERSION_5416_PCIE: 544 case AR_SREV_VERSION_9160: 545 case AR_SREV_VERSION_9100: 546 case AR_SREV_VERSION_9280: 547 case AR_SREV_VERSION_9285: 548 case AR_SREV_VERSION_9287: 549 case AR_SREV_VERSION_9271: 550 case AR_SREV_VERSION_9300: 551 case AR_SREV_VERSION_9485: 552 break; 553 default: 554 ath_err(common, 555 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 556 ah->hw_version.macVersion, ah->hw_version.macRev); 557 return -EOPNOTSUPP; 558 } 559 560 if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) 561 ah->is_pciexpress = false; 562 563 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 564 ath9k_hw_init_cal_settings(ah); 565 566 ah->ani_function = ATH9K_ANI_ALL; 567 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 568 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 569 if (!AR_SREV_9300_20_OR_LATER(ah)) 570 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 571 572 ath9k_hw_init_mode_regs(ah); 573 574 575 if (ah->is_pciexpress) 576 ath9k_hw_configpcipowersave(ah, 0, 0); 577 else 578 ath9k_hw_disablepcie(ah); 579 580 if (!AR_SREV_9300_20_OR_LATER(ah)) 581 ar9002_hw_cck_chan14_spread(ah); 582 583 r = ath9k_hw_post_init(ah); 584 if (r) 585 return r; 586 587 ath9k_hw_init_mode_gain_regs(ah); 588 r = ath9k_hw_fill_cap_info(ah); 589 if (r) 590 return r; 591 592 r = ath9k_hw_init_macaddr(ah); 593 if (r) { 594 ath_err(common, "Failed to initialize MAC address\n"); 595 return r; 596 } 597 598 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 599 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 600 else 601 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 602 603 ah->bb_watchdog_timeout_ms = 25; 604 605 common->state = ATH_HW_INITIALIZED; 606 607 return 0; 608} 609 610int ath9k_hw_init(struct ath_hw *ah) 611{ 612 int ret; 613 struct ath_common *common = ath9k_hw_common(ah); 614 615 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 616 switch (ah->hw_version.devid) { 617 case AR5416_DEVID_PCI: 618 case AR5416_DEVID_PCIE: 619 case AR5416_AR9100_DEVID: 620 case AR9160_DEVID_PCI: 621 case AR9280_DEVID_PCI: 622 case AR9280_DEVID_PCIE: 623 case AR9285_DEVID_PCIE: 624 case AR9287_DEVID_PCI: 625 case AR9287_DEVID_PCIE: 626 case AR2427_DEVID_PCIE: 627 case AR9300_DEVID_PCIE: 628 case AR9300_DEVID_AR9485_PCIE: 629 break; 630 default: 631 if (common->bus_ops->ath_bus_type == ATH_USB) 632 break; 633 ath_err(common, "Hardware device ID 0x%04x not supported\n", 634 ah->hw_version.devid); 635 return -EOPNOTSUPP; 636 } 637 638 ret = __ath9k_hw_init(ah); 639 if (ret) { 640 ath_err(common, 641 "Unable to initialize hardware; initialization status: %d\n", 642 ret); 643 return ret; 644 } 645 646 return 0; 647} 648EXPORT_SYMBOL(ath9k_hw_init); 649 650static void ath9k_hw_init_qos(struct ath_hw *ah) 651{ 652 ENABLE_REGWRITE_BUFFER(ah); 653 654 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 655 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 656 657 REG_WRITE(ah, AR_QOS_NO_ACK, 658 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 659 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 660 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 661 662 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 663 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 664 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 665 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 666 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 667 668 REGWRITE_BUFFER_FLUSH(ah); 669} 670 671static void ath9k_hw_init_pll(struct ath_hw *ah, 672 struct ath9k_channel *chan) 673{ 674 u32 pll; 675 676 if (AR_SREV_9485(ah)) 677 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666); 678 679 pll = ath9k_hw_compute_pll_control(ah, chan); 680 681 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 682 683 /* Switch the core clock for ar9271 to 117Mhz */ 684 if (AR_SREV_9271(ah)) { 685 udelay(500); 686 REG_WRITE(ah, 0x50040, 0x304); 687 } 688 689 udelay(RTC_PLL_SETTLE_DELAY); 690 691 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 692} 693 694static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 695 enum nl80211_iftype opmode) 696{ 697 u32 imr_reg = AR_IMR_TXERR | 698 AR_IMR_TXURN | 699 AR_IMR_RXERR | 700 AR_IMR_RXORN | 701 AR_IMR_BCNMISC; 702 703 if (AR_SREV_9300_20_OR_LATER(ah)) { 704 imr_reg |= AR_IMR_RXOK_HP; 705 if (ah->config.rx_intr_mitigation) 706 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 707 else 708 imr_reg |= AR_IMR_RXOK_LP; 709 710 } else { 711 if (ah->config.rx_intr_mitigation) 712 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 713 else 714 imr_reg |= AR_IMR_RXOK; 715 } 716 717 if (ah->config.tx_intr_mitigation) 718 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 719 else 720 imr_reg |= AR_IMR_TXOK; 721 722 if (opmode == NL80211_IFTYPE_AP) 723 imr_reg |= AR_IMR_MIB; 724 725 ENABLE_REGWRITE_BUFFER(ah); 726 727 REG_WRITE(ah, AR_IMR, imr_reg); 728 ah->imrs2_reg |= AR_IMR_S2_GTT; 729 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 730 731 if (!AR_SREV_9100(ah)) { 732 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 733 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 734 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 735 } 736 737 REGWRITE_BUFFER_FLUSH(ah); 738 739 if (AR_SREV_9300_20_OR_LATER(ah)) { 740 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 741 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 742 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 743 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 744 } 745} 746 747static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 748{ 749 u32 val = ath9k_hw_mac_to_clks(ah, us); 750 val = min(val, (u32) 0xFFFF); 751 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 752} 753 754static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 755{ 756 u32 val = ath9k_hw_mac_to_clks(ah, us); 757 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 758 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 759} 760 761static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 762{ 763 u32 val = ath9k_hw_mac_to_clks(ah, us); 764 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 765 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 766} 767 768static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 769{ 770 if (tu > 0xFFFF) { 771 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 772 "bad global tx timeout %u\n", tu); 773 ah->globaltxtimeout = (u32) -1; 774 return false; 775 } else { 776 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 777 ah->globaltxtimeout = tu; 778 return true; 779 } 780} 781 782void ath9k_hw_init_global_settings(struct ath_hw *ah) 783{ 784 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 785 int acktimeout; 786 int slottime; 787 int sifstime; 788 789 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 790 ah->misc_mode); 791 792 if (ah->misc_mode != 0) 793 REG_WRITE(ah, AR_PCU_MISC, 794 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 795 796 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 797 sifstime = 16; 798 else 799 sifstime = 10; 800 801 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 802 slottime = ah->slottime + 3 * ah->coverage_class; 803 acktimeout = slottime + sifstime; 804 805 /* 806 * Workaround for early ACK timeouts, add an offset to match the 807 * initval's 64us ack timeout value. 808 * This was initially only meant to work around an issue with delayed 809 * BA frames in some implementations, but it has been found to fix ACK 810 * timeout issues in other cases as well. 811 */ 812 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 813 acktimeout += 64 - sifstime - ah->slottime; 814 815 ath9k_hw_setslottime(ah, ah->slottime); 816 ath9k_hw_set_ack_timeout(ah, acktimeout); 817 ath9k_hw_set_cts_timeout(ah, acktimeout); 818 if (ah->globaltxtimeout != (u32) -1) 819 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 820} 821EXPORT_SYMBOL(ath9k_hw_init_global_settings); 822 823void ath9k_hw_deinit(struct ath_hw *ah) 824{ 825 struct ath_common *common = ath9k_hw_common(ah); 826 827 if (common->state < ATH_HW_INITIALIZED) 828 goto free_hw; 829 830 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 831 832free_hw: 833 ath9k_hw_rf_free_ext_banks(ah); 834} 835EXPORT_SYMBOL(ath9k_hw_deinit); 836 837/*******/ 838/* INI */ 839/*******/ 840 841u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 842{ 843 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 844 845 if (IS_CHAN_B(chan)) 846 ctl |= CTL_11B; 847 else if (IS_CHAN_G(chan)) 848 ctl |= CTL_11G; 849 else 850 ctl |= CTL_11A; 851 852 return ctl; 853} 854 855/****************************************/ 856/* Reset and Channel Switching Routines */ 857/****************************************/ 858 859static inline void ath9k_hw_set_dma(struct ath_hw *ah) 860{ 861 struct ath_common *common = ath9k_hw_common(ah); 862 u32 regval; 863 864 ENABLE_REGWRITE_BUFFER(ah); 865 866 /* 867 * set AHB_MODE not to do cacheline prefetches 868 */ 869 if (!AR_SREV_9300_20_OR_LATER(ah)) { 870 regval = REG_READ(ah, AR_AHB_MODE); 871 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 872 } 873 874 /* 875 * let mac dma reads be in 128 byte chunks 876 */ 877 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 878 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 879 880 REGWRITE_BUFFER_FLUSH(ah); 881 882 /* 883 * Restore TX Trigger Level to its pre-reset value. 884 * The initial value depends on whether aggregation is enabled, and is 885 * adjusted whenever underruns are detected. 886 */ 887 if (!AR_SREV_9300_20_OR_LATER(ah)) 888 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 889 890 ENABLE_REGWRITE_BUFFER(ah); 891 892 /* 893 * let mac dma writes be in 128 byte chunks 894 */ 895 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 896 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 897 898 /* 899 * Setup receive FIFO threshold to hold off TX activities 900 */ 901 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 902 903 if (AR_SREV_9300_20_OR_LATER(ah)) { 904 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 905 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 906 907 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 908 ah->caps.rx_status_len); 909 } 910 911 /* 912 * reduce the number of usable entries in PCU TXBUF to avoid 913 * wrap around issues. 914 */ 915 if (AR_SREV_9285(ah)) { 916 /* For AR9285 the number of Fifos are reduced to half. 917 * So set the usable tx buf size also to half to 918 * avoid data/delimiter underruns 919 */ 920 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 921 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 922 } else if (!AR_SREV_9271(ah)) { 923 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 924 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 925 } 926 927 REGWRITE_BUFFER_FLUSH(ah); 928 929 if (AR_SREV_9300_20_OR_LATER(ah)) 930 ath9k_hw_reset_txstatus_ring(ah); 931} 932 933static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 934{ 935 u32 val; 936 937 val = REG_READ(ah, AR_STA_ID1); 938 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 939 switch (opmode) { 940 case NL80211_IFTYPE_AP: 941 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 942 | AR_STA_ID1_KSRCH_MODE); 943 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 944 break; 945 case NL80211_IFTYPE_ADHOC: 946 case NL80211_IFTYPE_MESH_POINT: 947 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 948 | AR_STA_ID1_KSRCH_MODE); 949 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 950 break; 951 case NL80211_IFTYPE_STATION: 952 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 953 break; 954 default: 955 if (ah->is_monitoring) 956 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 957 break; 958 } 959} 960 961void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 962 u32 *coef_mantissa, u32 *coef_exponent) 963{ 964 u32 coef_exp, coef_man; 965 966 for (coef_exp = 31; coef_exp > 0; coef_exp--) 967 if ((coef_scaled >> coef_exp) & 0x1) 968 break; 969 970 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 971 972 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 973 974 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 975 *coef_exponent = coef_exp - 16; 976} 977 978static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 979{ 980 u32 rst_flags; 981 u32 tmpReg; 982 983 if (AR_SREV_9100(ah)) { 984 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 985 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 986 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 987 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 988 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 989 } 990 991 ENABLE_REGWRITE_BUFFER(ah); 992 993 if (AR_SREV_9300_20_OR_LATER(ah)) { 994 REG_WRITE(ah, AR_WA, ah->WARegVal); 995 udelay(10); 996 } 997 998 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 999 AR_RTC_FORCE_WAKE_ON_INT); 1000 1001 if (AR_SREV_9100(ah)) { 1002 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1003 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1004 } else { 1005 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1006 if (tmpReg & 1007 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1008 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1009 u32 val; 1010 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1011 1012 val = AR_RC_HOSTIF; 1013 if (!AR_SREV_9300_20_OR_LATER(ah)) 1014 val |= AR_RC_AHB; 1015 REG_WRITE(ah, AR_RC, val); 1016 1017 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1018 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1019 1020 rst_flags = AR_RTC_RC_MAC_WARM; 1021 if (type == ATH9K_RESET_COLD) 1022 rst_flags |= AR_RTC_RC_MAC_COLD; 1023 } 1024 1025 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1026 1027 REGWRITE_BUFFER_FLUSH(ah); 1028 1029 udelay(50); 1030 1031 REG_WRITE(ah, AR_RTC_RC, 0); 1032 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1033 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1034 "RTC stuck in MAC reset\n"); 1035 return false; 1036 } 1037 1038 if (!AR_SREV_9100(ah)) 1039 REG_WRITE(ah, AR_RC, 0); 1040 1041 if (AR_SREV_9100(ah)) 1042 udelay(50); 1043 1044 return true; 1045} 1046 1047static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1048{ 1049 ENABLE_REGWRITE_BUFFER(ah); 1050 1051 if (AR_SREV_9300_20_OR_LATER(ah)) { 1052 REG_WRITE(ah, AR_WA, ah->WARegVal); 1053 udelay(10); 1054 } 1055 1056 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1057 AR_RTC_FORCE_WAKE_ON_INT); 1058 1059 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1060 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1061 1062 REG_WRITE(ah, AR_RTC_RESET, 0); 1063 udelay(2); 1064 1065 REGWRITE_BUFFER_FLUSH(ah); 1066 1067 if (!AR_SREV_9300_20_OR_LATER(ah)) 1068 udelay(2); 1069 1070 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1071 REG_WRITE(ah, AR_RC, 0); 1072 1073 REG_WRITE(ah, AR_RTC_RESET, 1); 1074 1075 if (!ath9k_hw_wait(ah, 1076 AR_RTC_STATUS, 1077 AR_RTC_STATUS_M, 1078 AR_RTC_STATUS_ON, 1079 AH_WAIT_TIMEOUT)) { 1080 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1081 "RTC not waking up\n"); 1082 return false; 1083 } 1084 1085 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1086} 1087 1088static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1089{ 1090 if (AR_SREV_9300_20_OR_LATER(ah)) { 1091 REG_WRITE(ah, AR_WA, ah->WARegVal); 1092 udelay(10); 1093 } 1094 1095 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1096 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1097 1098 switch (type) { 1099 case ATH9K_RESET_POWER_ON: 1100 return ath9k_hw_set_reset_power_on(ah); 1101 case ATH9K_RESET_WARM: 1102 case ATH9K_RESET_COLD: 1103 return ath9k_hw_set_reset(ah, type); 1104 default: 1105 return false; 1106 } 1107} 1108 1109static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1110 struct ath9k_channel *chan) 1111{ 1112 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1113 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1114 return false; 1115 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1116 return false; 1117 1118 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1119 return false; 1120 1121 ah->chip_fullsleep = false; 1122 ath9k_hw_init_pll(ah, chan); 1123 ath9k_hw_set_rfmode(ah, chan); 1124 1125 return true; 1126} 1127 1128static bool ath9k_hw_channel_change(struct ath_hw *ah, 1129 struct ath9k_channel *chan) 1130{ 1131 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1132 struct ath_common *common = ath9k_hw_common(ah); 1133 struct ieee80211_channel *channel = chan->chan; 1134 u32 qnum; 1135 int r; 1136 1137 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1138 if (ath9k_hw_numtxpending(ah, qnum)) { 1139 ath_dbg(common, ATH_DBG_QUEUE, 1140 "Transmit frames pending on queue %d\n", qnum); 1141 return false; 1142 } 1143 } 1144 1145 if (!ath9k_hw_rfbus_req(ah)) { 1146 ath_err(common, "Could not kill baseband RX\n"); 1147 return false; 1148 } 1149 1150 ath9k_hw_set_channel_regs(ah, chan); 1151 1152 r = ath9k_hw_rf_set_freq(ah, chan); 1153 if (r) { 1154 ath_err(common, "Failed to set channel\n"); 1155 return false; 1156 } 1157 ath9k_hw_set_clockrate(ah); 1158 1159 ah->eep_ops->set_txpower(ah, chan, 1160 ath9k_regd_get_ctl(regulatory, chan), 1161 channel->max_antenna_gain * 2, 1162 channel->max_power * 2, 1163 min((u32) MAX_RATE_POWER, 1164 (u32) regulatory->power_limit), false); 1165 1166 ath9k_hw_rfbus_done(ah); 1167 1168 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1169 ath9k_hw_set_delta_slope(ah, chan); 1170 1171 ath9k_hw_spur_mitigate_freq(ah, chan); 1172 1173 return true; 1174} 1175 1176bool ath9k_hw_check_alive(struct ath_hw *ah) 1177{ 1178 int count = 50; 1179 u32 reg; 1180 1181 if (AR_SREV_9285_12_OR_LATER(ah)) 1182 return true; 1183 1184 do { 1185 reg = REG_READ(ah, AR_OBS_BUS_1); 1186 1187 if ((reg & 0x7E7FFFEF) == 0x00702400) 1188 continue; 1189 1190 switch (reg & 0x7E000B00) { 1191 case 0x1E000000: 1192 case 0x52000B00: 1193 case 0x18000B00: 1194 continue; 1195 default: 1196 return true; 1197 } 1198 } while (count-- > 0); 1199 1200 return false; 1201} 1202EXPORT_SYMBOL(ath9k_hw_check_alive); 1203 1204int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1205 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1206{ 1207 struct ath_common *common = ath9k_hw_common(ah); 1208 u32 saveLedState; 1209 struct ath9k_channel *curchan = ah->curchan; 1210 u32 saveDefAntenna; 1211 u32 macStaId1; 1212 u64 tsf = 0; 1213 int i, r; 1214 1215 ah->txchainmask = common->tx_chainmask; 1216 ah->rxchainmask = common->rx_chainmask; 1217 1218 if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) { 1219 ath9k_hw_abortpcurecv(ah); 1220 if (!ath9k_hw_stopdmarecv(ah)) { 1221 ath_dbg(common, ATH_DBG_XMIT, 1222 "Failed to stop receive dma\n"); 1223 bChannelChange = false; 1224 } 1225 } 1226 1227 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1228 return -EIO; 1229 1230 if (curchan && !ah->chip_fullsleep) 1231 ath9k_hw_getnf(ah, curchan); 1232 1233 ah->caldata = caldata; 1234 if (caldata && 1235 (chan->channel != caldata->channel || 1236 (chan->channelFlags & ~CHANNEL_CW_INT) != 1237 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1238 /* Operating channel changed, reset channel calibration data */ 1239 memset(caldata, 0, sizeof(*caldata)); 1240 ath9k_init_nfcal_hist_buffer(ah, chan); 1241 } 1242 1243 if (bChannelChange && 1244 (ah->chip_fullsleep != true) && 1245 (ah->curchan != NULL) && 1246 (chan->channel != ah->curchan->channel) && 1247 ((chan->channelFlags & CHANNEL_ALL) == 1248 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1249 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { 1250 1251 if (ath9k_hw_channel_change(ah, chan)) { 1252 ath9k_hw_loadnf(ah, ah->curchan); 1253 ath9k_hw_start_nfcal(ah, true); 1254 if (AR_SREV_9271(ah)) 1255 ar9002_hw_load_ani_reg(ah, chan); 1256 return 0; 1257 } 1258 } 1259 1260 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1261 if (saveDefAntenna == 0) 1262 saveDefAntenna = 1; 1263 1264 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1265 1266 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1267 if (AR_SREV_9100(ah) || 1268 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1269 tsf = ath9k_hw_gettsf64(ah); 1270 1271 saveLedState = REG_READ(ah, AR_CFG_LED) & 1272 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1273 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1274 1275 ath9k_hw_mark_phy_inactive(ah); 1276 1277 ah->paprd_table_write_done = false; 1278 1279 /* Only required on the first reset */ 1280 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1281 REG_WRITE(ah, 1282 AR9271_RESET_POWER_DOWN_CONTROL, 1283 AR9271_RADIO_RF_RST); 1284 udelay(50); 1285 } 1286 1287 if (!ath9k_hw_chip_reset(ah, chan)) { 1288 ath_err(common, "Chip reset failed\n"); 1289 return -EINVAL; 1290 } 1291 1292 /* Only required on the first reset */ 1293 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1294 ah->htc_reset_init = false; 1295 REG_WRITE(ah, 1296 AR9271_RESET_POWER_DOWN_CONTROL, 1297 AR9271_GATE_MAC_CTL); 1298 udelay(50); 1299 } 1300 1301 /* Restore TSF */ 1302 if (tsf) 1303 ath9k_hw_settsf64(ah, tsf); 1304 1305 if (AR_SREV_9280_20_OR_LATER(ah)) 1306 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1307 1308 if (!AR_SREV_9300_20_OR_LATER(ah)) 1309 ar9002_hw_enable_async_fifo(ah); 1310 1311 r = ath9k_hw_process_ini(ah, chan); 1312 if (r) 1313 return r; 1314 1315 /* 1316 * Some AR91xx SoC devices frequently fail to accept TSF writes 1317 * right after the chip reset. When that happens, write a new 1318 * value after the initvals have been applied, with an offset 1319 * based on measured time difference 1320 */ 1321 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1322 tsf += 1500; 1323 ath9k_hw_settsf64(ah, tsf); 1324 } 1325 1326 /* Setup MFP options for CCMP */ 1327 if (AR_SREV_9280_20_OR_LATER(ah)) { 1328 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1329 * frames when constructing CCMP AAD. */ 1330 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1331 0xc7ff); 1332 ah->sw_mgmt_crypto = false; 1333 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1334 /* Disable hardware crypto for management frames */ 1335 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1336 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1337 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1338 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1339 ah->sw_mgmt_crypto = true; 1340 } else 1341 ah->sw_mgmt_crypto = true; 1342 1343 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1344 ath9k_hw_set_delta_slope(ah, chan); 1345 1346 ath9k_hw_spur_mitigate_freq(ah, chan); 1347 ah->eep_ops->set_board_values(ah, chan); 1348 1349 ENABLE_REGWRITE_BUFFER(ah); 1350 1351 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1352 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1353 | macStaId1 1354 | AR_STA_ID1_RTS_USE_DEF 1355 | (ah->config. 1356 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1357 | ah->sta_id1_defaults); 1358 ath_hw_setbssidmask(common); 1359 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1360 ath9k_hw_write_associd(ah); 1361 REG_WRITE(ah, AR_ISR, ~0); 1362 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1363 1364 REGWRITE_BUFFER_FLUSH(ah); 1365 1366 ath9k_hw_set_operating_mode(ah, ah->opmode); 1367 1368 r = ath9k_hw_rf_set_freq(ah, chan); 1369 if (r) 1370 return r; 1371 1372 ath9k_hw_set_clockrate(ah); 1373 1374 ENABLE_REGWRITE_BUFFER(ah); 1375 1376 for (i = 0; i < AR_NUM_DCU; i++) 1377 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1378 1379 REGWRITE_BUFFER_FLUSH(ah); 1380 1381 ah->intr_txqs = 0; 1382 for (i = 0; i < ah->caps.total_queues; i++) 1383 ath9k_hw_resettxqueue(ah, i); 1384 1385 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1386 ath9k_hw_ani_cache_ini_regs(ah); 1387 ath9k_hw_init_qos(ah); 1388 1389 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1390 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1391 1392 ath9k_hw_init_global_settings(ah); 1393 1394 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1395 ar9002_hw_update_async_fifo(ah); 1396 ar9002_hw_enable_wep_aggregation(ah); 1397 } 1398 1399 REG_WRITE(ah, AR_STA_ID1, 1400 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 1401 1402 ath9k_hw_set_dma(ah); 1403 1404 REG_WRITE(ah, AR_OBS, 8); 1405 1406 if (ah->config.rx_intr_mitigation) { 1407 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1408 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1409 } 1410 1411 if (ah->config.tx_intr_mitigation) { 1412 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1413 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1414 } 1415 1416 ath9k_hw_init_bb(ah, chan); 1417 1418 if (!ath9k_hw_init_cal(ah, chan)) 1419 return -EIO; 1420 1421 ENABLE_REGWRITE_BUFFER(ah); 1422 1423 ath9k_hw_restore_chainmask(ah); 1424 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1425 1426 REGWRITE_BUFFER_FLUSH(ah); 1427 1428 /* 1429 * For big endian systems turn on swapping for descriptors 1430 */ 1431 if (AR_SREV_9100(ah)) { 1432 u32 mask; 1433 mask = REG_READ(ah, AR_CFG); 1434 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1435 ath_dbg(common, ATH_DBG_RESET, 1436 "CFG Byte Swap Set 0x%x\n", mask); 1437 } else { 1438 mask = 1439 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1440 REG_WRITE(ah, AR_CFG, mask); 1441 ath_dbg(common, ATH_DBG_RESET, 1442 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1443 } 1444 } else { 1445 if (common->bus_ops->ath_bus_type == ATH_USB) { 1446 /* Configure AR9271 target WLAN */ 1447 if (AR_SREV_9271(ah)) 1448 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1449 else 1450 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1451 } 1452#ifdef __BIG_ENDIAN 1453 else 1454 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1455#endif 1456 } 1457 1458 if (ah->btcoex_hw.enabled) 1459 ath9k_hw_btcoex_enable(ah); 1460 1461 if (AR_SREV_9300_20_OR_LATER(ah)) 1462 ar9003_hw_bb_watchdog_config(ah); 1463 1464 return 0; 1465} 1466EXPORT_SYMBOL(ath9k_hw_reset); 1467 1468/******************************/ 1469/* Power Management (Chipset) */ 1470/******************************/ 1471 1472/* 1473 * Notify Power Mgt is disabled in self-generated frames. 1474 * If requested, force chip to sleep. 1475 */ 1476static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1477{ 1478 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1479 if (setChip) { 1480 /* 1481 * Clear the RTC force wake bit to allow the 1482 * mac to go to sleep. 1483 */ 1484 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1485 AR_RTC_FORCE_WAKE_EN); 1486 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1487 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1488 1489 /* Shutdown chip. Active low */ 1490 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1491 REG_CLR_BIT(ah, (AR_RTC_RESET), 1492 AR_RTC_RESET_EN); 1493 } 1494 1495 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1496 if (AR_SREV_9300_20_OR_LATER(ah)) 1497 REG_WRITE(ah, AR_WA, 1498 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1499} 1500 1501/* 1502 * Notify Power Management is enabled in self-generating 1503 * frames. If request, set power mode of chip to 1504 * auto/normal. Duration in units of 128us (1/8 TU). 1505 */ 1506static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1507{ 1508 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1509 if (setChip) { 1510 struct ath9k_hw_capabilities *pCap = &ah->caps; 1511 1512 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1513 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1514 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1515 AR_RTC_FORCE_WAKE_ON_INT); 1516 } else { 1517 /* 1518 * Clear the RTC force wake bit to allow the 1519 * mac to go to sleep. 1520 */ 1521 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1522 AR_RTC_FORCE_WAKE_EN); 1523 } 1524 } 1525 1526 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1527 if (AR_SREV_9300_20_OR_LATER(ah)) 1528 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1529} 1530 1531static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1532{ 1533 u32 val; 1534 int i; 1535 1536 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1537 if (AR_SREV_9300_20_OR_LATER(ah)) { 1538 REG_WRITE(ah, AR_WA, ah->WARegVal); 1539 udelay(10); 1540 } 1541 1542 if (setChip) { 1543 if ((REG_READ(ah, AR_RTC_STATUS) & 1544 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1545 if (ath9k_hw_set_reset_reg(ah, 1546 ATH9K_RESET_POWER_ON) != true) { 1547 return false; 1548 } 1549 if (!AR_SREV_9300_20_OR_LATER(ah)) 1550 ath9k_hw_init_pll(ah, NULL); 1551 } 1552 if (AR_SREV_9100(ah)) 1553 REG_SET_BIT(ah, AR_RTC_RESET, 1554 AR_RTC_RESET_EN); 1555 1556 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1557 AR_RTC_FORCE_WAKE_EN); 1558 udelay(50); 1559 1560 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1561 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1562 if (val == AR_RTC_STATUS_ON) 1563 break; 1564 udelay(50); 1565 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1566 AR_RTC_FORCE_WAKE_EN); 1567 } 1568 if (i == 0) { 1569 ath_err(ath9k_hw_common(ah), 1570 "Failed to wakeup in %uus\n", 1571 POWER_UP_TIME / 20); 1572 return false; 1573 } 1574 } 1575 1576 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1577 1578 return true; 1579} 1580 1581bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1582{ 1583 struct ath_common *common = ath9k_hw_common(ah); 1584 int status = true, setChip = true; 1585 static const char *modes[] = { 1586 "AWAKE", 1587 "FULL-SLEEP", 1588 "NETWORK SLEEP", 1589 "UNDEFINED" 1590 }; 1591 1592 if (ah->power_mode == mode) 1593 return status; 1594 1595 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", 1596 modes[ah->power_mode], modes[mode]); 1597 1598 switch (mode) { 1599 case ATH9K_PM_AWAKE: 1600 status = ath9k_hw_set_power_awake(ah, setChip); 1601 break; 1602 case ATH9K_PM_FULL_SLEEP: 1603 ath9k_set_power_sleep(ah, setChip); 1604 ah->chip_fullsleep = true; 1605 break; 1606 case ATH9K_PM_NETWORK_SLEEP: 1607 ath9k_set_power_network_sleep(ah, setChip); 1608 break; 1609 default: 1610 ath_err(common, "Unknown power mode %u\n", mode); 1611 return false; 1612 } 1613 ah->power_mode = mode; 1614 1615 /* 1616 * XXX: If this warning never comes up after a while then 1617 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 1618 * ath9k_hw_setpower() return type void. 1619 */ 1620 1621 if (!(ah->ah_flags & AH_UNPLUGGED)) 1622 ATH_DBG_WARN_ON_ONCE(!status); 1623 1624 return status; 1625} 1626EXPORT_SYMBOL(ath9k_hw_setpower); 1627 1628/*******************/ 1629/* Beacon Handling */ 1630/*******************/ 1631 1632void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1633{ 1634 int flags = 0; 1635 1636 ENABLE_REGWRITE_BUFFER(ah); 1637 1638 switch (ah->opmode) { 1639 case NL80211_IFTYPE_ADHOC: 1640 case NL80211_IFTYPE_MESH_POINT: 1641 REG_SET_BIT(ah, AR_TXCFG, 1642 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1643 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 1644 TU_TO_USEC(next_beacon + 1645 (ah->atim_window ? ah-> 1646 atim_window : 1))); 1647 flags |= AR_NDP_TIMER_EN; 1648 case NL80211_IFTYPE_AP: 1649 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1650 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 1651 TU_TO_USEC(next_beacon - 1652 ah->config. 1653 dma_beacon_response_time)); 1654 REG_WRITE(ah, AR_NEXT_SWBA, 1655 TU_TO_USEC(next_beacon - 1656 ah->config. 1657 sw_beacon_response_time)); 1658 flags |= 1659 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1660 break; 1661 default: 1662 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, 1663 "%s: unsupported opmode: %d\n", 1664 __func__, ah->opmode); 1665 return; 1666 break; 1667 } 1668 1669 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1670 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1671 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1672 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1673 1674 REGWRITE_BUFFER_FLUSH(ah); 1675 1676 beacon_period &= ~ATH9K_BEACON_ENA; 1677 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1678 ath9k_hw_reset_tsf(ah); 1679 } 1680 1681 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1682} 1683EXPORT_SYMBOL(ath9k_hw_beaconinit); 1684 1685void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1686 const struct ath9k_beacon_state *bs) 1687{ 1688 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 1689 struct ath9k_hw_capabilities *pCap = &ah->caps; 1690 struct ath_common *common = ath9k_hw_common(ah); 1691 1692 ENABLE_REGWRITE_BUFFER(ah); 1693 1694 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1695 1696 REG_WRITE(ah, AR_BEACON_PERIOD, 1697 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1698 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1699 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1700 1701 REGWRITE_BUFFER_FLUSH(ah); 1702 1703 REG_RMW_FIELD(ah, AR_RSSI_THR, 1704 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1705 1706 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 1707 1708 if (bs->bs_sleepduration > beaconintval) 1709 beaconintval = bs->bs_sleepduration; 1710 1711 dtimperiod = bs->bs_dtimperiod; 1712 if (bs->bs_sleepduration > dtimperiod) 1713 dtimperiod = bs->bs_sleepduration; 1714 1715 if (beaconintval == dtimperiod) 1716 nextTbtt = bs->bs_nextdtim; 1717 else 1718 nextTbtt = bs->bs_nexttbtt; 1719 1720 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 1721 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 1722 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1723 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1724 1725 ENABLE_REGWRITE_BUFFER(ah); 1726 1727 REG_WRITE(ah, AR_NEXT_DTIM, 1728 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 1729 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 1730 1731 REG_WRITE(ah, AR_SLEEP1, 1732 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 1733 | AR_SLEEP1_ASSUME_DTIM); 1734 1735 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 1736 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 1737 else 1738 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 1739 1740 REG_WRITE(ah, AR_SLEEP2, 1741 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 1742 1743 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 1744 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1745 1746 REGWRITE_BUFFER_FLUSH(ah); 1747 1748 REG_SET_BIT(ah, AR_TIMER_MODE, 1749 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1750 AR_DTIM_TIMER_EN); 1751 1752 /* TSF Out of Range Threshold */ 1753 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 1754} 1755EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 1756 1757/*******************/ 1758/* HW Capabilities */ 1759/*******************/ 1760 1761int ath9k_hw_fill_cap_info(struct ath_hw *ah) 1762{ 1763 struct ath9k_hw_capabilities *pCap = &ah->caps; 1764 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1765 struct ath_common *common = ath9k_hw_common(ah); 1766 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 1767 1768 u16 capField = 0, eeval; 1769 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 1770 1771 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 1772 regulatory->current_rd = eeval; 1773 1774 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 1775 if (AR_SREV_9285_12_OR_LATER(ah)) 1776 eeval |= AR9285_RDEXT_DEFAULT; 1777 regulatory->current_rd_ext = eeval; 1778 1779 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 1780 1781 if (ah->opmode != NL80211_IFTYPE_AP && 1782 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 1783 if (regulatory->current_rd == 0x64 || 1784 regulatory->current_rd == 0x65) 1785 regulatory->current_rd += 5; 1786 else if (regulatory->current_rd == 0x41) 1787 regulatory->current_rd = 0x43; 1788 ath_dbg(common, ATH_DBG_REGULATORY, 1789 "regdomain mapped to 0x%x\n", regulatory->current_rd); 1790 } 1791 1792 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 1793 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 1794 ath_err(common, 1795 "no band has been marked as supported in EEPROM\n"); 1796 return -EINVAL; 1797 } 1798 1799 if (eeval & AR5416_OPFLAGS_11A) 1800 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 1801 1802 if (eeval & AR5416_OPFLAGS_11G) 1803 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 1804 1805 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 1806 /* 1807 * For AR9271 we will temporarilly uses the rx chainmax as read from 1808 * the EEPROM. 1809 */ 1810 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 1811 !(eeval & AR5416_OPFLAGS_11A) && 1812 !(AR_SREV_9271(ah))) 1813 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 1814 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 1815 else 1816 /* Use rx_chainmask from EEPROM. */ 1817 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 1818 1819 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 1820 1821 /* enable key search for every frame in an aggregate */ 1822 if (AR_SREV_9300_20_OR_LATER(ah)) 1823 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 1824 1825 pCap->low_2ghz_chan = 2312; 1826 pCap->high_2ghz_chan = 2732; 1827 1828 pCap->low_5ghz_chan = 4920; 1829 pCap->high_5ghz_chan = 6100; 1830 1831 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 1832 1833 if (ah->config.ht_enable) 1834 pCap->hw_caps |= ATH9K_HW_CAP_HT; 1835 else 1836 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 1837 1838 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 1839 pCap->total_queues = 1840 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 1841 else 1842 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 1843 1844 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 1845 pCap->keycache_size = 1846 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 1847 else 1848 pCap->keycache_size = AR_KEYTABLE_SIZE; 1849 1850 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 1851 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; 1852 else 1853 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 1854 1855 if (AR_SREV_9271(ah)) 1856 pCap->num_gpio_pins = AR9271_NUM_GPIO; 1857 else if (AR_DEVID_7010(ah)) 1858 pCap->num_gpio_pins = AR7010_NUM_GPIO; 1859 else if (AR_SREV_9285_12_OR_LATER(ah)) 1860 pCap->num_gpio_pins = AR9285_NUM_GPIO; 1861 else if (AR_SREV_9280_20_OR_LATER(ah)) 1862 pCap->num_gpio_pins = AR928X_NUM_GPIO; 1863 else 1864 pCap->num_gpio_pins = AR_NUM_GPIO; 1865 1866 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 1867 pCap->hw_caps |= ATH9K_HW_CAP_CST; 1868 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 1869 } else { 1870 pCap->rts_aggr_limit = (8 * 1024); 1871 } 1872 1873 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 1874 1875#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1876 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 1877 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 1878 ah->rfkill_gpio = 1879 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 1880 ah->rfkill_polarity = 1881 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 1882 1883 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 1884 } 1885#endif 1886 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 1887 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 1888 else 1889 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 1890 1891 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 1892 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 1893 else 1894 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 1895 1896 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 1897 pCap->reg_cap = 1898 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 1899 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 1900 AR_EEPROM_EEREGCAP_EN_KK_U2 | 1901 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 1902 } else { 1903 pCap->reg_cap = 1904 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 1905 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 1906 } 1907 1908 /* Advertise midband for AR5416 with FCC midband set in eeprom */ 1909 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && 1910 AR_SREV_5416(ah)) 1911 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 1912 1913 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) { 1914 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 1915 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 1916 1917 if (AR_SREV_9285(ah)) { 1918 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 1919 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; 1920 } else { 1921 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 1922 } 1923 } else { 1924 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 1925 } 1926 1927 if (AR_SREV_9300_20_OR_LATER(ah)) { 1928 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 1929 if (!AR_SREV_9485(ah)) 1930 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 1931 1932 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 1933 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 1934 pCap->rx_status_len = sizeof(struct ar9003_rxs); 1935 pCap->tx_desc_len = sizeof(struct ar9003_txc); 1936 pCap->txs_len = sizeof(struct ar9003_txs); 1937 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 1938 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 1939 } else { 1940 pCap->tx_desc_len = sizeof(struct ath_desc); 1941 if (AR_SREV_9280_20(ah) && 1942 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= 1943 AR5416_EEP_MINOR_VER_16) || 1944 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) 1945 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 1946 } 1947 1948 if (AR_SREV_9300_20_OR_LATER(ah)) 1949 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 1950 1951 if (AR_SREV_9300_20_OR_LATER(ah)) 1952 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 1953 1954 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 1955 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 1956 1957 if (AR_SREV_9285(ah)) 1958 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 1959 ant_div_ctl1 = 1960 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 1961 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 1962 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 1963 } 1964 if (AR_SREV_9300_20_OR_LATER(ah)) { 1965 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 1966 pCap->hw_caps |= ATH9K_HW_CAP_APM; 1967 } 1968 1969 1970 1971 if (AR_SREV_9485_10(ah)) { 1972 pCap->pcie_lcr_extsync_en = true; 1973 pCap->pcie_lcr_offset = 0x80; 1974 } 1975 1976 tx_chainmask = pCap->tx_chainmask; 1977 rx_chainmask = pCap->rx_chainmask; 1978 while (tx_chainmask || rx_chainmask) { 1979 if (tx_chainmask & BIT(0)) 1980 pCap->max_txchains++; 1981 if (rx_chainmask & BIT(0)) 1982 pCap->max_rxchains++; 1983 1984 tx_chainmask >>= 1; 1985 rx_chainmask >>= 1; 1986 } 1987 1988 return 0; 1989} 1990 1991/****************************/ 1992/* GPIO / RFKILL / Antennae */ 1993/****************************/ 1994 1995static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 1996 u32 gpio, u32 type) 1997{ 1998 int addr; 1999 u32 gpio_shift, tmp; 2000 2001 if (gpio > 11) 2002 addr = AR_GPIO_OUTPUT_MUX3; 2003 else if (gpio > 5) 2004 addr = AR_GPIO_OUTPUT_MUX2; 2005 else 2006 addr = AR_GPIO_OUTPUT_MUX1; 2007 2008 gpio_shift = (gpio % 6) * 5; 2009 2010 if (AR_SREV_9280_20_OR_LATER(ah) 2011 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2012 REG_RMW(ah, addr, (type << gpio_shift), 2013 (0x1f << gpio_shift)); 2014 } else { 2015 tmp = REG_READ(ah, addr); 2016 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2017 tmp &= ~(0x1f << gpio_shift); 2018 tmp |= (type << gpio_shift); 2019 REG_WRITE(ah, addr, tmp); 2020 } 2021} 2022 2023void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2024{ 2025 u32 gpio_shift; 2026 2027 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2028 2029 if (AR_DEVID_7010(ah)) { 2030 gpio_shift = gpio; 2031 REG_RMW(ah, AR7010_GPIO_OE, 2032 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2033 (AR7010_GPIO_OE_MASK << gpio_shift)); 2034 return; 2035 } 2036 2037 gpio_shift = gpio << 1; 2038 REG_RMW(ah, 2039 AR_GPIO_OE_OUT, 2040 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2041 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2042} 2043EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2044 2045u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2046{ 2047#define MS_REG_READ(x, y) \ 2048 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2049 2050 if (gpio >= ah->caps.num_gpio_pins) 2051 return 0xffffffff; 2052 2053 if (AR_DEVID_7010(ah)) { 2054 u32 val; 2055 val = REG_READ(ah, AR7010_GPIO_IN); 2056 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2057 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2058 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2059 AR_GPIO_BIT(gpio)) != 0; 2060 else if (AR_SREV_9271(ah)) 2061 return MS_REG_READ(AR9271, gpio) != 0; 2062 else if (AR_SREV_9287_11_OR_LATER(ah)) 2063 return MS_REG_READ(AR9287, gpio) != 0; 2064 else if (AR_SREV_9285_12_OR_LATER(ah)) 2065 return MS_REG_READ(AR9285, gpio) != 0; 2066 else if (AR_SREV_9280_20_OR_LATER(ah)) 2067 return MS_REG_READ(AR928X, gpio) != 0; 2068 else 2069 return MS_REG_READ(AR, gpio) != 0; 2070} 2071EXPORT_SYMBOL(ath9k_hw_gpio_get); 2072 2073void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2074 u32 ah_signal_type) 2075{ 2076 u32 gpio_shift; 2077 2078 if (AR_DEVID_7010(ah)) { 2079 gpio_shift = gpio; 2080 REG_RMW(ah, AR7010_GPIO_OE, 2081 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2082 (AR7010_GPIO_OE_MASK << gpio_shift)); 2083 return; 2084 } 2085 2086 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2087 gpio_shift = 2 * gpio; 2088 REG_RMW(ah, 2089 AR_GPIO_OE_OUT, 2090 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2091 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2092} 2093EXPORT_SYMBOL(ath9k_hw_cfg_output); 2094 2095void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2096{ 2097 if (AR_DEVID_7010(ah)) { 2098 val = val ? 0 : 1; 2099 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2100 AR_GPIO_BIT(gpio)); 2101 return; 2102 } 2103 2104 if (AR_SREV_9271(ah)) 2105 val = ~val; 2106 2107 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2108 AR_GPIO_BIT(gpio)); 2109} 2110EXPORT_SYMBOL(ath9k_hw_set_gpio); 2111 2112u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2113{ 2114 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2115} 2116EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2117 2118void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2119{ 2120 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2121} 2122EXPORT_SYMBOL(ath9k_hw_setantenna); 2123 2124/*********************/ 2125/* General Operation */ 2126/*********************/ 2127 2128u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2129{ 2130 u32 bits = REG_READ(ah, AR_RX_FILTER); 2131 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2132 2133 if (phybits & AR_PHY_ERR_RADAR) 2134 bits |= ATH9K_RX_FILTER_PHYRADAR; 2135 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2136 bits |= ATH9K_RX_FILTER_PHYERR; 2137 2138 return bits; 2139} 2140EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2141 2142void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2143{ 2144 u32 phybits; 2145 2146 ENABLE_REGWRITE_BUFFER(ah); 2147 2148 REG_WRITE(ah, AR_RX_FILTER, bits); 2149 2150 phybits = 0; 2151 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2152 phybits |= AR_PHY_ERR_RADAR; 2153 if (bits & ATH9K_RX_FILTER_PHYERR) 2154 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2155 REG_WRITE(ah, AR_PHY_ERR, phybits); 2156 2157 if (phybits) 2158 REG_WRITE(ah, AR_RXCFG, 2159 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 2160 else 2161 REG_WRITE(ah, AR_RXCFG, 2162 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2163 2164 REGWRITE_BUFFER_FLUSH(ah); 2165} 2166EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2167 2168bool ath9k_hw_phy_disable(struct ath_hw *ah) 2169{ 2170 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2171 return false; 2172 2173 ath9k_hw_init_pll(ah, NULL); 2174 return true; 2175} 2176EXPORT_SYMBOL(ath9k_hw_phy_disable); 2177 2178bool ath9k_hw_disable(struct ath_hw *ah) 2179{ 2180 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2181 return false; 2182 2183 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2184 return false; 2185 2186 ath9k_hw_init_pll(ah, NULL); 2187 return true; 2188} 2189EXPORT_SYMBOL(ath9k_hw_disable); 2190 2191void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2192{ 2193 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2194 struct ath9k_channel *chan = ah->curchan; 2195 struct ieee80211_channel *channel = chan->chan; 2196 2197 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 2198 2199 ah->eep_ops->set_txpower(ah, chan, 2200 ath9k_regd_get_ctl(regulatory, chan), 2201 channel->max_antenna_gain * 2, 2202 channel->max_power * 2, 2203 min((u32) MAX_RATE_POWER, 2204 (u32) regulatory->power_limit), test); 2205} 2206EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2207 2208void ath9k_hw_setopmode(struct ath_hw *ah) 2209{ 2210 ath9k_hw_set_operating_mode(ah, ah->opmode); 2211} 2212EXPORT_SYMBOL(ath9k_hw_setopmode); 2213 2214void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2215{ 2216 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2217 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2218} 2219EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2220 2221void ath9k_hw_write_associd(struct ath_hw *ah) 2222{ 2223 struct ath_common *common = ath9k_hw_common(ah); 2224 2225 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2226 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2227 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2228} 2229EXPORT_SYMBOL(ath9k_hw_write_associd); 2230 2231#define ATH9K_MAX_TSF_READ 10 2232 2233u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2234{ 2235 u32 tsf_lower, tsf_upper1, tsf_upper2; 2236 int i; 2237 2238 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2239 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2240 tsf_lower = REG_READ(ah, AR_TSF_L32); 2241 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2242 if (tsf_upper2 == tsf_upper1) 2243 break; 2244 tsf_upper1 = tsf_upper2; 2245 } 2246 2247 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2248 2249 return (((u64)tsf_upper1 << 32) | tsf_lower); 2250} 2251EXPORT_SYMBOL(ath9k_hw_gettsf64); 2252 2253void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2254{ 2255 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2256 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2257} 2258EXPORT_SYMBOL(ath9k_hw_settsf64); 2259 2260void ath9k_hw_reset_tsf(struct ath_hw *ah) 2261{ 2262 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2263 AH_TSF_WRITE_TIMEOUT)) 2264 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 2265 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2266 2267 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2268} 2269EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2270 2271void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2272{ 2273 if (setting) 2274 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2275 else 2276 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2277} 2278EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2279 2280void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2281{ 2282 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2283 u32 macmode; 2284 2285 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2286 macmode = AR_2040_JOINED_RX_CLEAR; 2287 else 2288 macmode = 0; 2289 2290 REG_WRITE(ah, AR_2040_MODE, macmode); 2291} 2292 2293/* HW Generic timers configuration */ 2294 2295static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2296{ 2297 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2298 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2299 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2300 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2301 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2302 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2303 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2304 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2305 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2306 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2307 AR_NDP2_TIMER_MODE, 0x0002}, 2308 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2309 AR_NDP2_TIMER_MODE, 0x0004}, 2310 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2311 AR_NDP2_TIMER_MODE, 0x0008}, 2312 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2313 AR_NDP2_TIMER_MODE, 0x0010}, 2314 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2315 AR_NDP2_TIMER_MODE, 0x0020}, 2316 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2317 AR_NDP2_TIMER_MODE, 0x0040}, 2318 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2319 AR_NDP2_TIMER_MODE, 0x0080} 2320}; 2321 2322/* HW generic timer primitives */ 2323 2324/* compute and clear index of rightmost 1 */ 2325static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2326{ 2327 u32 b; 2328 2329 b = *mask; 2330 b &= (0-b); 2331 *mask &= ~b; 2332 b *= debruijn32; 2333 b >>= 27; 2334 2335 return timer_table->gen_timer_index[b]; 2336} 2337 2338static u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2339{ 2340 return REG_READ(ah, AR_TSF_L32); 2341} 2342 2343struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2344 void (*trigger)(void *), 2345 void (*overflow)(void *), 2346 void *arg, 2347 u8 timer_index) 2348{ 2349 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2350 struct ath_gen_timer *timer; 2351 2352 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2353 2354 if (timer == NULL) { 2355 ath_err(ath9k_hw_common(ah), 2356 "Failed to allocate memory for hw timer[%d]\n", 2357 timer_index); 2358 return NULL; 2359 } 2360 2361 /* allocate a hardware generic timer slot */ 2362 timer_table->timers[timer_index] = timer; 2363 timer->index = timer_index; 2364 timer->trigger = trigger; 2365 timer->overflow = overflow; 2366 timer->arg = arg; 2367 2368 return timer; 2369} 2370EXPORT_SYMBOL(ath_gen_timer_alloc); 2371 2372void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2373 struct ath_gen_timer *timer, 2374 u32 timer_next, 2375 u32 timer_period) 2376{ 2377 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2378 u32 tsf; 2379 2380 BUG_ON(!timer_period); 2381 2382 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2383 2384 tsf = ath9k_hw_gettsf32(ah); 2385 2386 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2387 "current tsf %x period %x timer_next %x\n", 2388 tsf, timer_period, timer_next); 2389 2390 /* 2391 * Pull timer_next forward if the current TSF already passed it 2392 * because of software latency 2393 */ 2394 if (timer_next < tsf) 2395 timer_next = tsf + timer_period; 2396 2397 /* 2398 * Program generic timer registers 2399 */ 2400 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2401 timer_next); 2402 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2403 timer_period); 2404 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2405 gen_tmr_configuration[timer->index].mode_mask); 2406 2407 /* Enable both trigger and thresh interrupt masks */ 2408 REG_SET_BIT(ah, AR_IMR_S5, 2409 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2410 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2411} 2412EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2413 2414void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2415{ 2416 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2417 2418 if ((timer->index < AR_FIRST_NDP_TIMER) || 2419 (timer->index >= ATH_MAX_GEN_TIMER)) { 2420 return; 2421 } 2422 2423 /* Clear generic timer enable bits. */ 2424 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2425 gen_tmr_configuration[timer->index].mode_mask); 2426 2427 /* Disable both trigger and thresh interrupt masks */ 2428 REG_CLR_BIT(ah, AR_IMR_S5, 2429 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2430 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2431 2432 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2433} 2434EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2435 2436void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2437{ 2438 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2439 2440 /* free the hardware generic timer slot */ 2441 timer_table->timers[timer->index] = NULL; 2442 kfree(timer); 2443} 2444EXPORT_SYMBOL(ath_gen_timer_free); 2445 2446/* 2447 * Generic Timer Interrupts handling 2448 */ 2449void ath_gen_timer_isr(struct ath_hw *ah) 2450{ 2451 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2452 struct ath_gen_timer *timer; 2453 struct ath_common *common = ath9k_hw_common(ah); 2454 u32 trigger_mask, thresh_mask, index; 2455 2456 /* get hardware generic timer interrupt status */ 2457 trigger_mask = ah->intr_gen_timer_trigger; 2458 thresh_mask = ah->intr_gen_timer_thresh; 2459 trigger_mask &= timer_table->timer_mask.val; 2460 thresh_mask &= timer_table->timer_mask.val; 2461 2462 trigger_mask &= ~thresh_mask; 2463 2464 while (thresh_mask) { 2465 index = rightmost_index(timer_table, &thresh_mask); 2466 timer = timer_table->timers[index]; 2467 BUG_ON(!timer); 2468 ath_dbg(common, ATH_DBG_HWTIMER, 2469 "TSF overflow for Gen timer %d\n", index); 2470 timer->overflow(timer->arg); 2471 } 2472 2473 while (trigger_mask) { 2474 index = rightmost_index(timer_table, &trigger_mask); 2475 timer = timer_table->timers[index]; 2476 BUG_ON(!timer); 2477 ath_dbg(common, ATH_DBG_HWTIMER, 2478 "Gen timer[%d] trigger\n", index); 2479 timer->trigger(timer->arg); 2480 } 2481} 2482EXPORT_SYMBOL(ath_gen_timer_isr); 2483 2484/********/ 2485/* HTC */ 2486/********/ 2487 2488void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2489{ 2490 ah->htc_reset_init = true; 2491} 2492EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2493 2494static struct { 2495 u32 version; 2496 const char * name; 2497} ath_mac_bb_names[] = { 2498 /* Devices with external radios */ 2499 { AR_SREV_VERSION_5416_PCI, "5416" }, 2500 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2501 { AR_SREV_VERSION_9100, "9100" }, 2502 { AR_SREV_VERSION_9160, "9160" }, 2503 /* Single-chip solutions */ 2504 { AR_SREV_VERSION_9280, "9280" }, 2505 { AR_SREV_VERSION_9285, "9285" }, 2506 { AR_SREV_VERSION_9287, "9287" }, 2507 { AR_SREV_VERSION_9271, "9271" }, 2508 { AR_SREV_VERSION_9300, "9300" }, 2509}; 2510 2511/* For devices with external radios */ 2512static struct { 2513 u16 version; 2514 const char * name; 2515} ath_rf_names[] = { 2516 { 0, "5133" }, 2517 { AR_RAD5133_SREV_MAJOR, "5133" }, 2518 { AR_RAD5122_SREV_MAJOR, "5122" }, 2519 { AR_RAD2133_SREV_MAJOR, "2133" }, 2520 { AR_RAD2122_SREV_MAJOR, "2122" } 2521}; 2522 2523/* 2524 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2525 */ 2526static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2527{ 2528 int i; 2529 2530 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2531 if (ath_mac_bb_names[i].version == mac_bb_version) { 2532 return ath_mac_bb_names[i].name; 2533 } 2534 } 2535 2536 return "????"; 2537} 2538 2539/* 2540 * Return the RF name. "????" is returned if the RF is unknown. 2541 * Used for devices with external radios. 2542 */ 2543static const char *ath9k_hw_rf_name(u16 rf_version) 2544{ 2545 int i; 2546 2547 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2548 if (ath_rf_names[i].version == rf_version) { 2549 return ath_rf_names[i].name; 2550 } 2551 } 2552 2553 return "????"; 2554} 2555 2556void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2557{ 2558 int used; 2559 2560 /* chipsets >= AR9280 are single-chip */ 2561 if (AR_SREV_9280_20_OR_LATER(ah)) { 2562 used = snprintf(hw_name, len, 2563 "Atheros AR%s Rev:%x", 2564 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2565 ah->hw_version.macRev); 2566 } 2567 else { 2568 used = snprintf(hw_name, len, 2569 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2570 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2571 ah->hw_version.macRev, 2572 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2573 AR_RADIO_SREV_MAJOR)), 2574 ah->hw_version.phyRev); 2575 } 2576 2577 hw_name[used] = '\0'; 2578} 2579EXPORT_SYMBOL(ath9k_hw_name); 2580