hw.c revision 040b74f741b20dbf07359716d5c540356a036ade
1/* 2 * Copyright (c) 2008-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <asm/unaligned.h> 20 21#include "hw.h" 22#include "hw-ops.h" 23#include "rc.h" 24#include "ar9003_mac.h" 25 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 27 28MODULE_AUTHOR("Atheros Communications"); 29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 31MODULE_LICENSE("Dual BSD/GPL"); 32 33static int __init ath9k_init(void) 34{ 35 return 0; 36} 37module_init(ath9k_init); 38 39static void __exit ath9k_exit(void) 40{ 41 return; 42} 43module_exit(ath9k_exit); 44 45/* Private hardware callbacks */ 46 47static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 48{ 49 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 50} 51 52static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 53{ 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 55} 56 57static bool ath9k_hw_macversion_supported(struct ath_hw *ah) 58{ 59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 60 61 return priv_ops->macversion_supported(ah->hw_version.macVersion); 62} 63 64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 65 struct ath9k_channel *chan) 66{ 67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 68} 69 70static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 71{ 72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 73 return; 74 75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 76} 77 78static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 79{ 80 /* You will not have this callback if using the old ANI */ 81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 82 return; 83 84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 85} 86 87/********************/ 88/* Helper Functions */ 89/********************/ 90 91static void ath9k_hw_set_clockrate(struct ath_hw *ah) 92{ 93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 94 struct ath_common *common = ath9k_hw_common(ah); 95 unsigned int clockrate; 96 97 if (!ah->curchan) /* should really check for CCK instead */ 98 clockrate = ATH9K_CLOCK_RATE_CCK; 99 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 100 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 101 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 102 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 103 else 104 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 105 106 if (conf_is_ht40(conf)) 107 clockrate *= 2; 108 109 common->clockrate = clockrate; 110} 111 112static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 113{ 114 struct ath_common *common = ath9k_hw_common(ah); 115 116 return usecs * common->clockrate; 117} 118 119bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 120{ 121 int i; 122 123 BUG_ON(timeout < AH_TIME_QUANTUM); 124 125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 126 if ((REG_READ(ah, reg) & mask) == val) 127 return true; 128 129 udelay(AH_TIME_QUANTUM); 130 } 131 132 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, 133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 134 timeout, reg, REG_READ(ah, reg), mask, val); 135 136 return false; 137} 138EXPORT_SYMBOL(ath9k_hw_wait); 139 140u32 ath9k_hw_reverse_bits(u32 val, u32 n) 141{ 142 u32 retval; 143 int i; 144 145 for (i = 0, retval = 0; i < n; i++) { 146 retval = (retval << 1) | (val & 1); 147 val >>= 1; 148 } 149 return retval; 150} 151 152bool ath9k_get_channel_edges(struct ath_hw *ah, 153 u16 flags, u16 *low, 154 u16 *high) 155{ 156 struct ath9k_hw_capabilities *pCap = &ah->caps; 157 158 if (flags & CHANNEL_5GHZ) { 159 *low = pCap->low_5ghz_chan; 160 *high = pCap->high_5ghz_chan; 161 return true; 162 } 163 if ((flags & CHANNEL_2GHZ)) { 164 *low = pCap->low_2ghz_chan; 165 *high = pCap->high_2ghz_chan; 166 return true; 167 } 168 return false; 169} 170 171u16 ath9k_hw_computetxtime(struct ath_hw *ah, 172 u8 phy, int kbps, 173 u32 frameLen, u16 rateix, 174 bool shortPreamble) 175{ 176 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 177 178 if (kbps == 0) 179 return 0; 180 181 switch (phy) { 182 case WLAN_RC_PHY_CCK: 183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 184 if (shortPreamble) 185 phyTime >>= 1; 186 numBits = frameLen << 3; 187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 188 break; 189 case WLAN_RC_PHY_OFDM: 190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 192 numBits = OFDM_PLCP_BITS + (frameLen << 3); 193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 194 txTime = OFDM_SIFS_TIME_QUARTER 195 + OFDM_PREAMBLE_TIME_QUARTER 196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 197 } else if (ah->curchan && 198 IS_CHAN_HALF_RATE(ah->curchan)) { 199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 200 numBits = OFDM_PLCP_BITS + (frameLen << 3); 201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 202 txTime = OFDM_SIFS_TIME_HALF + 203 OFDM_PREAMBLE_TIME_HALF 204 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 205 } else { 206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 207 numBits = OFDM_PLCP_BITS + (frameLen << 3); 208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 210 + (numSymbols * OFDM_SYMBOL_TIME); 211 } 212 break; 213 default: 214 ath_err(ath9k_hw_common(ah), 215 "Unknown phy %u (rate ix %u)\n", phy, rateix); 216 txTime = 0; 217 break; 218 } 219 220 return txTime; 221} 222EXPORT_SYMBOL(ath9k_hw_computetxtime); 223 224void ath9k_hw_get_channel_centers(struct ath_hw *ah, 225 struct ath9k_channel *chan, 226 struct chan_centers *centers) 227{ 228 int8_t extoff; 229 230 if (!IS_CHAN_HT40(chan)) { 231 centers->ctl_center = centers->ext_center = 232 centers->synth_center = chan->channel; 233 return; 234 } 235 236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 237 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 238 centers->synth_center = 239 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 240 extoff = 1; 241 } else { 242 centers->synth_center = 243 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 244 extoff = -1; 245 } 246 247 centers->ctl_center = 248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 249 /* 25 MHz spacing is supported by hw but not on upper layers */ 250 centers->ext_center = 251 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 252} 253 254/******************/ 255/* Chip Revisions */ 256/******************/ 257 258static void ath9k_hw_read_revisions(struct ath_hw *ah) 259{ 260 u32 val; 261 262 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 263 264 if (val == 0xFF) { 265 val = REG_READ(ah, AR_SREV); 266 ah->hw_version.macVersion = 267 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 269 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 270 } else { 271 if (!AR_SREV_9100(ah)) 272 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 273 274 ah->hw_version.macRev = val & AR_SREV_REVISION; 275 276 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 277 ah->is_pciexpress = true; 278 } 279} 280 281/************************************/ 282/* HW Attach, Detach, Init Routines */ 283/************************************/ 284 285static void ath9k_hw_disablepcie(struct ath_hw *ah) 286{ 287 if (!AR_SREV_5416(ah)) 288 return; 289 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 293 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 294 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 295 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 296 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 297 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 298 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 299 300 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 301} 302 303/* This should work for all families including legacy */ 304static bool ath9k_hw_chip_test(struct ath_hw *ah) 305{ 306 struct ath_common *common = ath9k_hw_common(ah); 307 u32 regAddr[2] = { AR_STA_ID0 }; 308 u32 regHold[2]; 309 static const u32 patternData[4] = { 310 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 311 }; 312 int i, j, loop_max; 313 314 if (!AR_SREV_9300_20_OR_LATER(ah)) { 315 loop_max = 2; 316 regAddr[1] = AR_PHY_BASE + (8 << 2); 317 } else 318 loop_max = 1; 319 320 for (i = 0; i < loop_max; i++) { 321 u32 addr = regAddr[i]; 322 u32 wrData, rdData; 323 324 regHold[i] = REG_READ(ah, addr); 325 for (j = 0; j < 0x100; j++) { 326 wrData = (j << 16) | j; 327 REG_WRITE(ah, addr, wrData); 328 rdData = REG_READ(ah, addr); 329 if (rdData != wrData) { 330 ath_err(common, 331 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 332 addr, wrData, rdData); 333 return false; 334 } 335 } 336 for (j = 0; j < 4; j++) { 337 wrData = patternData[j]; 338 REG_WRITE(ah, addr, wrData); 339 rdData = REG_READ(ah, addr); 340 if (wrData != rdData) { 341 ath_err(common, 342 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 343 addr, wrData, rdData); 344 return false; 345 } 346 } 347 REG_WRITE(ah, regAddr[i], regHold[i]); 348 } 349 udelay(100); 350 351 return true; 352} 353 354static void ath9k_hw_init_config(struct ath_hw *ah) 355{ 356 int i; 357 358 ah->config.dma_beacon_response_time = 2; 359 ah->config.sw_beacon_response_time = 10; 360 ah->config.additional_swba_backoff = 0; 361 ah->config.ack_6mb = 0x0; 362 ah->config.cwm_ignore_extcca = 0; 363 ah->config.pcie_powersave_enable = 0; 364 ah->config.pcie_clock_req = 0; 365 ah->config.pcie_waen = 0; 366 ah->config.analog_shiftreg = 1; 367 ah->config.enable_ani = true; 368 369 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 370 ah->config.spurchans[i][0] = AR_NO_SPUR; 371 ah->config.spurchans[i][1] = AR_NO_SPUR; 372 } 373 374 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 375 ah->config.ht_enable = 1; 376 else 377 ah->config.ht_enable = 0; 378 379 ah->config.rx_intr_mitigation = true; 380 ah->config.pcieSerDesWrite = true; 381 382 /* 383 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 384 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 385 * This means we use it for all AR5416 devices, and the few 386 * minor PCI AR9280 devices out there. 387 * 388 * Serialization is required because these devices do not handle 389 * well the case of two concurrent reads/writes due to the latency 390 * involved. During one read/write another read/write can be issued 391 * on another CPU while the previous read/write may still be working 392 * on our hardware, if we hit this case the hardware poops in a loop. 393 * We prevent this by serializing reads and writes. 394 * 395 * This issue is not present on PCI-Express devices or pre-AR5416 396 * devices (legacy, 802.11abg). 397 */ 398 if (num_possible_cpus() > 1) 399 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 400} 401 402static void ath9k_hw_init_defaults(struct ath_hw *ah) 403{ 404 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 405 406 regulatory->country_code = CTRY_DEFAULT; 407 regulatory->power_limit = MAX_RATE_POWER; 408 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 409 410 ah->hw_version.magic = AR5416_MAGIC; 411 ah->hw_version.subvendorid = 0; 412 413 ah->atim_window = 0; 414 ah->sta_id1_defaults = 415 AR_STA_ID1_CRPT_MIC_ENABLE | 416 AR_STA_ID1_MCAST_KSRCH; 417 ah->beacon_interval = 100; 418 ah->enable_32kHz_clock = DONT_USE_32KHZ; 419 ah->slottime = (u32) -1; 420 ah->globaltxtimeout = (u32) -1; 421 ah->power_mode = ATH9K_PM_UNDEFINED; 422} 423 424static int ath9k_hw_init_macaddr(struct ath_hw *ah) 425{ 426 struct ath_common *common = ath9k_hw_common(ah); 427 u32 sum; 428 int i; 429 u16 eeval; 430 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 431 432 sum = 0; 433 for (i = 0; i < 3; i++) { 434 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 435 sum += eeval; 436 common->macaddr[2 * i] = eeval >> 8; 437 common->macaddr[2 * i + 1] = eeval & 0xff; 438 } 439 if (sum == 0 || sum == 0xffff * 3) 440 return -EADDRNOTAVAIL; 441 442 return 0; 443} 444 445static int ath9k_hw_post_init(struct ath_hw *ah) 446{ 447 int ecode; 448 449 if (!AR_SREV_9271(ah)) { 450 if (!ath9k_hw_chip_test(ah)) 451 return -ENODEV; 452 } 453 454 if (!AR_SREV_9300_20_OR_LATER(ah)) { 455 ecode = ar9002_hw_rf_claim(ah); 456 if (ecode != 0) 457 return ecode; 458 } 459 460 ecode = ath9k_hw_eeprom_init(ah); 461 if (ecode != 0) 462 return ecode; 463 464 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, 465 "Eeprom VER: %d, REV: %d\n", 466 ah->eep_ops->get_eeprom_ver(ah), 467 ah->eep_ops->get_eeprom_rev(ah)); 468 469 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 470 if (ecode) { 471 ath_err(ath9k_hw_common(ah), 472 "Failed allocating banks for external radio\n"); 473 ath9k_hw_rf_free_ext_banks(ah); 474 return ecode; 475 } 476 477 if (!AR_SREV_9100(ah)) { 478 ath9k_hw_ani_setup(ah); 479 ath9k_hw_ani_init(ah); 480 } 481 482 return 0; 483} 484 485static void ath9k_hw_attach_ops(struct ath_hw *ah) 486{ 487 if (AR_SREV_9300_20_OR_LATER(ah)) 488 ar9003_hw_attach_ops(ah); 489 else 490 ar9002_hw_attach_ops(ah); 491} 492 493/* Called for all hardware families */ 494static int __ath9k_hw_init(struct ath_hw *ah) 495{ 496 struct ath_common *common = ath9k_hw_common(ah); 497 int r = 0; 498 499 if (ah->hw_version.devid == AR5416_AR9100_DEVID) 500 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 501 502 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 503 ath_err(common, "Couldn't reset chip\n"); 504 return -EIO; 505 } 506 507 ath9k_hw_init_defaults(ah); 508 ath9k_hw_init_config(ah); 509 510 ath9k_hw_attach_ops(ah); 511 512 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 513 ath_err(common, "Couldn't wakeup chip\n"); 514 return -EIO; 515 } 516 517 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 518 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 519 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 520 !ah->is_pciexpress)) { 521 ah->config.serialize_regmode = 522 SER_REG_MODE_ON; 523 } else { 524 ah->config.serialize_regmode = 525 SER_REG_MODE_OFF; 526 } 527 } 528 529 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 530 ah->config.serialize_regmode); 531 532 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 533 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 534 else 535 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 536 537 if (!ath9k_hw_macversion_supported(ah)) { 538 ath_err(common, 539 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 540 ah->hw_version.macVersion, ah->hw_version.macRev); 541 return -EOPNOTSUPP; 542 } 543 544 if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) 545 ah->is_pciexpress = false; 546 547 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 548 ath9k_hw_init_cal_settings(ah); 549 550 ah->ani_function = ATH9K_ANI_ALL; 551 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 552 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 553 if (!AR_SREV_9300_20_OR_LATER(ah)) 554 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 555 556 ath9k_hw_init_mode_regs(ah); 557 558 /* 559 * Read back AR_WA into a permanent copy and set bits 14 and 17. 560 * We need to do this to avoid RMW of this register. We cannot 561 * read the reg when chip is asleep. 562 */ 563 ah->WARegVal = REG_READ(ah, AR_WA); 564 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 565 AR_WA_ASPM_TIMER_BASED_DISABLE); 566 567 if (ah->is_pciexpress) 568 ath9k_hw_configpcipowersave(ah, 0, 0); 569 else 570 ath9k_hw_disablepcie(ah); 571 572 if (!AR_SREV_9300_20_OR_LATER(ah)) 573 ar9002_hw_cck_chan14_spread(ah); 574 575 r = ath9k_hw_post_init(ah); 576 if (r) 577 return r; 578 579 ath9k_hw_init_mode_gain_regs(ah); 580 r = ath9k_hw_fill_cap_info(ah); 581 if (r) 582 return r; 583 584 r = ath9k_hw_init_macaddr(ah); 585 if (r) { 586 ath_err(common, "Failed to initialize MAC address\n"); 587 return r; 588 } 589 590 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 591 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 592 else 593 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 594 595 ah->bb_watchdog_timeout_ms = 25; 596 597 common->state = ATH_HW_INITIALIZED; 598 599 return 0; 600} 601 602int ath9k_hw_init(struct ath_hw *ah) 603{ 604 int ret; 605 struct ath_common *common = ath9k_hw_common(ah); 606 607 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 608 switch (ah->hw_version.devid) { 609 case AR5416_DEVID_PCI: 610 case AR5416_DEVID_PCIE: 611 case AR5416_AR9100_DEVID: 612 case AR9160_DEVID_PCI: 613 case AR9280_DEVID_PCI: 614 case AR9280_DEVID_PCIE: 615 case AR9285_DEVID_PCIE: 616 case AR9287_DEVID_PCI: 617 case AR9287_DEVID_PCIE: 618 case AR2427_DEVID_PCIE: 619 case AR9300_DEVID_PCIE: 620 case AR9300_DEVID_AR9485_PCIE: 621 break; 622 default: 623 if (common->bus_ops->ath_bus_type == ATH_USB) 624 break; 625 ath_err(common, "Hardware device ID 0x%04x not supported\n", 626 ah->hw_version.devid); 627 return -EOPNOTSUPP; 628 } 629 630 ret = __ath9k_hw_init(ah); 631 if (ret) { 632 ath_err(common, 633 "Unable to initialize hardware; initialization status: %d\n", 634 ret); 635 return ret; 636 } 637 638 return 0; 639} 640EXPORT_SYMBOL(ath9k_hw_init); 641 642static void ath9k_hw_init_qos(struct ath_hw *ah) 643{ 644 ENABLE_REGWRITE_BUFFER(ah); 645 646 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 647 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 648 649 REG_WRITE(ah, AR_QOS_NO_ACK, 650 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 651 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 652 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 653 654 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 655 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 656 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 657 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 658 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 659 660 REGWRITE_BUFFER_FLUSH(ah); 661} 662 663static void ath9k_hw_init_pll(struct ath_hw *ah, 664 struct ath9k_channel *chan) 665{ 666 u32 pll; 667 668 if (AR_SREV_9485(ah)) 669 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666); 670 671 pll = ath9k_hw_compute_pll_control(ah, chan); 672 673 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 674 675 /* Switch the core clock for ar9271 to 117Mhz */ 676 if (AR_SREV_9271(ah)) { 677 udelay(500); 678 REG_WRITE(ah, 0x50040, 0x304); 679 } 680 681 udelay(RTC_PLL_SETTLE_DELAY); 682 683 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 684} 685 686static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 687 enum nl80211_iftype opmode) 688{ 689 u32 imr_reg = AR_IMR_TXERR | 690 AR_IMR_TXURN | 691 AR_IMR_RXERR | 692 AR_IMR_RXORN | 693 AR_IMR_BCNMISC; 694 695 if (AR_SREV_9300_20_OR_LATER(ah)) { 696 imr_reg |= AR_IMR_RXOK_HP; 697 if (ah->config.rx_intr_mitigation) 698 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 699 else 700 imr_reg |= AR_IMR_RXOK_LP; 701 702 } else { 703 if (ah->config.rx_intr_mitigation) 704 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 705 else 706 imr_reg |= AR_IMR_RXOK; 707 } 708 709 if (ah->config.tx_intr_mitigation) 710 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 711 else 712 imr_reg |= AR_IMR_TXOK; 713 714 if (opmode == NL80211_IFTYPE_AP) 715 imr_reg |= AR_IMR_MIB; 716 717 ENABLE_REGWRITE_BUFFER(ah); 718 719 REG_WRITE(ah, AR_IMR, imr_reg); 720 ah->imrs2_reg |= AR_IMR_S2_GTT; 721 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 722 723 if (!AR_SREV_9100(ah)) { 724 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 725 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 726 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 727 } 728 729 REGWRITE_BUFFER_FLUSH(ah); 730 731 if (AR_SREV_9300_20_OR_LATER(ah)) { 732 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 733 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 734 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 735 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 736 } 737} 738 739static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 740{ 741 u32 val = ath9k_hw_mac_to_clks(ah, us); 742 val = min(val, (u32) 0xFFFF); 743 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 744} 745 746static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 747{ 748 u32 val = ath9k_hw_mac_to_clks(ah, us); 749 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 750 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 751} 752 753static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 754{ 755 u32 val = ath9k_hw_mac_to_clks(ah, us); 756 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 757 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 758} 759 760static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 761{ 762 if (tu > 0xFFFF) { 763 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 764 "bad global tx timeout %u\n", tu); 765 ah->globaltxtimeout = (u32) -1; 766 return false; 767 } else { 768 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 769 ah->globaltxtimeout = tu; 770 return true; 771 } 772} 773 774void ath9k_hw_init_global_settings(struct ath_hw *ah) 775{ 776 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 777 int acktimeout; 778 int slottime; 779 int sifstime; 780 781 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 782 ah->misc_mode); 783 784 if (ah->misc_mode != 0) 785 REG_WRITE(ah, AR_PCU_MISC, 786 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 787 788 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 789 sifstime = 16; 790 else 791 sifstime = 10; 792 793 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 794 slottime = ah->slottime + 3 * ah->coverage_class; 795 acktimeout = slottime + sifstime; 796 797 /* 798 * Workaround for early ACK timeouts, add an offset to match the 799 * initval's 64us ack timeout value. 800 * This was initially only meant to work around an issue with delayed 801 * BA frames in some implementations, but it has been found to fix ACK 802 * timeout issues in other cases as well. 803 */ 804 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 805 acktimeout += 64 - sifstime - ah->slottime; 806 807 ath9k_hw_setslottime(ah, slottime); 808 ath9k_hw_set_ack_timeout(ah, acktimeout); 809 ath9k_hw_set_cts_timeout(ah, acktimeout); 810 if (ah->globaltxtimeout != (u32) -1) 811 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 812} 813EXPORT_SYMBOL(ath9k_hw_init_global_settings); 814 815void ath9k_hw_deinit(struct ath_hw *ah) 816{ 817 struct ath_common *common = ath9k_hw_common(ah); 818 819 if (common->state < ATH_HW_INITIALIZED) 820 goto free_hw; 821 822 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 823 824free_hw: 825 ath9k_hw_rf_free_ext_banks(ah); 826} 827EXPORT_SYMBOL(ath9k_hw_deinit); 828 829/*******/ 830/* INI */ 831/*******/ 832 833u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 834{ 835 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 836 837 if (IS_CHAN_B(chan)) 838 ctl |= CTL_11B; 839 else if (IS_CHAN_G(chan)) 840 ctl |= CTL_11G; 841 else 842 ctl |= CTL_11A; 843 844 return ctl; 845} 846 847/****************************************/ 848/* Reset and Channel Switching Routines */ 849/****************************************/ 850 851static inline void ath9k_hw_set_dma(struct ath_hw *ah) 852{ 853 struct ath_common *common = ath9k_hw_common(ah); 854 u32 regval; 855 856 ENABLE_REGWRITE_BUFFER(ah); 857 858 /* 859 * set AHB_MODE not to do cacheline prefetches 860 */ 861 if (!AR_SREV_9300_20_OR_LATER(ah)) { 862 regval = REG_READ(ah, AR_AHB_MODE); 863 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 864 } 865 866 /* 867 * let mac dma reads be in 128 byte chunks 868 */ 869 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 870 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 871 872 REGWRITE_BUFFER_FLUSH(ah); 873 874 /* 875 * Restore TX Trigger Level to its pre-reset value. 876 * The initial value depends on whether aggregation is enabled, and is 877 * adjusted whenever underruns are detected. 878 */ 879 if (!AR_SREV_9300_20_OR_LATER(ah)) 880 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 881 882 ENABLE_REGWRITE_BUFFER(ah); 883 884 /* 885 * let mac dma writes be in 128 byte chunks 886 */ 887 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 888 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 889 890 /* 891 * Setup receive FIFO threshold to hold off TX activities 892 */ 893 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 894 895 if (AR_SREV_9300_20_OR_LATER(ah)) { 896 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 897 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 898 899 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 900 ah->caps.rx_status_len); 901 } 902 903 /* 904 * reduce the number of usable entries in PCU TXBUF to avoid 905 * wrap around issues. 906 */ 907 if (AR_SREV_9285(ah)) { 908 /* For AR9285 the number of Fifos are reduced to half. 909 * So set the usable tx buf size also to half to 910 * avoid data/delimiter underruns 911 */ 912 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 913 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 914 } else if (!AR_SREV_9271(ah)) { 915 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 916 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 917 } 918 919 REGWRITE_BUFFER_FLUSH(ah); 920 921 if (AR_SREV_9300_20_OR_LATER(ah)) 922 ath9k_hw_reset_txstatus_ring(ah); 923} 924 925static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 926{ 927 u32 val; 928 929 val = REG_READ(ah, AR_STA_ID1); 930 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 931 switch (opmode) { 932 case NL80211_IFTYPE_AP: 933 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 934 | AR_STA_ID1_KSRCH_MODE); 935 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 936 break; 937 case NL80211_IFTYPE_ADHOC: 938 case NL80211_IFTYPE_MESH_POINT: 939 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 940 | AR_STA_ID1_KSRCH_MODE); 941 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 942 break; 943 case NL80211_IFTYPE_STATION: 944 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 945 break; 946 default: 947 if (ah->is_monitoring) 948 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 949 break; 950 } 951} 952 953void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 954 u32 *coef_mantissa, u32 *coef_exponent) 955{ 956 u32 coef_exp, coef_man; 957 958 for (coef_exp = 31; coef_exp > 0; coef_exp--) 959 if ((coef_scaled >> coef_exp) & 0x1) 960 break; 961 962 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 963 964 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 965 966 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 967 *coef_exponent = coef_exp - 16; 968} 969 970static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 971{ 972 u32 rst_flags; 973 u32 tmpReg; 974 975 if (AR_SREV_9100(ah)) { 976 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 977 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 978 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 979 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 980 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 981 } 982 983 ENABLE_REGWRITE_BUFFER(ah); 984 985 if (AR_SREV_9300_20_OR_LATER(ah)) { 986 REG_WRITE(ah, AR_WA, ah->WARegVal); 987 udelay(10); 988 } 989 990 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 991 AR_RTC_FORCE_WAKE_ON_INT); 992 993 if (AR_SREV_9100(ah)) { 994 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 995 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 996 } else { 997 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 998 if (tmpReg & 999 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1000 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1001 u32 val; 1002 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1003 1004 val = AR_RC_HOSTIF; 1005 if (!AR_SREV_9300_20_OR_LATER(ah)) 1006 val |= AR_RC_AHB; 1007 REG_WRITE(ah, AR_RC, val); 1008 1009 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1010 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1011 1012 rst_flags = AR_RTC_RC_MAC_WARM; 1013 if (type == ATH9K_RESET_COLD) 1014 rst_flags |= AR_RTC_RC_MAC_COLD; 1015 } 1016 1017 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1018 1019 REGWRITE_BUFFER_FLUSH(ah); 1020 1021 udelay(50); 1022 1023 REG_WRITE(ah, AR_RTC_RC, 0); 1024 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1025 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1026 "RTC stuck in MAC reset\n"); 1027 return false; 1028 } 1029 1030 if (!AR_SREV_9100(ah)) 1031 REG_WRITE(ah, AR_RC, 0); 1032 1033 if (AR_SREV_9100(ah)) 1034 udelay(50); 1035 1036 return true; 1037} 1038 1039static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1040{ 1041 ENABLE_REGWRITE_BUFFER(ah); 1042 1043 if (AR_SREV_9300_20_OR_LATER(ah)) { 1044 REG_WRITE(ah, AR_WA, ah->WARegVal); 1045 udelay(10); 1046 } 1047 1048 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1049 AR_RTC_FORCE_WAKE_ON_INT); 1050 1051 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1052 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1053 1054 REG_WRITE(ah, AR_RTC_RESET, 0); 1055 udelay(2); 1056 1057 REGWRITE_BUFFER_FLUSH(ah); 1058 1059 if (!AR_SREV_9300_20_OR_LATER(ah)) 1060 udelay(2); 1061 1062 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1063 REG_WRITE(ah, AR_RC, 0); 1064 1065 REG_WRITE(ah, AR_RTC_RESET, 1); 1066 1067 if (!ath9k_hw_wait(ah, 1068 AR_RTC_STATUS, 1069 AR_RTC_STATUS_M, 1070 AR_RTC_STATUS_ON, 1071 AH_WAIT_TIMEOUT)) { 1072 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1073 "RTC not waking up\n"); 1074 return false; 1075 } 1076 1077 ath9k_hw_read_revisions(ah); 1078 1079 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1080} 1081 1082static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1083{ 1084 if (AR_SREV_9300_20_OR_LATER(ah)) { 1085 REG_WRITE(ah, AR_WA, ah->WARegVal); 1086 udelay(10); 1087 } 1088 1089 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1090 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1091 1092 switch (type) { 1093 case ATH9K_RESET_POWER_ON: 1094 return ath9k_hw_set_reset_power_on(ah); 1095 case ATH9K_RESET_WARM: 1096 case ATH9K_RESET_COLD: 1097 return ath9k_hw_set_reset(ah, type); 1098 default: 1099 return false; 1100 } 1101} 1102 1103static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1104 struct ath9k_channel *chan) 1105{ 1106 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1107 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1108 return false; 1109 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1110 return false; 1111 1112 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1113 return false; 1114 1115 ah->chip_fullsleep = false; 1116 ath9k_hw_init_pll(ah, chan); 1117 ath9k_hw_set_rfmode(ah, chan); 1118 1119 return true; 1120} 1121 1122static bool ath9k_hw_channel_change(struct ath_hw *ah, 1123 struct ath9k_channel *chan) 1124{ 1125 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1126 struct ath_common *common = ath9k_hw_common(ah); 1127 struct ieee80211_channel *channel = chan->chan; 1128 u32 qnum; 1129 int r; 1130 1131 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1132 if (ath9k_hw_numtxpending(ah, qnum)) { 1133 ath_dbg(common, ATH_DBG_QUEUE, 1134 "Transmit frames pending on queue %d\n", qnum); 1135 return false; 1136 } 1137 } 1138 1139 if (!ath9k_hw_rfbus_req(ah)) { 1140 ath_err(common, "Could not kill baseband RX\n"); 1141 return false; 1142 } 1143 1144 ath9k_hw_set_channel_regs(ah, chan); 1145 1146 r = ath9k_hw_rf_set_freq(ah, chan); 1147 if (r) { 1148 ath_err(common, "Failed to set channel\n"); 1149 return false; 1150 } 1151 ath9k_hw_set_clockrate(ah); 1152 1153 ah->eep_ops->set_txpower(ah, chan, 1154 ath9k_regd_get_ctl(regulatory, chan), 1155 channel->max_antenna_gain * 2, 1156 channel->max_power * 2, 1157 min((u32) MAX_RATE_POWER, 1158 (u32) regulatory->power_limit), false); 1159 1160 ath9k_hw_rfbus_done(ah); 1161 1162 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1163 ath9k_hw_set_delta_slope(ah, chan); 1164 1165 ath9k_hw_spur_mitigate_freq(ah, chan); 1166 1167 return true; 1168} 1169 1170bool ath9k_hw_check_alive(struct ath_hw *ah) 1171{ 1172 int count = 50; 1173 u32 reg; 1174 1175 if (AR_SREV_9285_12_OR_LATER(ah)) 1176 return true; 1177 1178 do { 1179 reg = REG_READ(ah, AR_OBS_BUS_1); 1180 1181 if ((reg & 0x7E7FFFEF) == 0x00702400) 1182 continue; 1183 1184 switch (reg & 0x7E000B00) { 1185 case 0x1E000000: 1186 case 0x52000B00: 1187 case 0x18000B00: 1188 continue; 1189 default: 1190 return true; 1191 } 1192 } while (count-- > 0); 1193 1194 return false; 1195} 1196EXPORT_SYMBOL(ath9k_hw_check_alive); 1197 1198int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1199 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1200{ 1201 struct ath_common *common = ath9k_hw_common(ah); 1202 u32 saveLedState; 1203 struct ath9k_channel *curchan = ah->curchan; 1204 u32 saveDefAntenna; 1205 u32 macStaId1; 1206 u64 tsf = 0; 1207 int i, r; 1208 1209 ah->txchainmask = common->tx_chainmask; 1210 ah->rxchainmask = common->rx_chainmask; 1211 1212 if (!ah->chip_fullsleep) { 1213 ath9k_hw_abortpcurecv(ah); 1214 if (!ath9k_hw_stopdmarecv(ah)) { 1215 ath_dbg(common, ATH_DBG_XMIT, 1216 "Failed to stop receive dma\n"); 1217 bChannelChange = false; 1218 } 1219 } 1220 1221 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1222 return -EIO; 1223 1224 if (curchan && !ah->chip_fullsleep) 1225 ath9k_hw_getnf(ah, curchan); 1226 1227 ah->caldata = caldata; 1228 if (caldata && 1229 (chan->channel != caldata->channel || 1230 (chan->channelFlags & ~CHANNEL_CW_INT) != 1231 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1232 /* Operating channel changed, reset channel calibration data */ 1233 memset(caldata, 0, sizeof(*caldata)); 1234 ath9k_init_nfcal_hist_buffer(ah, chan); 1235 } 1236 1237 if (bChannelChange && 1238 (ah->chip_fullsleep != true) && 1239 (ah->curchan != NULL) && 1240 (chan->channel != ah->curchan->channel) && 1241 ((chan->channelFlags & CHANNEL_ALL) == 1242 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1243 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { 1244 1245 if (ath9k_hw_channel_change(ah, chan)) { 1246 ath9k_hw_loadnf(ah, ah->curchan); 1247 ath9k_hw_start_nfcal(ah, true); 1248 if (AR_SREV_9271(ah)) 1249 ar9002_hw_load_ani_reg(ah, chan); 1250 return 0; 1251 } 1252 } 1253 1254 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1255 if (saveDefAntenna == 0) 1256 saveDefAntenna = 1; 1257 1258 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1259 1260 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1261 if (AR_SREV_9100(ah) || 1262 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1263 tsf = ath9k_hw_gettsf64(ah); 1264 1265 saveLedState = REG_READ(ah, AR_CFG_LED) & 1266 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1267 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1268 1269 ath9k_hw_mark_phy_inactive(ah); 1270 1271 /* Only required on the first reset */ 1272 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1273 REG_WRITE(ah, 1274 AR9271_RESET_POWER_DOWN_CONTROL, 1275 AR9271_RADIO_RF_RST); 1276 udelay(50); 1277 } 1278 1279 if (!ath9k_hw_chip_reset(ah, chan)) { 1280 ath_err(common, "Chip reset failed\n"); 1281 return -EINVAL; 1282 } 1283 1284 /* Only required on the first reset */ 1285 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1286 ah->htc_reset_init = false; 1287 REG_WRITE(ah, 1288 AR9271_RESET_POWER_DOWN_CONTROL, 1289 AR9271_GATE_MAC_CTL); 1290 udelay(50); 1291 } 1292 1293 /* Restore TSF */ 1294 if (tsf) 1295 ath9k_hw_settsf64(ah, tsf); 1296 1297 if (AR_SREV_9280_20_OR_LATER(ah)) 1298 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1299 1300 if (!AR_SREV_9300_20_OR_LATER(ah)) 1301 ar9002_hw_enable_async_fifo(ah); 1302 1303 r = ath9k_hw_process_ini(ah, chan); 1304 if (r) 1305 return r; 1306 1307 /* 1308 * Some AR91xx SoC devices frequently fail to accept TSF writes 1309 * right after the chip reset. When that happens, write a new 1310 * value after the initvals have been applied, with an offset 1311 * based on measured time difference 1312 */ 1313 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1314 tsf += 1500; 1315 ath9k_hw_settsf64(ah, tsf); 1316 } 1317 1318 /* Setup MFP options for CCMP */ 1319 if (AR_SREV_9280_20_OR_LATER(ah)) { 1320 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1321 * frames when constructing CCMP AAD. */ 1322 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1323 0xc7ff); 1324 ah->sw_mgmt_crypto = false; 1325 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1326 /* Disable hardware crypto for management frames */ 1327 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1328 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1329 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1330 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1331 ah->sw_mgmt_crypto = true; 1332 } else 1333 ah->sw_mgmt_crypto = true; 1334 1335 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1336 ath9k_hw_set_delta_slope(ah, chan); 1337 1338 ath9k_hw_spur_mitigate_freq(ah, chan); 1339 ah->eep_ops->set_board_values(ah, chan); 1340 1341 ath9k_hw_set_operating_mode(ah, ah->opmode); 1342 1343 ENABLE_REGWRITE_BUFFER(ah); 1344 1345 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1346 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1347 | macStaId1 1348 | AR_STA_ID1_RTS_USE_DEF 1349 | (ah->config. 1350 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1351 | ah->sta_id1_defaults); 1352 ath_hw_setbssidmask(common); 1353 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1354 ath9k_hw_write_associd(ah); 1355 REG_WRITE(ah, AR_ISR, ~0); 1356 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1357 1358 REGWRITE_BUFFER_FLUSH(ah); 1359 1360 r = ath9k_hw_rf_set_freq(ah, chan); 1361 if (r) 1362 return r; 1363 1364 ath9k_hw_set_clockrate(ah); 1365 1366 ENABLE_REGWRITE_BUFFER(ah); 1367 1368 for (i = 0; i < AR_NUM_DCU; i++) 1369 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1370 1371 REGWRITE_BUFFER_FLUSH(ah); 1372 1373 ah->intr_txqs = 0; 1374 for (i = 0; i < ah->caps.total_queues; i++) 1375 ath9k_hw_resettxqueue(ah, i); 1376 1377 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1378 ath9k_hw_ani_cache_ini_regs(ah); 1379 ath9k_hw_init_qos(ah); 1380 1381 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1382 ath9k_enable_rfkill(ah); 1383 1384 ath9k_hw_init_global_settings(ah); 1385 1386 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1387 ar9002_hw_update_async_fifo(ah); 1388 ar9002_hw_enable_wep_aggregation(ah); 1389 } 1390 1391 REG_WRITE(ah, AR_STA_ID1, 1392 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 1393 1394 ath9k_hw_set_dma(ah); 1395 1396 REG_WRITE(ah, AR_OBS, 8); 1397 1398 if (ah->config.rx_intr_mitigation) { 1399 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1400 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1401 } 1402 1403 if (ah->config.tx_intr_mitigation) { 1404 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1405 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1406 } 1407 1408 ath9k_hw_init_bb(ah, chan); 1409 1410 if (!ath9k_hw_init_cal(ah, chan)) 1411 return -EIO; 1412 1413 ENABLE_REGWRITE_BUFFER(ah); 1414 1415 ath9k_hw_restore_chainmask(ah); 1416 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1417 1418 REGWRITE_BUFFER_FLUSH(ah); 1419 1420 /* 1421 * For big endian systems turn on swapping for descriptors 1422 */ 1423 if (AR_SREV_9100(ah)) { 1424 u32 mask; 1425 mask = REG_READ(ah, AR_CFG); 1426 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1427 ath_dbg(common, ATH_DBG_RESET, 1428 "CFG Byte Swap Set 0x%x\n", mask); 1429 } else { 1430 mask = 1431 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1432 REG_WRITE(ah, AR_CFG, mask); 1433 ath_dbg(common, ATH_DBG_RESET, 1434 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1435 } 1436 } else { 1437 if (common->bus_ops->ath_bus_type == ATH_USB) { 1438 /* Configure AR9271 target WLAN */ 1439 if (AR_SREV_9271(ah)) 1440 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1441 else 1442 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1443 } 1444#ifdef __BIG_ENDIAN 1445 else 1446 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1447#endif 1448 } 1449 1450 if (ah->btcoex_hw.enabled) 1451 ath9k_hw_btcoex_enable(ah); 1452 1453 if (AR_SREV_9300_20_OR_LATER(ah)) 1454 ar9003_hw_bb_watchdog_config(ah); 1455 1456 return 0; 1457} 1458EXPORT_SYMBOL(ath9k_hw_reset); 1459 1460/******************************/ 1461/* Power Management (Chipset) */ 1462/******************************/ 1463 1464/* 1465 * Notify Power Mgt is disabled in self-generated frames. 1466 * If requested, force chip to sleep. 1467 */ 1468static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1469{ 1470 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1471 if (setChip) { 1472 /* 1473 * Clear the RTC force wake bit to allow the 1474 * mac to go to sleep. 1475 */ 1476 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1477 AR_RTC_FORCE_WAKE_EN); 1478 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1479 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1480 1481 /* Shutdown chip. Active low */ 1482 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1483 REG_CLR_BIT(ah, (AR_RTC_RESET), 1484 AR_RTC_RESET_EN); 1485 } 1486 1487 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1488 if (AR_SREV_9300_20_OR_LATER(ah)) 1489 REG_WRITE(ah, AR_WA, 1490 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1491} 1492 1493/* 1494 * Notify Power Management is enabled in self-generating 1495 * frames. If request, set power mode of chip to 1496 * auto/normal. Duration in units of 128us (1/8 TU). 1497 */ 1498static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1499{ 1500 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1501 if (setChip) { 1502 struct ath9k_hw_capabilities *pCap = &ah->caps; 1503 1504 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1505 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1506 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1507 AR_RTC_FORCE_WAKE_ON_INT); 1508 } else { 1509 /* 1510 * Clear the RTC force wake bit to allow the 1511 * mac to go to sleep. 1512 */ 1513 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1514 AR_RTC_FORCE_WAKE_EN); 1515 } 1516 } 1517 1518 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1519 if (AR_SREV_9300_20_OR_LATER(ah)) 1520 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1521} 1522 1523static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1524{ 1525 u32 val; 1526 int i; 1527 1528 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1529 if (AR_SREV_9300_20_OR_LATER(ah)) { 1530 REG_WRITE(ah, AR_WA, ah->WARegVal); 1531 udelay(10); 1532 } 1533 1534 if (setChip) { 1535 if ((REG_READ(ah, AR_RTC_STATUS) & 1536 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1537 if (ath9k_hw_set_reset_reg(ah, 1538 ATH9K_RESET_POWER_ON) != true) { 1539 return false; 1540 } 1541 if (!AR_SREV_9300_20_OR_LATER(ah)) 1542 ath9k_hw_init_pll(ah, NULL); 1543 } 1544 if (AR_SREV_9100(ah)) 1545 REG_SET_BIT(ah, AR_RTC_RESET, 1546 AR_RTC_RESET_EN); 1547 1548 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1549 AR_RTC_FORCE_WAKE_EN); 1550 udelay(50); 1551 1552 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1553 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1554 if (val == AR_RTC_STATUS_ON) 1555 break; 1556 udelay(50); 1557 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1558 AR_RTC_FORCE_WAKE_EN); 1559 } 1560 if (i == 0) { 1561 ath_err(ath9k_hw_common(ah), 1562 "Failed to wakeup in %uus\n", 1563 POWER_UP_TIME / 20); 1564 return false; 1565 } 1566 } 1567 1568 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1569 1570 return true; 1571} 1572 1573bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1574{ 1575 struct ath_common *common = ath9k_hw_common(ah); 1576 int status = true, setChip = true; 1577 static const char *modes[] = { 1578 "AWAKE", 1579 "FULL-SLEEP", 1580 "NETWORK SLEEP", 1581 "UNDEFINED" 1582 }; 1583 1584 if (ah->power_mode == mode) 1585 return status; 1586 1587 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", 1588 modes[ah->power_mode], modes[mode]); 1589 1590 switch (mode) { 1591 case ATH9K_PM_AWAKE: 1592 status = ath9k_hw_set_power_awake(ah, setChip); 1593 break; 1594 case ATH9K_PM_FULL_SLEEP: 1595 ath9k_set_power_sleep(ah, setChip); 1596 ah->chip_fullsleep = true; 1597 break; 1598 case ATH9K_PM_NETWORK_SLEEP: 1599 ath9k_set_power_network_sleep(ah, setChip); 1600 break; 1601 default: 1602 ath_err(common, "Unknown power mode %u\n", mode); 1603 return false; 1604 } 1605 ah->power_mode = mode; 1606 1607 /* 1608 * XXX: If this warning never comes up after a while then 1609 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 1610 * ath9k_hw_setpower() return type void. 1611 */ 1612 ATH_DBG_WARN_ON_ONCE(!status); 1613 1614 return status; 1615} 1616EXPORT_SYMBOL(ath9k_hw_setpower); 1617 1618/*******************/ 1619/* Beacon Handling */ 1620/*******************/ 1621 1622void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1623{ 1624 int flags = 0; 1625 1626 ah->beacon_interval = beacon_period; 1627 1628 ENABLE_REGWRITE_BUFFER(ah); 1629 1630 switch (ah->opmode) { 1631 case NL80211_IFTYPE_ADHOC: 1632 case NL80211_IFTYPE_MESH_POINT: 1633 REG_SET_BIT(ah, AR_TXCFG, 1634 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1635 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 1636 TU_TO_USEC(next_beacon + 1637 (ah->atim_window ? ah-> 1638 atim_window : 1))); 1639 flags |= AR_NDP_TIMER_EN; 1640 case NL80211_IFTYPE_AP: 1641 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1642 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 1643 TU_TO_USEC(next_beacon - 1644 ah->config. 1645 dma_beacon_response_time)); 1646 REG_WRITE(ah, AR_NEXT_SWBA, 1647 TU_TO_USEC(next_beacon - 1648 ah->config. 1649 sw_beacon_response_time)); 1650 flags |= 1651 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1652 break; 1653 default: 1654 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, 1655 "%s: unsupported opmode: %d\n", 1656 __func__, ah->opmode); 1657 return; 1658 break; 1659 } 1660 1661 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1662 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1663 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1664 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1665 1666 REGWRITE_BUFFER_FLUSH(ah); 1667 1668 beacon_period &= ~ATH9K_BEACON_ENA; 1669 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1670 ath9k_hw_reset_tsf(ah); 1671 } 1672 1673 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1674} 1675EXPORT_SYMBOL(ath9k_hw_beaconinit); 1676 1677void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1678 const struct ath9k_beacon_state *bs) 1679{ 1680 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 1681 struct ath9k_hw_capabilities *pCap = &ah->caps; 1682 struct ath_common *common = ath9k_hw_common(ah); 1683 1684 ENABLE_REGWRITE_BUFFER(ah); 1685 1686 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1687 1688 REG_WRITE(ah, AR_BEACON_PERIOD, 1689 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1690 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1691 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1692 1693 REGWRITE_BUFFER_FLUSH(ah); 1694 1695 REG_RMW_FIELD(ah, AR_RSSI_THR, 1696 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1697 1698 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 1699 1700 if (bs->bs_sleepduration > beaconintval) 1701 beaconintval = bs->bs_sleepduration; 1702 1703 dtimperiod = bs->bs_dtimperiod; 1704 if (bs->bs_sleepduration > dtimperiod) 1705 dtimperiod = bs->bs_sleepduration; 1706 1707 if (beaconintval == dtimperiod) 1708 nextTbtt = bs->bs_nextdtim; 1709 else 1710 nextTbtt = bs->bs_nexttbtt; 1711 1712 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 1713 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 1714 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1715 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1716 1717 ENABLE_REGWRITE_BUFFER(ah); 1718 1719 REG_WRITE(ah, AR_NEXT_DTIM, 1720 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 1721 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 1722 1723 REG_WRITE(ah, AR_SLEEP1, 1724 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 1725 | AR_SLEEP1_ASSUME_DTIM); 1726 1727 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 1728 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 1729 else 1730 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 1731 1732 REG_WRITE(ah, AR_SLEEP2, 1733 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 1734 1735 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 1736 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1737 1738 REGWRITE_BUFFER_FLUSH(ah); 1739 1740 REG_SET_BIT(ah, AR_TIMER_MODE, 1741 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1742 AR_DTIM_TIMER_EN); 1743 1744 /* TSF Out of Range Threshold */ 1745 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 1746} 1747EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 1748 1749/*******************/ 1750/* HW Capabilities */ 1751/*******************/ 1752 1753int ath9k_hw_fill_cap_info(struct ath_hw *ah) 1754{ 1755 struct ath9k_hw_capabilities *pCap = &ah->caps; 1756 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1757 struct ath_common *common = ath9k_hw_common(ah); 1758 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 1759 1760 u16 capField = 0, eeval; 1761 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 1762 1763 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 1764 regulatory->current_rd = eeval; 1765 1766 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 1767 if (AR_SREV_9285_12_OR_LATER(ah)) 1768 eeval |= AR9285_RDEXT_DEFAULT; 1769 regulatory->current_rd_ext = eeval; 1770 1771 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 1772 1773 if (ah->opmode != NL80211_IFTYPE_AP && 1774 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 1775 if (regulatory->current_rd == 0x64 || 1776 regulatory->current_rd == 0x65) 1777 regulatory->current_rd += 5; 1778 else if (regulatory->current_rd == 0x41) 1779 regulatory->current_rd = 0x43; 1780 ath_dbg(common, ATH_DBG_REGULATORY, 1781 "regdomain mapped to 0x%x\n", regulatory->current_rd); 1782 } 1783 1784 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 1785 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 1786 ath_err(common, 1787 "no band has been marked as supported in EEPROM\n"); 1788 return -EINVAL; 1789 } 1790 1791 if (eeval & AR5416_OPFLAGS_11A) 1792 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 1793 1794 if (eeval & AR5416_OPFLAGS_11G) 1795 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 1796 1797 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 1798 /* 1799 * For AR9271 we will temporarilly uses the rx chainmax as read from 1800 * the EEPROM. 1801 */ 1802 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 1803 !(eeval & AR5416_OPFLAGS_11A) && 1804 !(AR_SREV_9271(ah))) 1805 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 1806 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 1807 else 1808 /* Use rx_chainmask from EEPROM. */ 1809 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 1810 1811 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 1812 1813 /* enable key search for every frame in an aggregate */ 1814 if (AR_SREV_9300_20_OR_LATER(ah)) 1815 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 1816 1817 pCap->low_2ghz_chan = 2312; 1818 pCap->high_2ghz_chan = 2732; 1819 1820 pCap->low_5ghz_chan = 4920; 1821 pCap->high_5ghz_chan = 6100; 1822 1823 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 1824 1825 if (ah->config.ht_enable) 1826 pCap->hw_caps |= ATH9K_HW_CAP_HT; 1827 else 1828 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 1829 1830 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 1831 pCap->total_queues = 1832 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 1833 else 1834 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 1835 1836 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 1837 pCap->keycache_size = 1838 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 1839 else 1840 pCap->keycache_size = AR_KEYTABLE_SIZE; 1841 1842 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 1843 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; 1844 else 1845 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 1846 1847 if (AR_SREV_9271(ah)) 1848 pCap->num_gpio_pins = AR9271_NUM_GPIO; 1849 else if (AR_DEVID_7010(ah)) 1850 pCap->num_gpio_pins = AR7010_NUM_GPIO; 1851 else if (AR_SREV_9285_12_OR_LATER(ah)) 1852 pCap->num_gpio_pins = AR9285_NUM_GPIO; 1853 else if (AR_SREV_9280_20_OR_LATER(ah)) 1854 pCap->num_gpio_pins = AR928X_NUM_GPIO; 1855 else 1856 pCap->num_gpio_pins = AR_NUM_GPIO; 1857 1858 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 1859 pCap->hw_caps |= ATH9K_HW_CAP_CST; 1860 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 1861 } else { 1862 pCap->rts_aggr_limit = (8 * 1024); 1863 } 1864 1865 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 1866 1867#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1868 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 1869 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 1870 ah->rfkill_gpio = 1871 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 1872 ah->rfkill_polarity = 1873 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 1874 1875 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 1876 } 1877#endif 1878 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 1879 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 1880 else 1881 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 1882 1883 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 1884 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 1885 else 1886 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 1887 1888 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 1889 pCap->reg_cap = 1890 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 1891 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 1892 AR_EEPROM_EEREGCAP_EN_KK_U2 | 1893 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 1894 } else { 1895 pCap->reg_cap = 1896 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 1897 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 1898 } 1899 1900 /* Advertise midband for AR5416 with FCC midband set in eeprom */ 1901 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && 1902 AR_SREV_5416(ah)) 1903 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 1904 1905 pCap->num_antcfg_5ghz = 1906 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 1907 pCap->num_antcfg_2ghz = 1908 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 1909 1910 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) { 1911 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 1912 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 1913 1914 if (AR_SREV_9285(ah)) { 1915 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 1916 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; 1917 } else { 1918 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 1919 } 1920 } else { 1921 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 1922 } 1923 1924 if (AR_SREV_9300_20_OR_LATER(ah)) { 1925 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 1926 if (!AR_SREV_9485(ah)) 1927 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 1928 1929 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 1930 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 1931 pCap->rx_status_len = sizeof(struct ar9003_rxs); 1932 pCap->tx_desc_len = sizeof(struct ar9003_txc); 1933 pCap->txs_len = sizeof(struct ar9003_txs); 1934 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 1935 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 1936 } else { 1937 pCap->tx_desc_len = sizeof(struct ath_desc); 1938 if (AR_SREV_9280_20(ah) && 1939 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= 1940 AR5416_EEP_MINOR_VER_16) || 1941 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) 1942 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 1943 } 1944 1945 if (AR_SREV_9300_20_OR_LATER(ah)) 1946 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 1947 1948 if (AR_SREV_9300_20_OR_LATER(ah)) 1949 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 1950 1951 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 1952 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 1953 1954 if (AR_SREV_9285(ah)) 1955 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 1956 ant_div_ctl1 = 1957 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 1958 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 1959 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 1960 } 1961 if (AR_SREV_9300_20_OR_LATER(ah)) { 1962 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 1963 pCap->hw_caps |= ATH9K_HW_CAP_APM; 1964 } 1965 1966 1967 1968 if (AR_SREV_9485_10(ah)) { 1969 pCap->pcie_lcr_extsync_en = true; 1970 pCap->pcie_lcr_offset = 0x80; 1971 } 1972 1973 tx_chainmask = pCap->tx_chainmask; 1974 rx_chainmask = pCap->rx_chainmask; 1975 while (tx_chainmask || rx_chainmask) { 1976 if (tx_chainmask & BIT(0)) 1977 pCap->max_txchains++; 1978 if (rx_chainmask & BIT(0)) 1979 pCap->max_rxchains++; 1980 1981 tx_chainmask >>= 1; 1982 rx_chainmask >>= 1; 1983 } 1984 1985 return 0; 1986} 1987 1988/****************************/ 1989/* GPIO / RFKILL / Antennae */ 1990/****************************/ 1991 1992static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 1993 u32 gpio, u32 type) 1994{ 1995 int addr; 1996 u32 gpio_shift, tmp; 1997 1998 if (gpio > 11) 1999 addr = AR_GPIO_OUTPUT_MUX3; 2000 else if (gpio > 5) 2001 addr = AR_GPIO_OUTPUT_MUX2; 2002 else 2003 addr = AR_GPIO_OUTPUT_MUX1; 2004 2005 gpio_shift = (gpio % 6) * 5; 2006 2007 if (AR_SREV_9280_20_OR_LATER(ah) 2008 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2009 REG_RMW(ah, addr, (type << gpio_shift), 2010 (0x1f << gpio_shift)); 2011 } else { 2012 tmp = REG_READ(ah, addr); 2013 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2014 tmp &= ~(0x1f << gpio_shift); 2015 tmp |= (type << gpio_shift); 2016 REG_WRITE(ah, addr, tmp); 2017 } 2018} 2019 2020void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2021{ 2022 u32 gpio_shift; 2023 2024 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2025 2026 if (AR_DEVID_7010(ah)) { 2027 gpio_shift = gpio; 2028 REG_RMW(ah, AR7010_GPIO_OE, 2029 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2030 (AR7010_GPIO_OE_MASK << gpio_shift)); 2031 return; 2032 } 2033 2034 gpio_shift = gpio << 1; 2035 REG_RMW(ah, 2036 AR_GPIO_OE_OUT, 2037 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2038 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2039} 2040EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2041 2042u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2043{ 2044#define MS_REG_READ(x, y) \ 2045 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2046 2047 if (gpio >= ah->caps.num_gpio_pins) 2048 return 0xffffffff; 2049 2050 if (AR_DEVID_7010(ah)) { 2051 u32 val; 2052 val = REG_READ(ah, AR7010_GPIO_IN); 2053 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2054 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2055 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2056 AR_GPIO_BIT(gpio)) != 0; 2057 else if (AR_SREV_9271(ah)) 2058 return MS_REG_READ(AR9271, gpio) != 0; 2059 else if (AR_SREV_9287_11_OR_LATER(ah)) 2060 return MS_REG_READ(AR9287, gpio) != 0; 2061 else if (AR_SREV_9285_12_OR_LATER(ah)) 2062 return MS_REG_READ(AR9285, gpio) != 0; 2063 else if (AR_SREV_9280_20_OR_LATER(ah)) 2064 return MS_REG_READ(AR928X, gpio) != 0; 2065 else 2066 return MS_REG_READ(AR, gpio) != 0; 2067} 2068EXPORT_SYMBOL(ath9k_hw_gpio_get); 2069 2070void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2071 u32 ah_signal_type) 2072{ 2073 u32 gpio_shift; 2074 2075 if (AR_DEVID_7010(ah)) { 2076 gpio_shift = gpio; 2077 REG_RMW(ah, AR7010_GPIO_OE, 2078 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2079 (AR7010_GPIO_OE_MASK << gpio_shift)); 2080 return; 2081 } 2082 2083 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2084 gpio_shift = 2 * gpio; 2085 REG_RMW(ah, 2086 AR_GPIO_OE_OUT, 2087 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2088 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2089} 2090EXPORT_SYMBOL(ath9k_hw_cfg_output); 2091 2092void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2093{ 2094 if (AR_DEVID_7010(ah)) { 2095 val = val ? 0 : 1; 2096 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2097 AR_GPIO_BIT(gpio)); 2098 return; 2099 } 2100 2101 if (AR_SREV_9271(ah)) 2102 val = ~val; 2103 2104 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2105 AR_GPIO_BIT(gpio)); 2106} 2107EXPORT_SYMBOL(ath9k_hw_set_gpio); 2108 2109u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2110{ 2111 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2112} 2113EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2114 2115void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2116{ 2117 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2118} 2119EXPORT_SYMBOL(ath9k_hw_setantenna); 2120 2121/*********************/ 2122/* General Operation */ 2123/*********************/ 2124 2125u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2126{ 2127 u32 bits = REG_READ(ah, AR_RX_FILTER); 2128 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2129 2130 if (phybits & AR_PHY_ERR_RADAR) 2131 bits |= ATH9K_RX_FILTER_PHYRADAR; 2132 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2133 bits |= ATH9K_RX_FILTER_PHYERR; 2134 2135 return bits; 2136} 2137EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2138 2139void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2140{ 2141 u32 phybits; 2142 2143 ENABLE_REGWRITE_BUFFER(ah); 2144 2145 REG_WRITE(ah, AR_RX_FILTER, bits); 2146 2147 phybits = 0; 2148 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2149 phybits |= AR_PHY_ERR_RADAR; 2150 if (bits & ATH9K_RX_FILTER_PHYERR) 2151 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2152 REG_WRITE(ah, AR_PHY_ERR, phybits); 2153 2154 if (phybits) 2155 REG_WRITE(ah, AR_RXCFG, 2156 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 2157 else 2158 REG_WRITE(ah, AR_RXCFG, 2159 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2160 2161 REGWRITE_BUFFER_FLUSH(ah); 2162} 2163EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2164 2165bool ath9k_hw_phy_disable(struct ath_hw *ah) 2166{ 2167 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2168 return false; 2169 2170 ath9k_hw_init_pll(ah, NULL); 2171 return true; 2172} 2173EXPORT_SYMBOL(ath9k_hw_phy_disable); 2174 2175bool ath9k_hw_disable(struct ath_hw *ah) 2176{ 2177 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2178 return false; 2179 2180 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2181 return false; 2182 2183 ath9k_hw_init_pll(ah, NULL); 2184 return true; 2185} 2186EXPORT_SYMBOL(ath9k_hw_disable); 2187 2188void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2189{ 2190 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2191 struct ath9k_channel *chan = ah->curchan; 2192 struct ieee80211_channel *channel = chan->chan; 2193 2194 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 2195 2196 ah->eep_ops->set_txpower(ah, chan, 2197 ath9k_regd_get_ctl(regulatory, chan), 2198 channel->max_antenna_gain * 2, 2199 channel->max_power * 2, 2200 min((u32) MAX_RATE_POWER, 2201 (u32) regulatory->power_limit), test); 2202} 2203EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2204 2205void ath9k_hw_setopmode(struct ath_hw *ah) 2206{ 2207 ath9k_hw_set_operating_mode(ah, ah->opmode); 2208} 2209EXPORT_SYMBOL(ath9k_hw_setopmode); 2210 2211void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2212{ 2213 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2214 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2215} 2216EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2217 2218void ath9k_hw_write_associd(struct ath_hw *ah) 2219{ 2220 struct ath_common *common = ath9k_hw_common(ah); 2221 2222 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2223 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2224 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2225} 2226EXPORT_SYMBOL(ath9k_hw_write_associd); 2227 2228#define ATH9K_MAX_TSF_READ 10 2229 2230u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2231{ 2232 u32 tsf_lower, tsf_upper1, tsf_upper2; 2233 int i; 2234 2235 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2236 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2237 tsf_lower = REG_READ(ah, AR_TSF_L32); 2238 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2239 if (tsf_upper2 == tsf_upper1) 2240 break; 2241 tsf_upper1 = tsf_upper2; 2242 } 2243 2244 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2245 2246 return (((u64)tsf_upper1 << 32) | tsf_lower); 2247} 2248EXPORT_SYMBOL(ath9k_hw_gettsf64); 2249 2250void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2251{ 2252 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2253 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2254} 2255EXPORT_SYMBOL(ath9k_hw_settsf64); 2256 2257void ath9k_hw_reset_tsf(struct ath_hw *ah) 2258{ 2259 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2260 AH_TSF_WRITE_TIMEOUT)) 2261 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 2262 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2263 2264 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2265} 2266EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2267 2268void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2269{ 2270 if (setting) 2271 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2272 else 2273 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2274} 2275EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2276 2277void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2278{ 2279 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2280 u32 macmode; 2281 2282 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2283 macmode = AR_2040_JOINED_RX_CLEAR; 2284 else 2285 macmode = 0; 2286 2287 REG_WRITE(ah, AR_2040_MODE, macmode); 2288} 2289 2290/* HW Generic timers configuration */ 2291 2292static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2293{ 2294 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2295 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2296 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2297 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2298 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2299 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2300 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2301 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2302 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2303 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2304 AR_NDP2_TIMER_MODE, 0x0002}, 2305 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2306 AR_NDP2_TIMER_MODE, 0x0004}, 2307 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2308 AR_NDP2_TIMER_MODE, 0x0008}, 2309 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2310 AR_NDP2_TIMER_MODE, 0x0010}, 2311 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2312 AR_NDP2_TIMER_MODE, 0x0020}, 2313 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2314 AR_NDP2_TIMER_MODE, 0x0040}, 2315 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2316 AR_NDP2_TIMER_MODE, 0x0080} 2317}; 2318 2319/* HW generic timer primitives */ 2320 2321/* compute and clear index of rightmost 1 */ 2322static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2323{ 2324 u32 b; 2325 2326 b = *mask; 2327 b &= (0-b); 2328 *mask &= ~b; 2329 b *= debruijn32; 2330 b >>= 27; 2331 2332 return timer_table->gen_timer_index[b]; 2333} 2334 2335static u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2336{ 2337 return REG_READ(ah, AR_TSF_L32); 2338} 2339 2340struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2341 void (*trigger)(void *), 2342 void (*overflow)(void *), 2343 void *arg, 2344 u8 timer_index) 2345{ 2346 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2347 struct ath_gen_timer *timer; 2348 2349 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2350 2351 if (timer == NULL) { 2352 ath_err(ath9k_hw_common(ah), 2353 "Failed to allocate memory for hw timer[%d]\n", 2354 timer_index); 2355 return NULL; 2356 } 2357 2358 /* allocate a hardware generic timer slot */ 2359 timer_table->timers[timer_index] = timer; 2360 timer->index = timer_index; 2361 timer->trigger = trigger; 2362 timer->overflow = overflow; 2363 timer->arg = arg; 2364 2365 return timer; 2366} 2367EXPORT_SYMBOL(ath_gen_timer_alloc); 2368 2369void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2370 struct ath_gen_timer *timer, 2371 u32 timer_next, 2372 u32 timer_period) 2373{ 2374 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2375 u32 tsf; 2376 2377 BUG_ON(!timer_period); 2378 2379 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2380 2381 tsf = ath9k_hw_gettsf32(ah); 2382 2383 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2384 "current tsf %x period %x timer_next %x\n", 2385 tsf, timer_period, timer_next); 2386 2387 /* 2388 * Pull timer_next forward if the current TSF already passed it 2389 * because of software latency 2390 */ 2391 if (timer_next < tsf) 2392 timer_next = tsf + timer_period; 2393 2394 /* 2395 * Program generic timer registers 2396 */ 2397 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2398 timer_next); 2399 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2400 timer_period); 2401 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2402 gen_tmr_configuration[timer->index].mode_mask); 2403 2404 /* Enable both trigger and thresh interrupt masks */ 2405 REG_SET_BIT(ah, AR_IMR_S5, 2406 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2407 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2408} 2409EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2410 2411void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2412{ 2413 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2414 2415 if ((timer->index < AR_FIRST_NDP_TIMER) || 2416 (timer->index >= ATH_MAX_GEN_TIMER)) { 2417 return; 2418 } 2419 2420 /* Clear generic timer enable bits. */ 2421 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2422 gen_tmr_configuration[timer->index].mode_mask); 2423 2424 /* Disable both trigger and thresh interrupt masks */ 2425 REG_CLR_BIT(ah, AR_IMR_S5, 2426 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2427 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2428 2429 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2430} 2431EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2432 2433void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2434{ 2435 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2436 2437 /* free the hardware generic timer slot */ 2438 timer_table->timers[timer->index] = NULL; 2439 kfree(timer); 2440} 2441EXPORT_SYMBOL(ath_gen_timer_free); 2442 2443/* 2444 * Generic Timer Interrupts handling 2445 */ 2446void ath_gen_timer_isr(struct ath_hw *ah) 2447{ 2448 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2449 struct ath_gen_timer *timer; 2450 struct ath_common *common = ath9k_hw_common(ah); 2451 u32 trigger_mask, thresh_mask, index; 2452 2453 /* get hardware generic timer interrupt status */ 2454 trigger_mask = ah->intr_gen_timer_trigger; 2455 thresh_mask = ah->intr_gen_timer_thresh; 2456 trigger_mask &= timer_table->timer_mask.val; 2457 thresh_mask &= timer_table->timer_mask.val; 2458 2459 trigger_mask &= ~thresh_mask; 2460 2461 while (thresh_mask) { 2462 index = rightmost_index(timer_table, &thresh_mask); 2463 timer = timer_table->timers[index]; 2464 BUG_ON(!timer); 2465 ath_dbg(common, ATH_DBG_HWTIMER, 2466 "TSF overflow for Gen timer %d\n", index); 2467 timer->overflow(timer->arg); 2468 } 2469 2470 while (trigger_mask) { 2471 index = rightmost_index(timer_table, &trigger_mask); 2472 timer = timer_table->timers[index]; 2473 BUG_ON(!timer); 2474 ath_dbg(common, ATH_DBG_HWTIMER, 2475 "Gen timer[%d] trigger\n", index); 2476 timer->trigger(timer->arg); 2477 } 2478} 2479EXPORT_SYMBOL(ath_gen_timer_isr); 2480 2481/********/ 2482/* HTC */ 2483/********/ 2484 2485void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2486{ 2487 ah->htc_reset_init = true; 2488} 2489EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2490 2491static struct { 2492 u32 version; 2493 const char * name; 2494} ath_mac_bb_names[] = { 2495 /* Devices with external radios */ 2496 { AR_SREV_VERSION_5416_PCI, "5416" }, 2497 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2498 { AR_SREV_VERSION_9100, "9100" }, 2499 { AR_SREV_VERSION_9160, "9160" }, 2500 /* Single-chip solutions */ 2501 { AR_SREV_VERSION_9280, "9280" }, 2502 { AR_SREV_VERSION_9285, "9285" }, 2503 { AR_SREV_VERSION_9287, "9287" }, 2504 { AR_SREV_VERSION_9271, "9271" }, 2505 { AR_SREV_VERSION_9300, "9300" }, 2506}; 2507 2508/* For devices with external radios */ 2509static struct { 2510 u16 version; 2511 const char * name; 2512} ath_rf_names[] = { 2513 { 0, "5133" }, 2514 { AR_RAD5133_SREV_MAJOR, "5133" }, 2515 { AR_RAD5122_SREV_MAJOR, "5122" }, 2516 { AR_RAD2133_SREV_MAJOR, "2133" }, 2517 { AR_RAD2122_SREV_MAJOR, "2122" } 2518}; 2519 2520/* 2521 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2522 */ 2523static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2524{ 2525 int i; 2526 2527 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2528 if (ath_mac_bb_names[i].version == mac_bb_version) { 2529 return ath_mac_bb_names[i].name; 2530 } 2531 } 2532 2533 return "????"; 2534} 2535 2536/* 2537 * Return the RF name. "????" is returned if the RF is unknown. 2538 * Used for devices with external radios. 2539 */ 2540static const char *ath9k_hw_rf_name(u16 rf_version) 2541{ 2542 int i; 2543 2544 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2545 if (ath_rf_names[i].version == rf_version) { 2546 return ath_rf_names[i].name; 2547 } 2548 } 2549 2550 return "????"; 2551} 2552 2553void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2554{ 2555 int used; 2556 2557 /* chipsets >= AR9280 are single-chip */ 2558 if (AR_SREV_9280_20_OR_LATER(ah)) { 2559 used = snprintf(hw_name, len, 2560 "Atheros AR%s Rev:%x", 2561 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2562 ah->hw_version.macRev); 2563 } 2564 else { 2565 used = snprintf(hw_name, len, 2566 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2567 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2568 ah->hw_version.macRev, 2569 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2570 AR_RADIO_SREV_MAJOR)), 2571 ah->hw_version.phyRev); 2572 } 2573 2574 hw_name[used] = '\0'; 2575} 2576EXPORT_SYMBOL(ath9k_hw_name); 2577