hw.c revision 153dccd467b818b1dd3a6801b14e94a7a48ef859
1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <linux/module.h> 20#include <asm/unaligned.h> 21 22#include "hw.h" 23#include "hw-ops.h" 24#include "rc.h" 25#include "ar9003_mac.h" 26#include "ar9003_mci.h" 27#include "debug.h" 28#include "ath9k.h" 29 30static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 31 32MODULE_AUTHOR("Atheros Communications"); 33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 34MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 35MODULE_LICENSE("Dual BSD/GPL"); 36 37static int __init ath9k_init(void) 38{ 39 return 0; 40} 41module_init(ath9k_init); 42 43static void __exit ath9k_exit(void) 44{ 45 return; 46} 47module_exit(ath9k_exit); 48 49/* Private hardware callbacks */ 50 51static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 52{ 53 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 54} 55 56static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 57{ 58 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 59} 60 61static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 62 struct ath9k_channel *chan) 63{ 64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 65} 66 67static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 68{ 69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 70 return; 71 72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 73} 74 75static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 76{ 77 /* You will not have this callback if using the old ANI */ 78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 79 return; 80 81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 82} 83 84/********************/ 85/* Helper Functions */ 86/********************/ 87 88#ifdef CONFIG_ATH9K_DEBUGFS 89 90void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause) 91{ 92 struct ath_softc *sc = common->priv; 93 if (sync_cause) 94 sc->debug.stats.istats.sync_cause_all++; 95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ) 96 sc->debug.stats.istats.sync_rtc_irq++; 97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ) 98 sc->debug.stats.istats.sync_mac_irq++; 99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS) 100 sc->debug.stats.istats.eeprom_illegal_access++; 101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT) 102 sc->debug.stats.istats.apb_timeout++; 103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT) 104 sc->debug.stats.istats.pci_mode_conflict++; 105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) 106 sc->debug.stats.istats.host1_fatal++; 107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) 108 sc->debug.stats.istats.host1_perr++; 109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR) 110 sc->debug.stats.istats.trcv_fifo_perr++; 111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP) 112 sc->debug.stats.istats.radm_cpl_ep++; 113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT) 114 sc->debug.stats.istats.radm_cpl_dllp_abort++; 115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT) 116 sc->debug.stats.istats.radm_cpl_tlp_abort++; 117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR) 118 sc->debug.stats.istats.radm_cpl_ecrc_err++; 119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) 120 sc->debug.stats.istats.radm_cpl_timeout++; 121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 122 sc->debug.stats.istats.local_timeout++; 123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS) 124 sc->debug.stats.istats.pm_access++; 125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE) 126 sc->debug.stats.istats.mac_awake++; 127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP) 128 sc->debug.stats.istats.mac_asleep++; 129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS) 130 sc->debug.stats.istats.mac_sleep_access++; 131} 132#endif 133 134 135static void ath9k_hw_set_clockrate(struct ath_hw *ah) 136{ 137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 138 struct ath_common *common = ath9k_hw_common(ah); 139 unsigned int clockrate; 140 141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 143 clockrate = 117; 144 else if (!ah->curchan) /* should really check for CCK instead */ 145 clockrate = ATH9K_CLOCK_RATE_CCK; 146 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 150 else 151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 152 153 if (conf_is_ht40(conf)) 154 clockrate *= 2; 155 156 if (ah->curchan) { 157 if (IS_CHAN_HALF_RATE(ah->curchan)) 158 clockrate /= 2; 159 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 160 clockrate /= 4; 161 } 162 163 common->clockrate = clockrate; 164} 165 166static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 167{ 168 struct ath_common *common = ath9k_hw_common(ah); 169 170 return usecs * common->clockrate; 171} 172 173bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 174{ 175 int i; 176 177 BUG_ON(timeout < AH_TIME_QUANTUM); 178 179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 180 if ((REG_READ(ah, reg) & mask) == val) 181 return true; 182 183 udelay(AH_TIME_QUANTUM); 184 } 185 186 ath_dbg(ath9k_hw_common(ah), ANY, 187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 188 timeout, reg, REG_READ(ah, reg), mask, val); 189 190 return false; 191} 192EXPORT_SYMBOL(ath9k_hw_wait); 193 194void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 195 int hw_delay) 196{ 197 if (IS_CHAN_B(chan)) 198 hw_delay = (4 * hw_delay) / 22; 199 else 200 hw_delay /= 10; 201 202 if (IS_CHAN_HALF_RATE(chan)) 203 hw_delay *= 2; 204 else if (IS_CHAN_QUARTER_RATE(chan)) 205 hw_delay *= 4; 206 207 udelay(hw_delay + BASE_ACTIVATE_DELAY); 208} 209 210void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 211 int column, unsigned int *writecnt) 212{ 213 int r; 214 215 ENABLE_REGWRITE_BUFFER(ah); 216 for (r = 0; r < array->ia_rows; r++) { 217 REG_WRITE(ah, INI_RA(array, r, 0), 218 INI_RA(array, r, column)); 219 DO_DELAY(*writecnt); 220 } 221 REGWRITE_BUFFER_FLUSH(ah); 222} 223 224u32 ath9k_hw_reverse_bits(u32 val, u32 n) 225{ 226 u32 retval; 227 int i; 228 229 for (i = 0, retval = 0; i < n; i++) { 230 retval = (retval << 1) | (val & 1); 231 val >>= 1; 232 } 233 return retval; 234} 235 236u16 ath9k_hw_computetxtime(struct ath_hw *ah, 237 u8 phy, int kbps, 238 u32 frameLen, u16 rateix, 239 bool shortPreamble) 240{ 241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 242 243 if (kbps == 0) 244 return 0; 245 246 switch (phy) { 247 case WLAN_RC_PHY_CCK: 248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 249 if (shortPreamble) 250 phyTime >>= 1; 251 numBits = frameLen << 3; 252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 253 break; 254 case WLAN_RC_PHY_OFDM: 255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 257 numBits = OFDM_PLCP_BITS + (frameLen << 3); 258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 259 txTime = OFDM_SIFS_TIME_QUARTER 260 + OFDM_PREAMBLE_TIME_QUARTER 261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 262 } else if (ah->curchan && 263 IS_CHAN_HALF_RATE(ah->curchan)) { 264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 265 numBits = OFDM_PLCP_BITS + (frameLen << 3); 266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 267 txTime = OFDM_SIFS_TIME_HALF + 268 OFDM_PREAMBLE_TIME_HALF 269 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 270 } else { 271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 272 numBits = OFDM_PLCP_BITS + (frameLen << 3); 273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 275 + (numSymbols * OFDM_SYMBOL_TIME); 276 } 277 break; 278 default: 279 ath_err(ath9k_hw_common(ah), 280 "Unknown phy %u (rate ix %u)\n", phy, rateix); 281 txTime = 0; 282 break; 283 } 284 285 return txTime; 286} 287EXPORT_SYMBOL(ath9k_hw_computetxtime); 288 289void ath9k_hw_get_channel_centers(struct ath_hw *ah, 290 struct ath9k_channel *chan, 291 struct chan_centers *centers) 292{ 293 int8_t extoff; 294 295 if (!IS_CHAN_HT40(chan)) { 296 centers->ctl_center = centers->ext_center = 297 centers->synth_center = chan->channel; 298 return; 299 } 300 301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 302 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 303 centers->synth_center = 304 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 305 extoff = 1; 306 } else { 307 centers->synth_center = 308 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 309 extoff = -1; 310 } 311 312 centers->ctl_center = 313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 314 /* 25 MHz spacing is supported by hw but not on upper layers */ 315 centers->ext_center = 316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 317} 318 319/******************/ 320/* Chip Revisions */ 321/******************/ 322 323static void ath9k_hw_read_revisions(struct ath_hw *ah) 324{ 325 u32 val; 326 327 switch (ah->hw_version.devid) { 328 case AR5416_AR9100_DEVID: 329 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 330 break; 331 case AR9300_DEVID_AR9330: 332 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 333 if (ah->get_mac_revision) { 334 ah->hw_version.macRev = ah->get_mac_revision(); 335 } else { 336 val = REG_READ(ah, AR_SREV); 337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 338 } 339 return; 340 case AR9300_DEVID_AR9340: 341 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 342 val = REG_READ(ah, AR_SREV); 343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 344 return; 345 } 346 347 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 348 349 if (val == 0xFF) { 350 val = REG_READ(ah, AR_SREV); 351 ah->hw_version.macVersion = 352 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 353 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 354 355 if (AR_SREV_9462(ah)) 356 ah->is_pciexpress = true; 357 else 358 ah->is_pciexpress = (val & 359 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 360 } else { 361 if (!AR_SREV_9100(ah)) 362 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 363 364 ah->hw_version.macRev = val & AR_SREV_REVISION; 365 366 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 367 ah->is_pciexpress = true; 368 } 369} 370 371/************************************/ 372/* HW Attach, Detach, Init Routines */ 373/************************************/ 374 375static void ath9k_hw_disablepcie(struct ath_hw *ah) 376{ 377 if (!AR_SREV_5416(ah)) 378 return; 379 380 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 381 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 382 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 383 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 384 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 385 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 386 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 387 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 388 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 389 390 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 391} 392 393/* This should work for all families including legacy */ 394static bool ath9k_hw_chip_test(struct ath_hw *ah) 395{ 396 struct ath_common *common = ath9k_hw_common(ah); 397 u32 regAddr[2] = { AR_STA_ID0 }; 398 u32 regHold[2]; 399 static const u32 patternData[4] = { 400 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 401 }; 402 int i, j, loop_max; 403 404 if (!AR_SREV_9300_20_OR_LATER(ah)) { 405 loop_max = 2; 406 regAddr[1] = AR_PHY_BASE + (8 << 2); 407 } else 408 loop_max = 1; 409 410 for (i = 0; i < loop_max; i++) { 411 u32 addr = regAddr[i]; 412 u32 wrData, rdData; 413 414 regHold[i] = REG_READ(ah, addr); 415 for (j = 0; j < 0x100; j++) { 416 wrData = (j << 16) | j; 417 REG_WRITE(ah, addr, wrData); 418 rdData = REG_READ(ah, addr); 419 if (rdData != wrData) { 420 ath_err(common, 421 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 422 addr, wrData, rdData); 423 return false; 424 } 425 } 426 for (j = 0; j < 4; j++) { 427 wrData = patternData[j]; 428 REG_WRITE(ah, addr, wrData); 429 rdData = REG_READ(ah, addr); 430 if (wrData != rdData) { 431 ath_err(common, 432 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 433 addr, wrData, rdData); 434 return false; 435 } 436 } 437 REG_WRITE(ah, regAddr[i], regHold[i]); 438 } 439 udelay(100); 440 441 return true; 442} 443 444static void ath9k_hw_init_config(struct ath_hw *ah) 445{ 446 int i; 447 448 ah->config.dma_beacon_response_time = 1; 449 ah->config.sw_beacon_response_time = 6; 450 ah->config.additional_swba_backoff = 0; 451 ah->config.ack_6mb = 0x0; 452 ah->config.cwm_ignore_extcca = 0; 453 ah->config.pcie_clock_req = 0; 454 ah->config.pcie_waen = 0; 455 ah->config.analog_shiftreg = 1; 456 ah->config.enable_ani = true; 457 458 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 459 ah->config.spurchans[i][0] = AR_NO_SPUR; 460 ah->config.spurchans[i][1] = AR_NO_SPUR; 461 } 462 463 /* PAPRD needs some more work to be enabled */ 464 ah->config.paprd_disable = 1; 465 466 ah->config.rx_intr_mitigation = true; 467 ah->config.pcieSerDesWrite = true; 468 469 /* 470 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 471 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 472 * This means we use it for all AR5416 devices, and the few 473 * minor PCI AR9280 devices out there. 474 * 475 * Serialization is required because these devices do not handle 476 * well the case of two concurrent reads/writes due to the latency 477 * involved. During one read/write another read/write can be issued 478 * on another CPU while the previous read/write may still be working 479 * on our hardware, if we hit this case the hardware poops in a loop. 480 * We prevent this by serializing reads and writes. 481 * 482 * This issue is not present on PCI-Express devices or pre-AR5416 483 * devices (legacy, 802.11abg). 484 */ 485 if (num_possible_cpus() > 1) 486 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 487} 488 489static void ath9k_hw_init_defaults(struct ath_hw *ah) 490{ 491 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 492 493 regulatory->country_code = CTRY_DEFAULT; 494 regulatory->power_limit = MAX_RATE_POWER; 495 496 ah->hw_version.magic = AR5416_MAGIC; 497 ah->hw_version.subvendorid = 0; 498 499 ah->atim_window = 0; 500 ah->sta_id1_defaults = 501 AR_STA_ID1_CRPT_MIC_ENABLE | 502 AR_STA_ID1_MCAST_KSRCH; 503 if (AR_SREV_9100(ah)) 504 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 505 ah->slottime = ATH9K_SLOT_TIME_9; 506 ah->globaltxtimeout = (u32) -1; 507 ah->power_mode = ATH9K_PM_UNDEFINED; 508 ah->htc_reset_init = true; 509} 510 511static int ath9k_hw_init_macaddr(struct ath_hw *ah) 512{ 513 struct ath_common *common = ath9k_hw_common(ah); 514 u32 sum; 515 int i; 516 u16 eeval; 517 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 518 519 sum = 0; 520 for (i = 0; i < 3; i++) { 521 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 522 sum += eeval; 523 common->macaddr[2 * i] = eeval >> 8; 524 common->macaddr[2 * i + 1] = eeval & 0xff; 525 } 526 if (sum == 0 || sum == 0xffff * 3) 527 return -EADDRNOTAVAIL; 528 529 return 0; 530} 531 532static int ath9k_hw_post_init(struct ath_hw *ah) 533{ 534 struct ath_common *common = ath9k_hw_common(ah); 535 int ecode; 536 537 if (common->bus_ops->ath_bus_type != ATH_USB) { 538 if (!ath9k_hw_chip_test(ah)) 539 return -ENODEV; 540 } 541 542 if (!AR_SREV_9300_20_OR_LATER(ah)) { 543 ecode = ar9002_hw_rf_claim(ah); 544 if (ecode != 0) 545 return ecode; 546 } 547 548 ecode = ath9k_hw_eeprom_init(ah); 549 if (ecode != 0) 550 return ecode; 551 552 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 553 ah->eep_ops->get_eeprom_ver(ah), 554 ah->eep_ops->get_eeprom_rev(ah)); 555 556 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 557 if (ecode) { 558 ath_err(ath9k_hw_common(ah), 559 "Failed allocating banks for external radio\n"); 560 ath9k_hw_rf_free_ext_banks(ah); 561 return ecode; 562 } 563 564 if (ah->config.enable_ani) { 565 ath9k_hw_ani_setup(ah); 566 ath9k_hw_ani_init(ah); 567 } 568 569 return 0; 570} 571 572static void ath9k_hw_attach_ops(struct ath_hw *ah) 573{ 574 if (AR_SREV_9300_20_OR_LATER(ah)) 575 ar9003_hw_attach_ops(ah); 576 else 577 ar9002_hw_attach_ops(ah); 578} 579 580/* Called for all hardware families */ 581static int __ath9k_hw_init(struct ath_hw *ah) 582{ 583 struct ath_common *common = ath9k_hw_common(ah); 584 int r = 0; 585 586 ath9k_hw_read_revisions(ah); 587 588 /* 589 * Read back AR_WA into a permanent copy and set bits 14 and 17. 590 * We need to do this to avoid RMW of this register. We cannot 591 * read the reg when chip is asleep. 592 */ 593 ah->WARegVal = REG_READ(ah, AR_WA); 594 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 595 AR_WA_ASPM_TIMER_BASED_DISABLE); 596 597 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 598 ath_err(common, "Couldn't reset chip\n"); 599 return -EIO; 600 } 601 602 if (AR_SREV_9462(ah)) 603 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 604 605 ath9k_hw_init_defaults(ah); 606 ath9k_hw_init_config(ah); 607 608 ath9k_hw_attach_ops(ah); 609 610 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 611 ath_err(common, "Couldn't wakeup chip\n"); 612 return -EIO; 613 } 614 615 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 616 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 617 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 618 !ah->is_pciexpress)) { 619 ah->config.serialize_regmode = 620 SER_REG_MODE_ON; 621 } else { 622 ah->config.serialize_regmode = 623 SER_REG_MODE_OFF; 624 } 625 } 626 627 ath_dbg(common, RESET, "serialize_regmode is %d\n", 628 ah->config.serialize_regmode); 629 630 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 631 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 632 else 633 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 634 635 switch (ah->hw_version.macVersion) { 636 case AR_SREV_VERSION_5416_PCI: 637 case AR_SREV_VERSION_5416_PCIE: 638 case AR_SREV_VERSION_9160: 639 case AR_SREV_VERSION_9100: 640 case AR_SREV_VERSION_9280: 641 case AR_SREV_VERSION_9285: 642 case AR_SREV_VERSION_9287: 643 case AR_SREV_VERSION_9271: 644 case AR_SREV_VERSION_9300: 645 case AR_SREV_VERSION_9330: 646 case AR_SREV_VERSION_9485: 647 case AR_SREV_VERSION_9340: 648 case AR_SREV_VERSION_9462: 649 break; 650 default: 651 ath_err(common, 652 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 653 ah->hw_version.macVersion, ah->hw_version.macRev); 654 return -EOPNOTSUPP; 655 } 656 657 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 658 AR_SREV_9330(ah)) 659 ah->is_pciexpress = false; 660 661 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 662 ath9k_hw_init_cal_settings(ah); 663 664 ah->ani_function = ATH9K_ANI_ALL; 665 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 666 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 667 if (!AR_SREV_9300_20_OR_LATER(ah)) 668 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 669 670 /* disable ANI for 9340 */ 671 if (AR_SREV_9340(ah)) 672 ah->config.enable_ani = false; 673 674 ath9k_hw_init_mode_regs(ah); 675 676 if (!ah->is_pciexpress) 677 ath9k_hw_disablepcie(ah); 678 679 r = ath9k_hw_post_init(ah); 680 if (r) 681 return r; 682 683 ath9k_hw_init_mode_gain_regs(ah); 684 r = ath9k_hw_fill_cap_info(ah); 685 if (r) 686 return r; 687 688 r = ath9k_hw_init_macaddr(ah); 689 if (r) { 690 ath_err(common, "Failed to initialize MAC address\n"); 691 return r; 692 } 693 694 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 695 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 696 else 697 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 698 699 if (AR_SREV_9330(ah)) 700 ah->bb_watchdog_timeout_ms = 85; 701 else 702 ah->bb_watchdog_timeout_ms = 25; 703 704 common->state = ATH_HW_INITIALIZED; 705 706 return 0; 707} 708 709int ath9k_hw_init(struct ath_hw *ah) 710{ 711 int ret; 712 struct ath_common *common = ath9k_hw_common(ah); 713 714 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 715 switch (ah->hw_version.devid) { 716 case AR5416_DEVID_PCI: 717 case AR5416_DEVID_PCIE: 718 case AR5416_AR9100_DEVID: 719 case AR9160_DEVID_PCI: 720 case AR9280_DEVID_PCI: 721 case AR9280_DEVID_PCIE: 722 case AR9285_DEVID_PCIE: 723 case AR9287_DEVID_PCI: 724 case AR9287_DEVID_PCIE: 725 case AR2427_DEVID_PCIE: 726 case AR9300_DEVID_PCIE: 727 case AR9300_DEVID_AR9485_PCIE: 728 case AR9300_DEVID_AR9330: 729 case AR9300_DEVID_AR9340: 730 case AR9300_DEVID_AR9580: 731 case AR9300_DEVID_AR9462: 732 break; 733 default: 734 if (common->bus_ops->ath_bus_type == ATH_USB) 735 break; 736 ath_err(common, "Hardware device ID 0x%04x not supported\n", 737 ah->hw_version.devid); 738 return -EOPNOTSUPP; 739 } 740 741 ret = __ath9k_hw_init(ah); 742 if (ret) { 743 ath_err(common, 744 "Unable to initialize hardware; initialization status: %d\n", 745 ret); 746 return ret; 747 } 748 749 return 0; 750} 751EXPORT_SYMBOL(ath9k_hw_init); 752 753static void ath9k_hw_init_qos(struct ath_hw *ah) 754{ 755 ENABLE_REGWRITE_BUFFER(ah); 756 757 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 758 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 759 760 REG_WRITE(ah, AR_QOS_NO_ACK, 761 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 762 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 763 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 764 765 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 766 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 767 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 768 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 769 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 770 771 REGWRITE_BUFFER_FLUSH(ah); 772} 773 774u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 775{ 776 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 777 udelay(100); 778 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 779 780 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 781 udelay(100); 782 783 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 784} 785EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 786 787static void ath9k_hw_init_pll(struct ath_hw *ah, 788 struct ath9k_channel *chan) 789{ 790 u32 pll; 791 792 if (AR_SREV_9485(ah)) { 793 794 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 796 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 797 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 798 AR_CH0_DPLL2_KD, 0x40); 799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 800 AR_CH0_DPLL2_KI, 0x4); 801 802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 803 AR_CH0_BB_DPLL1_REFDIV, 0x5); 804 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 805 AR_CH0_BB_DPLL1_NINI, 0x58); 806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 807 AR_CH0_BB_DPLL1_NFRAC, 0x0); 808 809 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 810 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 812 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 814 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 815 816 /* program BB PLL phase_shift to 0x6 */ 817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 818 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 819 820 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 821 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 822 udelay(1000); 823 } else if (AR_SREV_9330(ah)) { 824 u32 ddr_dpll2, pll_control2, kd; 825 826 if (ah->is_clk_25mhz) { 827 ddr_dpll2 = 0x18e82f01; 828 pll_control2 = 0xe04a3d; 829 kd = 0x1d; 830 } else { 831 ddr_dpll2 = 0x19e82f01; 832 pll_control2 = 0x886666; 833 kd = 0x3d; 834 } 835 836 /* program DDR PLL ki and kd value */ 837 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 838 839 /* program DDR PLL phase_shift */ 840 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 841 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 842 843 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 844 udelay(1000); 845 846 /* program refdiv, nint, frac to RTC register */ 847 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 848 849 /* program BB PLL kd and ki value */ 850 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 851 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 852 853 /* program BB PLL phase_shift */ 854 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 855 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 856 } else if (AR_SREV_9340(ah)) { 857 u32 regval, pll2_divint, pll2_divfrac, refdiv; 858 859 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 860 udelay(1000); 861 862 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 863 udelay(100); 864 865 if (ah->is_clk_25mhz) { 866 pll2_divint = 0x54; 867 pll2_divfrac = 0x1eb85; 868 refdiv = 3; 869 } else { 870 pll2_divint = 88; 871 pll2_divfrac = 0; 872 refdiv = 5; 873 } 874 875 regval = REG_READ(ah, AR_PHY_PLL_MODE); 876 regval |= (0x1 << 16); 877 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 878 udelay(100); 879 880 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 881 (pll2_divint << 18) | pll2_divfrac); 882 udelay(100); 883 884 regval = REG_READ(ah, AR_PHY_PLL_MODE); 885 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 886 (0x4 << 26) | (0x18 << 19); 887 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 888 REG_WRITE(ah, AR_PHY_PLL_MODE, 889 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 890 udelay(1000); 891 } 892 893 pll = ath9k_hw_compute_pll_control(ah, chan); 894 895 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 896 897 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 898 udelay(1000); 899 900 /* Switch the core clock for ar9271 to 117Mhz */ 901 if (AR_SREV_9271(ah)) { 902 udelay(500); 903 REG_WRITE(ah, 0x50040, 0x304); 904 } 905 906 udelay(RTC_PLL_SETTLE_DELAY); 907 908 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 909 910 if (AR_SREV_9340(ah)) { 911 if (ah->is_clk_25mhz) { 912 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 913 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 914 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 915 } else { 916 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 917 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 918 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 919 } 920 udelay(100); 921 } 922} 923 924static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 925 enum nl80211_iftype opmode) 926{ 927 u32 sync_default = AR_INTR_SYNC_DEFAULT; 928 u32 imr_reg = AR_IMR_TXERR | 929 AR_IMR_TXURN | 930 AR_IMR_RXERR | 931 AR_IMR_RXORN | 932 AR_IMR_BCNMISC; 933 934 if (AR_SREV_9340(ah)) 935 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 936 937 if (AR_SREV_9300_20_OR_LATER(ah)) { 938 imr_reg |= AR_IMR_RXOK_HP; 939 if (ah->config.rx_intr_mitigation) 940 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 941 else 942 imr_reg |= AR_IMR_RXOK_LP; 943 944 } else { 945 if (ah->config.rx_intr_mitigation) 946 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 947 else 948 imr_reg |= AR_IMR_RXOK; 949 } 950 951 if (ah->config.tx_intr_mitigation) 952 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 953 else 954 imr_reg |= AR_IMR_TXOK; 955 956 if (opmode == NL80211_IFTYPE_AP) 957 imr_reg |= AR_IMR_MIB; 958 959 ENABLE_REGWRITE_BUFFER(ah); 960 961 REG_WRITE(ah, AR_IMR, imr_reg); 962 ah->imrs2_reg |= AR_IMR_S2_GTT; 963 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 964 965 if (!AR_SREV_9100(ah)) { 966 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 967 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 968 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 969 } 970 971 REGWRITE_BUFFER_FLUSH(ah); 972 973 if (AR_SREV_9300_20_OR_LATER(ah)) { 974 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 975 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 976 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 977 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 978 } 979} 980 981static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 982{ 983 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 984 val = min(val, (u32) 0xFFFF); 985 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 986} 987 988static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 989{ 990 u32 val = ath9k_hw_mac_to_clks(ah, us); 991 val = min(val, (u32) 0xFFFF); 992 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 993} 994 995static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 996{ 997 u32 val = ath9k_hw_mac_to_clks(ah, us); 998 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 999 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1000} 1001 1002static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1003{ 1004 u32 val = ath9k_hw_mac_to_clks(ah, us); 1005 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1006 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1007} 1008 1009static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1010{ 1011 if (tu > 0xFFFF) { 1012 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1013 tu); 1014 ah->globaltxtimeout = (u32) -1; 1015 return false; 1016 } else { 1017 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1018 ah->globaltxtimeout = tu; 1019 return true; 1020 } 1021} 1022 1023void ath9k_hw_init_global_settings(struct ath_hw *ah) 1024{ 1025 struct ath_common *common = ath9k_hw_common(ah); 1026 struct ieee80211_conf *conf = &common->hw->conf; 1027 const struct ath9k_channel *chan = ah->curchan; 1028 int acktimeout, ctstimeout, ack_offset = 0; 1029 int slottime; 1030 int sifstime; 1031 int rx_lat = 0, tx_lat = 0, eifs = 0; 1032 u32 reg; 1033 1034 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1035 ah->misc_mode); 1036 1037 if (!chan) 1038 return; 1039 1040 if (ah->misc_mode != 0) 1041 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1042 1043 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1044 rx_lat = 41; 1045 else 1046 rx_lat = 37; 1047 tx_lat = 54; 1048 1049 if (IS_CHAN_5GHZ(chan)) 1050 sifstime = 16; 1051 else 1052 sifstime = 10; 1053 1054 if (IS_CHAN_HALF_RATE(chan)) { 1055 eifs = 175; 1056 rx_lat *= 2; 1057 tx_lat *= 2; 1058 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1059 tx_lat += 11; 1060 1061 sifstime *= 2; 1062 ack_offset = 16; 1063 slottime = 13; 1064 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1065 eifs = 340; 1066 rx_lat = (rx_lat * 4) - 1; 1067 tx_lat *= 4; 1068 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1069 tx_lat += 22; 1070 1071 sifstime *= 4; 1072 ack_offset = 32; 1073 slottime = 21; 1074 } else { 1075 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1076 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1077 reg = AR_USEC_ASYNC_FIFO; 1078 } else { 1079 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1080 common->clockrate; 1081 reg = REG_READ(ah, AR_USEC); 1082 } 1083 rx_lat = MS(reg, AR_USEC_RX_LAT); 1084 tx_lat = MS(reg, AR_USEC_TX_LAT); 1085 1086 slottime = ah->slottime; 1087 } 1088 1089 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1090 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset; 1091 ctstimeout = acktimeout; 1092 1093 /* 1094 * Workaround for early ACK timeouts, add an offset to match the 1095 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1096 * This was initially only meant to work around an issue with delayed 1097 * BA frames in some implementations, but it has been found to fix ACK 1098 * timeout issues in other cases as well. 1099 */ 1100 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ && 1101 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1102 acktimeout += 64 - sifstime - ah->slottime; 1103 ctstimeout += 48 - sifstime - ah->slottime; 1104 } 1105 1106 1107 ath9k_hw_set_sifs_time(ah, sifstime); 1108 ath9k_hw_setslottime(ah, slottime); 1109 ath9k_hw_set_ack_timeout(ah, acktimeout); 1110 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1111 if (ah->globaltxtimeout != (u32) -1) 1112 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1113 1114 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1115 REG_RMW(ah, AR_USEC, 1116 (common->clockrate - 1) | 1117 SM(rx_lat, AR_USEC_RX_LAT) | 1118 SM(tx_lat, AR_USEC_TX_LAT), 1119 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1120 1121} 1122EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1123 1124void ath9k_hw_deinit(struct ath_hw *ah) 1125{ 1126 struct ath_common *common = ath9k_hw_common(ah); 1127 1128 if (common->state < ATH_HW_INITIALIZED) 1129 goto free_hw; 1130 1131 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1132 1133free_hw: 1134 ath9k_hw_rf_free_ext_banks(ah); 1135} 1136EXPORT_SYMBOL(ath9k_hw_deinit); 1137 1138/*******/ 1139/* INI */ 1140/*******/ 1141 1142u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1143{ 1144 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1145 1146 if (IS_CHAN_B(chan)) 1147 ctl |= CTL_11B; 1148 else if (IS_CHAN_G(chan)) 1149 ctl |= CTL_11G; 1150 else 1151 ctl |= CTL_11A; 1152 1153 return ctl; 1154} 1155 1156/****************************************/ 1157/* Reset and Channel Switching Routines */ 1158/****************************************/ 1159 1160static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1161{ 1162 struct ath_common *common = ath9k_hw_common(ah); 1163 1164 ENABLE_REGWRITE_BUFFER(ah); 1165 1166 /* 1167 * set AHB_MODE not to do cacheline prefetches 1168 */ 1169 if (!AR_SREV_9300_20_OR_LATER(ah)) 1170 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1171 1172 /* 1173 * let mac dma reads be in 128 byte chunks 1174 */ 1175 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1176 1177 REGWRITE_BUFFER_FLUSH(ah); 1178 1179 /* 1180 * Restore TX Trigger Level to its pre-reset value. 1181 * The initial value depends on whether aggregation is enabled, and is 1182 * adjusted whenever underruns are detected. 1183 */ 1184 if (!AR_SREV_9300_20_OR_LATER(ah)) 1185 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1186 1187 ENABLE_REGWRITE_BUFFER(ah); 1188 1189 /* 1190 * let mac dma writes be in 128 byte chunks 1191 */ 1192 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1193 1194 /* 1195 * Setup receive FIFO threshold to hold off TX activities 1196 */ 1197 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1198 1199 if (AR_SREV_9300_20_OR_LATER(ah)) { 1200 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1201 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1202 1203 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1204 ah->caps.rx_status_len); 1205 } 1206 1207 /* 1208 * reduce the number of usable entries in PCU TXBUF to avoid 1209 * wrap around issues. 1210 */ 1211 if (AR_SREV_9285(ah)) { 1212 /* For AR9285 the number of Fifos are reduced to half. 1213 * So set the usable tx buf size also to half to 1214 * avoid data/delimiter underruns 1215 */ 1216 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1217 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1218 } else if (!AR_SREV_9271(ah)) { 1219 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1220 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1221 } 1222 1223 REGWRITE_BUFFER_FLUSH(ah); 1224 1225 if (AR_SREV_9300_20_OR_LATER(ah)) 1226 ath9k_hw_reset_txstatus_ring(ah); 1227} 1228 1229static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1230{ 1231 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1232 u32 set = AR_STA_ID1_KSRCH_MODE; 1233 1234 switch (opmode) { 1235 case NL80211_IFTYPE_ADHOC: 1236 case NL80211_IFTYPE_MESH_POINT: 1237 set |= AR_STA_ID1_ADHOC; 1238 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1239 break; 1240 case NL80211_IFTYPE_AP: 1241 set |= AR_STA_ID1_STA_AP; 1242 /* fall through */ 1243 case NL80211_IFTYPE_STATION: 1244 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1245 break; 1246 default: 1247 if (!ah->is_monitoring) 1248 set = 0; 1249 break; 1250 } 1251 REG_RMW(ah, AR_STA_ID1, set, mask); 1252} 1253 1254void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1255 u32 *coef_mantissa, u32 *coef_exponent) 1256{ 1257 u32 coef_exp, coef_man; 1258 1259 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1260 if ((coef_scaled >> coef_exp) & 0x1) 1261 break; 1262 1263 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1264 1265 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1266 1267 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1268 *coef_exponent = coef_exp - 16; 1269} 1270 1271static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1272{ 1273 u32 rst_flags; 1274 u32 tmpReg; 1275 1276 if (AR_SREV_9100(ah)) { 1277 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1278 AR_RTC_DERIVED_CLK_PERIOD, 1); 1279 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1280 } 1281 1282 ENABLE_REGWRITE_BUFFER(ah); 1283 1284 if (AR_SREV_9300_20_OR_LATER(ah)) { 1285 REG_WRITE(ah, AR_WA, ah->WARegVal); 1286 udelay(10); 1287 } 1288 1289 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1290 AR_RTC_FORCE_WAKE_ON_INT); 1291 1292 if (AR_SREV_9100(ah)) { 1293 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1294 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1295 } else { 1296 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1297 if (tmpReg & 1298 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1299 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1300 u32 val; 1301 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1302 1303 val = AR_RC_HOSTIF; 1304 if (!AR_SREV_9300_20_OR_LATER(ah)) 1305 val |= AR_RC_AHB; 1306 REG_WRITE(ah, AR_RC, val); 1307 1308 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1309 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1310 1311 rst_flags = AR_RTC_RC_MAC_WARM; 1312 if (type == ATH9K_RESET_COLD) 1313 rst_flags |= AR_RTC_RC_MAC_COLD; 1314 } 1315 1316 if (AR_SREV_9330(ah)) { 1317 int npend = 0; 1318 int i; 1319 1320 /* AR9330 WAR: 1321 * call external reset function to reset WMAC if: 1322 * - doing a cold reset 1323 * - we have pending frames in the TX queues 1324 */ 1325 1326 for (i = 0; i < AR_NUM_QCU; i++) { 1327 npend = ath9k_hw_numtxpending(ah, i); 1328 if (npend) 1329 break; 1330 } 1331 1332 if (ah->external_reset && 1333 (npend || type == ATH9K_RESET_COLD)) { 1334 int reset_err = 0; 1335 1336 ath_dbg(ath9k_hw_common(ah), RESET, 1337 "reset MAC via external reset\n"); 1338 1339 reset_err = ah->external_reset(); 1340 if (reset_err) { 1341 ath_err(ath9k_hw_common(ah), 1342 "External reset failed, err=%d\n", 1343 reset_err); 1344 return false; 1345 } 1346 1347 REG_WRITE(ah, AR_RTC_RESET, 1); 1348 } 1349 } 1350 1351 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1352 1353 REGWRITE_BUFFER_FLUSH(ah); 1354 1355 udelay(50); 1356 1357 REG_WRITE(ah, AR_RTC_RC, 0); 1358 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1359 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1360 return false; 1361 } 1362 1363 if (!AR_SREV_9100(ah)) 1364 REG_WRITE(ah, AR_RC, 0); 1365 1366 if (AR_SREV_9100(ah)) 1367 udelay(50); 1368 1369 return true; 1370} 1371 1372static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1373{ 1374 ENABLE_REGWRITE_BUFFER(ah); 1375 1376 if (AR_SREV_9300_20_OR_LATER(ah)) { 1377 REG_WRITE(ah, AR_WA, ah->WARegVal); 1378 udelay(10); 1379 } 1380 1381 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1382 AR_RTC_FORCE_WAKE_ON_INT); 1383 1384 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1385 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1386 1387 REG_WRITE(ah, AR_RTC_RESET, 0); 1388 1389 REGWRITE_BUFFER_FLUSH(ah); 1390 1391 if (!AR_SREV_9300_20_OR_LATER(ah)) 1392 udelay(2); 1393 1394 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1395 REG_WRITE(ah, AR_RC, 0); 1396 1397 REG_WRITE(ah, AR_RTC_RESET, 1); 1398 1399 if (!ath9k_hw_wait(ah, 1400 AR_RTC_STATUS, 1401 AR_RTC_STATUS_M, 1402 AR_RTC_STATUS_ON, 1403 AH_WAIT_TIMEOUT)) { 1404 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1405 return false; 1406 } 1407 1408 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1409} 1410 1411static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1412{ 1413 bool ret = false; 1414 1415 if (AR_SREV_9300_20_OR_LATER(ah)) { 1416 REG_WRITE(ah, AR_WA, ah->WARegVal); 1417 udelay(10); 1418 } 1419 1420 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1421 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1422 1423 switch (type) { 1424 case ATH9K_RESET_POWER_ON: 1425 ret = ath9k_hw_set_reset_power_on(ah); 1426 break; 1427 case ATH9K_RESET_WARM: 1428 case ATH9K_RESET_COLD: 1429 ret = ath9k_hw_set_reset(ah, type); 1430 break; 1431 default: 1432 break; 1433 } 1434 1435 return ret; 1436} 1437 1438static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1439 struct ath9k_channel *chan) 1440{ 1441 int reset_type = ATH9K_RESET_WARM; 1442 1443 if (AR_SREV_9280(ah)) { 1444 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1445 reset_type = ATH9K_RESET_POWER_ON; 1446 else 1447 reset_type = ATH9K_RESET_COLD; 1448 } 1449 1450 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1451 return false; 1452 1453 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1454 return false; 1455 1456 ah->chip_fullsleep = false; 1457 1458 if (AR_SREV_9330(ah)) 1459 ar9003_hw_internal_regulator_apply(ah); 1460 ath9k_hw_init_pll(ah, chan); 1461 ath9k_hw_set_rfmode(ah, chan); 1462 1463 return true; 1464} 1465 1466static bool ath9k_hw_channel_change(struct ath_hw *ah, 1467 struct ath9k_channel *chan) 1468{ 1469 struct ath_common *common = ath9k_hw_common(ah); 1470 u32 qnum; 1471 int r; 1472 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1473 bool band_switch, mode_diff; 1474 u8 ini_reloaded; 1475 1476 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != 1477 (ah->curchan->channelFlags & (CHANNEL_2GHZ | 1478 CHANNEL_5GHZ)); 1479 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1480 1481 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1482 if (ath9k_hw_numtxpending(ah, qnum)) { 1483 ath_dbg(common, QUEUE, 1484 "Transmit frames pending on queue %d\n", qnum); 1485 return false; 1486 } 1487 } 1488 1489 if (!ath9k_hw_rfbus_req(ah)) { 1490 ath_err(common, "Could not kill baseband RX\n"); 1491 return false; 1492 } 1493 1494 if (edma && (band_switch || mode_diff)) { 1495 ath9k_hw_mark_phy_inactive(ah); 1496 udelay(5); 1497 1498 ath9k_hw_init_pll(ah, NULL); 1499 1500 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1501 ath_err(common, "Failed to do fast channel change\n"); 1502 return false; 1503 } 1504 } 1505 1506 ath9k_hw_set_channel_regs(ah, chan); 1507 1508 r = ath9k_hw_rf_set_freq(ah, chan); 1509 if (r) { 1510 ath_err(common, "Failed to set channel\n"); 1511 return false; 1512 } 1513 ath9k_hw_set_clockrate(ah); 1514 ath9k_hw_apply_txpower(ah, chan, false); 1515 ath9k_hw_rfbus_done(ah); 1516 1517 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1518 ath9k_hw_set_delta_slope(ah, chan); 1519 1520 ath9k_hw_spur_mitigate_freq(ah, chan); 1521 1522 if (edma && (band_switch || mode_diff)) { 1523 ah->ah_flags |= AH_FASTCC; 1524 if (band_switch || ini_reloaded) 1525 ah->eep_ops->set_board_values(ah, chan); 1526 1527 ath9k_hw_init_bb(ah, chan); 1528 1529 if (band_switch || ini_reloaded) 1530 ath9k_hw_init_cal(ah, chan); 1531 ah->ah_flags &= ~AH_FASTCC; 1532 } 1533 1534 return true; 1535} 1536 1537static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1538{ 1539 u32 gpio_mask = ah->gpio_mask; 1540 int i; 1541 1542 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1543 if (!(gpio_mask & 1)) 1544 continue; 1545 1546 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1547 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1548 } 1549} 1550 1551static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states, 1552 int *hang_state, int *hang_pos) 1553{ 1554 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */ 1555 u32 chain_state, dcs_pos, i; 1556 1557 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) { 1558 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f; 1559 for (i = 0; i < 3; i++) { 1560 if (chain_state == dcu_chain_state[i]) { 1561 *hang_state = chain_state; 1562 *hang_pos = dcs_pos; 1563 return true; 1564 } 1565 } 1566 } 1567 return false; 1568} 1569 1570#define DCU_COMPLETE_STATE 1 1571#define DCU_COMPLETE_STATE_MASK 0x3 1572#define NUM_STATUS_READS 50 1573static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah) 1574{ 1575 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4; 1576 u32 i, hang_pos, hang_state, num_state = 6; 1577 1578 comp_state = REG_READ(ah, AR_DMADBG_6); 1579 1580 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) { 1581 ath_dbg(ath9k_hw_common(ah), RESET, 1582 "MAC Hang signature not found at DCU complete\n"); 1583 return false; 1584 } 1585 1586 chain_state = REG_READ(ah, dcs_reg); 1587 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1588 goto hang_check_iter; 1589 1590 dcs_reg = AR_DMADBG_5; 1591 num_state = 4; 1592 chain_state = REG_READ(ah, dcs_reg); 1593 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1594 goto hang_check_iter; 1595 1596 ath_dbg(ath9k_hw_common(ah), RESET, 1597 "MAC Hang signature 1 not found\n"); 1598 return false; 1599 1600hang_check_iter: 1601 ath_dbg(ath9k_hw_common(ah), RESET, 1602 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n", 1603 chain_state, comp_state, hang_state, hang_pos); 1604 1605 for (i = 0; i < NUM_STATUS_READS; i++) { 1606 chain_state = REG_READ(ah, dcs_reg); 1607 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f; 1608 comp_state = REG_READ(ah, AR_DMADBG_6); 1609 1610 if (((comp_state & DCU_COMPLETE_STATE_MASK) != 1611 DCU_COMPLETE_STATE) || 1612 (chain_state != hang_state)) 1613 return false; 1614 } 1615 1616 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n"); 1617 1618 return true; 1619} 1620 1621bool ath9k_hw_check_alive(struct ath_hw *ah) 1622{ 1623 int count = 50; 1624 u32 reg; 1625 1626 if (AR_SREV_9300(ah)) 1627 return !ath9k_hw_detect_mac_hang(ah); 1628 1629 if (AR_SREV_9285_12_OR_LATER(ah)) 1630 return true; 1631 1632 do { 1633 reg = REG_READ(ah, AR_OBS_BUS_1); 1634 1635 if ((reg & 0x7E7FFFEF) == 0x00702400) 1636 continue; 1637 1638 switch (reg & 0x7E000B00) { 1639 case 0x1E000000: 1640 case 0x52000B00: 1641 case 0x18000B00: 1642 continue; 1643 default: 1644 return true; 1645 } 1646 } while (count-- > 0); 1647 1648 return false; 1649} 1650EXPORT_SYMBOL(ath9k_hw_check_alive); 1651 1652/* 1653 * Fast channel change: 1654 * (Change synthesizer based on channel freq without resetting chip) 1655 * 1656 * Don't do FCC when 1657 * - Flag is not set 1658 * - Chip is just coming out of full sleep 1659 * - Channel to be set is same as current channel 1660 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel) 1661 */ 1662static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1663{ 1664 struct ath_common *common = ath9k_hw_common(ah); 1665 int ret; 1666 1667 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1668 goto fail; 1669 1670 if (ah->chip_fullsleep) 1671 goto fail; 1672 1673 if (!ah->curchan) 1674 goto fail; 1675 1676 if (chan->channel == ah->curchan->channel) 1677 goto fail; 1678 1679 if ((ah->curchan->channelFlags | chan->channelFlags) & 1680 (CHANNEL_HALF | CHANNEL_QUARTER)) 1681 goto fail; 1682 1683 if ((chan->channelFlags & CHANNEL_ALL) != 1684 (ah->curchan->channelFlags & CHANNEL_ALL)) 1685 goto fail; 1686 1687 if (!ath9k_hw_check_alive(ah)) 1688 goto fail; 1689 1690 /* 1691 * For AR9462, make sure that calibration data for 1692 * re-using are present. 1693 */ 1694 if (AR_SREV_9462(ah) && (ah->caldata && 1695 (!ah->caldata->done_txiqcal_once || 1696 !ah->caldata->done_txclcal_once || 1697 !ah->caldata->rtt_done))) 1698 goto fail; 1699 1700 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1701 ah->curchan->channel, chan->channel); 1702 1703 ret = ath9k_hw_channel_change(ah, chan); 1704 if (!ret) 1705 goto fail; 1706 1707 ath9k_hw_loadnf(ah, ah->curchan); 1708 ath9k_hw_start_nfcal(ah, true); 1709 1710 if (ath9k_hw_mci_is_enabled(ah)) 1711 ar9003_mci_2g5g_switch(ah, true); 1712 1713 if (AR_SREV_9271(ah)) 1714 ar9002_hw_load_ani_reg(ah, chan); 1715 1716 return 0; 1717fail: 1718 return -EINVAL; 1719} 1720 1721int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1722 struct ath9k_hw_cal_data *caldata, bool fastcc) 1723{ 1724 struct ath_common *common = ath9k_hw_common(ah); 1725 u32 saveLedState; 1726 u32 saveDefAntenna; 1727 u32 macStaId1; 1728 u64 tsf = 0; 1729 int i, r; 1730 bool start_mci_reset = false; 1731 bool save_fullsleep = ah->chip_fullsleep; 1732 1733 if (ath9k_hw_mci_is_enabled(ah)) { 1734 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1735 if (start_mci_reset) 1736 return 0; 1737 } 1738 1739 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1740 return -EIO; 1741 1742 if (ah->curchan && !ah->chip_fullsleep) 1743 ath9k_hw_getnf(ah, ah->curchan); 1744 1745 ah->caldata = caldata; 1746 if (caldata && 1747 (chan->channel != caldata->channel || 1748 (chan->channelFlags & ~CHANNEL_CW_INT) != 1749 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1750 /* Operating channel changed, reset channel calibration data */ 1751 memset(caldata, 0, sizeof(*caldata)); 1752 ath9k_init_nfcal_hist_buffer(ah, chan); 1753 } 1754 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1755 1756 if (fastcc) { 1757 r = ath9k_hw_do_fastcc(ah, chan); 1758 if (!r) 1759 return r; 1760 } 1761 1762 if (ath9k_hw_mci_is_enabled(ah)) 1763 ar9003_mci_stop_bt(ah, save_fullsleep); 1764 1765 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1766 if (saveDefAntenna == 0) 1767 saveDefAntenna = 1; 1768 1769 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1770 1771 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1772 if (AR_SREV_9100(ah) || 1773 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1774 tsf = ath9k_hw_gettsf64(ah); 1775 1776 saveLedState = REG_READ(ah, AR_CFG_LED) & 1777 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1778 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1779 1780 ath9k_hw_mark_phy_inactive(ah); 1781 1782 ah->paprd_table_write_done = false; 1783 1784 /* Only required on the first reset */ 1785 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1786 REG_WRITE(ah, 1787 AR9271_RESET_POWER_DOWN_CONTROL, 1788 AR9271_RADIO_RF_RST); 1789 udelay(50); 1790 } 1791 1792 if (!ath9k_hw_chip_reset(ah, chan)) { 1793 ath_err(common, "Chip reset failed\n"); 1794 return -EINVAL; 1795 } 1796 1797 /* Only required on the first reset */ 1798 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1799 ah->htc_reset_init = false; 1800 REG_WRITE(ah, 1801 AR9271_RESET_POWER_DOWN_CONTROL, 1802 AR9271_GATE_MAC_CTL); 1803 udelay(50); 1804 } 1805 1806 /* Restore TSF */ 1807 if (tsf) 1808 ath9k_hw_settsf64(ah, tsf); 1809 1810 if (AR_SREV_9280_20_OR_LATER(ah)) 1811 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1812 1813 if (!AR_SREV_9300_20_OR_LATER(ah)) 1814 ar9002_hw_enable_async_fifo(ah); 1815 1816 r = ath9k_hw_process_ini(ah, chan); 1817 if (r) 1818 return r; 1819 1820 if (ath9k_hw_mci_is_enabled(ah)) 1821 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1822 1823 /* 1824 * Some AR91xx SoC devices frequently fail to accept TSF writes 1825 * right after the chip reset. When that happens, write a new 1826 * value after the initvals have been applied, with an offset 1827 * based on measured time difference 1828 */ 1829 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1830 tsf += 1500; 1831 ath9k_hw_settsf64(ah, tsf); 1832 } 1833 1834 /* Setup MFP options for CCMP */ 1835 if (AR_SREV_9280_20_OR_LATER(ah)) { 1836 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1837 * frames when constructing CCMP AAD. */ 1838 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1839 0xc7ff); 1840 ah->sw_mgmt_crypto = false; 1841 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1842 /* Disable hardware crypto for management frames */ 1843 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1844 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1845 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1846 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1847 ah->sw_mgmt_crypto = true; 1848 } else 1849 ah->sw_mgmt_crypto = true; 1850 1851 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1852 ath9k_hw_set_delta_slope(ah, chan); 1853 1854 ath9k_hw_spur_mitigate_freq(ah, chan); 1855 ah->eep_ops->set_board_values(ah, chan); 1856 1857 ENABLE_REGWRITE_BUFFER(ah); 1858 1859 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1860 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1861 | macStaId1 1862 | AR_STA_ID1_RTS_USE_DEF 1863 | (ah->config. 1864 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1865 | ah->sta_id1_defaults); 1866 ath_hw_setbssidmask(common); 1867 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1868 ath9k_hw_write_associd(ah); 1869 REG_WRITE(ah, AR_ISR, ~0); 1870 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1871 1872 REGWRITE_BUFFER_FLUSH(ah); 1873 1874 ath9k_hw_set_operating_mode(ah, ah->opmode); 1875 1876 r = ath9k_hw_rf_set_freq(ah, chan); 1877 if (r) 1878 return r; 1879 1880 ath9k_hw_set_clockrate(ah); 1881 1882 ENABLE_REGWRITE_BUFFER(ah); 1883 1884 for (i = 0; i < AR_NUM_DCU; i++) 1885 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1886 1887 REGWRITE_BUFFER_FLUSH(ah); 1888 1889 ah->intr_txqs = 0; 1890 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1891 ath9k_hw_resettxqueue(ah, i); 1892 1893 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1894 ath9k_hw_ani_cache_ini_regs(ah); 1895 ath9k_hw_init_qos(ah); 1896 1897 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1898 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1899 1900 ath9k_hw_init_global_settings(ah); 1901 1902 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1903 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1904 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1905 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1906 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1907 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1908 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1909 } 1910 1911 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1912 1913 ath9k_hw_set_dma(ah); 1914 1915 REG_WRITE(ah, AR_OBS, 8); 1916 1917 if (ah->config.rx_intr_mitigation) { 1918 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1919 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1920 } 1921 1922 if (ah->config.tx_intr_mitigation) { 1923 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1924 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1925 } 1926 1927 ath9k_hw_init_bb(ah, chan); 1928 1929 if (caldata) { 1930 caldata->done_txiqcal_once = false; 1931 caldata->done_txclcal_once = false; 1932 } 1933 if (!ath9k_hw_init_cal(ah, chan)) 1934 return -EIO; 1935 1936 ath9k_hw_loadnf(ah, chan); 1937 ath9k_hw_start_nfcal(ah, true); 1938 1939 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1940 return -EIO; 1941 1942 ENABLE_REGWRITE_BUFFER(ah); 1943 1944 ath9k_hw_restore_chainmask(ah); 1945 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1946 1947 REGWRITE_BUFFER_FLUSH(ah); 1948 1949 /* 1950 * For big endian systems turn on swapping for descriptors 1951 */ 1952 if (AR_SREV_9100(ah)) { 1953 u32 mask; 1954 mask = REG_READ(ah, AR_CFG); 1955 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1956 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1957 mask); 1958 } else { 1959 mask = 1960 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1961 REG_WRITE(ah, AR_CFG, mask); 1962 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1963 REG_READ(ah, AR_CFG)); 1964 } 1965 } else { 1966 if (common->bus_ops->ath_bus_type == ATH_USB) { 1967 /* Configure AR9271 target WLAN */ 1968 if (AR_SREV_9271(ah)) 1969 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1970 else 1971 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1972 } 1973#ifdef __BIG_ENDIAN 1974 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) 1975 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1976 else 1977 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1978#endif 1979 } 1980 1981 if (ath9k_hw_btcoex_is_enabled(ah)) 1982 ath9k_hw_btcoex_enable(ah); 1983 1984 if (ath9k_hw_mci_is_enabled(ah)) 1985 ar9003_mci_check_bt(ah); 1986 1987 if (AR_SREV_9300_20_OR_LATER(ah)) { 1988 ar9003_hw_bb_watchdog_config(ah); 1989 1990 ar9003_hw_disable_phy_restart(ah); 1991 } 1992 1993 ath9k_hw_apply_gpio_override(ah); 1994 1995 return 0; 1996} 1997EXPORT_SYMBOL(ath9k_hw_reset); 1998 1999/******************************/ 2000/* Power Management (Chipset) */ 2001/******************************/ 2002 2003/* 2004 * Notify Power Mgt is disabled in self-generated frames. 2005 * If requested, force chip to sleep. 2006 */ 2007static void ath9k_set_power_sleep(struct ath_hw *ah) 2008{ 2009 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2010 2011 if (AR_SREV_9462(ah)) { 2012 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2013 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2014 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2015 /* xxx Required for WLAN only case ? */ 2016 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2017 udelay(100); 2018 } 2019 2020 /* 2021 * Clear the RTC force wake bit to allow the 2022 * mac to go to sleep. 2023 */ 2024 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2025 2026 if (ath9k_hw_mci_is_enabled(ah)) 2027 udelay(100); 2028 2029 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2030 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2031 2032 /* Shutdown chip. Active low */ 2033 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2034 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2035 udelay(2); 2036 } 2037 2038 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2039 if (AR_SREV_9300_20_OR_LATER(ah)) 2040 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2041} 2042 2043/* 2044 * Notify Power Management is enabled in self-generating 2045 * frames. If request, set power mode of chip to 2046 * auto/normal. Duration in units of 128us (1/8 TU). 2047 */ 2048static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2049{ 2050 struct ath9k_hw_capabilities *pCap = &ah->caps; 2051 2052 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2053 2054 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2055 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2056 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2057 AR_RTC_FORCE_WAKE_ON_INT); 2058 } else { 2059 2060 /* When chip goes into network sleep, it could be waken 2061 * up by MCI_INT interrupt caused by BT's HW messages 2062 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2063 * rate (~100us). This will cause chip to leave and 2064 * re-enter network sleep mode frequently, which in 2065 * consequence will have WLAN MCI HW to generate lots of 2066 * SYS_WAKING and SYS_SLEEPING messages which will make 2067 * BT CPU to busy to process. 2068 */ 2069 if (ath9k_hw_mci_is_enabled(ah)) 2070 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2071 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2072 /* 2073 * Clear the RTC force wake bit to allow the 2074 * mac to go to sleep. 2075 */ 2076 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2077 2078 if (ath9k_hw_mci_is_enabled(ah)) 2079 udelay(30); 2080 } 2081 2082 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2083 if (AR_SREV_9300_20_OR_LATER(ah)) 2084 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2085} 2086 2087static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2088{ 2089 u32 val; 2090 int i; 2091 2092 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2093 if (AR_SREV_9300_20_OR_LATER(ah)) { 2094 REG_WRITE(ah, AR_WA, ah->WARegVal); 2095 udelay(10); 2096 } 2097 2098 if ((REG_READ(ah, AR_RTC_STATUS) & 2099 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2100 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2101 return false; 2102 } 2103 if (!AR_SREV_9300_20_OR_LATER(ah)) 2104 ath9k_hw_init_pll(ah, NULL); 2105 } 2106 if (AR_SREV_9100(ah)) 2107 REG_SET_BIT(ah, AR_RTC_RESET, 2108 AR_RTC_RESET_EN); 2109 2110 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2111 AR_RTC_FORCE_WAKE_EN); 2112 udelay(50); 2113 2114 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2115 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2116 if (val == AR_RTC_STATUS_ON) 2117 break; 2118 udelay(50); 2119 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2120 AR_RTC_FORCE_WAKE_EN); 2121 } 2122 if (i == 0) { 2123 ath_err(ath9k_hw_common(ah), 2124 "Failed to wakeup in %uus\n", 2125 POWER_UP_TIME / 20); 2126 return false; 2127 } 2128 2129 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2130 2131 return true; 2132} 2133 2134bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2135{ 2136 struct ath_common *common = ath9k_hw_common(ah); 2137 int status = true; 2138 static const char *modes[] = { 2139 "AWAKE", 2140 "FULL-SLEEP", 2141 "NETWORK SLEEP", 2142 "UNDEFINED" 2143 }; 2144 2145 if (ah->power_mode == mode) 2146 return status; 2147 2148 ath_dbg(common, RESET, "%s -> %s\n", 2149 modes[ah->power_mode], modes[mode]); 2150 2151 switch (mode) { 2152 case ATH9K_PM_AWAKE: 2153 status = ath9k_hw_set_power_awake(ah); 2154 break; 2155 case ATH9K_PM_FULL_SLEEP: 2156 if (ath9k_hw_mci_is_enabled(ah)) 2157 ar9003_mci_set_full_sleep(ah); 2158 2159 ath9k_set_power_sleep(ah); 2160 ah->chip_fullsleep = true; 2161 break; 2162 case ATH9K_PM_NETWORK_SLEEP: 2163 ath9k_set_power_network_sleep(ah); 2164 break; 2165 default: 2166 ath_err(common, "Unknown power mode %u\n", mode); 2167 return false; 2168 } 2169 ah->power_mode = mode; 2170 2171 /* 2172 * XXX: If this warning never comes up after a while then 2173 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2174 * ath9k_hw_setpower() return type void. 2175 */ 2176 2177 if (!(ah->ah_flags & AH_UNPLUGGED)) 2178 ATH_DBG_WARN_ON_ONCE(!status); 2179 2180 return status; 2181} 2182EXPORT_SYMBOL(ath9k_hw_setpower); 2183 2184/*******************/ 2185/* Beacon Handling */ 2186/*******************/ 2187 2188void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2189{ 2190 int flags = 0; 2191 2192 ENABLE_REGWRITE_BUFFER(ah); 2193 2194 switch (ah->opmode) { 2195 case NL80211_IFTYPE_ADHOC: 2196 case NL80211_IFTYPE_MESH_POINT: 2197 REG_SET_BIT(ah, AR_TXCFG, 2198 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2199 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2200 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2201 flags |= AR_NDP_TIMER_EN; 2202 case NL80211_IFTYPE_AP: 2203 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2204 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2205 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2206 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2207 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2208 flags |= 2209 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2210 break; 2211 default: 2212 ath_dbg(ath9k_hw_common(ah), BEACON, 2213 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2214 return; 2215 break; 2216 } 2217 2218 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2219 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2220 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2221 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2222 2223 REGWRITE_BUFFER_FLUSH(ah); 2224 2225 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2226} 2227EXPORT_SYMBOL(ath9k_hw_beaconinit); 2228 2229void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2230 const struct ath9k_beacon_state *bs) 2231{ 2232 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2233 struct ath9k_hw_capabilities *pCap = &ah->caps; 2234 struct ath_common *common = ath9k_hw_common(ah); 2235 2236 ENABLE_REGWRITE_BUFFER(ah); 2237 2238 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2239 2240 REG_WRITE(ah, AR_BEACON_PERIOD, 2241 TU_TO_USEC(bs->bs_intval)); 2242 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2243 TU_TO_USEC(bs->bs_intval)); 2244 2245 REGWRITE_BUFFER_FLUSH(ah); 2246 2247 REG_RMW_FIELD(ah, AR_RSSI_THR, 2248 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2249 2250 beaconintval = bs->bs_intval; 2251 2252 if (bs->bs_sleepduration > beaconintval) 2253 beaconintval = bs->bs_sleepduration; 2254 2255 dtimperiod = bs->bs_dtimperiod; 2256 if (bs->bs_sleepduration > dtimperiod) 2257 dtimperiod = bs->bs_sleepduration; 2258 2259 if (beaconintval == dtimperiod) 2260 nextTbtt = bs->bs_nextdtim; 2261 else 2262 nextTbtt = bs->bs_nexttbtt; 2263 2264 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2265 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2266 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2267 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2268 2269 ENABLE_REGWRITE_BUFFER(ah); 2270 2271 REG_WRITE(ah, AR_NEXT_DTIM, 2272 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2273 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2274 2275 REG_WRITE(ah, AR_SLEEP1, 2276 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2277 | AR_SLEEP1_ASSUME_DTIM); 2278 2279 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2280 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2281 else 2282 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2283 2284 REG_WRITE(ah, AR_SLEEP2, 2285 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2286 2287 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2288 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2289 2290 REGWRITE_BUFFER_FLUSH(ah); 2291 2292 REG_SET_BIT(ah, AR_TIMER_MODE, 2293 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2294 AR_DTIM_TIMER_EN); 2295 2296 /* TSF Out of Range Threshold */ 2297 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2298} 2299EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2300 2301/*******************/ 2302/* HW Capabilities */ 2303/*******************/ 2304 2305static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2306{ 2307 eeprom_chainmask &= chip_chainmask; 2308 if (eeprom_chainmask) 2309 return eeprom_chainmask; 2310 else 2311 return chip_chainmask; 2312} 2313 2314/** 2315 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2316 * @ah: the atheros hardware data structure 2317 * 2318 * We enable DFS support upstream on chipsets which have passed a series 2319 * of tests. The testing requirements are going to be documented. Desired 2320 * test requirements are documented at: 2321 * 2322 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2323 * 2324 * Once a new chipset gets properly tested an individual commit can be used 2325 * to document the testing for DFS for that chipset. 2326 */ 2327static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2328{ 2329 2330 switch (ah->hw_version.macVersion) { 2331 /* AR9580 will likely be our first target to get testing on */ 2332 case AR_SREV_VERSION_9580: 2333 default: 2334 return false; 2335 } 2336} 2337 2338int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2339{ 2340 struct ath9k_hw_capabilities *pCap = &ah->caps; 2341 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2342 struct ath_common *common = ath9k_hw_common(ah); 2343 unsigned int chip_chainmask; 2344 2345 u16 eeval; 2346 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2347 2348 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2349 regulatory->current_rd = eeval; 2350 2351 if (ah->opmode != NL80211_IFTYPE_AP && 2352 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2353 if (regulatory->current_rd == 0x64 || 2354 regulatory->current_rd == 0x65) 2355 regulatory->current_rd += 5; 2356 else if (regulatory->current_rd == 0x41) 2357 regulatory->current_rd = 0x43; 2358 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2359 regulatory->current_rd); 2360 } 2361 2362 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2363 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2364 ath_err(common, 2365 "no band has been marked as supported in EEPROM\n"); 2366 return -EINVAL; 2367 } 2368 2369 if (eeval & AR5416_OPFLAGS_11A) 2370 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2371 2372 if (eeval & AR5416_OPFLAGS_11G) 2373 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2374 2375 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2376 chip_chainmask = 1; 2377 else if (AR_SREV_9462(ah)) 2378 chip_chainmask = 3; 2379 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2380 chip_chainmask = 7; 2381 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2382 chip_chainmask = 3; 2383 else 2384 chip_chainmask = 7; 2385 2386 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2387 /* 2388 * For AR9271 we will temporarilly uses the rx chainmax as read from 2389 * the EEPROM. 2390 */ 2391 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2392 !(eeval & AR5416_OPFLAGS_11A) && 2393 !(AR_SREV_9271(ah))) 2394 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2395 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2396 else if (AR_SREV_9100(ah)) 2397 pCap->rx_chainmask = 0x7; 2398 else 2399 /* Use rx_chainmask from EEPROM. */ 2400 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2401 2402 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2403 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2404 ah->txchainmask = pCap->tx_chainmask; 2405 ah->rxchainmask = pCap->rx_chainmask; 2406 2407 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2408 2409 /* enable key search for every frame in an aggregate */ 2410 if (AR_SREV_9300_20_OR_LATER(ah)) 2411 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2412 2413 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2414 2415 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2416 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2417 else 2418 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2419 2420 if (AR_SREV_9271(ah)) 2421 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2422 else if (AR_DEVID_7010(ah)) 2423 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2424 else if (AR_SREV_9300_20_OR_LATER(ah)) 2425 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2426 else if (AR_SREV_9287_11_OR_LATER(ah)) 2427 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2428 else if (AR_SREV_9285_12_OR_LATER(ah)) 2429 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2430 else if (AR_SREV_9280_20_OR_LATER(ah)) 2431 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2432 else 2433 pCap->num_gpio_pins = AR_NUM_GPIO; 2434 2435 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2436 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2437 else 2438 pCap->rts_aggr_limit = (8 * 1024); 2439 2440#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2441 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2442 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2443 ah->rfkill_gpio = 2444 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2445 ah->rfkill_polarity = 2446 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2447 2448 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2449 } 2450#endif 2451 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2452 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2453 else 2454 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2455 2456 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2457 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2458 else 2459 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2460 2461 if (AR_SREV_9300_20_OR_LATER(ah)) { 2462 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2463 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2464 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2465 2466 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2467 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2468 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2469 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2470 pCap->txs_len = sizeof(struct ar9003_txs); 2471 if (!ah->config.paprd_disable && 2472 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2473 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2474 } else { 2475 pCap->tx_desc_len = sizeof(struct ath_desc); 2476 if (AR_SREV_9280_20(ah)) 2477 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2478 } 2479 2480 if (AR_SREV_9300_20_OR_LATER(ah)) 2481 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2482 2483 if (AR_SREV_9300_20_OR_LATER(ah)) 2484 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2485 2486 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2487 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2488 2489 if (AR_SREV_9285(ah)) 2490 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2491 ant_div_ctl1 = 2492 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2493 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2494 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2495 } 2496 if (AR_SREV_9300_20_OR_LATER(ah)) { 2497 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2498 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2499 } 2500 2501 2502 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2503 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2504 /* 2505 * enable the diversity-combining algorithm only when 2506 * both enable_lna_div and enable_fast_div are set 2507 * Table for Diversity 2508 * ant_div_alt_lnaconf bit 0-1 2509 * ant_div_main_lnaconf bit 2-3 2510 * ant_div_alt_gaintb bit 4 2511 * ant_div_main_gaintb bit 5 2512 * enable_ant_div_lnadiv bit 6 2513 * enable_ant_fast_div bit 7 2514 */ 2515 if ((ant_div_ctl1 >> 0x6) == 0x3) 2516 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2517 } 2518 2519 if (AR_SREV_9485_10(ah)) { 2520 pCap->pcie_lcr_extsync_en = true; 2521 pCap->pcie_lcr_offset = 0x80; 2522 } 2523 2524 if (ath9k_hw_dfs_tested(ah)) 2525 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2526 2527 tx_chainmask = pCap->tx_chainmask; 2528 rx_chainmask = pCap->rx_chainmask; 2529 while (tx_chainmask || rx_chainmask) { 2530 if (tx_chainmask & BIT(0)) 2531 pCap->max_txchains++; 2532 if (rx_chainmask & BIT(0)) 2533 pCap->max_rxchains++; 2534 2535 tx_chainmask >>= 1; 2536 rx_chainmask >>= 1; 2537 } 2538 2539 if (AR_SREV_9300_20_OR_LATER(ah)) { 2540 ah->enabled_cals |= TX_IQ_CAL; 2541 if (AR_SREV_9485_OR_LATER(ah)) 2542 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2543 } 2544 2545 if (AR_SREV_9462(ah)) { 2546 2547 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2548 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2549 2550 if (AR_SREV_9462_20(ah)) 2551 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2552 2553 } 2554 2555 2556 return 0; 2557} 2558 2559/****************************/ 2560/* GPIO / RFKILL / Antennae */ 2561/****************************/ 2562 2563static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2564 u32 gpio, u32 type) 2565{ 2566 int addr; 2567 u32 gpio_shift, tmp; 2568 2569 if (gpio > 11) 2570 addr = AR_GPIO_OUTPUT_MUX3; 2571 else if (gpio > 5) 2572 addr = AR_GPIO_OUTPUT_MUX2; 2573 else 2574 addr = AR_GPIO_OUTPUT_MUX1; 2575 2576 gpio_shift = (gpio % 6) * 5; 2577 2578 if (AR_SREV_9280_20_OR_LATER(ah) 2579 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2580 REG_RMW(ah, addr, (type << gpio_shift), 2581 (0x1f << gpio_shift)); 2582 } else { 2583 tmp = REG_READ(ah, addr); 2584 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2585 tmp &= ~(0x1f << gpio_shift); 2586 tmp |= (type << gpio_shift); 2587 REG_WRITE(ah, addr, tmp); 2588 } 2589} 2590 2591void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2592{ 2593 u32 gpio_shift; 2594 2595 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2596 2597 if (AR_DEVID_7010(ah)) { 2598 gpio_shift = gpio; 2599 REG_RMW(ah, AR7010_GPIO_OE, 2600 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2601 (AR7010_GPIO_OE_MASK << gpio_shift)); 2602 return; 2603 } 2604 2605 gpio_shift = gpio << 1; 2606 REG_RMW(ah, 2607 AR_GPIO_OE_OUT, 2608 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2609 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2610} 2611EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2612 2613u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2614{ 2615#define MS_REG_READ(x, y) \ 2616 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2617 2618 if (gpio >= ah->caps.num_gpio_pins) 2619 return 0xffffffff; 2620 2621 if (AR_DEVID_7010(ah)) { 2622 u32 val; 2623 val = REG_READ(ah, AR7010_GPIO_IN); 2624 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2625 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2626 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2627 AR_GPIO_BIT(gpio)) != 0; 2628 else if (AR_SREV_9271(ah)) 2629 return MS_REG_READ(AR9271, gpio) != 0; 2630 else if (AR_SREV_9287_11_OR_LATER(ah)) 2631 return MS_REG_READ(AR9287, gpio) != 0; 2632 else if (AR_SREV_9285_12_OR_LATER(ah)) 2633 return MS_REG_READ(AR9285, gpio) != 0; 2634 else if (AR_SREV_9280_20_OR_LATER(ah)) 2635 return MS_REG_READ(AR928X, gpio) != 0; 2636 else 2637 return MS_REG_READ(AR, gpio) != 0; 2638} 2639EXPORT_SYMBOL(ath9k_hw_gpio_get); 2640 2641void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2642 u32 ah_signal_type) 2643{ 2644 u32 gpio_shift; 2645 2646 if (AR_DEVID_7010(ah)) { 2647 gpio_shift = gpio; 2648 REG_RMW(ah, AR7010_GPIO_OE, 2649 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2650 (AR7010_GPIO_OE_MASK << gpio_shift)); 2651 return; 2652 } 2653 2654 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2655 gpio_shift = 2 * gpio; 2656 REG_RMW(ah, 2657 AR_GPIO_OE_OUT, 2658 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2659 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2660} 2661EXPORT_SYMBOL(ath9k_hw_cfg_output); 2662 2663void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2664{ 2665 if (AR_DEVID_7010(ah)) { 2666 val = val ? 0 : 1; 2667 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2668 AR_GPIO_BIT(gpio)); 2669 return; 2670 } 2671 2672 if (AR_SREV_9271(ah)) 2673 val = ~val; 2674 2675 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2676 AR_GPIO_BIT(gpio)); 2677} 2678EXPORT_SYMBOL(ath9k_hw_set_gpio); 2679 2680void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2681{ 2682 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2683} 2684EXPORT_SYMBOL(ath9k_hw_setantenna); 2685 2686/*********************/ 2687/* General Operation */ 2688/*********************/ 2689 2690u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2691{ 2692 u32 bits = REG_READ(ah, AR_RX_FILTER); 2693 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2694 2695 if (phybits & AR_PHY_ERR_RADAR) 2696 bits |= ATH9K_RX_FILTER_PHYRADAR; 2697 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2698 bits |= ATH9K_RX_FILTER_PHYERR; 2699 2700 return bits; 2701} 2702EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2703 2704void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2705{ 2706 u32 phybits; 2707 2708 ENABLE_REGWRITE_BUFFER(ah); 2709 2710 if (AR_SREV_9462(ah)) 2711 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2712 2713 REG_WRITE(ah, AR_RX_FILTER, bits); 2714 2715 phybits = 0; 2716 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2717 phybits |= AR_PHY_ERR_RADAR; 2718 if (bits & ATH9K_RX_FILTER_PHYERR) 2719 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2720 REG_WRITE(ah, AR_PHY_ERR, phybits); 2721 2722 if (phybits) 2723 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2724 else 2725 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2726 2727 REGWRITE_BUFFER_FLUSH(ah); 2728} 2729EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2730 2731bool ath9k_hw_phy_disable(struct ath_hw *ah) 2732{ 2733 if (ath9k_hw_mci_is_enabled(ah)) 2734 ar9003_mci_bt_gain_ctrl(ah); 2735 2736 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2737 return false; 2738 2739 ath9k_hw_init_pll(ah, NULL); 2740 ah->htc_reset_init = true; 2741 return true; 2742} 2743EXPORT_SYMBOL(ath9k_hw_phy_disable); 2744 2745bool ath9k_hw_disable(struct ath_hw *ah) 2746{ 2747 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2748 return false; 2749 2750 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2751 return false; 2752 2753 ath9k_hw_init_pll(ah, NULL); 2754 return true; 2755} 2756EXPORT_SYMBOL(ath9k_hw_disable); 2757 2758static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2759{ 2760 enum eeprom_param gain_param; 2761 2762 if (IS_CHAN_2GHZ(chan)) 2763 gain_param = EEP_ANTENNA_GAIN_2G; 2764 else 2765 gain_param = EEP_ANTENNA_GAIN_5G; 2766 2767 return ah->eep_ops->get_eeprom(ah, gain_param); 2768} 2769 2770void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2771 bool test) 2772{ 2773 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2774 struct ieee80211_channel *channel; 2775 int chan_pwr, new_pwr, max_gain; 2776 int ant_gain, ant_reduction = 0; 2777 2778 if (!chan) 2779 return; 2780 2781 channel = chan->chan; 2782 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2783 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2784 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2785 2786 ant_gain = get_antenna_gain(ah, chan); 2787 if (ant_gain > max_gain) 2788 ant_reduction = ant_gain - max_gain; 2789 2790 ah->eep_ops->set_txpower(ah, chan, 2791 ath9k_regd_get_ctl(reg, chan), 2792 ant_reduction, new_pwr, test); 2793} 2794 2795void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2796{ 2797 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2798 struct ath9k_channel *chan = ah->curchan; 2799 struct ieee80211_channel *channel = chan->chan; 2800 2801 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2802 if (test) 2803 channel->max_power = MAX_RATE_POWER / 2; 2804 2805 ath9k_hw_apply_txpower(ah, chan, test); 2806 2807 if (test) 2808 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2809} 2810EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2811 2812void ath9k_hw_setopmode(struct ath_hw *ah) 2813{ 2814 ath9k_hw_set_operating_mode(ah, ah->opmode); 2815} 2816EXPORT_SYMBOL(ath9k_hw_setopmode); 2817 2818void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2819{ 2820 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2821 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2822} 2823EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2824 2825void ath9k_hw_write_associd(struct ath_hw *ah) 2826{ 2827 struct ath_common *common = ath9k_hw_common(ah); 2828 2829 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2830 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2831 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2832} 2833EXPORT_SYMBOL(ath9k_hw_write_associd); 2834 2835#define ATH9K_MAX_TSF_READ 10 2836 2837u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2838{ 2839 u32 tsf_lower, tsf_upper1, tsf_upper2; 2840 int i; 2841 2842 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2843 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2844 tsf_lower = REG_READ(ah, AR_TSF_L32); 2845 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2846 if (tsf_upper2 == tsf_upper1) 2847 break; 2848 tsf_upper1 = tsf_upper2; 2849 } 2850 2851 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2852 2853 return (((u64)tsf_upper1 << 32) | tsf_lower); 2854} 2855EXPORT_SYMBOL(ath9k_hw_gettsf64); 2856 2857void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2858{ 2859 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2860 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2861} 2862EXPORT_SYMBOL(ath9k_hw_settsf64); 2863 2864void ath9k_hw_reset_tsf(struct ath_hw *ah) 2865{ 2866 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2867 AH_TSF_WRITE_TIMEOUT)) 2868 ath_dbg(ath9k_hw_common(ah), RESET, 2869 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2870 2871 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2872} 2873EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2874 2875void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2876{ 2877 if (setting) 2878 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2879 else 2880 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2881} 2882EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2883 2884void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2885{ 2886 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2887 u32 macmode; 2888 2889 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2890 macmode = AR_2040_JOINED_RX_CLEAR; 2891 else 2892 macmode = 0; 2893 2894 REG_WRITE(ah, AR_2040_MODE, macmode); 2895} 2896 2897/* HW Generic timers configuration */ 2898 2899static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2900{ 2901 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2902 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2903 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2904 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2905 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2906 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2907 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2908 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2909 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2910 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2911 AR_NDP2_TIMER_MODE, 0x0002}, 2912 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2913 AR_NDP2_TIMER_MODE, 0x0004}, 2914 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2915 AR_NDP2_TIMER_MODE, 0x0008}, 2916 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2917 AR_NDP2_TIMER_MODE, 0x0010}, 2918 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2919 AR_NDP2_TIMER_MODE, 0x0020}, 2920 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2921 AR_NDP2_TIMER_MODE, 0x0040}, 2922 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2923 AR_NDP2_TIMER_MODE, 0x0080} 2924}; 2925 2926/* HW generic timer primitives */ 2927 2928/* compute and clear index of rightmost 1 */ 2929static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2930{ 2931 u32 b; 2932 2933 b = *mask; 2934 b &= (0-b); 2935 *mask &= ~b; 2936 b *= debruijn32; 2937 b >>= 27; 2938 2939 return timer_table->gen_timer_index[b]; 2940} 2941 2942u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2943{ 2944 return REG_READ(ah, AR_TSF_L32); 2945} 2946EXPORT_SYMBOL(ath9k_hw_gettsf32); 2947 2948struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2949 void (*trigger)(void *), 2950 void (*overflow)(void *), 2951 void *arg, 2952 u8 timer_index) 2953{ 2954 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2955 struct ath_gen_timer *timer; 2956 2957 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2958 2959 if (timer == NULL) { 2960 ath_err(ath9k_hw_common(ah), 2961 "Failed to allocate memory for hw timer[%d]\n", 2962 timer_index); 2963 return NULL; 2964 } 2965 2966 /* allocate a hardware generic timer slot */ 2967 timer_table->timers[timer_index] = timer; 2968 timer->index = timer_index; 2969 timer->trigger = trigger; 2970 timer->overflow = overflow; 2971 timer->arg = arg; 2972 2973 return timer; 2974} 2975EXPORT_SYMBOL(ath_gen_timer_alloc); 2976 2977void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2978 struct ath_gen_timer *timer, 2979 u32 trig_timeout, 2980 u32 timer_period) 2981{ 2982 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2983 u32 tsf, timer_next; 2984 2985 BUG_ON(!timer_period); 2986 2987 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2988 2989 tsf = ath9k_hw_gettsf32(ah); 2990 2991 timer_next = tsf + trig_timeout; 2992 2993 ath_dbg(ath9k_hw_common(ah), HWTIMER, 2994 "current tsf %x period %x timer_next %x\n", 2995 tsf, timer_period, timer_next); 2996 2997 /* 2998 * Program generic timer registers 2999 */ 3000 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3001 timer_next); 3002 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3003 timer_period); 3004 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3005 gen_tmr_configuration[timer->index].mode_mask); 3006 3007 if (AR_SREV_9462(ah)) { 3008 /* 3009 * Starting from AR9462, each generic timer can select which tsf 3010 * to use. But we still follow the old rule, 0 - 7 use tsf and 3011 * 8 - 15 use tsf2. 3012 */ 3013 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3014 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3015 (1 << timer->index)); 3016 else 3017 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3018 (1 << timer->index)); 3019 } 3020 3021 /* Enable both trigger and thresh interrupt masks */ 3022 REG_SET_BIT(ah, AR_IMR_S5, 3023 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3024 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3025} 3026EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3027 3028void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3029{ 3030 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3031 3032 if ((timer->index < AR_FIRST_NDP_TIMER) || 3033 (timer->index >= ATH_MAX_GEN_TIMER)) { 3034 return; 3035 } 3036 3037 /* Clear generic timer enable bits. */ 3038 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3039 gen_tmr_configuration[timer->index].mode_mask); 3040 3041 /* Disable both trigger and thresh interrupt masks */ 3042 REG_CLR_BIT(ah, AR_IMR_S5, 3043 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3044 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3045 3046 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3047} 3048EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3049 3050void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3051{ 3052 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3053 3054 /* free the hardware generic timer slot */ 3055 timer_table->timers[timer->index] = NULL; 3056 kfree(timer); 3057} 3058EXPORT_SYMBOL(ath_gen_timer_free); 3059 3060/* 3061 * Generic Timer Interrupts handling 3062 */ 3063void ath_gen_timer_isr(struct ath_hw *ah) 3064{ 3065 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3066 struct ath_gen_timer *timer; 3067 struct ath_common *common = ath9k_hw_common(ah); 3068 u32 trigger_mask, thresh_mask, index; 3069 3070 /* get hardware generic timer interrupt status */ 3071 trigger_mask = ah->intr_gen_timer_trigger; 3072 thresh_mask = ah->intr_gen_timer_thresh; 3073 trigger_mask &= timer_table->timer_mask.val; 3074 thresh_mask &= timer_table->timer_mask.val; 3075 3076 trigger_mask &= ~thresh_mask; 3077 3078 while (thresh_mask) { 3079 index = rightmost_index(timer_table, &thresh_mask); 3080 timer = timer_table->timers[index]; 3081 BUG_ON(!timer); 3082 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", 3083 index); 3084 timer->overflow(timer->arg); 3085 } 3086 3087 while (trigger_mask) { 3088 index = rightmost_index(timer_table, &trigger_mask); 3089 timer = timer_table->timers[index]; 3090 BUG_ON(!timer); 3091 ath_dbg(common, HWTIMER, 3092 "Gen timer[%d] trigger\n", index); 3093 timer->trigger(timer->arg); 3094 } 3095} 3096EXPORT_SYMBOL(ath_gen_timer_isr); 3097 3098/********/ 3099/* HTC */ 3100/********/ 3101 3102static struct { 3103 u32 version; 3104 const char * name; 3105} ath_mac_bb_names[] = { 3106 /* Devices with external radios */ 3107 { AR_SREV_VERSION_5416_PCI, "5416" }, 3108 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3109 { AR_SREV_VERSION_9100, "9100" }, 3110 { AR_SREV_VERSION_9160, "9160" }, 3111 /* Single-chip solutions */ 3112 { AR_SREV_VERSION_9280, "9280" }, 3113 { AR_SREV_VERSION_9285, "9285" }, 3114 { AR_SREV_VERSION_9287, "9287" }, 3115 { AR_SREV_VERSION_9271, "9271" }, 3116 { AR_SREV_VERSION_9300, "9300" }, 3117 { AR_SREV_VERSION_9330, "9330" }, 3118 { AR_SREV_VERSION_9340, "9340" }, 3119 { AR_SREV_VERSION_9485, "9485" }, 3120 { AR_SREV_VERSION_9462, "9462" }, 3121}; 3122 3123/* For devices with external radios */ 3124static struct { 3125 u16 version; 3126 const char * name; 3127} ath_rf_names[] = { 3128 { 0, "5133" }, 3129 { AR_RAD5133_SREV_MAJOR, "5133" }, 3130 { AR_RAD5122_SREV_MAJOR, "5122" }, 3131 { AR_RAD2133_SREV_MAJOR, "2133" }, 3132 { AR_RAD2122_SREV_MAJOR, "2122" } 3133}; 3134 3135/* 3136 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3137 */ 3138static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3139{ 3140 int i; 3141 3142 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3143 if (ath_mac_bb_names[i].version == mac_bb_version) { 3144 return ath_mac_bb_names[i].name; 3145 } 3146 } 3147 3148 return "????"; 3149} 3150 3151/* 3152 * Return the RF name. "????" is returned if the RF is unknown. 3153 * Used for devices with external radios. 3154 */ 3155static const char *ath9k_hw_rf_name(u16 rf_version) 3156{ 3157 int i; 3158 3159 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3160 if (ath_rf_names[i].version == rf_version) { 3161 return ath_rf_names[i].name; 3162 } 3163 } 3164 3165 return "????"; 3166} 3167 3168void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3169{ 3170 int used; 3171 3172 /* chipsets >= AR9280 are single-chip */ 3173 if (AR_SREV_9280_20_OR_LATER(ah)) { 3174 used = snprintf(hw_name, len, 3175 "Atheros AR%s Rev:%x", 3176 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3177 ah->hw_version.macRev); 3178 } 3179 else { 3180 used = snprintf(hw_name, len, 3181 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3182 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3183 ah->hw_version.macRev, 3184 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3185 AR_RADIO_SREV_MAJOR)), 3186 ah->hw_version.phyRev); 3187 } 3188 3189 hw_name[used] = '\0'; 3190} 3191EXPORT_SYMBOL(ath9k_hw_name); 3192