hw.c revision 3762561aa8afb0bd9fb60d3d847961f9945f8143
1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <asm/unaligned.h> 20 21#include "hw.h" 22#include "hw-ops.h" 23#include "rc.h" 24#include "ar9003_mac.h" 25 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 27 28MODULE_AUTHOR("Atheros Communications"); 29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 31MODULE_LICENSE("Dual BSD/GPL"); 32 33static int __init ath9k_init(void) 34{ 35 return 0; 36} 37module_init(ath9k_init); 38 39static void __exit ath9k_exit(void) 40{ 41 return; 42} 43module_exit(ath9k_exit); 44 45/* Private hardware callbacks */ 46 47static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 48{ 49 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 50} 51 52static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 53{ 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 55} 56 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 58 struct ath9k_channel *chan) 59{ 60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 61} 62 63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 64{ 65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 66 return; 67 68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 69} 70 71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 72{ 73 /* You will not have this callback if using the old ANI */ 74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 75 return; 76 77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 78} 79 80/********************/ 81/* Helper Functions */ 82/********************/ 83 84static void ath9k_hw_set_clockrate(struct ath_hw *ah) 85{ 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 87 struct ath_common *common = ath9k_hw_common(ah); 88 unsigned int clockrate; 89 90 if (!ah->curchan) /* should really check for CCK instead */ 91 clockrate = ATH9K_CLOCK_RATE_CCK; 92 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 96 else 97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 98 99 if (conf_is_ht40(conf)) 100 clockrate *= 2; 101 102 common->clockrate = clockrate; 103} 104 105static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 106{ 107 struct ath_common *common = ath9k_hw_common(ah); 108 109 return usecs * common->clockrate; 110} 111 112bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 113{ 114 int i; 115 116 BUG_ON(timeout < AH_TIME_QUANTUM); 117 118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 119 if ((REG_READ(ah, reg) & mask) == val) 120 return true; 121 122 udelay(AH_TIME_QUANTUM); 123 } 124 125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, 126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 127 timeout, reg, REG_READ(ah, reg), mask, val); 128 129 return false; 130} 131EXPORT_SYMBOL(ath9k_hw_wait); 132 133void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 134 int column, unsigned int *writecnt) 135{ 136 int r; 137 138 ENABLE_REGWRITE_BUFFER(ah); 139 for (r = 0; r < array->ia_rows; r++) { 140 REG_WRITE(ah, INI_RA(array, r, 0), 141 INI_RA(array, r, column)); 142 DO_DELAY(*writecnt); 143 } 144 REGWRITE_BUFFER_FLUSH(ah); 145} 146 147u32 ath9k_hw_reverse_bits(u32 val, u32 n) 148{ 149 u32 retval; 150 int i; 151 152 for (i = 0, retval = 0; i < n; i++) { 153 retval = (retval << 1) | (val & 1); 154 val >>= 1; 155 } 156 return retval; 157} 158 159u16 ath9k_hw_computetxtime(struct ath_hw *ah, 160 u8 phy, int kbps, 161 u32 frameLen, u16 rateix, 162 bool shortPreamble) 163{ 164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 165 166 if (kbps == 0) 167 return 0; 168 169 switch (phy) { 170 case WLAN_RC_PHY_CCK: 171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 172 if (shortPreamble) 173 phyTime >>= 1; 174 numBits = frameLen << 3; 175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 176 break; 177 case WLAN_RC_PHY_OFDM: 178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 180 numBits = OFDM_PLCP_BITS + (frameLen << 3); 181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 182 txTime = OFDM_SIFS_TIME_QUARTER 183 + OFDM_PREAMBLE_TIME_QUARTER 184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 185 } else if (ah->curchan && 186 IS_CHAN_HALF_RATE(ah->curchan)) { 187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 188 numBits = OFDM_PLCP_BITS + (frameLen << 3); 189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 190 txTime = OFDM_SIFS_TIME_HALF + 191 OFDM_PREAMBLE_TIME_HALF 192 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 193 } else { 194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 195 numBits = OFDM_PLCP_BITS + (frameLen << 3); 196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 198 + (numSymbols * OFDM_SYMBOL_TIME); 199 } 200 break; 201 default: 202 ath_err(ath9k_hw_common(ah), 203 "Unknown phy %u (rate ix %u)\n", phy, rateix); 204 txTime = 0; 205 break; 206 } 207 208 return txTime; 209} 210EXPORT_SYMBOL(ath9k_hw_computetxtime); 211 212void ath9k_hw_get_channel_centers(struct ath_hw *ah, 213 struct ath9k_channel *chan, 214 struct chan_centers *centers) 215{ 216 int8_t extoff; 217 218 if (!IS_CHAN_HT40(chan)) { 219 centers->ctl_center = centers->ext_center = 220 centers->synth_center = chan->channel; 221 return; 222 } 223 224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 225 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 226 centers->synth_center = 227 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 228 extoff = 1; 229 } else { 230 centers->synth_center = 231 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 232 extoff = -1; 233 } 234 235 centers->ctl_center = 236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 237 /* 25 MHz spacing is supported by hw but not on upper layers */ 238 centers->ext_center = 239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 240} 241 242/******************/ 243/* Chip Revisions */ 244/******************/ 245 246static void ath9k_hw_read_revisions(struct ath_hw *ah) 247{ 248 u32 val; 249 250 switch (ah->hw_version.devid) { 251 case AR5416_AR9100_DEVID: 252 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 253 break; 254 case AR9300_DEVID_AR9330: 255 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 256 if (ah->get_mac_revision) { 257 ah->hw_version.macRev = ah->get_mac_revision(); 258 } else { 259 val = REG_READ(ah, AR_SREV); 260 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 261 } 262 return; 263 case AR9300_DEVID_AR9340: 264 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 265 val = REG_READ(ah, AR_SREV); 266 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 267 return; 268 } 269 270 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 271 272 if (val == 0xFF) { 273 val = REG_READ(ah, AR_SREV); 274 ah->hw_version.macVersion = 275 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 277 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 278 } else { 279 if (!AR_SREV_9100(ah)) 280 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 281 282 ah->hw_version.macRev = val & AR_SREV_REVISION; 283 284 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 285 ah->is_pciexpress = true; 286 } 287} 288 289/************************************/ 290/* HW Attach, Detach, Init Routines */ 291/************************************/ 292 293static void ath9k_hw_disablepcie(struct ath_hw *ah) 294{ 295 if (!AR_SREV_5416(ah)) 296 return; 297 298 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 299 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 300 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 301 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 302 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 303 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 304 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 305 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 306 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 307 308 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 309} 310 311/* This should work for all families including legacy */ 312static bool ath9k_hw_chip_test(struct ath_hw *ah) 313{ 314 struct ath_common *common = ath9k_hw_common(ah); 315 u32 regAddr[2] = { AR_STA_ID0 }; 316 u32 regHold[2]; 317 static const u32 patternData[4] = { 318 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 319 }; 320 int i, j, loop_max; 321 322 if (!AR_SREV_9300_20_OR_LATER(ah)) { 323 loop_max = 2; 324 regAddr[1] = AR_PHY_BASE + (8 << 2); 325 } else 326 loop_max = 1; 327 328 for (i = 0; i < loop_max; i++) { 329 u32 addr = regAddr[i]; 330 u32 wrData, rdData; 331 332 regHold[i] = REG_READ(ah, addr); 333 for (j = 0; j < 0x100; j++) { 334 wrData = (j << 16) | j; 335 REG_WRITE(ah, addr, wrData); 336 rdData = REG_READ(ah, addr); 337 if (rdData != wrData) { 338 ath_err(common, 339 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 340 addr, wrData, rdData); 341 return false; 342 } 343 } 344 for (j = 0; j < 4; j++) { 345 wrData = patternData[j]; 346 REG_WRITE(ah, addr, wrData); 347 rdData = REG_READ(ah, addr); 348 if (wrData != rdData) { 349 ath_err(common, 350 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 351 addr, wrData, rdData); 352 return false; 353 } 354 } 355 REG_WRITE(ah, regAddr[i], regHold[i]); 356 } 357 udelay(100); 358 359 return true; 360} 361 362static void ath9k_hw_init_config(struct ath_hw *ah) 363{ 364 int i; 365 366 ah->config.dma_beacon_response_time = 2; 367 ah->config.sw_beacon_response_time = 10; 368 ah->config.additional_swba_backoff = 0; 369 ah->config.ack_6mb = 0x0; 370 ah->config.cwm_ignore_extcca = 0; 371 ah->config.pcie_powersave_enable = 0; 372 ah->config.pcie_clock_req = 0; 373 ah->config.pcie_waen = 0; 374 ah->config.analog_shiftreg = 1; 375 ah->config.enable_ani = true; 376 377 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 378 ah->config.spurchans[i][0] = AR_NO_SPUR; 379 ah->config.spurchans[i][1] = AR_NO_SPUR; 380 } 381 382 /* PAPRD needs some more work to be enabled */ 383 ah->config.paprd_disable = 1; 384 385 ah->config.rx_intr_mitigation = true; 386 ah->config.pcieSerDesWrite = true; 387 388 /* 389 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 390 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 391 * This means we use it for all AR5416 devices, and the few 392 * minor PCI AR9280 devices out there. 393 * 394 * Serialization is required because these devices do not handle 395 * well the case of two concurrent reads/writes due to the latency 396 * involved. During one read/write another read/write can be issued 397 * on another CPU while the previous read/write may still be working 398 * on our hardware, if we hit this case the hardware poops in a loop. 399 * We prevent this by serializing reads and writes. 400 * 401 * This issue is not present on PCI-Express devices or pre-AR5416 402 * devices (legacy, 802.11abg). 403 */ 404 if (num_possible_cpus() > 1) 405 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 406} 407 408static void ath9k_hw_init_defaults(struct ath_hw *ah) 409{ 410 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 411 412 regulatory->country_code = CTRY_DEFAULT; 413 regulatory->power_limit = MAX_RATE_POWER; 414 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 415 416 ah->hw_version.magic = AR5416_MAGIC; 417 ah->hw_version.subvendorid = 0; 418 419 ah->atim_window = 0; 420 ah->sta_id1_defaults = 421 AR_STA_ID1_CRPT_MIC_ENABLE | 422 AR_STA_ID1_MCAST_KSRCH; 423 if (AR_SREV_9100(ah)) 424 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 425 ah->enable_32kHz_clock = DONT_USE_32KHZ; 426 ah->slottime = 20; 427 ah->globaltxtimeout = (u32) -1; 428 ah->power_mode = ATH9K_PM_UNDEFINED; 429} 430 431static int ath9k_hw_init_macaddr(struct ath_hw *ah) 432{ 433 struct ath_common *common = ath9k_hw_common(ah); 434 u32 sum; 435 int i; 436 u16 eeval; 437 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 438 439 sum = 0; 440 for (i = 0; i < 3; i++) { 441 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 442 sum += eeval; 443 common->macaddr[2 * i] = eeval >> 8; 444 common->macaddr[2 * i + 1] = eeval & 0xff; 445 } 446 if (sum == 0 || sum == 0xffff * 3) 447 return -EADDRNOTAVAIL; 448 449 return 0; 450} 451 452static int ath9k_hw_post_init(struct ath_hw *ah) 453{ 454 struct ath_common *common = ath9k_hw_common(ah); 455 int ecode; 456 457 if (common->bus_ops->ath_bus_type != ATH_USB) { 458 if (!ath9k_hw_chip_test(ah)) 459 return -ENODEV; 460 } 461 462 if (!AR_SREV_9300_20_OR_LATER(ah)) { 463 ecode = ar9002_hw_rf_claim(ah); 464 if (ecode != 0) 465 return ecode; 466 } 467 468 ecode = ath9k_hw_eeprom_init(ah); 469 if (ecode != 0) 470 return ecode; 471 472 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, 473 "Eeprom VER: %d, REV: %d\n", 474 ah->eep_ops->get_eeprom_ver(ah), 475 ah->eep_ops->get_eeprom_rev(ah)); 476 477 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 478 if (ecode) { 479 ath_err(ath9k_hw_common(ah), 480 "Failed allocating banks for external radio\n"); 481 ath9k_hw_rf_free_ext_banks(ah); 482 return ecode; 483 } 484 485 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) { 486 ath9k_hw_ani_setup(ah); 487 ath9k_hw_ani_init(ah); 488 } 489 490 return 0; 491} 492 493static void ath9k_hw_attach_ops(struct ath_hw *ah) 494{ 495 if (AR_SREV_9300_20_OR_LATER(ah)) 496 ar9003_hw_attach_ops(ah); 497 else 498 ar9002_hw_attach_ops(ah); 499} 500 501/* Called for all hardware families */ 502static int __ath9k_hw_init(struct ath_hw *ah) 503{ 504 struct ath_common *common = ath9k_hw_common(ah); 505 int r = 0; 506 507 ath9k_hw_read_revisions(ah); 508 509 /* 510 * Read back AR_WA into a permanent copy and set bits 14 and 17. 511 * We need to do this to avoid RMW of this register. We cannot 512 * read the reg when chip is asleep. 513 */ 514 ah->WARegVal = REG_READ(ah, AR_WA); 515 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 516 AR_WA_ASPM_TIMER_BASED_DISABLE); 517 518 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 519 ath_err(common, "Couldn't reset chip\n"); 520 return -EIO; 521 } 522 523 ath9k_hw_init_defaults(ah); 524 ath9k_hw_init_config(ah); 525 526 ath9k_hw_attach_ops(ah); 527 528 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 529 ath_err(common, "Couldn't wakeup chip\n"); 530 return -EIO; 531 } 532 533 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 534 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 535 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 536 !ah->is_pciexpress)) { 537 ah->config.serialize_regmode = 538 SER_REG_MODE_ON; 539 } else { 540 ah->config.serialize_regmode = 541 SER_REG_MODE_OFF; 542 } 543 } 544 545 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 546 ah->config.serialize_regmode); 547 548 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 549 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 550 else 551 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 552 553 switch (ah->hw_version.macVersion) { 554 case AR_SREV_VERSION_5416_PCI: 555 case AR_SREV_VERSION_5416_PCIE: 556 case AR_SREV_VERSION_9160: 557 case AR_SREV_VERSION_9100: 558 case AR_SREV_VERSION_9280: 559 case AR_SREV_VERSION_9285: 560 case AR_SREV_VERSION_9287: 561 case AR_SREV_VERSION_9271: 562 case AR_SREV_VERSION_9300: 563 case AR_SREV_VERSION_9330: 564 case AR_SREV_VERSION_9485: 565 case AR_SREV_VERSION_9340: 566 break; 567 default: 568 ath_err(common, 569 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 570 ah->hw_version.macVersion, ah->hw_version.macRev); 571 return -EOPNOTSUPP; 572 } 573 574 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 575 AR_SREV_9330(ah)) 576 ah->is_pciexpress = false; 577 578 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 579 ath9k_hw_init_cal_settings(ah); 580 581 ah->ani_function = ATH9K_ANI_ALL; 582 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 583 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 584 if (!AR_SREV_9300_20_OR_LATER(ah)) 585 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 586 587 ath9k_hw_init_mode_regs(ah); 588 589 590 if (ah->is_pciexpress) 591 ath9k_hw_configpcipowersave(ah, 0, 0); 592 else 593 ath9k_hw_disablepcie(ah); 594 595 if (!AR_SREV_9300_20_OR_LATER(ah)) 596 ar9002_hw_cck_chan14_spread(ah); 597 598 r = ath9k_hw_post_init(ah); 599 if (r) 600 return r; 601 602 ath9k_hw_init_mode_gain_regs(ah); 603 r = ath9k_hw_fill_cap_info(ah); 604 if (r) 605 return r; 606 607 r = ath9k_hw_init_macaddr(ah); 608 if (r) { 609 ath_err(common, "Failed to initialize MAC address\n"); 610 return r; 611 } 612 613 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 614 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 615 else 616 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 617 618 ah->bb_watchdog_timeout_ms = 25; 619 620 common->state = ATH_HW_INITIALIZED; 621 622 return 0; 623} 624 625int ath9k_hw_init(struct ath_hw *ah) 626{ 627 int ret; 628 struct ath_common *common = ath9k_hw_common(ah); 629 630 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 631 switch (ah->hw_version.devid) { 632 case AR5416_DEVID_PCI: 633 case AR5416_DEVID_PCIE: 634 case AR5416_AR9100_DEVID: 635 case AR9160_DEVID_PCI: 636 case AR9280_DEVID_PCI: 637 case AR9280_DEVID_PCIE: 638 case AR9285_DEVID_PCIE: 639 case AR9287_DEVID_PCI: 640 case AR9287_DEVID_PCIE: 641 case AR2427_DEVID_PCIE: 642 case AR9300_DEVID_PCIE: 643 case AR9300_DEVID_AR9485_PCIE: 644 case AR9300_DEVID_AR9340: 645 break; 646 default: 647 if (common->bus_ops->ath_bus_type == ATH_USB) 648 break; 649 ath_err(common, "Hardware device ID 0x%04x not supported\n", 650 ah->hw_version.devid); 651 return -EOPNOTSUPP; 652 } 653 654 ret = __ath9k_hw_init(ah); 655 if (ret) { 656 ath_err(common, 657 "Unable to initialize hardware; initialization status: %d\n", 658 ret); 659 return ret; 660 } 661 662 return 0; 663} 664EXPORT_SYMBOL(ath9k_hw_init); 665 666static void ath9k_hw_init_qos(struct ath_hw *ah) 667{ 668 ENABLE_REGWRITE_BUFFER(ah); 669 670 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 671 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 672 673 REG_WRITE(ah, AR_QOS_NO_ACK, 674 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 675 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 676 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 677 678 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 679 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 680 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 681 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 682 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 683 684 REGWRITE_BUFFER_FLUSH(ah); 685} 686 687u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 688{ 689 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 690 udelay(100); 691 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 692 693 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 694 udelay(100); 695 696 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 697} 698EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 699 700static void ath9k_hw_init_pll(struct ath_hw *ah, 701 struct ath9k_channel *chan) 702{ 703 u32 pll; 704 705 if (AR_SREV_9485(ah)) { 706 707 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 709 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 711 AR_CH0_DPLL2_KD, 0x40); 712 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 713 AR_CH0_DPLL2_KI, 0x4); 714 715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 716 AR_CH0_BB_DPLL1_REFDIV, 0x5); 717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 718 AR_CH0_BB_DPLL1_NINI, 0x58); 719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 720 AR_CH0_BB_DPLL1_NFRAC, 0x0); 721 722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 723 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 725 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 727 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 728 729 /* program BB PLL phase_shift to 0x6 */ 730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 731 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 732 733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 734 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 735 udelay(1000); 736 } else if (AR_SREV_9340(ah)) { 737 u32 regval, pll2_divint, pll2_divfrac, refdiv; 738 739 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 740 udelay(1000); 741 742 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 743 udelay(100); 744 745 if (ah->is_clk_25mhz) { 746 pll2_divint = 0x54; 747 pll2_divfrac = 0x1eb85; 748 refdiv = 3; 749 } else { 750 pll2_divint = 88; 751 pll2_divfrac = 0; 752 refdiv = 5; 753 } 754 755 regval = REG_READ(ah, AR_PHY_PLL_MODE); 756 regval |= (0x1 << 16); 757 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 758 udelay(100); 759 760 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 761 (pll2_divint << 18) | pll2_divfrac); 762 udelay(100); 763 764 regval = REG_READ(ah, AR_PHY_PLL_MODE); 765 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 766 (0x4 << 26) | (0x18 << 19); 767 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 768 REG_WRITE(ah, AR_PHY_PLL_MODE, 769 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 770 udelay(1000); 771 } 772 773 pll = ath9k_hw_compute_pll_control(ah, chan); 774 775 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 776 777 if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) 778 udelay(1000); 779 780 /* Switch the core clock for ar9271 to 117Mhz */ 781 if (AR_SREV_9271(ah)) { 782 udelay(500); 783 REG_WRITE(ah, 0x50040, 0x304); 784 } 785 786 udelay(RTC_PLL_SETTLE_DELAY); 787 788 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 789 790 if (AR_SREV_9340(ah)) { 791 if (ah->is_clk_25mhz) { 792 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 793 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 794 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 795 } else { 796 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 797 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 798 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 799 } 800 udelay(100); 801 } 802} 803 804static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 805 enum nl80211_iftype opmode) 806{ 807 u32 sync_default = AR_INTR_SYNC_DEFAULT; 808 u32 imr_reg = AR_IMR_TXERR | 809 AR_IMR_TXURN | 810 AR_IMR_RXERR | 811 AR_IMR_RXORN | 812 AR_IMR_BCNMISC; 813 814 if (AR_SREV_9340(ah)) 815 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 816 817 if (AR_SREV_9300_20_OR_LATER(ah)) { 818 imr_reg |= AR_IMR_RXOK_HP; 819 if (ah->config.rx_intr_mitigation) 820 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 821 else 822 imr_reg |= AR_IMR_RXOK_LP; 823 824 } else { 825 if (ah->config.rx_intr_mitigation) 826 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 827 else 828 imr_reg |= AR_IMR_RXOK; 829 } 830 831 if (ah->config.tx_intr_mitigation) 832 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 833 else 834 imr_reg |= AR_IMR_TXOK; 835 836 if (opmode == NL80211_IFTYPE_AP) 837 imr_reg |= AR_IMR_MIB; 838 839 ENABLE_REGWRITE_BUFFER(ah); 840 841 REG_WRITE(ah, AR_IMR, imr_reg); 842 ah->imrs2_reg |= AR_IMR_S2_GTT; 843 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 844 845 if (!AR_SREV_9100(ah)) { 846 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 847 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 848 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 849 } 850 851 REGWRITE_BUFFER_FLUSH(ah); 852 853 if (AR_SREV_9300_20_OR_LATER(ah)) { 854 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 855 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 856 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 857 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 858 } 859} 860 861static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 862{ 863 u32 val = ath9k_hw_mac_to_clks(ah, us); 864 val = min(val, (u32) 0xFFFF); 865 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 866} 867 868static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 869{ 870 u32 val = ath9k_hw_mac_to_clks(ah, us); 871 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 872 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 873} 874 875static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 876{ 877 u32 val = ath9k_hw_mac_to_clks(ah, us); 878 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 879 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 880} 881 882static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 883{ 884 if (tu > 0xFFFF) { 885 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 886 "bad global tx timeout %u\n", tu); 887 ah->globaltxtimeout = (u32) -1; 888 return false; 889 } else { 890 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 891 ah->globaltxtimeout = tu; 892 return true; 893 } 894} 895 896void ath9k_hw_init_global_settings(struct ath_hw *ah) 897{ 898 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 899 int acktimeout; 900 int slottime; 901 int sifstime; 902 903 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 904 ah->misc_mode); 905 906 if (ah->misc_mode != 0) 907 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 908 909 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 910 sifstime = 16; 911 else 912 sifstime = 10; 913 914 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 915 slottime = ah->slottime + 3 * ah->coverage_class; 916 acktimeout = slottime + sifstime; 917 918 /* 919 * Workaround for early ACK timeouts, add an offset to match the 920 * initval's 64us ack timeout value. 921 * This was initially only meant to work around an issue with delayed 922 * BA frames in some implementations, but it has been found to fix ACK 923 * timeout issues in other cases as well. 924 */ 925 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 926 acktimeout += 64 - sifstime - ah->slottime; 927 928 ath9k_hw_setslottime(ah, ah->slottime); 929 ath9k_hw_set_ack_timeout(ah, acktimeout); 930 ath9k_hw_set_cts_timeout(ah, acktimeout); 931 if (ah->globaltxtimeout != (u32) -1) 932 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 933} 934EXPORT_SYMBOL(ath9k_hw_init_global_settings); 935 936void ath9k_hw_deinit(struct ath_hw *ah) 937{ 938 struct ath_common *common = ath9k_hw_common(ah); 939 940 if (common->state < ATH_HW_INITIALIZED) 941 goto free_hw; 942 943 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 944 945free_hw: 946 ath9k_hw_rf_free_ext_banks(ah); 947} 948EXPORT_SYMBOL(ath9k_hw_deinit); 949 950/*******/ 951/* INI */ 952/*******/ 953 954u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 955{ 956 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 957 958 if (IS_CHAN_B(chan)) 959 ctl |= CTL_11B; 960 else if (IS_CHAN_G(chan)) 961 ctl |= CTL_11G; 962 else 963 ctl |= CTL_11A; 964 965 return ctl; 966} 967 968/****************************************/ 969/* Reset and Channel Switching Routines */ 970/****************************************/ 971 972static inline void ath9k_hw_set_dma(struct ath_hw *ah) 973{ 974 struct ath_common *common = ath9k_hw_common(ah); 975 976 ENABLE_REGWRITE_BUFFER(ah); 977 978 /* 979 * set AHB_MODE not to do cacheline prefetches 980 */ 981 if (!AR_SREV_9300_20_OR_LATER(ah)) 982 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 983 984 /* 985 * let mac dma reads be in 128 byte chunks 986 */ 987 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 988 989 REGWRITE_BUFFER_FLUSH(ah); 990 991 /* 992 * Restore TX Trigger Level to its pre-reset value. 993 * The initial value depends on whether aggregation is enabled, and is 994 * adjusted whenever underruns are detected. 995 */ 996 if (!AR_SREV_9300_20_OR_LATER(ah)) 997 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 998 999 ENABLE_REGWRITE_BUFFER(ah); 1000 1001 /* 1002 * let mac dma writes be in 128 byte chunks 1003 */ 1004 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1005 1006 /* 1007 * Setup receive FIFO threshold to hold off TX activities 1008 */ 1009 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1010 1011 if (AR_SREV_9300_20_OR_LATER(ah)) { 1012 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1013 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1014 1015 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1016 ah->caps.rx_status_len); 1017 } 1018 1019 /* 1020 * reduce the number of usable entries in PCU TXBUF to avoid 1021 * wrap around issues. 1022 */ 1023 if (AR_SREV_9285(ah)) { 1024 /* For AR9285 the number of Fifos are reduced to half. 1025 * So set the usable tx buf size also to half to 1026 * avoid data/delimiter underruns 1027 */ 1028 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1029 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1030 } else if (!AR_SREV_9271(ah)) { 1031 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1032 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1033 } 1034 1035 REGWRITE_BUFFER_FLUSH(ah); 1036 1037 if (AR_SREV_9300_20_OR_LATER(ah)) 1038 ath9k_hw_reset_txstatus_ring(ah); 1039} 1040 1041static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1042{ 1043 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1044 u32 set = AR_STA_ID1_KSRCH_MODE; 1045 1046 switch (opmode) { 1047 case NL80211_IFTYPE_ADHOC: 1048 case NL80211_IFTYPE_MESH_POINT: 1049 set |= AR_STA_ID1_ADHOC; 1050 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1051 break; 1052 case NL80211_IFTYPE_AP: 1053 set |= AR_STA_ID1_STA_AP; 1054 /* fall through */ 1055 case NL80211_IFTYPE_STATION: 1056 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1057 break; 1058 default: 1059 if (!ah->is_monitoring) 1060 set = 0; 1061 break; 1062 } 1063 REG_RMW(ah, AR_STA_ID1, set, mask); 1064} 1065 1066void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1067 u32 *coef_mantissa, u32 *coef_exponent) 1068{ 1069 u32 coef_exp, coef_man; 1070 1071 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1072 if ((coef_scaled >> coef_exp) & 0x1) 1073 break; 1074 1075 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1076 1077 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1078 1079 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1080 *coef_exponent = coef_exp - 16; 1081} 1082 1083static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1084{ 1085 u32 rst_flags; 1086 u32 tmpReg; 1087 1088 if (AR_SREV_9100(ah)) { 1089 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1090 AR_RTC_DERIVED_CLK_PERIOD, 1); 1091 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1092 } 1093 1094 ENABLE_REGWRITE_BUFFER(ah); 1095 1096 if (AR_SREV_9300_20_OR_LATER(ah)) { 1097 REG_WRITE(ah, AR_WA, ah->WARegVal); 1098 udelay(10); 1099 } 1100 1101 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1102 AR_RTC_FORCE_WAKE_ON_INT); 1103 1104 if (AR_SREV_9100(ah)) { 1105 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1106 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1107 } else { 1108 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1109 if (tmpReg & 1110 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1111 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1112 u32 val; 1113 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1114 1115 val = AR_RC_HOSTIF; 1116 if (!AR_SREV_9300_20_OR_LATER(ah)) 1117 val |= AR_RC_AHB; 1118 REG_WRITE(ah, AR_RC, val); 1119 1120 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1121 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1122 1123 rst_flags = AR_RTC_RC_MAC_WARM; 1124 if (type == ATH9K_RESET_COLD) 1125 rst_flags |= AR_RTC_RC_MAC_COLD; 1126 } 1127 1128 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1129 1130 REGWRITE_BUFFER_FLUSH(ah); 1131 1132 udelay(50); 1133 1134 REG_WRITE(ah, AR_RTC_RC, 0); 1135 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1136 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1137 "RTC stuck in MAC reset\n"); 1138 return false; 1139 } 1140 1141 if (!AR_SREV_9100(ah)) 1142 REG_WRITE(ah, AR_RC, 0); 1143 1144 if (AR_SREV_9100(ah)) 1145 udelay(50); 1146 1147 return true; 1148} 1149 1150static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1151{ 1152 ENABLE_REGWRITE_BUFFER(ah); 1153 1154 if (AR_SREV_9300_20_OR_LATER(ah)) { 1155 REG_WRITE(ah, AR_WA, ah->WARegVal); 1156 udelay(10); 1157 } 1158 1159 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1160 AR_RTC_FORCE_WAKE_ON_INT); 1161 1162 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1163 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1164 1165 REG_WRITE(ah, AR_RTC_RESET, 0); 1166 1167 REGWRITE_BUFFER_FLUSH(ah); 1168 1169 if (!AR_SREV_9300_20_OR_LATER(ah)) 1170 udelay(2); 1171 1172 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1173 REG_WRITE(ah, AR_RC, 0); 1174 1175 REG_WRITE(ah, AR_RTC_RESET, 1); 1176 1177 if (!ath9k_hw_wait(ah, 1178 AR_RTC_STATUS, 1179 AR_RTC_STATUS_M, 1180 AR_RTC_STATUS_ON, 1181 AH_WAIT_TIMEOUT)) { 1182 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1183 "RTC not waking up\n"); 1184 return false; 1185 } 1186 1187 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1188} 1189 1190static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1191{ 1192 if (AR_SREV_9300_20_OR_LATER(ah)) { 1193 REG_WRITE(ah, AR_WA, ah->WARegVal); 1194 udelay(10); 1195 } 1196 1197 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1198 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1199 1200 switch (type) { 1201 case ATH9K_RESET_POWER_ON: 1202 return ath9k_hw_set_reset_power_on(ah); 1203 case ATH9K_RESET_WARM: 1204 case ATH9K_RESET_COLD: 1205 return ath9k_hw_set_reset(ah, type); 1206 default: 1207 return false; 1208 } 1209} 1210 1211static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1212 struct ath9k_channel *chan) 1213{ 1214 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1215 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1216 return false; 1217 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1218 return false; 1219 1220 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1221 return false; 1222 1223 ah->chip_fullsleep = false; 1224 ath9k_hw_init_pll(ah, chan); 1225 ath9k_hw_set_rfmode(ah, chan); 1226 1227 return true; 1228} 1229 1230static bool ath9k_hw_channel_change(struct ath_hw *ah, 1231 struct ath9k_channel *chan) 1232{ 1233 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1234 struct ath_common *common = ath9k_hw_common(ah); 1235 struct ieee80211_channel *channel = chan->chan; 1236 u32 qnum; 1237 int r; 1238 1239 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1240 if (ath9k_hw_numtxpending(ah, qnum)) { 1241 ath_dbg(common, ATH_DBG_QUEUE, 1242 "Transmit frames pending on queue %d\n", qnum); 1243 return false; 1244 } 1245 } 1246 1247 if (!ath9k_hw_rfbus_req(ah)) { 1248 ath_err(common, "Could not kill baseband RX\n"); 1249 return false; 1250 } 1251 1252 ath9k_hw_set_channel_regs(ah, chan); 1253 1254 r = ath9k_hw_rf_set_freq(ah, chan); 1255 if (r) { 1256 ath_err(common, "Failed to set channel\n"); 1257 return false; 1258 } 1259 ath9k_hw_set_clockrate(ah); 1260 1261 ah->eep_ops->set_txpower(ah, chan, 1262 ath9k_regd_get_ctl(regulatory, chan), 1263 channel->max_antenna_gain * 2, 1264 channel->max_power * 2, 1265 min((u32) MAX_RATE_POWER, 1266 (u32) regulatory->power_limit), false); 1267 1268 ath9k_hw_rfbus_done(ah); 1269 1270 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1271 ath9k_hw_set_delta_slope(ah, chan); 1272 1273 ath9k_hw_spur_mitigate_freq(ah, chan); 1274 1275 return true; 1276} 1277 1278static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1279{ 1280 u32 gpio_mask = ah->gpio_mask; 1281 int i; 1282 1283 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1284 if (!(gpio_mask & 1)) 1285 continue; 1286 1287 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1288 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1289 } 1290} 1291 1292bool ath9k_hw_check_alive(struct ath_hw *ah) 1293{ 1294 int count = 50; 1295 u32 reg; 1296 1297 if (AR_SREV_9285_12_OR_LATER(ah)) 1298 return true; 1299 1300 do { 1301 reg = REG_READ(ah, AR_OBS_BUS_1); 1302 1303 if ((reg & 0x7E7FFFEF) == 0x00702400) 1304 continue; 1305 1306 switch (reg & 0x7E000B00) { 1307 case 0x1E000000: 1308 case 0x52000B00: 1309 case 0x18000B00: 1310 continue; 1311 default: 1312 return true; 1313 } 1314 } while (count-- > 0); 1315 1316 return false; 1317} 1318EXPORT_SYMBOL(ath9k_hw_check_alive); 1319 1320int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1321 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1322{ 1323 struct ath_common *common = ath9k_hw_common(ah); 1324 u32 saveLedState; 1325 struct ath9k_channel *curchan = ah->curchan; 1326 u32 saveDefAntenna; 1327 u32 macStaId1; 1328 u64 tsf = 0; 1329 int i, r; 1330 1331 ah->txchainmask = common->tx_chainmask; 1332 ah->rxchainmask = common->rx_chainmask; 1333 1334 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1335 return -EIO; 1336 1337 if (curchan && !ah->chip_fullsleep) 1338 ath9k_hw_getnf(ah, curchan); 1339 1340 ah->caldata = caldata; 1341 if (caldata && 1342 (chan->channel != caldata->channel || 1343 (chan->channelFlags & ~CHANNEL_CW_INT) != 1344 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1345 /* Operating channel changed, reset channel calibration data */ 1346 memset(caldata, 0, sizeof(*caldata)); 1347 ath9k_init_nfcal_hist_buffer(ah, chan); 1348 } 1349 1350 if (bChannelChange && 1351 (ah->chip_fullsleep != true) && 1352 (ah->curchan != NULL) && 1353 (chan->channel != ah->curchan->channel) && 1354 ((chan->channelFlags & CHANNEL_ALL) == 1355 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1356 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { 1357 1358 if (ath9k_hw_channel_change(ah, chan)) { 1359 ath9k_hw_loadnf(ah, ah->curchan); 1360 ath9k_hw_start_nfcal(ah, true); 1361 if (AR_SREV_9271(ah)) 1362 ar9002_hw_load_ani_reg(ah, chan); 1363 return 0; 1364 } 1365 } 1366 1367 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1368 if (saveDefAntenna == 0) 1369 saveDefAntenna = 1; 1370 1371 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1372 1373 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1374 if (AR_SREV_9100(ah) || 1375 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1376 tsf = ath9k_hw_gettsf64(ah); 1377 1378 saveLedState = REG_READ(ah, AR_CFG_LED) & 1379 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1380 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1381 1382 ath9k_hw_mark_phy_inactive(ah); 1383 1384 ah->paprd_table_write_done = false; 1385 1386 /* Only required on the first reset */ 1387 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1388 REG_WRITE(ah, 1389 AR9271_RESET_POWER_DOWN_CONTROL, 1390 AR9271_RADIO_RF_RST); 1391 udelay(50); 1392 } 1393 1394 if (!ath9k_hw_chip_reset(ah, chan)) { 1395 ath_err(common, "Chip reset failed\n"); 1396 return -EINVAL; 1397 } 1398 1399 /* Only required on the first reset */ 1400 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1401 ah->htc_reset_init = false; 1402 REG_WRITE(ah, 1403 AR9271_RESET_POWER_DOWN_CONTROL, 1404 AR9271_GATE_MAC_CTL); 1405 udelay(50); 1406 } 1407 1408 /* Restore TSF */ 1409 if (tsf) 1410 ath9k_hw_settsf64(ah, tsf); 1411 1412 if (AR_SREV_9280_20_OR_LATER(ah)) 1413 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1414 1415 if (!AR_SREV_9300_20_OR_LATER(ah)) 1416 ar9002_hw_enable_async_fifo(ah); 1417 1418 r = ath9k_hw_process_ini(ah, chan); 1419 if (r) 1420 return r; 1421 1422 /* 1423 * Some AR91xx SoC devices frequently fail to accept TSF writes 1424 * right after the chip reset. When that happens, write a new 1425 * value after the initvals have been applied, with an offset 1426 * based on measured time difference 1427 */ 1428 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1429 tsf += 1500; 1430 ath9k_hw_settsf64(ah, tsf); 1431 } 1432 1433 /* Setup MFP options for CCMP */ 1434 if (AR_SREV_9280_20_OR_LATER(ah)) { 1435 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1436 * frames when constructing CCMP AAD. */ 1437 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1438 0xc7ff); 1439 ah->sw_mgmt_crypto = false; 1440 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1441 /* Disable hardware crypto for management frames */ 1442 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1443 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1444 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1445 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1446 ah->sw_mgmt_crypto = true; 1447 } else 1448 ah->sw_mgmt_crypto = true; 1449 1450 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1451 ath9k_hw_set_delta_slope(ah, chan); 1452 1453 ath9k_hw_spur_mitigate_freq(ah, chan); 1454 ah->eep_ops->set_board_values(ah, chan); 1455 1456 ENABLE_REGWRITE_BUFFER(ah); 1457 1458 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1459 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1460 | macStaId1 1461 | AR_STA_ID1_RTS_USE_DEF 1462 | (ah->config. 1463 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1464 | ah->sta_id1_defaults); 1465 ath_hw_setbssidmask(common); 1466 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1467 ath9k_hw_write_associd(ah); 1468 REG_WRITE(ah, AR_ISR, ~0); 1469 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1470 1471 REGWRITE_BUFFER_FLUSH(ah); 1472 1473 ath9k_hw_set_operating_mode(ah, ah->opmode); 1474 1475 r = ath9k_hw_rf_set_freq(ah, chan); 1476 if (r) 1477 return r; 1478 1479 ath9k_hw_set_clockrate(ah); 1480 1481 ENABLE_REGWRITE_BUFFER(ah); 1482 1483 for (i = 0; i < AR_NUM_DCU; i++) 1484 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1485 1486 REGWRITE_BUFFER_FLUSH(ah); 1487 1488 ah->intr_txqs = 0; 1489 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1490 ath9k_hw_resettxqueue(ah, i); 1491 1492 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1493 ath9k_hw_ani_cache_ini_regs(ah); 1494 ath9k_hw_init_qos(ah); 1495 1496 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1497 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1498 1499 ath9k_hw_init_global_settings(ah); 1500 1501 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1502 ar9002_hw_update_async_fifo(ah); 1503 ar9002_hw_enable_wep_aggregation(ah); 1504 } 1505 1506 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1507 1508 ath9k_hw_set_dma(ah); 1509 1510 REG_WRITE(ah, AR_OBS, 8); 1511 1512 if (ah->config.rx_intr_mitigation) { 1513 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1514 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1515 } 1516 1517 if (ah->config.tx_intr_mitigation) { 1518 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1519 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1520 } 1521 1522 ath9k_hw_init_bb(ah, chan); 1523 1524 if (!ath9k_hw_init_cal(ah, chan)) 1525 return -EIO; 1526 1527 ENABLE_REGWRITE_BUFFER(ah); 1528 1529 ath9k_hw_restore_chainmask(ah); 1530 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1531 1532 REGWRITE_BUFFER_FLUSH(ah); 1533 1534 /* 1535 * For big endian systems turn on swapping for descriptors 1536 */ 1537 if (AR_SREV_9100(ah)) { 1538 u32 mask; 1539 mask = REG_READ(ah, AR_CFG); 1540 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1541 ath_dbg(common, ATH_DBG_RESET, 1542 "CFG Byte Swap Set 0x%x\n", mask); 1543 } else { 1544 mask = 1545 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1546 REG_WRITE(ah, AR_CFG, mask); 1547 ath_dbg(common, ATH_DBG_RESET, 1548 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1549 } 1550 } else { 1551 if (common->bus_ops->ath_bus_type == ATH_USB) { 1552 /* Configure AR9271 target WLAN */ 1553 if (AR_SREV_9271(ah)) 1554 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1555 else 1556 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1557 } 1558#ifdef __BIG_ENDIAN 1559 else if (AR_SREV_9340(ah)) 1560 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1561 else 1562 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1563#endif 1564 } 1565 1566 if (ah->btcoex_hw.enabled) 1567 ath9k_hw_btcoex_enable(ah); 1568 1569 if (AR_SREV_9300_20_OR_LATER(ah)) { 1570 ar9003_hw_bb_watchdog_config(ah); 1571 1572 ar9003_hw_disable_phy_restart(ah); 1573 } 1574 1575 ath9k_hw_apply_gpio_override(ah); 1576 1577 return 0; 1578} 1579EXPORT_SYMBOL(ath9k_hw_reset); 1580 1581/******************************/ 1582/* Power Management (Chipset) */ 1583/******************************/ 1584 1585/* 1586 * Notify Power Mgt is disabled in self-generated frames. 1587 * If requested, force chip to sleep. 1588 */ 1589static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1590{ 1591 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1592 if (setChip) { 1593 /* 1594 * Clear the RTC force wake bit to allow the 1595 * mac to go to sleep. 1596 */ 1597 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1598 AR_RTC_FORCE_WAKE_EN); 1599 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1600 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1601 1602 /* Shutdown chip. Active low */ 1603 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1604 REG_CLR_BIT(ah, (AR_RTC_RESET), 1605 AR_RTC_RESET_EN); 1606 } 1607 1608 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1609 if (AR_SREV_9300_20_OR_LATER(ah)) 1610 REG_WRITE(ah, AR_WA, 1611 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1612} 1613 1614/* 1615 * Notify Power Management is enabled in self-generating 1616 * frames. If request, set power mode of chip to 1617 * auto/normal. Duration in units of 128us (1/8 TU). 1618 */ 1619static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1620{ 1621 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1622 if (setChip) { 1623 struct ath9k_hw_capabilities *pCap = &ah->caps; 1624 1625 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1626 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1627 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1628 AR_RTC_FORCE_WAKE_ON_INT); 1629 } else { 1630 /* 1631 * Clear the RTC force wake bit to allow the 1632 * mac to go to sleep. 1633 */ 1634 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1635 AR_RTC_FORCE_WAKE_EN); 1636 } 1637 } 1638 1639 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1640 if (AR_SREV_9300_20_OR_LATER(ah)) 1641 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1642} 1643 1644static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1645{ 1646 u32 val; 1647 int i; 1648 1649 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1650 if (AR_SREV_9300_20_OR_LATER(ah)) { 1651 REG_WRITE(ah, AR_WA, ah->WARegVal); 1652 udelay(10); 1653 } 1654 1655 if (setChip) { 1656 if ((REG_READ(ah, AR_RTC_STATUS) & 1657 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1658 if (ath9k_hw_set_reset_reg(ah, 1659 ATH9K_RESET_POWER_ON) != true) { 1660 return false; 1661 } 1662 if (!AR_SREV_9300_20_OR_LATER(ah)) 1663 ath9k_hw_init_pll(ah, NULL); 1664 } 1665 if (AR_SREV_9100(ah)) 1666 REG_SET_BIT(ah, AR_RTC_RESET, 1667 AR_RTC_RESET_EN); 1668 1669 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1670 AR_RTC_FORCE_WAKE_EN); 1671 udelay(50); 1672 1673 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1674 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1675 if (val == AR_RTC_STATUS_ON) 1676 break; 1677 udelay(50); 1678 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1679 AR_RTC_FORCE_WAKE_EN); 1680 } 1681 if (i == 0) { 1682 ath_err(ath9k_hw_common(ah), 1683 "Failed to wakeup in %uus\n", 1684 POWER_UP_TIME / 20); 1685 return false; 1686 } 1687 } 1688 1689 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1690 1691 return true; 1692} 1693 1694bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1695{ 1696 struct ath_common *common = ath9k_hw_common(ah); 1697 int status = true, setChip = true; 1698 static const char *modes[] = { 1699 "AWAKE", 1700 "FULL-SLEEP", 1701 "NETWORK SLEEP", 1702 "UNDEFINED" 1703 }; 1704 1705 if (ah->power_mode == mode) 1706 return status; 1707 1708 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", 1709 modes[ah->power_mode], modes[mode]); 1710 1711 switch (mode) { 1712 case ATH9K_PM_AWAKE: 1713 status = ath9k_hw_set_power_awake(ah, setChip); 1714 break; 1715 case ATH9K_PM_FULL_SLEEP: 1716 ath9k_set_power_sleep(ah, setChip); 1717 ah->chip_fullsleep = true; 1718 break; 1719 case ATH9K_PM_NETWORK_SLEEP: 1720 ath9k_set_power_network_sleep(ah, setChip); 1721 break; 1722 default: 1723 ath_err(common, "Unknown power mode %u\n", mode); 1724 return false; 1725 } 1726 ah->power_mode = mode; 1727 1728 /* 1729 * XXX: If this warning never comes up after a while then 1730 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 1731 * ath9k_hw_setpower() return type void. 1732 */ 1733 1734 if (!(ah->ah_flags & AH_UNPLUGGED)) 1735 ATH_DBG_WARN_ON_ONCE(!status); 1736 1737 return status; 1738} 1739EXPORT_SYMBOL(ath9k_hw_setpower); 1740 1741/*******************/ 1742/* Beacon Handling */ 1743/*******************/ 1744 1745void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1746{ 1747 int flags = 0; 1748 1749 ENABLE_REGWRITE_BUFFER(ah); 1750 1751 switch (ah->opmode) { 1752 case NL80211_IFTYPE_ADHOC: 1753 case NL80211_IFTYPE_MESH_POINT: 1754 REG_SET_BIT(ah, AR_TXCFG, 1755 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1756 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 1757 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 1758 flags |= AR_NDP_TIMER_EN; 1759 case NL80211_IFTYPE_AP: 1760 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 1761 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 1762 TU_TO_USEC(ah->config.dma_beacon_response_time)); 1763 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 1764 TU_TO_USEC(ah->config.sw_beacon_response_time)); 1765 flags |= 1766 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1767 break; 1768 default: 1769 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, 1770 "%s: unsupported opmode: %d\n", 1771 __func__, ah->opmode); 1772 return; 1773 break; 1774 } 1775 1776 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 1777 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 1778 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 1779 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 1780 1781 REGWRITE_BUFFER_FLUSH(ah); 1782 1783 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1784} 1785EXPORT_SYMBOL(ath9k_hw_beaconinit); 1786 1787void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1788 const struct ath9k_beacon_state *bs) 1789{ 1790 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 1791 struct ath9k_hw_capabilities *pCap = &ah->caps; 1792 struct ath_common *common = ath9k_hw_common(ah); 1793 1794 ENABLE_REGWRITE_BUFFER(ah); 1795 1796 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1797 1798 REG_WRITE(ah, AR_BEACON_PERIOD, 1799 TU_TO_USEC(bs->bs_intval)); 1800 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1801 TU_TO_USEC(bs->bs_intval)); 1802 1803 REGWRITE_BUFFER_FLUSH(ah); 1804 1805 REG_RMW_FIELD(ah, AR_RSSI_THR, 1806 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1807 1808 beaconintval = bs->bs_intval; 1809 1810 if (bs->bs_sleepduration > beaconintval) 1811 beaconintval = bs->bs_sleepduration; 1812 1813 dtimperiod = bs->bs_dtimperiod; 1814 if (bs->bs_sleepduration > dtimperiod) 1815 dtimperiod = bs->bs_sleepduration; 1816 1817 if (beaconintval == dtimperiod) 1818 nextTbtt = bs->bs_nextdtim; 1819 else 1820 nextTbtt = bs->bs_nexttbtt; 1821 1822 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 1823 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 1824 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1825 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1826 1827 ENABLE_REGWRITE_BUFFER(ah); 1828 1829 REG_WRITE(ah, AR_NEXT_DTIM, 1830 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 1831 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 1832 1833 REG_WRITE(ah, AR_SLEEP1, 1834 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 1835 | AR_SLEEP1_ASSUME_DTIM); 1836 1837 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 1838 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 1839 else 1840 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 1841 1842 REG_WRITE(ah, AR_SLEEP2, 1843 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 1844 1845 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 1846 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1847 1848 REGWRITE_BUFFER_FLUSH(ah); 1849 1850 REG_SET_BIT(ah, AR_TIMER_MODE, 1851 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1852 AR_DTIM_TIMER_EN); 1853 1854 /* TSF Out of Range Threshold */ 1855 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 1856} 1857EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 1858 1859/*******************/ 1860/* HW Capabilities */ 1861/*******************/ 1862 1863int ath9k_hw_fill_cap_info(struct ath_hw *ah) 1864{ 1865 struct ath9k_hw_capabilities *pCap = &ah->caps; 1866 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1867 struct ath_common *common = ath9k_hw_common(ah); 1868 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 1869 1870 u16 eeval; 1871 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 1872 1873 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 1874 regulatory->current_rd = eeval; 1875 1876 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 1877 if (AR_SREV_9285_12_OR_LATER(ah)) 1878 eeval |= AR9285_RDEXT_DEFAULT; 1879 regulatory->current_rd_ext = eeval; 1880 1881 if (ah->opmode != NL80211_IFTYPE_AP && 1882 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 1883 if (regulatory->current_rd == 0x64 || 1884 regulatory->current_rd == 0x65) 1885 regulatory->current_rd += 5; 1886 else if (regulatory->current_rd == 0x41) 1887 regulatory->current_rd = 0x43; 1888 ath_dbg(common, ATH_DBG_REGULATORY, 1889 "regdomain mapped to 0x%x\n", regulatory->current_rd); 1890 } 1891 1892 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 1893 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 1894 ath_err(common, 1895 "no band has been marked as supported in EEPROM\n"); 1896 return -EINVAL; 1897 } 1898 1899 if (eeval & AR5416_OPFLAGS_11A) 1900 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 1901 1902 if (eeval & AR5416_OPFLAGS_11G) 1903 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 1904 1905 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 1906 /* 1907 * For AR9271 we will temporarilly uses the rx chainmax as read from 1908 * the EEPROM. 1909 */ 1910 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 1911 !(eeval & AR5416_OPFLAGS_11A) && 1912 !(AR_SREV_9271(ah))) 1913 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 1914 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 1915 else if (AR_SREV_9100(ah)) 1916 pCap->rx_chainmask = 0x7; 1917 else 1918 /* Use rx_chainmask from EEPROM. */ 1919 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 1920 1921 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 1922 1923 /* enable key search for every frame in an aggregate */ 1924 if (AR_SREV_9300_20_OR_LATER(ah)) 1925 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 1926 1927 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 1928 1929 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 1930 pCap->hw_caps |= ATH9K_HW_CAP_HT; 1931 else 1932 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 1933 1934 if (AR_SREV_9271(ah)) 1935 pCap->num_gpio_pins = AR9271_NUM_GPIO; 1936 else if (AR_DEVID_7010(ah)) 1937 pCap->num_gpio_pins = AR7010_NUM_GPIO; 1938 else if (AR_SREV_9285_12_OR_LATER(ah)) 1939 pCap->num_gpio_pins = AR9285_NUM_GPIO; 1940 else if (AR_SREV_9280_20_OR_LATER(ah)) 1941 pCap->num_gpio_pins = AR928X_NUM_GPIO; 1942 else 1943 pCap->num_gpio_pins = AR_NUM_GPIO; 1944 1945 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 1946 pCap->hw_caps |= ATH9K_HW_CAP_CST; 1947 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 1948 } else { 1949 pCap->rts_aggr_limit = (8 * 1024); 1950 } 1951 1952#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1953 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 1954 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 1955 ah->rfkill_gpio = 1956 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 1957 ah->rfkill_polarity = 1958 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 1959 1960 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 1961 } 1962#endif 1963 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 1964 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 1965 else 1966 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 1967 1968 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 1969 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 1970 else 1971 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 1972 1973 if (common->btcoex_enabled) { 1974 if (AR_SREV_9300_20_OR_LATER(ah)) { 1975 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 1976 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300; 1977 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300; 1978 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300; 1979 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 1980 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280; 1981 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280; 1982 1983 if (AR_SREV_9285(ah)) { 1984 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 1985 btcoex_hw->btpriority_gpio = 1986 ATH_BTPRIORITY_GPIO_9285; 1987 } else { 1988 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 1989 } 1990 } 1991 } else { 1992 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 1993 } 1994 1995 if (AR_SREV_9300_20_OR_LATER(ah)) { 1996 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 1997 if (!AR_SREV_9485(ah)) 1998 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 1999 2000 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2001 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2002 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2003 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2004 pCap->txs_len = sizeof(struct ar9003_txs); 2005 if (!ah->config.paprd_disable && 2006 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2007 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2008 } else { 2009 pCap->tx_desc_len = sizeof(struct ath_desc); 2010 if (AR_SREV_9280_20(ah) && 2011 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= 2012 AR5416_EEP_MINOR_VER_16) || 2013 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) 2014 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2015 } 2016 2017 if (AR_SREV_9300_20_OR_LATER(ah)) 2018 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2019 2020 if (AR_SREV_9300_20_OR_LATER(ah)) 2021 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2022 2023 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2024 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2025 2026 if (AR_SREV_9285(ah)) 2027 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2028 ant_div_ctl1 = 2029 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2030 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2031 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2032 } 2033 if (AR_SREV_9300_20_OR_LATER(ah)) { 2034 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2035 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2036 } 2037 2038 2039 if (AR_SREV_9485(ah)) { 2040 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2041 /* 2042 * enable the diversity-combining algorithm only when 2043 * both enable_lna_div and enable_fast_div are set 2044 * Table for Diversity 2045 * ant_div_alt_lnaconf bit 0-1 2046 * ant_div_main_lnaconf bit 2-3 2047 * ant_div_alt_gaintb bit 4 2048 * ant_div_main_gaintb bit 5 2049 * enable_ant_div_lnadiv bit 6 2050 * enable_ant_fast_div bit 7 2051 */ 2052 if ((ant_div_ctl1 >> 0x6) == 0x3) 2053 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2054 } 2055 2056 if (AR_SREV_9485_10(ah)) { 2057 pCap->pcie_lcr_extsync_en = true; 2058 pCap->pcie_lcr_offset = 0x80; 2059 } 2060 2061 tx_chainmask = pCap->tx_chainmask; 2062 rx_chainmask = pCap->rx_chainmask; 2063 while (tx_chainmask || rx_chainmask) { 2064 if (tx_chainmask & BIT(0)) 2065 pCap->max_txchains++; 2066 if (rx_chainmask & BIT(0)) 2067 pCap->max_rxchains++; 2068 2069 tx_chainmask >>= 1; 2070 rx_chainmask >>= 1; 2071 } 2072 2073 return 0; 2074} 2075 2076/****************************/ 2077/* GPIO / RFKILL / Antennae */ 2078/****************************/ 2079 2080static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2081 u32 gpio, u32 type) 2082{ 2083 int addr; 2084 u32 gpio_shift, tmp; 2085 2086 if (gpio > 11) 2087 addr = AR_GPIO_OUTPUT_MUX3; 2088 else if (gpio > 5) 2089 addr = AR_GPIO_OUTPUT_MUX2; 2090 else 2091 addr = AR_GPIO_OUTPUT_MUX1; 2092 2093 gpio_shift = (gpio % 6) * 5; 2094 2095 if (AR_SREV_9280_20_OR_LATER(ah) 2096 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2097 REG_RMW(ah, addr, (type << gpio_shift), 2098 (0x1f << gpio_shift)); 2099 } else { 2100 tmp = REG_READ(ah, addr); 2101 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2102 tmp &= ~(0x1f << gpio_shift); 2103 tmp |= (type << gpio_shift); 2104 REG_WRITE(ah, addr, tmp); 2105 } 2106} 2107 2108void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2109{ 2110 u32 gpio_shift; 2111 2112 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2113 2114 if (AR_DEVID_7010(ah)) { 2115 gpio_shift = gpio; 2116 REG_RMW(ah, AR7010_GPIO_OE, 2117 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2118 (AR7010_GPIO_OE_MASK << gpio_shift)); 2119 return; 2120 } 2121 2122 gpio_shift = gpio << 1; 2123 REG_RMW(ah, 2124 AR_GPIO_OE_OUT, 2125 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2126 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2127} 2128EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2129 2130u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2131{ 2132#define MS_REG_READ(x, y) \ 2133 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2134 2135 if (gpio >= ah->caps.num_gpio_pins) 2136 return 0xffffffff; 2137 2138 if (AR_DEVID_7010(ah)) { 2139 u32 val; 2140 val = REG_READ(ah, AR7010_GPIO_IN); 2141 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2142 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2143 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2144 AR_GPIO_BIT(gpio)) != 0; 2145 else if (AR_SREV_9271(ah)) 2146 return MS_REG_READ(AR9271, gpio) != 0; 2147 else if (AR_SREV_9287_11_OR_LATER(ah)) 2148 return MS_REG_READ(AR9287, gpio) != 0; 2149 else if (AR_SREV_9285_12_OR_LATER(ah)) 2150 return MS_REG_READ(AR9285, gpio) != 0; 2151 else if (AR_SREV_9280_20_OR_LATER(ah)) 2152 return MS_REG_READ(AR928X, gpio) != 0; 2153 else 2154 return MS_REG_READ(AR, gpio) != 0; 2155} 2156EXPORT_SYMBOL(ath9k_hw_gpio_get); 2157 2158void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2159 u32 ah_signal_type) 2160{ 2161 u32 gpio_shift; 2162 2163 if (AR_DEVID_7010(ah)) { 2164 gpio_shift = gpio; 2165 REG_RMW(ah, AR7010_GPIO_OE, 2166 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2167 (AR7010_GPIO_OE_MASK << gpio_shift)); 2168 return; 2169 } 2170 2171 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2172 gpio_shift = 2 * gpio; 2173 REG_RMW(ah, 2174 AR_GPIO_OE_OUT, 2175 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2176 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2177} 2178EXPORT_SYMBOL(ath9k_hw_cfg_output); 2179 2180void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2181{ 2182 if (AR_DEVID_7010(ah)) { 2183 val = val ? 0 : 1; 2184 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2185 AR_GPIO_BIT(gpio)); 2186 return; 2187 } 2188 2189 if (AR_SREV_9271(ah)) 2190 val = ~val; 2191 2192 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2193 AR_GPIO_BIT(gpio)); 2194} 2195EXPORT_SYMBOL(ath9k_hw_set_gpio); 2196 2197u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2198{ 2199 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2200} 2201EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2202 2203void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2204{ 2205 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2206} 2207EXPORT_SYMBOL(ath9k_hw_setantenna); 2208 2209/*********************/ 2210/* General Operation */ 2211/*********************/ 2212 2213u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2214{ 2215 u32 bits = REG_READ(ah, AR_RX_FILTER); 2216 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2217 2218 if (phybits & AR_PHY_ERR_RADAR) 2219 bits |= ATH9K_RX_FILTER_PHYRADAR; 2220 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2221 bits |= ATH9K_RX_FILTER_PHYERR; 2222 2223 return bits; 2224} 2225EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2226 2227void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2228{ 2229 u32 phybits; 2230 2231 ENABLE_REGWRITE_BUFFER(ah); 2232 2233 REG_WRITE(ah, AR_RX_FILTER, bits); 2234 2235 phybits = 0; 2236 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2237 phybits |= AR_PHY_ERR_RADAR; 2238 if (bits & ATH9K_RX_FILTER_PHYERR) 2239 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2240 REG_WRITE(ah, AR_PHY_ERR, phybits); 2241 2242 if (phybits) 2243 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2244 else 2245 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2246 2247 REGWRITE_BUFFER_FLUSH(ah); 2248} 2249EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2250 2251bool ath9k_hw_phy_disable(struct ath_hw *ah) 2252{ 2253 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2254 return false; 2255 2256 ath9k_hw_init_pll(ah, NULL); 2257 return true; 2258} 2259EXPORT_SYMBOL(ath9k_hw_phy_disable); 2260 2261bool ath9k_hw_disable(struct ath_hw *ah) 2262{ 2263 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2264 return false; 2265 2266 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2267 return false; 2268 2269 ath9k_hw_init_pll(ah, NULL); 2270 return true; 2271} 2272EXPORT_SYMBOL(ath9k_hw_disable); 2273 2274void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2275{ 2276 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2277 struct ath9k_channel *chan = ah->curchan; 2278 struct ieee80211_channel *channel = chan->chan; 2279 2280 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 2281 2282 ah->eep_ops->set_txpower(ah, chan, 2283 ath9k_regd_get_ctl(regulatory, chan), 2284 channel->max_antenna_gain * 2, 2285 channel->max_power * 2, 2286 min((u32) MAX_RATE_POWER, 2287 (u32) regulatory->power_limit), test); 2288} 2289EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2290 2291void ath9k_hw_setopmode(struct ath_hw *ah) 2292{ 2293 ath9k_hw_set_operating_mode(ah, ah->opmode); 2294} 2295EXPORT_SYMBOL(ath9k_hw_setopmode); 2296 2297void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2298{ 2299 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2300 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2301} 2302EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2303 2304void ath9k_hw_write_associd(struct ath_hw *ah) 2305{ 2306 struct ath_common *common = ath9k_hw_common(ah); 2307 2308 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2309 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2310 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2311} 2312EXPORT_SYMBOL(ath9k_hw_write_associd); 2313 2314#define ATH9K_MAX_TSF_READ 10 2315 2316u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2317{ 2318 u32 tsf_lower, tsf_upper1, tsf_upper2; 2319 int i; 2320 2321 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2322 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2323 tsf_lower = REG_READ(ah, AR_TSF_L32); 2324 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2325 if (tsf_upper2 == tsf_upper1) 2326 break; 2327 tsf_upper1 = tsf_upper2; 2328 } 2329 2330 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2331 2332 return (((u64)tsf_upper1 << 32) | tsf_lower); 2333} 2334EXPORT_SYMBOL(ath9k_hw_gettsf64); 2335 2336void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2337{ 2338 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2339 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2340} 2341EXPORT_SYMBOL(ath9k_hw_settsf64); 2342 2343void ath9k_hw_reset_tsf(struct ath_hw *ah) 2344{ 2345 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2346 AH_TSF_WRITE_TIMEOUT)) 2347 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 2348 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2349 2350 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2351} 2352EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2353 2354void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2355{ 2356 if (setting) 2357 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2358 else 2359 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2360} 2361EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2362 2363void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2364{ 2365 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2366 u32 macmode; 2367 2368 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2369 macmode = AR_2040_JOINED_RX_CLEAR; 2370 else 2371 macmode = 0; 2372 2373 REG_WRITE(ah, AR_2040_MODE, macmode); 2374} 2375 2376/* HW Generic timers configuration */ 2377 2378static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2379{ 2380 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2381 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2382 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2383 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2384 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2385 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2386 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2387 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2388 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2389 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2390 AR_NDP2_TIMER_MODE, 0x0002}, 2391 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2392 AR_NDP2_TIMER_MODE, 0x0004}, 2393 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2394 AR_NDP2_TIMER_MODE, 0x0008}, 2395 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2396 AR_NDP2_TIMER_MODE, 0x0010}, 2397 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2398 AR_NDP2_TIMER_MODE, 0x0020}, 2399 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2400 AR_NDP2_TIMER_MODE, 0x0040}, 2401 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2402 AR_NDP2_TIMER_MODE, 0x0080} 2403}; 2404 2405/* HW generic timer primitives */ 2406 2407/* compute and clear index of rightmost 1 */ 2408static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2409{ 2410 u32 b; 2411 2412 b = *mask; 2413 b &= (0-b); 2414 *mask &= ~b; 2415 b *= debruijn32; 2416 b >>= 27; 2417 2418 return timer_table->gen_timer_index[b]; 2419} 2420 2421u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2422{ 2423 return REG_READ(ah, AR_TSF_L32); 2424} 2425EXPORT_SYMBOL(ath9k_hw_gettsf32); 2426 2427struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2428 void (*trigger)(void *), 2429 void (*overflow)(void *), 2430 void *arg, 2431 u8 timer_index) 2432{ 2433 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2434 struct ath_gen_timer *timer; 2435 2436 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2437 2438 if (timer == NULL) { 2439 ath_err(ath9k_hw_common(ah), 2440 "Failed to allocate memory for hw timer[%d]\n", 2441 timer_index); 2442 return NULL; 2443 } 2444 2445 /* allocate a hardware generic timer slot */ 2446 timer_table->timers[timer_index] = timer; 2447 timer->index = timer_index; 2448 timer->trigger = trigger; 2449 timer->overflow = overflow; 2450 timer->arg = arg; 2451 2452 return timer; 2453} 2454EXPORT_SYMBOL(ath_gen_timer_alloc); 2455 2456void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2457 struct ath_gen_timer *timer, 2458 u32 trig_timeout, 2459 u32 timer_period) 2460{ 2461 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2462 u32 tsf, timer_next; 2463 2464 BUG_ON(!timer_period); 2465 2466 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2467 2468 tsf = ath9k_hw_gettsf32(ah); 2469 2470 timer_next = tsf + trig_timeout; 2471 2472 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2473 "current tsf %x period %x timer_next %x\n", 2474 tsf, timer_period, timer_next); 2475 2476 /* 2477 * Program generic timer registers 2478 */ 2479 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2480 timer_next); 2481 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2482 timer_period); 2483 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2484 gen_tmr_configuration[timer->index].mode_mask); 2485 2486 /* Enable both trigger and thresh interrupt masks */ 2487 REG_SET_BIT(ah, AR_IMR_S5, 2488 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2489 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2490} 2491EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2492 2493void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2494{ 2495 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2496 2497 if ((timer->index < AR_FIRST_NDP_TIMER) || 2498 (timer->index >= ATH_MAX_GEN_TIMER)) { 2499 return; 2500 } 2501 2502 /* Clear generic timer enable bits. */ 2503 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2504 gen_tmr_configuration[timer->index].mode_mask); 2505 2506 /* Disable both trigger and thresh interrupt masks */ 2507 REG_CLR_BIT(ah, AR_IMR_S5, 2508 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2509 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2510 2511 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2512} 2513EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2514 2515void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2516{ 2517 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2518 2519 /* free the hardware generic timer slot */ 2520 timer_table->timers[timer->index] = NULL; 2521 kfree(timer); 2522} 2523EXPORT_SYMBOL(ath_gen_timer_free); 2524 2525/* 2526 * Generic Timer Interrupts handling 2527 */ 2528void ath_gen_timer_isr(struct ath_hw *ah) 2529{ 2530 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2531 struct ath_gen_timer *timer; 2532 struct ath_common *common = ath9k_hw_common(ah); 2533 u32 trigger_mask, thresh_mask, index; 2534 2535 /* get hardware generic timer interrupt status */ 2536 trigger_mask = ah->intr_gen_timer_trigger; 2537 thresh_mask = ah->intr_gen_timer_thresh; 2538 trigger_mask &= timer_table->timer_mask.val; 2539 thresh_mask &= timer_table->timer_mask.val; 2540 2541 trigger_mask &= ~thresh_mask; 2542 2543 while (thresh_mask) { 2544 index = rightmost_index(timer_table, &thresh_mask); 2545 timer = timer_table->timers[index]; 2546 BUG_ON(!timer); 2547 ath_dbg(common, ATH_DBG_HWTIMER, 2548 "TSF overflow for Gen timer %d\n", index); 2549 timer->overflow(timer->arg); 2550 } 2551 2552 while (trigger_mask) { 2553 index = rightmost_index(timer_table, &trigger_mask); 2554 timer = timer_table->timers[index]; 2555 BUG_ON(!timer); 2556 ath_dbg(common, ATH_DBG_HWTIMER, 2557 "Gen timer[%d] trigger\n", index); 2558 timer->trigger(timer->arg); 2559 } 2560} 2561EXPORT_SYMBOL(ath_gen_timer_isr); 2562 2563/********/ 2564/* HTC */ 2565/********/ 2566 2567void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2568{ 2569 ah->htc_reset_init = true; 2570} 2571EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2572 2573static struct { 2574 u32 version; 2575 const char * name; 2576} ath_mac_bb_names[] = { 2577 /* Devices with external radios */ 2578 { AR_SREV_VERSION_5416_PCI, "5416" }, 2579 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2580 { AR_SREV_VERSION_9100, "9100" }, 2581 { AR_SREV_VERSION_9160, "9160" }, 2582 /* Single-chip solutions */ 2583 { AR_SREV_VERSION_9280, "9280" }, 2584 { AR_SREV_VERSION_9285, "9285" }, 2585 { AR_SREV_VERSION_9287, "9287" }, 2586 { AR_SREV_VERSION_9271, "9271" }, 2587 { AR_SREV_VERSION_9300, "9300" }, 2588 { AR_SREV_VERSION_9330, "9330" }, 2589 { AR_SREV_VERSION_9485, "9485" }, 2590}; 2591 2592/* For devices with external radios */ 2593static struct { 2594 u16 version; 2595 const char * name; 2596} ath_rf_names[] = { 2597 { 0, "5133" }, 2598 { AR_RAD5133_SREV_MAJOR, "5133" }, 2599 { AR_RAD5122_SREV_MAJOR, "5122" }, 2600 { AR_RAD2133_SREV_MAJOR, "2133" }, 2601 { AR_RAD2122_SREV_MAJOR, "2122" } 2602}; 2603 2604/* 2605 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2606 */ 2607static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2608{ 2609 int i; 2610 2611 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2612 if (ath_mac_bb_names[i].version == mac_bb_version) { 2613 return ath_mac_bb_names[i].name; 2614 } 2615 } 2616 2617 return "????"; 2618} 2619 2620/* 2621 * Return the RF name. "????" is returned if the RF is unknown. 2622 * Used for devices with external radios. 2623 */ 2624static const char *ath9k_hw_rf_name(u16 rf_version) 2625{ 2626 int i; 2627 2628 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2629 if (ath_rf_names[i].version == rf_version) { 2630 return ath_rf_names[i].name; 2631 } 2632 } 2633 2634 return "????"; 2635} 2636 2637void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2638{ 2639 int used; 2640 2641 /* chipsets >= AR9280 are single-chip */ 2642 if (AR_SREV_9280_20_OR_LATER(ah)) { 2643 used = snprintf(hw_name, len, 2644 "Atheros AR%s Rev:%x", 2645 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2646 ah->hw_version.macRev); 2647 } 2648 else { 2649 used = snprintf(hw_name, len, 2650 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2651 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2652 ah->hw_version.macRev, 2653 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2654 AR_RADIO_SREV_MAJOR)), 2655 ah->hw_version.phyRev); 2656 } 2657 2658 hw_name[used] = '\0'; 2659} 2660EXPORT_SYMBOL(ath9k_hw_name); 2661