hw.c revision 397e5d5b93ba99ad3dc56f1e294f487e77d2daa8
1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <asm/unaligned.h> 20 21#include "hw.h" 22#include "hw-ops.h" 23#include "rc.h" 24#include "ar9003_mac.h" 25 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 27 28MODULE_AUTHOR("Atheros Communications"); 29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 31MODULE_LICENSE("Dual BSD/GPL"); 32 33static int __init ath9k_init(void) 34{ 35 return 0; 36} 37module_init(ath9k_init); 38 39static void __exit ath9k_exit(void) 40{ 41 return; 42} 43module_exit(ath9k_exit); 44 45/* Private hardware callbacks */ 46 47static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 48{ 49 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 50} 51 52static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 53{ 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 55} 56 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 58 struct ath9k_channel *chan) 59{ 60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 61} 62 63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 64{ 65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 66 return; 67 68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 69} 70 71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 72{ 73 /* You will not have this callback if using the old ANI */ 74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 75 return; 76 77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 78} 79 80/********************/ 81/* Helper Functions */ 82/********************/ 83 84static void ath9k_hw_set_clockrate(struct ath_hw *ah) 85{ 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 87 struct ath_common *common = ath9k_hw_common(ah); 88 unsigned int clockrate; 89 90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 92 clockrate = 117; 93 else if (!ah->curchan) /* should really check for CCK instead */ 94 clockrate = ATH9K_CLOCK_RATE_CCK; 95 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 97 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 98 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 99 else 100 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 101 102 if (conf_is_ht40(conf)) 103 clockrate *= 2; 104 105 if (ah->curchan) { 106 if (IS_CHAN_HALF_RATE(ah->curchan)) 107 clockrate /= 2; 108 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 109 clockrate /= 4; 110 } 111 112 common->clockrate = clockrate; 113} 114 115static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 116{ 117 struct ath_common *common = ath9k_hw_common(ah); 118 119 return usecs * common->clockrate; 120} 121 122bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 123{ 124 int i; 125 126 BUG_ON(timeout < AH_TIME_QUANTUM); 127 128 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 129 if ((REG_READ(ah, reg) & mask) == val) 130 return true; 131 132 udelay(AH_TIME_QUANTUM); 133 } 134 135 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, 136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 137 timeout, reg, REG_READ(ah, reg), mask, val); 138 139 return false; 140} 141EXPORT_SYMBOL(ath9k_hw_wait); 142 143void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 144 int column, unsigned int *writecnt) 145{ 146 int r; 147 148 ENABLE_REGWRITE_BUFFER(ah); 149 for (r = 0; r < array->ia_rows; r++) { 150 REG_WRITE(ah, INI_RA(array, r, 0), 151 INI_RA(array, r, column)); 152 DO_DELAY(*writecnt); 153 } 154 REGWRITE_BUFFER_FLUSH(ah); 155} 156 157u32 ath9k_hw_reverse_bits(u32 val, u32 n) 158{ 159 u32 retval; 160 int i; 161 162 for (i = 0, retval = 0; i < n; i++) { 163 retval = (retval << 1) | (val & 1); 164 val >>= 1; 165 } 166 return retval; 167} 168 169u16 ath9k_hw_computetxtime(struct ath_hw *ah, 170 u8 phy, int kbps, 171 u32 frameLen, u16 rateix, 172 bool shortPreamble) 173{ 174 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 175 176 if (kbps == 0) 177 return 0; 178 179 switch (phy) { 180 case WLAN_RC_PHY_CCK: 181 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 182 if (shortPreamble) 183 phyTime >>= 1; 184 numBits = frameLen << 3; 185 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 186 break; 187 case WLAN_RC_PHY_OFDM: 188 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 189 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 190 numBits = OFDM_PLCP_BITS + (frameLen << 3); 191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 192 txTime = OFDM_SIFS_TIME_QUARTER 193 + OFDM_PREAMBLE_TIME_QUARTER 194 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 195 } else if (ah->curchan && 196 IS_CHAN_HALF_RATE(ah->curchan)) { 197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 198 numBits = OFDM_PLCP_BITS + (frameLen << 3); 199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 200 txTime = OFDM_SIFS_TIME_HALF + 201 OFDM_PREAMBLE_TIME_HALF 202 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 203 } else { 204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 205 numBits = OFDM_PLCP_BITS + (frameLen << 3); 206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 208 + (numSymbols * OFDM_SYMBOL_TIME); 209 } 210 break; 211 default: 212 ath_err(ath9k_hw_common(ah), 213 "Unknown phy %u (rate ix %u)\n", phy, rateix); 214 txTime = 0; 215 break; 216 } 217 218 return txTime; 219} 220EXPORT_SYMBOL(ath9k_hw_computetxtime); 221 222void ath9k_hw_get_channel_centers(struct ath_hw *ah, 223 struct ath9k_channel *chan, 224 struct chan_centers *centers) 225{ 226 int8_t extoff; 227 228 if (!IS_CHAN_HT40(chan)) { 229 centers->ctl_center = centers->ext_center = 230 centers->synth_center = chan->channel; 231 return; 232 } 233 234 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 235 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 236 centers->synth_center = 237 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 238 extoff = 1; 239 } else { 240 centers->synth_center = 241 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 242 extoff = -1; 243 } 244 245 centers->ctl_center = 246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 247 /* 25 MHz spacing is supported by hw but not on upper layers */ 248 centers->ext_center = 249 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 250} 251 252/******************/ 253/* Chip Revisions */ 254/******************/ 255 256static void ath9k_hw_read_revisions(struct ath_hw *ah) 257{ 258 u32 val; 259 260 switch (ah->hw_version.devid) { 261 case AR5416_AR9100_DEVID: 262 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 263 break; 264 case AR9300_DEVID_AR9330: 265 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 266 if (ah->get_mac_revision) { 267 ah->hw_version.macRev = ah->get_mac_revision(); 268 } else { 269 val = REG_READ(ah, AR_SREV); 270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 271 } 272 return; 273 case AR9300_DEVID_AR9340: 274 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 275 val = REG_READ(ah, AR_SREV); 276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 277 return; 278 } 279 280 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 281 282 if (val == 0xFF) { 283 val = REG_READ(ah, AR_SREV); 284 ah->hw_version.macVersion = 285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 287 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 288 } else { 289 if (!AR_SREV_9100(ah)) 290 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 291 292 ah->hw_version.macRev = val & AR_SREV_REVISION; 293 294 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 295 ah->is_pciexpress = true; 296 } 297} 298 299/************************************/ 300/* HW Attach, Detach, Init Routines */ 301/************************************/ 302 303static void ath9k_hw_disablepcie(struct ath_hw *ah) 304{ 305 if (!AR_SREV_5416(ah)) 306 return; 307 308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 317 318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 319} 320 321static void ath9k_hw_aspm_init(struct ath_hw *ah) 322{ 323 struct ath_common *common = ath9k_hw_common(ah); 324 325 if (common->bus_ops->aspm_init) 326 common->bus_ops->aspm_init(common); 327} 328 329/* This should work for all families including legacy */ 330static bool ath9k_hw_chip_test(struct ath_hw *ah) 331{ 332 struct ath_common *common = ath9k_hw_common(ah); 333 u32 regAddr[2] = { AR_STA_ID0 }; 334 u32 regHold[2]; 335 static const u32 patternData[4] = { 336 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 337 }; 338 int i, j, loop_max; 339 340 if (!AR_SREV_9300_20_OR_LATER(ah)) { 341 loop_max = 2; 342 regAddr[1] = AR_PHY_BASE + (8 << 2); 343 } else 344 loop_max = 1; 345 346 for (i = 0; i < loop_max; i++) { 347 u32 addr = regAddr[i]; 348 u32 wrData, rdData; 349 350 regHold[i] = REG_READ(ah, addr); 351 for (j = 0; j < 0x100; j++) { 352 wrData = (j << 16) | j; 353 REG_WRITE(ah, addr, wrData); 354 rdData = REG_READ(ah, addr); 355 if (rdData != wrData) { 356 ath_err(common, 357 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 358 addr, wrData, rdData); 359 return false; 360 } 361 } 362 for (j = 0; j < 4; j++) { 363 wrData = patternData[j]; 364 REG_WRITE(ah, addr, wrData); 365 rdData = REG_READ(ah, addr); 366 if (wrData != rdData) { 367 ath_err(common, 368 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 369 addr, wrData, rdData); 370 return false; 371 } 372 } 373 REG_WRITE(ah, regAddr[i], regHold[i]); 374 } 375 udelay(100); 376 377 return true; 378} 379 380static void ath9k_hw_init_config(struct ath_hw *ah) 381{ 382 int i; 383 384 ah->config.dma_beacon_response_time = 2; 385 ah->config.sw_beacon_response_time = 10; 386 ah->config.additional_swba_backoff = 0; 387 ah->config.ack_6mb = 0x0; 388 ah->config.cwm_ignore_extcca = 0; 389 ah->config.pcie_clock_req = 0; 390 ah->config.pcie_waen = 0; 391 ah->config.analog_shiftreg = 1; 392 ah->config.enable_ani = true; 393 394 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 395 ah->config.spurchans[i][0] = AR_NO_SPUR; 396 ah->config.spurchans[i][1] = AR_NO_SPUR; 397 } 398 399 /* PAPRD needs some more work to be enabled */ 400 ah->config.paprd_disable = 1; 401 402 ah->config.rx_intr_mitigation = true; 403 ah->config.pcieSerDesWrite = true; 404 405 /* 406 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 407 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 408 * This means we use it for all AR5416 devices, and the few 409 * minor PCI AR9280 devices out there. 410 * 411 * Serialization is required because these devices do not handle 412 * well the case of two concurrent reads/writes due to the latency 413 * involved. During one read/write another read/write can be issued 414 * on another CPU while the previous read/write may still be working 415 * on our hardware, if we hit this case the hardware poops in a loop. 416 * We prevent this by serializing reads and writes. 417 * 418 * This issue is not present on PCI-Express devices or pre-AR5416 419 * devices (legacy, 802.11abg). 420 */ 421 if (num_possible_cpus() > 1) 422 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 423} 424 425static void ath9k_hw_init_defaults(struct ath_hw *ah) 426{ 427 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 428 429 regulatory->country_code = CTRY_DEFAULT; 430 regulatory->power_limit = MAX_RATE_POWER; 431 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 432 433 ah->hw_version.magic = AR5416_MAGIC; 434 ah->hw_version.subvendorid = 0; 435 436 ah->atim_window = 0; 437 ah->sta_id1_defaults = 438 AR_STA_ID1_CRPT_MIC_ENABLE | 439 AR_STA_ID1_MCAST_KSRCH; 440 if (AR_SREV_9100(ah)) 441 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 442 ah->enable_32kHz_clock = DONT_USE_32KHZ; 443 ah->slottime = 20; 444 ah->globaltxtimeout = (u32) -1; 445 ah->power_mode = ATH9K_PM_UNDEFINED; 446} 447 448static int ath9k_hw_init_macaddr(struct ath_hw *ah) 449{ 450 struct ath_common *common = ath9k_hw_common(ah); 451 u32 sum; 452 int i; 453 u16 eeval; 454 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 455 456 sum = 0; 457 for (i = 0; i < 3; i++) { 458 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 459 sum += eeval; 460 common->macaddr[2 * i] = eeval >> 8; 461 common->macaddr[2 * i + 1] = eeval & 0xff; 462 } 463 if (sum == 0 || sum == 0xffff * 3) 464 return -EADDRNOTAVAIL; 465 466 return 0; 467} 468 469static int ath9k_hw_post_init(struct ath_hw *ah) 470{ 471 struct ath_common *common = ath9k_hw_common(ah); 472 int ecode; 473 474 if (common->bus_ops->ath_bus_type != ATH_USB) { 475 if (!ath9k_hw_chip_test(ah)) 476 return -ENODEV; 477 } 478 479 if (!AR_SREV_9300_20_OR_LATER(ah)) { 480 ecode = ar9002_hw_rf_claim(ah); 481 if (ecode != 0) 482 return ecode; 483 } 484 485 ecode = ath9k_hw_eeprom_init(ah); 486 if (ecode != 0) 487 return ecode; 488 489 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, 490 "Eeprom VER: %d, REV: %d\n", 491 ah->eep_ops->get_eeprom_ver(ah), 492 ah->eep_ops->get_eeprom_rev(ah)); 493 494 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 495 if (ecode) { 496 ath_err(ath9k_hw_common(ah), 497 "Failed allocating banks for external radio\n"); 498 ath9k_hw_rf_free_ext_banks(ah); 499 return ecode; 500 } 501 502 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) { 503 ath9k_hw_ani_setup(ah); 504 ath9k_hw_ani_init(ah); 505 } 506 507 return 0; 508} 509 510static void ath9k_hw_attach_ops(struct ath_hw *ah) 511{ 512 if (AR_SREV_9300_20_OR_LATER(ah)) 513 ar9003_hw_attach_ops(ah); 514 else 515 ar9002_hw_attach_ops(ah); 516} 517 518/* Called for all hardware families */ 519static int __ath9k_hw_init(struct ath_hw *ah) 520{ 521 struct ath_common *common = ath9k_hw_common(ah); 522 int r = 0; 523 524 ath9k_hw_read_revisions(ah); 525 526 /* 527 * Read back AR_WA into a permanent copy and set bits 14 and 17. 528 * We need to do this to avoid RMW of this register. We cannot 529 * read the reg when chip is asleep. 530 */ 531 ah->WARegVal = REG_READ(ah, AR_WA); 532 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 533 AR_WA_ASPM_TIMER_BASED_DISABLE); 534 535 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 536 ath_err(common, "Couldn't reset chip\n"); 537 return -EIO; 538 } 539 540 ath9k_hw_init_defaults(ah); 541 ath9k_hw_init_config(ah); 542 543 ath9k_hw_attach_ops(ah); 544 545 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 546 ath_err(common, "Couldn't wakeup chip\n"); 547 return -EIO; 548 } 549 550 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 551 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 552 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 553 !ah->is_pciexpress)) { 554 ah->config.serialize_regmode = 555 SER_REG_MODE_ON; 556 } else { 557 ah->config.serialize_regmode = 558 SER_REG_MODE_OFF; 559 } 560 } 561 562 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 563 ah->config.serialize_regmode); 564 565 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 566 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 567 else 568 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 569 570 switch (ah->hw_version.macVersion) { 571 case AR_SREV_VERSION_5416_PCI: 572 case AR_SREV_VERSION_5416_PCIE: 573 case AR_SREV_VERSION_9160: 574 case AR_SREV_VERSION_9100: 575 case AR_SREV_VERSION_9280: 576 case AR_SREV_VERSION_9285: 577 case AR_SREV_VERSION_9287: 578 case AR_SREV_VERSION_9271: 579 case AR_SREV_VERSION_9300: 580 case AR_SREV_VERSION_9330: 581 case AR_SREV_VERSION_9485: 582 case AR_SREV_VERSION_9340: 583 break; 584 default: 585 ath_err(common, 586 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 587 ah->hw_version.macVersion, ah->hw_version.macRev); 588 return -EOPNOTSUPP; 589 } 590 591 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 592 AR_SREV_9330(ah)) 593 ah->is_pciexpress = false; 594 595 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 596 ath9k_hw_init_cal_settings(ah); 597 598 ah->ani_function = ATH9K_ANI_ALL; 599 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 600 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 601 if (!AR_SREV_9300_20_OR_LATER(ah)) 602 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 603 604 ath9k_hw_init_mode_regs(ah); 605 606 if (!ah->is_pciexpress) 607 ath9k_hw_disablepcie(ah); 608 609 if (!AR_SREV_9300_20_OR_LATER(ah)) 610 ar9002_hw_cck_chan14_spread(ah); 611 612 r = ath9k_hw_post_init(ah); 613 if (r) 614 return r; 615 616 ath9k_hw_init_mode_gain_regs(ah); 617 r = ath9k_hw_fill_cap_info(ah); 618 if (r) 619 return r; 620 621 if (ah->is_pciexpress) 622 ath9k_hw_aspm_init(ah); 623 624 r = ath9k_hw_init_macaddr(ah); 625 if (r) { 626 ath_err(common, "Failed to initialize MAC address\n"); 627 return r; 628 } 629 630 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 631 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 632 else 633 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 634 635 if (AR_SREV_9330(ah)) 636 ah->bb_watchdog_timeout_ms = 85; 637 else 638 ah->bb_watchdog_timeout_ms = 25; 639 640 common->state = ATH_HW_INITIALIZED; 641 642 return 0; 643} 644 645int ath9k_hw_init(struct ath_hw *ah) 646{ 647 int ret; 648 struct ath_common *common = ath9k_hw_common(ah); 649 650 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 651 switch (ah->hw_version.devid) { 652 case AR5416_DEVID_PCI: 653 case AR5416_DEVID_PCIE: 654 case AR5416_AR9100_DEVID: 655 case AR9160_DEVID_PCI: 656 case AR9280_DEVID_PCI: 657 case AR9280_DEVID_PCIE: 658 case AR9285_DEVID_PCIE: 659 case AR9287_DEVID_PCI: 660 case AR9287_DEVID_PCIE: 661 case AR2427_DEVID_PCIE: 662 case AR9300_DEVID_PCIE: 663 case AR9300_DEVID_AR9485_PCIE: 664 case AR9300_DEVID_AR9330: 665 case AR9300_DEVID_AR9340: 666 case AR9300_DEVID_AR9580: 667 break; 668 default: 669 if (common->bus_ops->ath_bus_type == ATH_USB) 670 break; 671 ath_err(common, "Hardware device ID 0x%04x not supported\n", 672 ah->hw_version.devid); 673 return -EOPNOTSUPP; 674 } 675 676 ret = __ath9k_hw_init(ah); 677 if (ret) { 678 ath_err(common, 679 "Unable to initialize hardware; initialization status: %d\n", 680 ret); 681 return ret; 682 } 683 684 return 0; 685} 686EXPORT_SYMBOL(ath9k_hw_init); 687 688static void ath9k_hw_init_qos(struct ath_hw *ah) 689{ 690 ENABLE_REGWRITE_BUFFER(ah); 691 692 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 693 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 694 695 REG_WRITE(ah, AR_QOS_NO_ACK, 696 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 697 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 698 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 699 700 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 701 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 702 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 703 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 704 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 705 706 REGWRITE_BUFFER_FLUSH(ah); 707} 708 709u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 710{ 711 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 712 udelay(100); 713 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 714 715 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 716 udelay(100); 717 718 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 719} 720EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 721 722static void ath9k_hw_init_pll(struct ath_hw *ah, 723 struct ath9k_channel *chan) 724{ 725 u32 pll; 726 727 if (AR_SREV_9485(ah)) { 728 729 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 731 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 732 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 733 AR_CH0_DPLL2_KD, 0x40); 734 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 735 AR_CH0_DPLL2_KI, 0x4); 736 737 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 738 AR_CH0_BB_DPLL1_REFDIV, 0x5); 739 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 740 AR_CH0_BB_DPLL1_NINI, 0x58); 741 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 742 AR_CH0_BB_DPLL1_NFRAC, 0x0); 743 744 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 745 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 746 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 747 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 748 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 749 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 750 751 /* program BB PLL phase_shift to 0x6 */ 752 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 753 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 754 755 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 756 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 757 udelay(1000); 758 } else if (AR_SREV_9330(ah)) { 759 u32 ddr_dpll2, pll_control2, kd; 760 761 if (ah->is_clk_25mhz) { 762 ddr_dpll2 = 0x18e82f01; 763 pll_control2 = 0xe04a3d; 764 kd = 0x1d; 765 } else { 766 ddr_dpll2 = 0x19e82f01; 767 pll_control2 = 0x886666; 768 kd = 0x3d; 769 } 770 771 /* program DDR PLL ki and kd value */ 772 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 773 774 /* program DDR PLL phase_shift */ 775 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 776 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 777 778 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 779 udelay(1000); 780 781 /* program refdiv, nint, frac to RTC register */ 782 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 783 784 /* program BB PLL kd and ki value */ 785 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 786 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 787 788 /* program BB PLL phase_shift */ 789 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 790 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 791 } else if (AR_SREV_9340(ah)) { 792 u32 regval, pll2_divint, pll2_divfrac, refdiv; 793 794 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 795 udelay(1000); 796 797 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 798 udelay(100); 799 800 if (ah->is_clk_25mhz) { 801 pll2_divint = 0x54; 802 pll2_divfrac = 0x1eb85; 803 refdiv = 3; 804 } else { 805 pll2_divint = 88; 806 pll2_divfrac = 0; 807 refdiv = 5; 808 } 809 810 regval = REG_READ(ah, AR_PHY_PLL_MODE); 811 regval |= (0x1 << 16); 812 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 813 udelay(100); 814 815 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 816 (pll2_divint << 18) | pll2_divfrac); 817 udelay(100); 818 819 regval = REG_READ(ah, AR_PHY_PLL_MODE); 820 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 821 (0x4 << 26) | (0x18 << 19); 822 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 823 REG_WRITE(ah, AR_PHY_PLL_MODE, 824 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 825 udelay(1000); 826 } 827 828 pll = ath9k_hw_compute_pll_control(ah, chan); 829 830 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 831 832 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 833 udelay(1000); 834 835 /* Switch the core clock for ar9271 to 117Mhz */ 836 if (AR_SREV_9271(ah)) { 837 udelay(500); 838 REG_WRITE(ah, 0x50040, 0x304); 839 } 840 841 udelay(RTC_PLL_SETTLE_DELAY); 842 843 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 844 845 if (AR_SREV_9340(ah)) { 846 if (ah->is_clk_25mhz) { 847 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 848 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 849 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 850 } else { 851 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 852 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 853 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 854 } 855 udelay(100); 856 } 857} 858 859static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 860 enum nl80211_iftype opmode) 861{ 862 u32 sync_default = AR_INTR_SYNC_DEFAULT; 863 u32 imr_reg = AR_IMR_TXERR | 864 AR_IMR_TXURN | 865 AR_IMR_RXERR | 866 AR_IMR_RXORN | 867 AR_IMR_BCNMISC; 868 869 if (AR_SREV_9340(ah)) 870 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 871 872 if (AR_SREV_9300_20_OR_LATER(ah)) { 873 imr_reg |= AR_IMR_RXOK_HP; 874 if (ah->config.rx_intr_mitigation) 875 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 876 else 877 imr_reg |= AR_IMR_RXOK_LP; 878 879 } else { 880 if (ah->config.rx_intr_mitigation) 881 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 882 else 883 imr_reg |= AR_IMR_RXOK; 884 } 885 886 if (ah->config.tx_intr_mitigation) 887 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 888 else 889 imr_reg |= AR_IMR_TXOK; 890 891 if (opmode == NL80211_IFTYPE_AP) 892 imr_reg |= AR_IMR_MIB; 893 894 ENABLE_REGWRITE_BUFFER(ah); 895 896 REG_WRITE(ah, AR_IMR, imr_reg); 897 ah->imrs2_reg |= AR_IMR_S2_GTT; 898 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 899 900 if (!AR_SREV_9100(ah)) { 901 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 902 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 903 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 904 } 905 906 REGWRITE_BUFFER_FLUSH(ah); 907 908 if (AR_SREV_9300_20_OR_LATER(ah)) { 909 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 910 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 911 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 912 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 913 } 914} 915 916static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 917{ 918 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 919 val = min(val, (u32) 0xFFFF); 920 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 921} 922 923static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 924{ 925 u32 val = ath9k_hw_mac_to_clks(ah, us); 926 val = min(val, (u32) 0xFFFF); 927 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 928} 929 930static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 931{ 932 u32 val = ath9k_hw_mac_to_clks(ah, us); 933 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 934 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 935} 936 937static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 938{ 939 u32 val = ath9k_hw_mac_to_clks(ah, us); 940 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 941 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 942} 943 944static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 945{ 946 if (tu > 0xFFFF) { 947 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 948 "bad global tx timeout %u\n", tu); 949 ah->globaltxtimeout = (u32) -1; 950 return false; 951 } else { 952 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 953 ah->globaltxtimeout = tu; 954 return true; 955 } 956} 957 958void ath9k_hw_init_global_settings(struct ath_hw *ah) 959{ 960 struct ath_common *common = ath9k_hw_common(ah); 961 struct ieee80211_conf *conf = &common->hw->conf; 962 const struct ath9k_channel *chan = ah->curchan; 963 int acktimeout; 964 int slottime; 965 int sifstime; 966 int rx_lat = 0, tx_lat = 0, eifs = 0; 967 u32 reg; 968 969 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 970 ah->misc_mode); 971 972 if (!chan) 973 return; 974 975 if (ah->misc_mode != 0) 976 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 977 978 rx_lat = 37; 979 tx_lat = 54; 980 981 if (IS_CHAN_HALF_RATE(chan)) { 982 eifs = 175; 983 rx_lat *= 2; 984 tx_lat *= 2; 985 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 986 tx_lat += 11; 987 988 slottime = 13; 989 sifstime = 32; 990 } else if (IS_CHAN_QUARTER_RATE(chan)) { 991 eifs = 340; 992 rx_lat *= 4; 993 tx_lat *= 4; 994 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 995 tx_lat += 22; 996 997 slottime = 21; 998 sifstime = 64; 999 } else { 1000 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/common->clockrate; 1001 reg = REG_READ(ah, AR_USEC); 1002 rx_lat = MS(reg, AR_USEC_RX_LAT); 1003 tx_lat = MS(reg, AR_USEC_TX_LAT); 1004 1005 slottime = ah->slottime; 1006 if (IS_CHAN_5GHZ(chan)) 1007 sifstime = 16; 1008 else 1009 sifstime = 10; 1010 } 1011 1012 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1013 acktimeout = slottime + sifstime + 3 * ah->coverage_class; 1014 1015 /* 1016 * Workaround for early ACK timeouts, add an offset to match the 1017 * initval's 64us ack timeout value. 1018 * This was initially only meant to work around an issue with delayed 1019 * BA frames in some implementations, but it has been found to fix ACK 1020 * timeout issues in other cases as well. 1021 */ 1022 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 1023 acktimeout += 64 - sifstime - ah->slottime; 1024 1025 ath9k_hw_set_sifs_time(ah, sifstime); 1026 ath9k_hw_setslottime(ah, slottime); 1027 ath9k_hw_set_ack_timeout(ah, acktimeout); 1028 ath9k_hw_set_cts_timeout(ah, acktimeout); 1029 if (ah->globaltxtimeout != (u32) -1) 1030 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1031 1032 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1033 REG_RMW(ah, AR_USEC, 1034 (common->clockrate - 1) | 1035 SM(rx_lat, AR_USEC_RX_LAT) | 1036 SM(tx_lat, AR_USEC_TX_LAT), 1037 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1038 1039} 1040EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1041 1042void ath9k_hw_deinit(struct ath_hw *ah) 1043{ 1044 struct ath_common *common = ath9k_hw_common(ah); 1045 1046 if (common->state < ATH_HW_INITIALIZED) 1047 goto free_hw; 1048 1049 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1050 1051free_hw: 1052 ath9k_hw_rf_free_ext_banks(ah); 1053} 1054EXPORT_SYMBOL(ath9k_hw_deinit); 1055 1056/*******/ 1057/* INI */ 1058/*******/ 1059 1060u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1061{ 1062 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1063 1064 if (IS_CHAN_B(chan)) 1065 ctl |= CTL_11B; 1066 else if (IS_CHAN_G(chan)) 1067 ctl |= CTL_11G; 1068 else 1069 ctl |= CTL_11A; 1070 1071 return ctl; 1072} 1073 1074/****************************************/ 1075/* Reset and Channel Switching Routines */ 1076/****************************************/ 1077 1078static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1079{ 1080 struct ath_common *common = ath9k_hw_common(ah); 1081 1082 ENABLE_REGWRITE_BUFFER(ah); 1083 1084 /* 1085 * set AHB_MODE not to do cacheline prefetches 1086 */ 1087 if (!AR_SREV_9300_20_OR_LATER(ah)) 1088 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1089 1090 /* 1091 * let mac dma reads be in 128 byte chunks 1092 */ 1093 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1094 1095 REGWRITE_BUFFER_FLUSH(ah); 1096 1097 /* 1098 * Restore TX Trigger Level to its pre-reset value. 1099 * The initial value depends on whether aggregation is enabled, and is 1100 * adjusted whenever underruns are detected. 1101 */ 1102 if (!AR_SREV_9300_20_OR_LATER(ah)) 1103 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1104 1105 ENABLE_REGWRITE_BUFFER(ah); 1106 1107 /* 1108 * let mac dma writes be in 128 byte chunks 1109 */ 1110 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1111 1112 /* 1113 * Setup receive FIFO threshold to hold off TX activities 1114 */ 1115 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1116 1117 if (AR_SREV_9300_20_OR_LATER(ah)) { 1118 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1119 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1120 1121 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1122 ah->caps.rx_status_len); 1123 } 1124 1125 /* 1126 * reduce the number of usable entries in PCU TXBUF to avoid 1127 * wrap around issues. 1128 */ 1129 if (AR_SREV_9285(ah)) { 1130 /* For AR9285 the number of Fifos are reduced to half. 1131 * So set the usable tx buf size also to half to 1132 * avoid data/delimiter underruns 1133 */ 1134 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1135 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1136 } else if (!AR_SREV_9271(ah)) { 1137 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1138 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1139 } 1140 1141 REGWRITE_BUFFER_FLUSH(ah); 1142 1143 if (AR_SREV_9300_20_OR_LATER(ah)) 1144 ath9k_hw_reset_txstatus_ring(ah); 1145} 1146 1147static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1148{ 1149 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1150 u32 set = AR_STA_ID1_KSRCH_MODE; 1151 1152 switch (opmode) { 1153 case NL80211_IFTYPE_ADHOC: 1154 case NL80211_IFTYPE_MESH_POINT: 1155 set |= AR_STA_ID1_ADHOC; 1156 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1157 break; 1158 case NL80211_IFTYPE_AP: 1159 set |= AR_STA_ID1_STA_AP; 1160 /* fall through */ 1161 case NL80211_IFTYPE_STATION: 1162 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1163 break; 1164 default: 1165 if (!ah->is_monitoring) 1166 set = 0; 1167 break; 1168 } 1169 REG_RMW(ah, AR_STA_ID1, set, mask); 1170} 1171 1172void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1173 u32 *coef_mantissa, u32 *coef_exponent) 1174{ 1175 u32 coef_exp, coef_man; 1176 1177 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1178 if ((coef_scaled >> coef_exp) & 0x1) 1179 break; 1180 1181 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1182 1183 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1184 1185 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1186 *coef_exponent = coef_exp - 16; 1187} 1188 1189static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1190{ 1191 u32 rst_flags; 1192 u32 tmpReg; 1193 1194 if (AR_SREV_9100(ah)) { 1195 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1196 AR_RTC_DERIVED_CLK_PERIOD, 1); 1197 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1198 } 1199 1200 ENABLE_REGWRITE_BUFFER(ah); 1201 1202 if (AR_SREV_9300_20_OR_LATER(ah)) { 1203 REG_WRITE(ah, AR_WA, ah->WARegVal); 1204 udelay(10); 1205 } 1206 1207 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1208 AR_RTC_FORCE_WAKE_ON_INT); 1209 1210 if (AR_SREV_9100(ah)) { 1211 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1212 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1213 } else { 1214 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1215 if (tmpReg & 1216 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1217 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1218 u32 val; 1219 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1220 1221 val = AR_RC_HOSTIF; 1222 if (!AR_SREV_9300_20_OR_LATER(ah)) 1223 val |= AR_RC_AHB; 1224 REG_WRITE(ah, AR_RC, val); 1225 1226 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1227 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1228 1229 rst_flags = AR_RTC_RC_MAC_WARM; 1230 if (type == ATH9K_RESET_COLD) 1231 rst_flags |= AR_RTC_RC_MAC_COLD; 1232 } 1233 1234 if (AR_SREV_9330(ah)) { 1235 int npend = 0; 1236 int i; 1237 1238 /* AR9330 WAR: 1239 * call external reset function to reset WMAC if: 1240 * - doing a cold reset 1241 * - we have pending frames in the TX queues 1242 */ 1243 1244 for (i = 0; i < AR_NUM_QCU; i++) { 1245 npend = ath9k_hw_numtxpending(ah, i); 1246 if (npend) 1247 break; 1248 } 1249 1250 if (ah->external_reset && 1251 (npend || type == ATH9K_RESET_COLD)) { 1252 int reset_err = 0; 1253 1254 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1255 "reset MAC via external reset\n"); 1256 1257 reset_err = ah->external_reset(); 1258 if (reset_err) { 1259 ath_err(ath9k_hw_common(ah), 1260 "External reset failed, err=%d\n", 1261 reset_err); 1262 return false; 1263 } 1264 1265 REG_WRITE(ah, AR_RTC_RESET, 1); 1266 } 1267 } 1268 1269 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1270 1271 REGWRITE_BUFFER_FLUSH(ah); 1272 1273 udelay(50); 1274 1275 REG_WRITE(ah, AR_RTC_RC, 0); 1276 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1277 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1278 "RTC stuck in MAC reset\n"); 1279 return false; 1280 } 1281 1282 if (!AR_SREV_9100(ah)) 1283 REG_WRITE(ah, AR_RC, 0); 1284 1285 if (AR_SREV_9100(ah)) 1286 udelay(50); 1287 1288 return true; 1289} 1290 1291static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1292{ 1293 ENABLE_REGWRITE_BUFFER(ah); 1294 1295 if (AR_SREV_9300_20_OR_LATER(ah)) { 1296 REG_WRITE(ah, AR_WA, ah->WARegVal); 1297 udelay(10); 1298 } 1299 1300 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1301 AR_RTC_FORCE_WAKE_ON_INT); 1302 1303 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1304 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1305 1306 REG_WRITE(ah, AR_RTC_RESET, 0); 1307 1308 REGWRITE_BUFFER_FLUSH(ah); 1309 1310 if (!AR_SREV_9300_20_OR_LATER(ah)) 1311 udelay(2); 1312 1313 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1314 REG_WRITE(ah, AR_RC, 0); 1315 1316 REG_WRITE(ah, AR_RTC_RESET, 1); 1317 1318 if (!ath9k_hw_wait(ah, 1319 AR_RTC_STATUS, 1320 AR_RTC_STATUS_M, 1321 AR_RTC_STATUS_ON, 1322 AH_WAIT_TIMEOUT)) { 1323 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1324 "RTC not waking up\n"); 1325 return false; 1326 } 1327 1328 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1329} 1330 1331static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1332{ 1333 if (AR_SREV_9300_20_OR_LATER(ah)) { 1334 REG_WRITE(ah, AR_WA, ah->WARegVal); 1335 udelay(10); 1336 } 1337 1338 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1339 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1340 1341 switch (type) { 1342 case ATH9K_RESET_POWER_ON: 1343 return ath9k_hw_set_reset_power_on(ah); 1344 case ATH9K_RESET_WARM: 1345 case ATH9K_RESET_COLD: 1346 return ath9k_hw_set_reset(ah, type); 1347 default: 1348 return false; 1349 } 1350} 1351 1352static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1353 struct ath9k_channel *chan) 1354{ 1355 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1356 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1357 return false; 1358 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1359 return false; 1360 1361 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1362 return false; 1363 1364 ah->chip_fullsleep = false; 1365 ath9k_hw_init_pll(ah, chan); 1366 ath9k_hw_set_rfmode(ah, chan); 1367 1368 return true; 1369} 1370 1371static bool ath9k_hw_channel_change(struct ath_hw *ah, 1372 struct ath9k_channel *chan) 1373{ 1374 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1375 struct ath_common *common = ath9k_hw_common(ah); 1376 struct ieee80211_channel *channel = chan->chan; 1377 u32 qnum; 1378 int r; 1379 1380 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1381 if (ath9k_hw_numtxpending(ah, qnum)) { 1382 ath_dbg(common, ATH_DBG_QUEUE, 1383 "Transmit frames pending on queue %d\n", qnum); 1384 return false; 1385 } 1386 } 1387 1388 if (!ath9k_hw_rfbus_req(ah)) { 1389 ath_err(common, "Could not kill baseband RX\n"); 1390 return false; 1391 } 1392 1393 ath9k_hw_set_channel_regs(ah, chan); 1394 1395 r = ath9k_hw_rf_set_freq(ah, chan); 1396 if (r) { 1397 ath_err(common, "Failed to set channel\n"); 1398 return false; 1399 } 1400 ath9k_hw_set_clockrate(ah); 1401 1402 ah->eep_ops->set_txpower(ah, chan, 1403 ath9k_regd_get_ctl(regulatory, chan), 1404 channel->max_antenna_gain * 2, 1405 channel->max_power * 2, 1406 min((u32) MAX_RATE_POWER, 1407 (u32) regulatory->power_limit), false); 1408 1409 ath9k_hw_rfbus_done(ah); 1410 1411 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1412 ath9k_hw_set_delta_slope(ah, chan); 1413 1414 ath9k_hw_spur_mitigate_freq(ah, chan); 1415 1416 return true; 1417} 1418 1419static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1420{ 1421 u32 gpio_mask = ah->gpio_mask; 1422 int i; 1423 1424 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1425 if (!(gpio_mask & 1)) 1426 continue; 1427 1428 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1429 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1430 } 1431} 1432 1433bool ath9k_hw_check_alive(struct ath_hw *ah) 1434{ 1435 int count = 50; 1436 u32 reg; 1437 1438 if (AR_SREV_9285_12_OR_LATER(ah)) 1439 return true; 1440 1441 do { 1442 reg = REG_READ(ah, AR_OBS_BUS_1); 1443 1444 if ((reg & 0x7E7FFFEF) == 0x00702400) 1445 continue; 1446 1447 switch (reg & 0x7E000B00) { 1448 case 0x1E000000: 1449 case 0x52000B00: 1450 case 0x18000B00: 1451 continue; 1452 default: 1453 return true; 1454 } 1455 } while (count-- > 0); 1456 1457 return false; 1458} 1459EXPORT_SYMBOL(ath9k_hw_check_alive); 1460 1461int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1462 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1463{ 1464 struct ath_common *common = ath9k_hw_common(ah); 1465 u32 saveLedState; 1466 struct ath9k_channel *curchan = ah->curchan; 1467 u32 saveDefAntenna; 1468 u32 macStaId1; 1469 u64 tsf = 0; 1470 int i, r; 1471 1472 ah->txchainmask = common->tx_chainmask; 1473 ah->rxchainmask = common->rx_chainmask; 1474 1475 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1476 return -EIO; 1477 1478 if (curchan && !ah->chip_fullsleep) 1479 ath9k_hw_getnf(ah, curchan); 1480 1481 ah->caldata = caldata; 1482 if (caldata && 1483 (chan->channel != caldata->channel || 1484 (chan->channelFlags & ~CHANNEL_CW_INT) != 1485 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1486 /* Operating channel changed, reset channel calibration data */ 1487 memset(caldata, 0, sizeof(*caldata)); 1488 ath9k_init_nfcal_hist_buffer(ah, chan); 1489 } 1490 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1491 1492 if (bChannelChange && 1493 (ah->chip_fullsleep != true) && 1494 (ah->curchan != NULL) && 1495 (chan->channel != ah->curchan->channel) && 1496 ((chan->channelFlags & CHANNEL_ALL) == 1497 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1498 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { 1499 1500 if (ath9k_hw_channel_change(ah, chan)) { 1501 ath9k_hw_loadnf(ah, ah->curchan); 1502 ath9k_hw_start_nfcal(ah, true); 1503 if (AR_SREV_9271(ah)) 1504 ar9002_hw_load_ani_reg(ah, chan); 1505 return 0; 1506 } 1507 } 1508 1509 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1510 if (saveDefAntenna == 0) 1511 saveDefAntenna = 1; 1512 1513 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1514 1515 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1516 if (AR_SREV_9100(ah) || 1517 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1518 tsf = ath9k_hw_gettsf64(ah); 1519 1520 saveLedState = REG_READ(ah, AR_CFG_LED) & 1521 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1522 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1523 1524 ath9k_hw_mark_phy_inactive(ah); 1525 1526 ah->paprd_table_write_done = false; 1527 1528 /* Only required on the first reset */ 1529 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1530 REG_WRITE(ah, 1531 AR9271_RESET_POWER_DOWN_CONTROL, 1532 AR9271_RADIO_RF_RST); 1533 udelay(50); 1534 } 1535 1536 if (!ath9k_hw_chip_reset(ah, chan)) { 1537 ath_err(common, "Chip reset failed\n"); 1538 return -EINVAL; 1539 } 1540 1541 /* Only required on the first reset */ 1542 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1543 ah->htc_reset_init = false; 1544 REG_WRITE(ah, 1545 AR9271_RESET_POWER_DOWN_CONTROL, 1546 AR9271_GATE_MAC_CTL); 1547 udelay(50); 1548 } 1549 1550 /* Restore TSF */ 1551 if (tsf) 1552 ath9k_hw_settsf64(ah, tsf); 1553 1554 if (AR_SREV_9280_20_OR_LATER(ah)) 1555 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1556 1557 if (!AR_SREV_9300_20_OR_LATER(ah)) 1558 ar9002_hw_enable_async_fifo(ah); 1559 1560 r = ath9k_hw_process_ini(ah, chan); 1561 if (r) 1562 return r; 1563 1564 /* 1565 * Some AR91xx SoC devices frequently fail to accept TSF writes 1566 * right after the chip reset. When that happens, write a new 1567 * value after the initvals have been applied, with an offset 1568 * based on measured time difference 1569 */ 1570 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1571 tsf += 1500; 1572 ath9k_hw_settsf64(ah, tsf); 1573 } 1574 1575 /* Setup MFP options for CCMP */ 1576 if (AR_SREV_9280_20_OR_LATER(ah)) { 1577 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1578 * frames when constructing CCMP AAD. */ 1579 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1580 0xc7ff); 1581 ah->sw_mgmt_crypto = false; 1582 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1583 /* Disable hardware crypto for management frames */ 1584 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1585 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1586 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1587 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1588 ah->sw_mgmt_crypto = true; 1589 } else 1590 ah->sw_mgmt_crypto = true; 1591 1592 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1593 ath9k_hw_set_delta_slope(ah, chan); 1594 1595 ath9k_hw_spur_mitigate_freq(ah, chan); 1596 ah->eep_ops->set_board_values(ah, chan); 1597 1598 ENABLE_REGWRITE_BUFFER(ah); 1599 1600 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1601 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1602 | macStaId1 1603 | AR_STA_ID1_RTS_USE_DEF 1604 | (ah->config. 1605 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1606 | ah->sta_id1_defaults); 1607 ath_hw_setbssidmask(common); 1608 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1609 ath9k_hw_write_associd(ah); 1610 REG_WRITE(ah, AR_ISR, ~0); 1611 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1612 1613 REGWRITE_BUFFER_FLUSH(ah); 1614 1615 ath9k_hw_set_operating_mode(ah, ah->opmode); 1616 1617 r = ath9k_hw_rf_set_freq(ah, chan); 1618 if (r) 1619 return r; 1620 1621 ath9k_hw_set_clockrate(ah); 1622 1623 ENABLE_REGWRITE_BUFFER(ah); 1624 1625 for (i = 0; i < AR_NUM_DCU; i++) 1626 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1627 1628 REGWRITE_BUFFER_FLUSH(ah); 1629 1630 ah->intr_txqs = 0; 1631 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1632 ath9k_hw_resettxqueue(ah, i); 1633 1634 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1635 ath9k_hw_ani_cache_ini_regs(ah); 1636 ath9k_hw_init_qos(ah); 1637 1638 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1639 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1640 1641 ath9k_hw_init_global_settings(ah); 1642 1643 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1644 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1645 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1646 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1647 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1648 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1649 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1650 } 1651 1652 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1653 1654 ath9k_hw_set_dma(ah); 1655 1656 REG_WRITE(ah, AR_OBS, 8); 1657 1658 if (ah->config.rx_intr_mitigation) { 1659 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1660 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1661 } 1662 1663 if (ah->config.tx_intr_mitigation) { 1664 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1665 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1666 } 1667 1668 ath9k_hw_init_bb(ah, chan); 1669 1670 if (!ath9k_hw_init_cal(ah, chan)) 1671 return -EIO; 1672 1673 ENABLE_REGWRITE_BUFFER(ah); 1674 1675 ath9k_hw_restore_chainmask(ah); 1676 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1677 1678 REGWRITE_BUFFER_FLUSH(ah); 1679 1680 /* 1681 * For big endian systems turn on swapping for descriptors 1682 */ 1683 if (AR_SREV_9100(ah)) { 1684 u32 mask; 1685 mask = REG_READ(ah, AR_CFG); 1686 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1687 ath_dbg(common, ATH_DBG_RESET, 1688 "CFG Byte Swap Set 0x%x\n", mask); 1689 } else { 1690 mask = 1691 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1692 REG_WRITE(ah, AR_CFG, mask); 1693 ath_dbg(common, ATH_DBG_RESET, 1694 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1695 } 1696 } else { 1697 if (common->bus_ops->ath_bus_type == ATH_USB) { 1698 /* Configure AR9271 target WLAN */ 1699 if (AR_SREV_9271(ah)) 1700 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1701 else 1702 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1703 } 1704#ifdef __BIG_ENDIAN 1705 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) 1706 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1707 else 1708 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1709#endif 1710 } 1711 1712 if (ah->btcoex_hw.enabled) 1713 ath9k_hw_btcoex_enable(ah); 1714 1715 if (AR_SREV_9300_20_OR_LATER(ah)) { 1716 ar9003_hw_bb_watchdog_config(ah); 1717 1718 ar9003_hw_disable_phy_restart(ah); 1719 } 1720 1721 ath9k_hw_apply_gpio_override(ah); 1722 1723 return 0; 1724} 1725EXPORT_SYMBOL(ath9k_hw_reset); 1726 1727/******************************/ 1728/* Power Management (Chipset) */ 1729/******************************/ 1730 1731/* 1732 * Notify Power Mgt is disabled in self-generated frames. 1733 * If requested, force chip to sleep. 1734 */ 1735static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1736{ 1737 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1738 if (setChip) { 1739 /* 1740 * Clear the RTC force wake bit to allow the 1741 * mac to go to sleep. 1742 */ 1743 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1744 AR_RTC_FORCE_WAKE_EN); 1745 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1746 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1747 1748 /* Shutdown chip. Active low */ 1749 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1750 REG_CLR_BIT(ah, (AR_RTC_RESET), 1751 AR_RTC_RESET_EN); 1752 } 1753 1754 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1755 if (AR_SREV_9300_20_OR_LATER(ah)) 1756 REG_WRITE(ah, AR_WA, 1757 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1758} 1759 1760/* 1761 * Notify Power Management is enabled in self-generating 1762 * frames. If request, set power mode of chip to 1763 * auto/normal. Duration in units of 128us (1/8 TU). 1764 */ 1765static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1766{ 1767 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1768 if (setChip) { 1769 struct ath9k_hw_capabilities *pCap = &ah->caps; 1770 1771 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1772 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1773 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1774 AR_RTC_FORCE_WAKE_ON_INT); 1775 } else { 1776 /* 1777 * Clear the RTC force wake bit to allow the 1778 * mac to go to sleep. 1779 */ 1780 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1781 AR_RTC_FORCE_WAKE_EN); 1782 } 1783 } 1784 1785 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1786 if (AR_SREV_9300_20_OR_LATER(ah)) 1787 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1788} 1789 1790static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1791{ 1792 u32 val; 1793 int i; 1794 1795 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1796 if (AR_SREV_9300_20_OR_LATER(ah)) { 1797 REG_WRITE(ah, AR_WA, ah->WARegVal); 1798 udelay(10); 1799 } 1800 1801 if (setChip) { 1802 if ((REG_READ(ah, AR_RTC_STATUS) & 1803 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1804 if (ath9k_hw_set_reset_reg(ah, 1805 ATH9K_RESET_POWER_ON) != true) { 1806 return false; 1807 } 1808 if (!AR_SREV_9300_20_OR_LATER(ah)) 1809 ath9k_hw_init_pll(ah, NULL); 1810 } 1811 if (AR_SREV_9100(ah)) 1812 REG_SET_BIT(ah, AR_RTC_RESET, 1813 AR_RTC_RESET_EN); 1814 1815 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1816 AR_RTC_FORCE_WAKE_EN); 1817 udelay(50); 1818 1819 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1820 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1821 if (val == AR_RTC_STATUS_ON) 1822 break; 1823 udelay(50); 1824 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1825 AR_RTC_FORCE_WAKE_EN); 1826 } 1827 if (i == 0) { 1828 ath_err(ath9k_hw_common(ah), 1829 "Failed to wakeup in %uus\n", 1830 POWER_UP_TIME / 20); 1831 return false; 1832 } 1833 } 1834 1835 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1836 1837 return true; 1838} 1839 1840bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1841{ 1842 struct ath_common *common = ath9k_hw_common(ah); 1843 int status = true, setChip = true; 1844 static const char *modes[] = { 1845 "AWAKE", 1846 "FULL-SLEEP", 1847 "NETWORK SLEEP", 1848 "UNDEFINED" 1849 }; 1850 1851 if (ah->power_mode == mode) 1852 return status; 1853 1854 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", 1855 modes[ah->power_mode], modes[mode]); 1856 1857 switch (mode) { 1858 case ATH9K_PM_AWAKE: 1859 status = ath9k_hw_set_power_awake(ah, setChip); 1860 break; 1861 case ATH9K_PM_FULL_SLEEP: 1862 ath9k_set_power_sleep(ah, setChip); 1863 ah->chip_fullsleep = true; 1864 break; 1865 case ATH9K_PM_NETWORK_SLEEP: 1866 ath9k_set_power_network_sleep(ah, setChip); 1867 break; 1868 default: 1869 ath_err(common, "Unknown power mode %u\n", mode); 1870 return false; 1871 } 1872 ah->power_mode = mode; 1873 1874 /* 1875 * XXX: If this warning never comes up after a while then 1876 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 1877 * ath9k_hw_setpower() return type void. 1878 */ 1879 1880 if (!(ah->ah_flags & AH_UNPLUGGED)) 1881 ATH_DBG_WARN_ON_ONCE(!status); 1882 1883 return status; 1884} 1885EXPORT_SYMBOL(ath9k_hw_setpower); 1886 1887/*******************/ 1888/* Beacon Handling */ 1889/*******************/ 1890 1891void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1892{ 1893 int flags = 0; 1894 1895 ENABLE_REGWRITE_BUFFER(ah); 1896 1897 switch (ah->opmode) { 1898 case NL80211_IFTYPE_ADHOC: 1899 case NL80211_IFTYPE_MESH_POINT: 1900 REG_SET_BIT(ah, AR_TXCFG, 1901 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1902 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 1903 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 1904 flags |= AR_NDP_TIMER_EN; 1905 case NL80211_IFTYPE_AP: 1906 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 1907 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 1908 TU_TO_USEC(ah->config.dma_beacon_response_time)); 1909 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 1910 TU_TO_USEC(ah->config.sw_beacon_response_time)); 1911 flags |= 1912 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1913 break; 1914 default: 1915 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, 1916 "%s: unsupported opmode: %d\n", 1917 __func__, ah->opmode); 1918 return; 1919 break; 1920 } 1921 1922 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 1923 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 1924 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 1925 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 1926 1927 REGWRITE_BUFFER_FLUSH(ah); 1928 1929 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1930} 1931EXPORT_SYMBOL(ath9k_hw_beaconinit); 1932 1933void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1934 const struct ath9k_beacon_state *bs) 1935{ 1936 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 1937 struct ath9k_hw_capabilities *pCap = &ah->caps; 1938 struct ath_common *common = ath9k_hw_common(ah); 1939 1940 ENABLE_REGWRITE_BUFFER(ah); 1941 1942 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1943 1944 REG_WRITE(ah, AR_BEACON_PERIOD, 1945 TU_TO_USEC(bs->bs_intval)); 1946 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1947 TU_TO_USEC(bs->bs_intval)); 1948 1949 REGWRITE_BUFFER_FLUSH(ah); 1950 1951 REG_RMW_FIELD(ah, AR_RSSI_THR, 1952 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1953 1954 beaconintval = bs->bs_intval; 1955 1956 if (bs->bs_sleepduration > beaconintval) 1957 beaconintval = bs->bs_sleepduration; 1958 1959 dtimperiod = bs->bs_dtimperiod; 1960 if (bs->bs_sleepduration > dtimperiod) 1961 dtimperiod = bs->bs_sleepduration; 1962 1963 if (beaconintval == dtimperiod) 1964 nextTbtt = bs->bs_nextdtim; 1965 else 1966 nextTbtt = bs->bs_nexttbtt; 1967 1968 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 1969 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 1970 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1971 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1972 1973 ENABLE_REGWRITE_BUFFER(ah); 1974 1975 REG_WRITE(ah, AR_NEXT_DTIM, 1976 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 1977 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 1978 1979 REG_WRITE(ah, AR_SLEEP1, 1980 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 1981 | AR_SLEEP1_ASSUME_DTIM); 1982 1983 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 1984 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 1985 else 1986 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 1987 1988 REG_WRITE(ah, AR_SLEEP2, 1989 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 1990 1991 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 1992 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1993 1994 REGWRITE_BUFFER_FLUSH(ah); 1995 1996 REG_SET_BIT(ah, AR_TIMER_MODE, 1997 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1998 AR_DTIM_TIMER_EN); 1999 2000 /* TSF Out of Range Threshold */ 2001 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2002} 2003EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2004 2005/*******************/ 2006/* HW Capabilities */ 2007/*******************/ 2008 2009static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2010{ 2011 eeprom_chainmask &= chip_chainmask; 2012 if (eeprom_chainmask) 2013 return eeprom_chainmask; 2014 else 2015 return chip_chainmask; 2016} 2017 2018int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2019{ 2020 struct ath9k_hw_capabilities *pCap = &ah->caps; 2021 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2022 struct ath_common *common = ath9k_hw_common(ah); 2023 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 2024 unsigned int chip_chainmask; 2025 2026 u16 eeval; 2027 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2028 2029 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2030 regulatory->current_rd = eeval; 2031 2032 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 2033 if (AR_SREV_9285_12_OR_LATER(ah)) 2034 eeval |= AR9285_RDEXT_DEFAULT; 2035 regulatory->current_rd_ext = eeval; 2036 2037 if (ah->opmode != NL80211_IFTYPE_AP && 2038 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2039 if (regulatory->current_rd == 0x64 || 2040 regulatory->current_rd == 0x65) 2041 regulatory->current_rd += 5; 2042 else if (regulatory->current_rd == 0x41) 2043 regulatory->current_rd = 0x43; 2044 ath_dbg(common, ATH_DBG_REGULATORY, 2045 "regdomain mapped to 0x%x\n", regulatory->current_rd); 2046 } 2047 2048 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2049 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2050 ath_err(common, 2051 "no band has been marked as supported in EEPROM\n"); 2052 return -EINVAL; 2053 } 2054 2055 if (eeval & AR5416_OPFLAGS_11A) 2056 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2057 2058 if (eeval & AR5416_OPFLAGS_11G) 2059 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2060 2061 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2062 chip_chainmask = 1; 2063 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2064 chip_chainmask = 7; 2065 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2066 chip_chainmask = 3; 2067 else 2068 chip_chainmask = 7; 2069 2070 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2071 /* 2072 * For AR9271 we will temporarilly uses the rx chainmax as read from 2073 * the EEPROM. 2074 */ 2075 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2076 !(eeval & AR5416_OPFLAGS_11A) && 2077 !(AR_SREV_9271(ah))) 2078 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2079 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2080 else if (AR_SREV_9100(ah)) 2081 pCap->rx_chainmask = 0x7; 2082 else 2083 /* Use rx_chainmask from EEPROM. */ 2084 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2085 2086 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2087 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2088 2089 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2090 2091 /* enable key search for every frame in an aggregate */ 2092 if (AR_SREV_9300_20_OR_LATER(ah)) 2093 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2094 2095 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2096 2097 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2098 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2099 else 2100 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2101 2102 if (AR_SREV_9271(ah)) 2103 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2104 else if (AR_DEVID_7010(ah)) 2105 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2106 else if (AR_SREV_9285_12_OR_LATER(ah)) 2107 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2108 else if (AR_SREV_9280_20_OR_LATER(ah)) 2109 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2110 else 2111 pCap->num_gpio_pins = AR_NUM_GPIO; 2112 2113 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 2114 pCap->hw_caps |= ATH9K_HW_CAP_CST; 2115 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2116 } else { 2117 pCap->rts_aggr_limit = (8 * 1024); 2118 } 2119 2120#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2121 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2122 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2123 ah->rfkill_gpio = 2124 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2125 ah->rfkill_polarity = 2126 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2127 2128 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2129 } 2130#endif 2131 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2132 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2133 else 2134 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2135 2136 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2137 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2138 else 2139 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2140 2141 if (common->btcoex_enabled) { 2142 if (AR_SREV_9300_20_OR_LATER(ah)) { 2143 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2144 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300; 2145 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300; 2146 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300; 2147 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 2148 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280; 2149 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280; 2150 2151 if (AR_SREV_9285(ah)) { 2152 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2153 btcoex_hw->btpriority_gpio = 2154 ATH_BTPRIORITY_GPIO_9285; 2155 } else { 2156 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 2157 } 2158 } 2159 } else { 2160 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2161 } 2162 2163 if (AR_SREV_9300_20_OR_LATER(ah)) { 2164 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2165 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2166 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2167 2168 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2169 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2170 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2171 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2172 pCap->txs_len = sizeof(struct ar9003_txs); 2173 if (!ah->config.paprd_disable && 2174 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2175 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2176 } else { 2177 pCap->tx_desc_len = sizeof(struct ath_desc); 2178 if (AR_SREV_9280_20(ah)) 2179 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2180 } 2181 2182 if (AR_SREV_9300_20_OR_LATER(ah)) 2183 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2184 2185 if (AR_SREV_9300_20_OR_LATER(ah)) 2186 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2187 2188 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2189 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2190 2191 if (AR_SREV_9285(ah)) 2192 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2193 ant_div_ctl1 = 2194 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2195 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2196 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2197 } 2198 if (AR_SREV_9300_20_OR_LATER(ah)) { 2199 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2200 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2201 } 2202 2203 2204 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2205 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2206 /* 2207 * enable the diversity-combining algorithm only when 2208 * both enable_lna_div and enable_fast_div are set 2209 * Table for Diversity 2210 * ant_div_alt_lnaconf bit 0-1 2211 * ant_div_main_lnaconf bit 2-3 2212 * ant_div_alt_gaintb bit 4 2213 * ant_div_main_gaintb bit 5 2214 * enable_ant_div_lnadiv bit 6 2215 * enable_ant_fast_div bit 7 2216 */ 2217 if ((ant_div_ctl1 >> 0x6) == 0x3) 2218 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2219 } 2220 2221 if (AR_SREV_9485_10(ah)) { 2222 pCap->pcie_lcr_extsync_en = true; 2223 pCap->pcie_lcr_offset = 0x80; 2224 } 2225 2226 tx_chainmask = pCap->tx_chainmask; 2227 rx_chainmask = pCap->rx_chainmask; 2228 while (tx_chainmask || rx_chainmask) { 2229 if (tx_chainmask & BIT(0)) 2230 pCap->max_txchains++; 2231 if (rx_chainmask & BIT(0)) 2232 pCap->max_rxchains++; 2233 2234 tx_chainmask >>= 1; 2235 rx_chainmask >>= 1; 2236 } 2237 2238 return 0; 2239} 2240 2241/****************************/ 2242/* GPIO / RFKILL / Antennae */ 2243/****************************/ 2244 2245static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2246 u32 gpio, u32 type) 2247{ 2248 int addr; 2249 u32 gpio_shift, tmp; 2250 2251 if (gpio > 11) 2252 addr = AR_GPIO_OUTPUT_MUX3; 2253 else if (gpio > 5) 2254 addr = AR_GPIO_OUTPUT_MUX2; 2255 else 2256 addr = AR_GPIO_OUTPUT_MUX1; 2257 2258 gpio_shift = (gpio % 6) * 5; 2259 2260 if (AR_SREV_9280_20_OR_LATER(ah) 2261 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2262 REG_RMW(ah, addr, (type << gpio_shift), 2263 (0x1f << gpio_shift)); 2264 } else { 2265 tmp = REG_READ(ah, addr); 2266 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2267 tmp &= ~(0x1f << gpio_shift); 2268 tmp |= (type << gpio_shift); 2269 REG_WRITE(ah, addr, tmp); 2270 } 2271} 2272 2273void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2274{ 2275 u32 gpio_shift; 2276 2277 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2278 2279 if (AR_DEVID_7010(ah)) { 2280 gpio_shift = gpio; 2281 REG_RMW(ah, AR7010_GPIO_OE, 2282 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2283 (AR7010_GPIO_OE_MASK << gpio_shift)); 2284 return; 2285 } 2286 2287 gpio_shift = gpio << 1; 2288 REG_RMW(ah, 2289 AR_GPIO_OE_OUT, 2290 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2291 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2292} 2293EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2294 2295u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2296{ 2297#define MS_REG_READ(x, y) \ 2298 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2299 2300 if (gpio >= ah->caps.num_gpio_pins) 2301 return 0xffffffff; 2302 2303 if (AR_DEVID_7010(ah)) { 2304 u32 val; 2305 val = REG_READ(ah, AR7010_GPIO_IN); 2306 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2307 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2308 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2309 AR_GPIO_BIT(gpio)) != 0; 2310 else if (AR_SREV_9271(ah)) 2311 return MS_REG_READ(AR9271, gpio) != 0; 2312 else if (AR_SREV_9287_11_OR_LATER(ah)) 2313 return MS_REG_READ(AR9287, gpio) != 0; 2314 else if (AR_SREV_9285_12_OR_LATER(ah)) 2315 return MS_REG_READ(AR9285, gpio) != 0; 2316 else if (AR_SREV_9280_20_OR_LATER(ah)) 2317 return MS_REG_READ(AR928X, gpio) != 0; 2318 else 2319 return MS_REG_READ(AR, gpio) != 0; 2320} 2321EXPORT_SYMBOL(ath9k_hw_gpio_get); 2322 2323void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2324 u32 ah_signal_type) 2325{ 2326 u32 gpio_shift; 2327 2328 if (AR_DEVID_7010(ah)) { 2329 gpio_shift = gpio; 2330 REG_RMW(ah, AR7010_GPIO_OE, 2331 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2332 (AR7010_GPIO_OE_MASK << gpio_shift)); 2333 return; 2334 } 2335 2336 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2337 gpio_shift = 2 * gpio; 2338 REG_RMW(ah, 2339 AR_GPIO_OE_OUT, 2340 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2341 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2342} 2343EXPORT_SYMBOL(ath9k_hw_cfg_output); 2344 2345void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2346{ 2347 if (AR_DEVID_7010(ah)) { 2348 val = val ? 0 : 1; 2349 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2350 AR_GPIO_BIT(gpio)); 2351 return; 2352 } 2353 2354 if (AR_SREV_9271(ah)) 2355 val = ~val; 2356 2357 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2358 AR_GPIO_BIT(gpio)); 2359} 2360EXPORT_SYMBOL(ath9k_hw_set_gpio); 2361 2362u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2363{ 2364 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2365} 2366EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2367 2368void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2369{ 2370 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2371} 2372EXPORT_SYMBOL(ath9k_hw_setantenna); 2373 2374/*********************/ 2375/* General Operation */ 2376/*********************/ 2377 2378u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2379{ 2380 u32 bits = REG_READ(ah, AR_RX_FILTER); 2381 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2382 2383 if (phybits & AR_PHY_ERR_RADAR) 2384 bits |= ATH9K_RX_FILTER_PHYRADAR; 2385 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2386 bits |= ATH9K_RX_FILTER_PHYERR; 2387 2388 return bits; 2389} 2390EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2391 2392void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2393{ 2394 u32 phybits; 2395 2396 ENABLE_REGWRITE_BUFFER(ah); 2397 2398 REG_WRITE(ah, AR_RX_FILTER, bits); 2399 2400 phybits = 0; 2401 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2402 phybits |= AR_PHY_ERR_RADAR; 2403 if (bits & ATH9K_RX_FILTER_PHYERR) 2404 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2405 REG_WRITE(ah, AR_PHY_ERR, phybits); 2406 2407 if (phybits) 2408 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2409 else 2410 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2411 2412 REGWRITE_BUFFER_FLUSH(ah); 2413} 2414EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2415 2416bool ath9k_hw_phy_disable(struct ath_hw *ah) 2417{ 2418 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2419 return false; 2420 2421 ath9k_hw_init_pll(ah, NULL); 2422 return true; 2423} 2424EXPORT_SYMBOL(ath9k_hw_phy_disable); 2425 2426bool ath9k_hw_disable(struct ath_hw *ah) 2427{ 2428 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2429 return false; 2430 2431 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2432 return false; 2433 2434 ath9k_hw_init_pll(ah, NULL); 2435 return true; 2436} 2437EXPORT_SYMBOL(ath9k_hw_disable); 2438 2439void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2440{ 2441 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2442 struct ath9k_channel *chan = ah->curchan; 2443 struct ieee80211_channel *channel = chan->chan; 2444 int reg_pwr = min_t(int, MAX_RATE_POWER, regulatory->power_limit); 2445 int chan_pwr = channel->max_power * 2; 2446 2447 if (test) 2448 reg_pwr = chan_pwr = MAX_RATE_POWER; 2449 2450 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 2451 2452 ah->eep_ops->set_txpower(ah, chan, 2453 ath9k_regd_get_ctl(regulatory, chan), 2454 channel->max_antenna_gain * 2, 2455 chan_pwr, reg_pwr, test); 2456} 2457EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2458 2459void ath9k_hw_setopmode(struct ath_hw *ah) 2460{ 2461 ath9k_hw_set_operating_mode(ah, ah->opmode); 2462} 2463EXPORT_SYMBOL(ath9k_hw_setopmode); 2464 2465void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2466{ 2467 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2468 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2469} 2470EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2471 2472void ath9k_hw_write_associd(struct ath_hw *ah) 2473{ 2474 struct ath_common *common = ath9k_hw_common(ah); 2475 2476 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2477 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2478 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2479} 2480EXPORT_SYMBOL(ath9k_hw_write_associd); 2481 2482#define ATH9K_MAX_TSF_READ 10 2483 2484u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2485{ 2486 u32 tsf_lower, tsf_upper1, tsf_upper2; 2487 int i; 2488 2489 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2490 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2491 tsf_lower = REG_READ(ah, AR_TSF_L32); 2492 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2493 if (tsf_upper2 == tsf_upper1) 2494 break; 2495 tsf_upper1 = tsf_upper2; 2496 } 2497 2498 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2499 2500 return (((u64)tsf_upper1 << 32) | tsf_lower); 2501} 2502EXPORT_SYMBOL(ath9k_hw_gettsf64); 2503 2504void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2505{ 2506 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2507 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2508} 2509EXPORT_SYMBOL(ath9k_hw_settsf64); 2510 2511void ath9k_hw_reset_tsf(struct ath_hw *ah) 2512{ 2513 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2514 AH_TSF_WRITE_TIMEOUT)) 2515 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 2516 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2517 2518 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2519} 2520EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2521 2522void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2523{ 2524 if (setting) 2525 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2526 else 2527 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2528} 2529EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2530 2531void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2532{ 2533 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2534 u32 macmode; 2535 2536 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2537 macmode = AR_2040_JOINED_RX_CLEAR; 2538 else 2539 macmode = 0; 2540 2541 REG_WRITE(ah, AR_2040_MODE, macmode); 2542} 2543 2544/* HW Generic timers configuration */ 2545 2546static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2547{ 2548 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2549 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2550 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2551 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2552 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2553 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2554 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2555 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2556 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2557 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2558 AR_NDP2_TIMER_MODE, 0x0002}, 2559 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2560 AR_NDP2_TIMER_MODE, 0x0004}, 2561 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2562 AR_NDP2_TIMER_MODE, 0x0008}, 2563 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2564 AR_NDP2_TIMER_MODE, 0x0010}, 2565 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2566 AR_NDP2_TIMER_MODE, 0x0020}, 2567 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2568 AR_NDP2_TIMER_MODE, 0x0040}, 2569 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2570 AR_NDP2_TIMER_MODE, 0x0080} 2571}; 2572 2573/* HW generic timer primitives */ 2574 2575/* compute and clear index of rightmost 1 */ 2576static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2577{ 2578 u32 b; 2579 2580 b = *mask; 2581 b &= (0-b); 2582 *mask &= ~b; 2583 b *= debruijn32; 2584 b >>= 27; 2585 2586 return timer_table->gen_timer_index[b]; 2587} 2588 2589u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2590{ 2591 return REG_READ(ah, AR_TSF_L32); 2592} 2593EXPORT_SYMBOL(ath9k_hw_gettsf32); 2594 2595struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2596 void (*trigger)(void *), 2597 void (*overflow)(void *), 2598 void *arg, 2599 u8 timer_index) 2600{ 2601 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2602 struct ath_gen_timer *timer; 2603 2604 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2605 2606 if (timer == NULL) { 2607 ath_err(ath9k_hw_common(ah), 2608 "Failed to allocate memory for hw timer[%d]\n", 2609 timer_index); 2610 return NULL; 2611 } 2612 2613 /* allocate a hardware generic timer slot */ 2614 timer_table->timers[timer_index] = timer; 2615 timer->index = timer_index; 2616 timer->trigger = trigger; 2617 timer->overflow = overflow; 2618 timer->arg = arg; 2619 2620 return timer; 2621} 2622EXPORT_SYMBOL(ath_gen_timer_alloc); 2623 2624void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2625 struct ath_gen_timer *timer, 2626 u32 trig_timeout, 2627 u32 timer_period) 2628{ 2629 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2630 u32 tsf, timer_next; 2631 2632 BUG_ON(!timer_period); 2633 2634 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2635 2636 tsf = ath9k_hw_gettsf32(ah); 2637 2638 timer_next = tsf + trig_timeout; 2639 2640 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2641 "current tsf %x period %x timer_next %x\n", 2642 tsf, timer_period, timer_next); 2643 2644 /* 2645 * Program generic timer registers 2646 */ 2647 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2648 timer_next); 2649 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2650 timer_period); 2651 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2652 gen_tmr_configuration[timer->index].mode_mask); 2653 2654 /* Enable both trigger and thresh interrupt masks */ 2655 REG_SET_BIT(ah, AR_IMR_S5, 2656 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2657 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2658} 2659EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2660 2661void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2662{ 2663 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2664 2665 if ((timer->index < AR_FIRST_NDP_TIMER) || 2666 (timer->index >= ATH_MAX_GEN_TIMER)) { 2667 return; 2668 } 2669 2670 /* Clear generic timer enable bits. */ 2671 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2672 gen_tmr_configuration[timer->index].mode_mask); 2673 2674 /* Disable both trigger and thresh interrupt masks */ 2675 REG_CLR_BIT(ah, AR_IMR_S5, 2676 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2677 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2678 2679 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2680} 2681EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2682 2683void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2684{ 2685 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2686 2687 /* free the hardware generic timer slot */ 2688 timer_table->timers[timer->index] = NULL; 2689 kfree(timer); 2690} 2691EXPORT_SYMBOL(ath_gen_timer_free); 2692 2693/* 2694 * Generic Timer Interrupts handling 2695 */ 2696void ath_gen_timer_isr(struct ath_hw *ah) 2697{ 2698 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2699 struct ath_gen_timer *timer; 2700 struct ath_common *common = ath9k_hw_common(ah); 2701 u32 trigger_mask, thresh_mask, index; 2702 2703 /* get hardware generic timer interrupt status */ 2704 trigger_mask = ah->intr_gen_timer_trigger; 2705 thresh_mask = ah->intr_gen_timer_thresh; 2706 trigger_mask &= timer_table->timer_mask.val; 2707 thresh_mask &= timer_table->timer_mask.val; 2708 2709 trigger_mask &= ~thresh_mask; 2710 2711 while (thresh_mask) { 2712 index = rightmost_index(timer_table, &thresh_mask); 2713 timer = timer_table->timers[index]; 2714 BUG_ON(!timer); 2715 ath_dbg(common, ATH_DBG_HWTIMER, 2716 "TSF overflow for Gen timer %d\n", index); 2717 timer->overflow(timer->arg); 2718 } 2719 2720 while (trigger_mask) { 2721 index = rightmost_index(timer_table, &trigger_mask); 2722 timer = timer_table->timers[index]; 2723 BUG_ON(!timer); 2724 ath_dbg(common, ATH_DBG_HWTIMER, 2725 "Gen timer[%d] trigger\n", index); 2726 timer->trigger(timer->arg); 2727 } 2728} 2729EXPORT_SYMBOL(ath_gen_timer_isr); 2730 2731/********/ 2732/* HTC */ 2733/********/ 2734 2735void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2736{ 2737 ah->htc_reset_init = true; 2738} 2739EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2740 2741static struct { 2742 u32 version; 2743 const char * name; 2744} ath_mac_bb_names[] = { 2745 /* Devices with external radios */ 2746 { AR_SREV_VERSION_5416_PCI, "5416" }, 2747 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2748 { AR_SREV_VERSION_9100, "9100" }, 2749 { AR_SREV_VERSION_9160, "9160" }, 2750 /* Single-chip solutions */ 2751 { AR_SREV_VERSION_9280, "9280" }, 2752 { AR_SREV_VERSION_9285, "9285" }, 2753 { AR_SREV_VERSION_9287, "9287" }, 2754 { AR_SREV_VERSION_9271, "9271" }, 2755 { AR_SREV_VERSION_9300, "9300" }, 2756 { AR_SREV_VERSION_9330, "9330" }, 2757 { AR_SREV_VERSION_9340, "9340" }, 2758 { AR_SREV_VERSION_9485, "9485" }, 2759}; 2760 2761/* For devices with external radios */ 2762static struct { 2763 u16 version; 2764 const char * name; 2765} ath_rf_names[] = { 2766 { 0, "5133" }, 2767 { AR_RAD5133_SREV_MAJOR, "5133" }, 2768 { AR_RAD5122_SREV_MAJOR, "5122" }, 2769 { AR_RAD2133_SREV_MAJOR, "2133" }, 2770 { AR_RAD2122_SREV_MAJOR, "2122" } 2771}; 2772 2773/* 2774 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2775 */ 2776static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2777{ 2778 int i; 2779 2780 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2781 if (ath_mac_bb_names[i].version == mac_bb_version) { 2782 return ath_mac_bb_names[i].name; 2783 } 2784 } 2785 2786 return "????"; 2787} 2788 2789/* 2790 * Return the RF name. "????" is returned if the RF is unknown. 2791 * Used for devices with external radios. 2792 */ 2793static const char *ath9k_hw_rf_name(u16 rf_version) 2794{ 2795 int i; 2796 2797 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2798 if (ath_rf_names[i].version == rf_version) { 2799 return ath_rf_names[i].name; 2800 } 2801 } 2802 2803 return "????"; 2804} 2805 2806void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2807{ 2808 int used; 2809 2810 /* chipsets >= AR9280 are single-chip */ 2811 if (AR_SREV_9280_20_OR_LATER(ah)) { 2812 used = snprintf(hw_name, len, 2813 "Atheros AR%s Rev:%x", 2814 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2815 ah->hw_version.macRev); 2816 } 2817 else { 2818 used = snprintf(hw_name, len, 2819 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2820 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2821 ah->hw_version.macRev, 2822 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2823 AR_RADIO_SREV_MAJOR)), 2824 ah->hw_version.phyRev); 2825 } 2826 2827 hw_name[used] = '\0'; 2828} 2829EXPORT_SYMBOL(ath9k_hw_name); 2830