hw.c revision 6a0ec30ad4acae63a81526ca8c157f718904993b
1/* 2 * Copyright (c) 2008-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <asm/unaligned.h> 20 21#include "hw.h" 22#include "hw-ops.h" 23#include "rc.h" 24#include "ar9003_mac.h" 25 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 27 28MODULE_AUTHOR("Atheros Communications"); 29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 31MODULE_LICENSE("Dual BSD/GPL"); 32 33static int __init ath9k_init(void) 34{ 35 return 0; 36} 37module_init(ath9k_init); 38 39static void __exit ath9k_exit(void) 40{ 41 return; 42} 43module_exit(ath9k_exit); 44 45/* Private hardware callbacks */ 46 47static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 48{ 49 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 50} 51 52static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 53{ 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 55} 56 57static bool ath9k_hw_macversion_supported(struct ath_hw *ah) 58{ 59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 60 61 return priv_ops->macversion_supported(ah->hw_version.macVersion); 62} 63 64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 65 struct ath9k_channel *chan) 66{ 67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 68} 69 70static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 71{ 72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 73 return; 74 75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 76} 77 78static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 79{ 80 /* You will not have this callback if using the old ANI */ 81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 82 return; 83 84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 85} 86 87/********************/ 88/* Helper Functions */ 89/********************/ 90 91static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) 92{ 93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 94 95 if (!ah->curchan) /* should really check for CCK instead */ 96 return usecs *ATH9K_CLOCK_RATE_CCK; 97 if (conf->channel->band == IEEE80211_BAND_2GHZ) 98 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 99 100 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 101 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 102 else 103 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM; 104} 105 106static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 107{ 108 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 109 110 if (conf_is_ht40(conf)) 111 return ath9k_hw_mac_clks(ah, usecs) * 2; 112 else 113 return ath9k_hw_mac_clks(ah, usecs); 114} 115 116bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 117{ 118 int i; 119 120 BUG_ON(timeout < AH_TIME_QUANTUM); 121 122 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 123 if ((REG_READ(ah, reg) & mask) == val) 124 return true; 125 126 udelay(AH_TIME_QUANTUM); 127 } 128 129 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, 130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 131 timeout, reg, REG_READ(ah, reg), mask, val); 132 133 return false; 134} 135EXPORT_SYMBOL(ath9k_hw_wait); 136 137u32 ath9k_hw_reverse_bits(u32 val, u32 n) 138{ 139 u32 retval; 140 int i; 141 142 for (i = 0, retval = 0; i < n; i++) { 143 retval = (retval << 1) | (val & 1); 144 val >>= 1; 145 } 146 return retval; 147} 148 149bool ath9k_get_channel_edges(struct ath_hw *ah, 150 u16 flags, u16 *low, 151 u16 *high) 152{ 153 struct ath9k_hw_capabilities *pCap = &ah->caps; 154 155 if (flags & CHANNEL_5GHZ) { 156 *low = pCap->low_5ghz_chan; 157 *high = pCap->high_5ghz_chan; 158 return true; 159 } 160 if ((flags & CHANNEL_2GHZ)) { 161 *low = pCap->low_2ghz_chan; 162 *high = pCap->high_2ghz_chan; 163 return true; 164 } 165 return false; 166} 167 168u16 ath9k_hw_computetxtime(struct ath_hw *ah, 169 u8 phy, int kbps, 170 u32 frameLen, u16 rateix, 171 bool shortPreamble) 172{ 173 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 174 175 if (kbps == 0) 176 return 0; 177 178 switch (phy) { 179 case WLAN_RC_PHY_CCK: 180 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 181 if (shortPreamble) 182 phyTime >>= 1; 183 numBits = frameLen << 3; 184 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 185 break; 186 case WLAN_RC_PHY_OFDM: 187 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 188 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 189 numBits = OFDM_PLCP_BITS + (frameLen << 3); 190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 191 txTime = OFDM_SIFS_TIME_QUARTER 192 + OFDM_PREAMBLE_TIME_QUARTER 193 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 194 } else if (ah->curchan && 195 IS_CHAN_HALF_RATE(ah->curchan)) { 196 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 197 numBits = OFDM_PLCP_BITS + (frameLen << 3); 198 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 199 txTime = OFDM_SIFS_TIME_HALF + 200 OFDM_PREAMBLE_TIME_HALF 201 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 202 } else { 203 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 204 numBits = OFDM_PLCP_BITS + (frameLen << 3); 205 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 206 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 207 + (numSymbols * OFDM_SYMBOL_TIME); 208 } 209 break; 210 default: 211 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 212 "Unknown phy %u (rate ix %u)\n", phy, rateix); 213 txTime = 0; 214 break; 215 } 216 217 return txTime; 218} 219EXPORT_SYMBOL(ath9k_hw_computetxtime); 220 221void ath9k_hw_get_channel_centers(struct ath_hw *ah, 222 struct ath9k_channel *chan, 223 struct chan_centers *centers) 224{ 225 int8_t extoff; 226 227 if (!IS_CHAN_HT40(chan)) { 228 centers->ctl_center = centers->ext_center = 229 centers->synth_center = chan->channel; 230 return; 231 } 232 233 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 234 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 235 centers->synth_center = 236 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 237 extoff = 1; 238 } else { 239 centers->synth_center = 240 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 241 extoff = -1; 242 } 243 244 centers->ctl_center = 245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 246 /* 25 MHz spacing is supported by hw but not on upper layers */ 247 centers->ext_center = 248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 249} 250 251/******************/ 252/* Chip Revisions */ 253/******************/ 254 255static void ath9k_hw_read_revisions(struct ath_hw *ah) 256{ 257 u32 val; 258 259 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 260 261 if (val == 0xFF) { 262 val = REG_READ(ah, AR_SREV); 263 ah->hw_version.macVersion = 264 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 265 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 266 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 267 } else { 268 if (!AR_SREV_9100(ah)) 269 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 270 271 ah->hw_version.macRev = val & AR_SREV_REVISION; 272 273 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 274 ah->is_pciexpress = true; 275 } 276} 277 278/************************************/ 279/* HW Attach, Detach, Init Routines */ 280/************************************/ 281 282static void ath9k_hw_disablepcie(struct ath_hw *ah) 283{ 284 if (AR_SREV_9100(ah)) 285 return; 286 287 ENABLE_REGWRITE_BUFFER(ah); 288 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 298 299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 300 301 REGWRITE_BUFFER_FLUSH(ah); 302 DISABLE_REGWRITE_BUFFER(ah); 303} 304 305/* This should work for all families including legacy */ 306static bool ath9k_hw_chip_test(struct ath_hw *ah) 307{ 308 struct ath_common *common = ath9k_hw_common(ah); 309 u32 regAddr[2] = { AR_STA_ID0 }; 310 u32 regHold[2]; 311 u32 patternData[4] = { 0x55555555, 312 0xaaaaaaaa, 313 0x66666666, 314 0x99999999 }; 315 int i, j, loop_max; 316 317 if (!AR_SREV_9300_20_OR_LATER(ah)) { 318 loop_max = 2; 319 regAddr[1] = AR_PHY_BASE + (8 << 2); 320 } else 321 loop_max = 1; 322 323 for (i = 0; i < loop_max; i++) { 324 u32 addr = regAddr[i]; 325 u32 wrData, rdData; 326 327 regHold[i] = REG_READ(ah, addr); 328 for (j = 0; j < 0x100; j++) { 329 wrData = (j << 16) | j; 330 REG_WRITE(ah, addr, wrData); 331 rdData = REG_READ(ah, addr); 332 if (rdData != wrData) { 333 ath_print(common, ATH_DBG_FATAL, 334 "address test failed " 335 "addr: 0x%08x - wr:0x%08x != " 336 "rd:0x%08x\n", 337 addr, wrData, rdData); 338 return false; 339 } 340 } 341 for (j = 0; j < 4; j++) { 342 wrData = patternData[j]; 343 REG_WRITE(ah, addr, wrData); 344 rdData = REG_READ(ah, addr); 345 if (wrData != rdData) { 346 ath_print(common, ATH_DBG_FATAL, 347 "address test failed " 348 "addr: 0x%08x - wr:0x%08x != " 349 "rd:0x%08x\n", 350 addr, wrData, rdData); 351 return false; 352 } 353 } 354 REG_WRITE(ah, regAddr[i], regHold[i]); 355 } 356 udelay(100); 357 358 return true; 359} 360 361static void ath9k_hw_init_config(struct ath_hw *ah) 362{ 363 int i; 364 365 ah->config.dma_beacon_response_time = 2; 366 ah->config.sw_beacon_response_time = 10; 367 ah->config.additional_swba_backoff = 0; 368 ah->config.ack_6mb = 0x0; 369 ah->config.cwm_ignore_extcca = 0; 370 ah->config.pcie_powersave_enable = 0; 371 ah->config.pcie_clock_req = 0; 372 ah->config.pcie_waen = 0; 373 ah->config.analog_shiftreg = 1; 374 ah->config.ofdm_trig_low = 200; 375 ah->config.ofdm_trig_high = 500; 376 ah->config.cck_trig_high = 200; 377 ah->config.cck_trig_low = 100; 378 ah->config.enable_ani = true; 379 380 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 381 ah->config.spurchans[i][0] = AR_NO_SPUR; 382 ah->config.spurchans[i][1] = AR_NO_SPUR; 383 } 384 385 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 386 ah->config.ht_enable = 1; 387 else 388 ah->config.ht_enable = 0; 389 390 ah->config.rx_intr_mitigation = true; 391 ah->config.pcieSerDesWrite = true; 392 393 /* 394 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 395 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 396 * This means we use it for all AR5416 devices, and the few 397 * minor PCI AR9280 devices out there. 398 * 399 * Serialization is required because these devices do not handle 400 * well the case of two concurrent reads/writes due to the latency 401 * involved. During one read/write another read/write can be issued 402 * on another CPU while the previous read/write may still be working 403 * on our hardware, if we hit this case the hardware poops in a loop. 404 * We prevent this by serializing reads and writes. 405 * 406 * This issue is not present on PCI-Express devices or pre-AR5416 407 * devices (legacy, 802.11abg). 408 */ 409 if (num_possible_cpus() > 1) 410 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 411} 412 413static void ath9k_hw_init_defaults(struct ath_hw *ah) 414{ 415 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 416 417 regulatory->country_code = CTRY_DEFAULT; 418 regulatory->power_limit = MAX_RATE_POWER; 419 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 420 421 ah->hw_version.magic = AR5416_MAGIC; 422 ah->hw_version.subvendorid = 0; 423 424 ah->ah_flags = 0; 425 if (!AR_SREV_9100(ah)) 426 ah->ah_flags = AH_USE_EEPROM; 427 428 ah->atim_window = 0; 429 ah->sta_id1_defaults = 430 AR_STA_ID1_CRPT_MIC_ENABLE | 431 AR_STA_ID1_MCAST_KSRCH; 432 ah->beacon_interval = 100; 433 ah->enable_32kHz_clock = DONT_USE_32KHZ; 434 ah->slottime = (u32) -1; 435 ah->globaltxtimeout = (u32) -1; 436 ah->power_mode = ATH9K_PM_UNDEFINED; 437} 438 439static int ath9k_hw_init_macaddr(struct ath_hw *ah) 440{ 441 struct ath_common *common = ath9k_hw_common(ah); 442 u32 sum; 443 int i; 444 u16 eeval; 445 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 446 447 sum = 0; 448 for (i = 0; i < 3; i++) { 449 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 450 sum += eeval; 451 common->macaddr[2 * i] = eeval >> 8; 452 common->macaddr[2 * i + 1] = eeval & 0xff; 453 } 454 if (sum == 0 || sum == 0xffff * 3) 455 return -EADDRNOTAVAIL; 456 457 return 0; 458} 459 460static int ath9k_hw_post_init(struct ath_hw *ah) 461{ 462 int ecode; 463 464 if (!AR_SREV_9271(ah)) { 465 if (!ath9k_hw_chip_test(ah)) 466 return -ENODEV; 467 } 468 469 if (!AR_SREV_9300_20_OR_LATER(ah)) { 470 ecode = ar9002_hw_rf_claim(ah); 471 if (ecode != 0) 472 return ecode; 473 } 474 475 ecode = ath9k_hw_eeprom_init(ah); 476 if (ecode != 0) 477 return ecode; 478 479 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, 480 "Eeprom VER: %d, REV: %d\n", 481 ah->eep_ops->get_eeprom_ver(ah), 482 ah->eep_ops->get_eeprom_rev(ah)); 483 484 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 485 if (ecode) { 486 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 487 "Failed allocating banks for " 488 "external radio\n"); 489 return ecode; 490 } 491 492 if (!AR_SREV_9100(ah)) { 493 ath9k_hw_ani_setup(ah); 494 ath9k_hw_ani_init(ah); 495 } 496 497 return 0; 498} 499 500static void ath9k_hw_attach_ops(struct ath_hw *ah) 501{ 502 if (AR_SREV_9300_20_OR_LATER(ah)) 503 ar9003_hw_attach_ops(ah); 504 else 505 ar9002_hw_attach_ops(ah); 506} 507 508/* Called for all hardware families */ 509static int __ath9k_hw_init(struct ath_hw *ah) 510{ 511 struct ath_common *common = ath9k_hw_common(ah); 512 int r = 0; 513 514 if (ah->hw_version.devid == AR5416_AR9100_DEVID) 515 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 516 517 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 518 ath_print(common, ATH_DBG_FATAL, 519 "Couldn't reset chip\n"); 520 return -EIO; 521 } 522 523 ath9k_hw_init_defaults(ah); 524 ath9k_hw_init_config(ah); 525 526 ath9k_hw_attach_ops(ah); 527 528 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 529 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 530 return -EIO; 531 } 532 533 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 534 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 535 (AR_SREV_9280(ah) && !ah->is_pciexpress)) { 536 ah->config.serialize_regmode = 537 SER_REG_MODE_ON; 538 } else { 539 ah->config.serialize_regmode = 540 SER_REG_MODE_OFF; 541 } 542 } 543 544 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 545 ah->config.serialize_regmode); 546 547 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 548 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 549 else 550 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 551 552 if (!ath9k_hw_macversion_supported(ah)) { 553 ath_print(common, ATH_DBG_FATAL, 554 "Mac Chip Rev 0x%02x.%x is not supported by " 555 "this driver\n", ah->hw_version.macVersion, 556 ah->hw_version.macRev); 557 return -EOPNOTSUPP; 558 } 559 560 if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) 561 ah->is_pciexpress = false; 562 563 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 564 ath9k_hw_init_cal_settings(ah); 565 566 ah->ani_function = ATH9K_ANI_ALL; 567 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 568 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 569 if (!AR_SREV_9300_20_OR_LATER(ah)) 570 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 571 572 ath9k_hw_init_mode_regs(ah); 573 574 /* 575 * Read back AR_WA into a permanent copy and set bits 14 and 17. 576 * We need to do this to avoid RMW of this register. We cannot 577 * read the reg when chip is asleep. 578 */ 579 ah->WARegVal = REG_READ(ah, AR_WA); 580 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 581 AR_WA_ASPM_TIMER_BASED_DISABLE); 582 583 if (ah->is_pciexpress) 584 ath9k_hw_configpcipowersave(ah, 0, 0); 585 else 586 ath9k_hw_disablepcie(ah); 587 588 if (!AR_SREV_9300_20_OR_LATER(ah)) 589 ar9002_hw_cck_chan14_spread(ah); 590 591 r = ath9k_hw_post_init(ah); 592 if (r) 593 return r; 594 595 ath9k_hw_init_mode_gain_regs(ah); 596 r = ath9k_hw_fill_cap_info(ah); 597 if (r) 598 return r; 599 600 r = ath9k_hw_init_macaddr(ah); 601 if (r) { 602 ath_print(common, ATH_DBG_FATAL, 603 "Failed to initialize MAC address\n"); 604 return r; 605 } 606 607 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 608 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 609 else 610 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 611 612 if (AR_SREV_9300_20_OR_LATER(ah)) 613 ar9003_hw_set_nf_limits(ah); 614 615 ath9k_init_nfcal_hist_buffer(ah); 616 ah->bb_watchdog_timeout_ms = 25; 617 618 common->state = ATH_HW_INITIALIZED; 619 620 return 0; 621} 622 623int ath9k_hw_init(struct ath_hw *ah) 624{ 625 int ret; 626 struct ath_common *common = ath9k_hw_common(ah); 627 628 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 629 switch (ah->hw_version.devid) { 630 case AR5416_DEVID_PCI: 631 case AR5416_DEVID_PCIE: 632 case AR5416_AR9100_DEVID: 633 case AR9160_DEVID_PCI: 634 case AR9280_DEVID_PCI: 635 case AR9280_DEVID_PCIE: 636 case AR9285_DEVID_PCIE: 637 case AR9287_DEVID_PCI: 638 case AR9287_DEVID_PCIE: 639 case AR2427_DEVID_PCIE: 640 case AR9300_DEVID_PCIE: 641 break; 642 default: 643 if (common->bus_ops->ath_bus_type == ATH_USB) 644 break; 645 ath_print(common, ATH_DBG_FATAL, 646 "Hardware device ID 0x%04x not supported\n", 647 ah->hw_version.devid); 648 return -EOPNOTSUPP; 649 } 650 651 ret = __ath9k_hw_init(ah); 652 if (ret) { 653 ath_print(common, ATH_DBG_FATAL, 654 "Unable to initialize hardware; " 655 "initialization status: %d\n", ret); 656 return ret; 657 } 658 659 return 0; 660} 661EXPORT_SYMBOL(ath9k_hw_init); 662 663static void ath9k_hw_init_qos(struct ath_hw *ah) 664{ 665 ENABLE_REGWRITE_BUFFER(ah); 666 667 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 668 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 669 670 REG_WRITE(ah, AR_QOS_NO_ACK, 671 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 672 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 673 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 674 675 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 676 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 677 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 678 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 679 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 680 681 REGWRITE_BUFFER_FLUSH(ah); 682 DISABLE_REGWRITE_BUFFER(ah); 683} 684 685static void ath9k_hw_init_pll(struct ath_hw *ah, 686 struct ath9k_channel *chan) 687{ 688 u32 pll = ath9k_hw_compute_pll_control(ah, chan); 689 690 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 691 692 /* Switch the core clock for ar9271 to 117Mhz */ 693 if (AR_SREV_9271(ah)) { 694 udelay(500); 695 REG_WRITE(ah, 0x50040, 0x304); 696 } 697 698 udelay(RTC_PLL_SETTLE_DELAY); 699 700 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 701} 702 703static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 704 enum nl80211_iftype opmode) 705{ 706 u32 imr_reg = AR_IMR_TXERR | 707 AR_IMR_TXURN | 708 AR_IMR_RXERR | 709 AR_IMR_RXORN | 710 AR_IMR_BCNMISC; 711 712 if (AR_SREV_9300_20_OR_LATER(ah)) { 713 imr_reg |= AR_IMR_RXOK_HP; 714 if (ah->config.rx_intr_mitigation) 715 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 716 else 717 imr_reg |= AR_IMR_RXOK_LP; 718 719 } else { 720 if (ah->config.rx_intr_mitigation) 721 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 722 else 723 imr_reg |= AR_IMR_RXOK; 724 } 725 726 if (ah->config.tx_intr_mitigation) 727 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 728 else 729 imr_reg |= AR_IMR_TXOK; 730 731 if (opmode == NL80211_IFTYPE_AP) 732 imr_reg |= AR_IMR_MIB; 733 734 ENABLE_REGWRITE_BUFFER(ah); 735 736 REG_WRITE(ah, AR_IMR, imr_reg); 737 ah->imrs2_reg |= AR_IMR_S2_GTT; 738 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 739 740 if (!AR_SREV_9100(ah)) { 741 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 742 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 743 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 744 } 745 746 REGWRITE_BUFFER_FLUSH(ah); 747 DISABLE_REGWRITE_BUFFER(ah); 748 749 if (AR_SREV_9300_20_OR_LATER(ah)) { 750 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 751 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 752 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 753 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 754 } 755} 756 757static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 758{ 759 u32 val = ath9k_hw_mac_to_clks(ah, us); 760 val = min(val, (u32) 0xFFFF); 761 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 762} 763 764static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 765{ 766 u32 val = ath9k_hw_mac_to_clks(ah, us); 767 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 768 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 769} 770 771static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 772{ 773 u32 val = ath9k_hw_mac_to_clks(ah, us); 774 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 775 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 776} 777 778static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 779{ 780 if (tu > 0xFFFF) { 781 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 782 "bad global tx timeout %u\n", tu); 783 ah->globaltxtimeout = (u32) -1; 784 return false; 785 } else { 786 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 787 ah->globaltxtimeout = tu; 788 return true; 789 } 790} 791 792void ath9k_hw_init_global_settings(struct ath_hw *ah) 793{ 794 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 795 int acktimeout; 796 int slottime; 797 int sifstime; 798 799 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 800 ah->misc_mode); 801 802 if (ah->misc_mode != 0) 803 REG_WRITE(ah, AR_PCU_MISC, 804 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 805 806 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 807 sifstime = 16; 808 else 809 sifstime = 10; 810 811 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 812 slottime = ah->slottime + 3 * ah->coverage_class; 813 acktimeout = slottime + sifstime; 814 815 /* 816 * Workaround for early ACK timeouts, add an offset to match the 817 * initval's 64us ack timeout value. 818 * This was initially only meant to work around an issue with delayed 819 * BA frames in some implementations, but it has been found to fix ACK 820 * timeout issues in other cases as well. 821 */ 822 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 823 acktimeout += 64 - sifstime - ah->slottime; 824 825 ath9k_hw_setslottime(ah, slottime); 826 ath9k_hw_set_ack_timeout(ah, acktimeout); 827 ath9k_hw_set_cts_timeout(ah, acktimeout); 828 if (ah->globaltxtimeout != (u32) -1) 829 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 830} 831EXPORT_SYMBOL(ath9k_hw_init_global_settings); 832 833void ath9k_hw_deinit(struct ath_hw *ah) 834{ 835 struct ath_common *common = ath9k_hw_common(ah); 836 837 if (common->state < ATH_HW_INITIALIZED) 838 goto free_hw; 839 840 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 841 842free_hw: 843 ath9k_hw_rf_free_ext_banks(ah); 844} 845EXPORT_SYMBOL(ath9k_hw_deinit); 846 847/*******/ 848/* INI */ 849/*******/ 850 851u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 852{ 853 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 854 855 if (IS_CHAN_B(chan)) 856 ctl |= CTL_11B; 857 else if (IS_CHAN_G(chan)) 858 ctl |= CTL_11G; 859 else 860 ctl |= CTL_11A; 861 862 return ctl; 863} 864 865/****************************************/ 866/* Reset and Channel Switching Routines */ 867/****************************************/ 868 869static inline void ath9k_hw_set_dma(struct ath_hw *ah) 870{ 871 struct ath_common *common = ath9k_hw_common(ah); 872 u32 regval; 873 874 ENABLE_REGWRITE_BUFFER(ah); 875 876 /* 877 * set AHB_MODE not to do cacheline prefetches 878 */ 879 if (!AR_SREV_9300_20_OR_LATER(ah)) { 880 regval = REG_READ(ah, AR_AHB_MODE); 881 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 882 } 883 884 /* 885 * let mac dma reads be in 128 byte chunks 886 */ 887 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 888 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 889 890 REGWRITE_BUFFER_FLUSH(ah); 891 DISABLE_REGWRITE_BUFFER(ah); 892 893 /* 894 * Restore TX Trigger Level to its pre-reset value. 895 * The initial value depends on whether aggregation is enabled, and is 896 * adjusted whenever underruns are detected. 897 */ 898 if (!AR_SREV_9300_20_OR_LATER(ah)) 899 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 900 901 ENABLE_REGWRITE_BUFFER(ah); 902 903 /* 904 * let mac dma writes be in 128 byte chunks 905 */ 906 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 907 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 908 909 /* 910 * Setup receive FIFO threshold to hold off TX activities 911 */ 912 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 913 914 if (AR_SREV_9300_20_OR_LATER(ah)) { 915 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 916 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 917 918 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 919 ah->caps.rx_status_len); 920 } 921 922 /* 923 * reduce the number of usable entries in PCU TXBUF to avoid 924 * wrap around issues. 925 */ 926 if (AR_SREV_9285(ah)) { 927 /* For AR9285 the number of Fifos are reduced to half. 928 * So set the usable tx buf size also to half to 929 * avoid data/delimiter underruns 930 */ 931 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 932 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 933 } else if (!AR_SREV_9271(ah)) { 934 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 935 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 936 } 937 938 REGWRITE_BUFFER_FLUSH(ah); 939 DISABLE_REGWRITE_BUFFER(ah); 940 941 if (AR_SREV_9300_20_OR_LATER(ah)) 942 ath9k_hw_reset_txstatus_ring(ah); 943} 944 945static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 946{ 947 u32 val; 948 949 val = REG_READ(ah, AR_STA_ID1); 950 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 951 switch (opmode) { 952 case NL80211_IFTYPE_AP: 953 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 954 | AR_STA_ID1_KSRCH_MODE); 955 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 956 break; 957 case NL80211_IFTYPE_ADHOC: 958 case NL80211_IFTYPE_MESH_POINT: 959 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 960 | AR_STA_ID1_KSRCH_MODE); 961 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 962 break; 963 case NL80211_IFTYPE_STATION: 964 case NL80211_IFTYPE_MONITOR: 965 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 966 break; 967 } 968} 969 970void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 971 u32 *coef_mantissa, u32 *coef_exponent) 972{ 973 u32 coef_exp, coef_man; 974 975 for (coef_exp = 31; coef_exp > 0; coef_exp--) 976 if ((coef_scaled >> coef_exp) & 0x1) 977 break; 978 979 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 980 981 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 982 983 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 984 *coef_exponent = coef_exp - 16; 985} 986 987static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 988{ 989 u32 rst_flags; 990 u32 tmpReg; 991 992 if (AR_SREV_9100(ah)) { 993 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 994 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 995 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 996 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 997 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 998 } 999 1000 ENABLE_REGWRITE_BUFFER(ah); 1001 1002 if (AR_SREV_9300_20_OR_LATER(ah)) { 1003 REG_WRITE(ah, AR_WA, ah->WARegVal); 1004 udelay(10); 1005 } 1006 1007 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1008 AR_RTC_FORCE_WAKE_ON_INT); 1009 1010 if (AR_SREV_9100(ah)) { 1011 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1012 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1013 } else { 1014 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1015 if (tmpReg & 1016 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1017 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1018 u32 val; 1019 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1020 1021 val = AR_RC_HOSTIF; 1022 if (!AR_SREV_9300_20_OR_LATER(ah)) 1023 val |= AR_RC_AHB; 1024 REG_WRITE(ah, AR_RC, val); 1025 1026 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1027 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1028 1029 rst_flags = AR_RTC_RC_MAC_WARM; 1030 if (type == ATH9K_RESET_COLD) 1031 rst_flags |= AR_RTC_RC_MAC_COLD; 1032 } 1033 1034 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1035 1036 REGWRITE_BUFFER_FLUSH(ah); 1037 DISABLE_REGWRITE_BUFFER(ah); 1038 1039 udelay(50); 1040 1041 REG_WRITE(ah, AR_RTC_RC, 0); 1042 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1043 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1044 "RTC stuck in MAC reset\n"); 1045 return false; 1046 } 1047 1048 if (!AR_SREV_9100(ah)) 1049 REG_WRITE(ah, AR_RC, 0); 1050 1051 if (AR_SREV_9100(ah)) 1052 udelay(50); 1053 1054 return true; 1055} 1056 1057static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1058{ 1059 ENABLE_REGWRITE_BUFFER(ah); 1060 1061 if (AR_SREV_9300_20_OR_LATER(ah)) { 1062 REG_WRITE(ah, AR_WA, ah->WARegVal); 1063 udelay(10); 1064 } 1065 1066 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1067 AR_RTC_FORCE_WAKE_ON_INT); 1068 1069 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1070 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1071 1072 REG_WRITE(ah, AR_RTC_RESET, 0); 1073 1074 REGWRITE_BUFFER_FLUSH(ah); 1075 DISABLE_REGWRITE_BUFFER(ah); 1076 1077 if (!AR_SREV_9300_20_OR_LATER(ah)) 1078 udelay(2); 1079 1080 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1081 REG_WRITE(ah, AR_RC, 0); 1082 1083 REG_WRITE(ah, AR_RTC_RESET, 1); 1084 1085 if (!ath9k_hw_wait(ah, 1086 AR_RTC_STATUS, 1087 AR_RTC_STATUS_M, 1088 AR_RTC_STATUS_ON, 1089 AH_WAIT_TIMEOUT)) { 1090 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1091 "RTC not waking up\n"); 1092 return false; 1093 } 1094 1095 ath9k_hw_read_revisions(ah); 1096 1097 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1098} 1099 1100static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1101{ 1102 if (AR_SREV_9300_20_OR_LATER(ah)) { 1103 REG_WRITE(ah, AR_WA, ah->WARegVal); 1104 udelay(10); 1105 } 1106 1107 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1108 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1109 1110 switch (type) { 1111 case ATH9K_RESET_POWER_ON: 1112 return ath9k_hw_set_reset_power_on(ah); 1113 case ATH9K_RESET_WARM: 1114 case ATH9K_RESET_COLD: 1115 return ath9k_hw_set_reset(ah, type); 1116 default: 1117 return false; 1118 } 1119} 1120 1121static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1122 struct ath9k_channel *chan) 1123{ 1124 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1125 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1126 return false; 1127 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1128 return false; 1129 1130 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1131 return false; 1132 1133 ah->chip_fullsleep = false; 1134 ath9k_hw_init_pll(ah, chan); 1135 ath9k_hw_set_rfmode(ah, chan); 1136 1137 return true; 1138} 1139 1140static bool ath9k_hw_channel_change(struct ath_hw *ah, 1141 struct ath9k_channel *chan) 1142{ 1143 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1144 struct ath_common *common = ath9k_hw_common(ah); 1145 struct ieee80211_channel *channel = chan->chan; 1146 u32 qnum; 1147 int r; 1148 1149 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1150 if (ath9k_hw_numtxpending(ah, qnum)) { 1151 ath_print(common, ATH_DBG_QUEUE, 1152 "Transmit frames pending on " 1153 "queue %d\n", qnum); 1154 return false; 1155 } 1156 } 1157 1158 if (!ath9k_hw_rfbus_req(ah)) { 1159 ath_print(common, ATH_DBG_FATAL, 1160 "Could not kill baseband RX\n"); 1161 return false; 1162 } 1163 1164 ath9k_hw_set_channel_regs(ah, chan); 1165 1166 r = ath9k_hw_rf_set_freq(ah, chan); 1167 if (r) { 1168 ath_print(common, ATH_DBG_FATAL, 1169 "Failed to set channel\n"); 1170 return false; 1171 } 1172 1173 ah->eep_ops->set_txpower(ah, chan, 1174 ath9k_regd_get_ctl(regulatory, chan), 1175 channel->max_antenna_gain * 2, 1176 channel->max_power * 2, 1177 min((u32) MAX_RATE_POWER, 1178 (u32) regulatory->power_limit)); 1179 1180 ath9k_hw_rfbus_done(ah); 1181 1182 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1183 ath9k_hw_set_delta_slope(ah, chan); 1184 1185 ath9k_hw_spur_mitigate_freq(ah, chan); 1186 1187 if (!chan->oneTimeCalsDone) 1188 chan->oneTimeCalsDone = true; 1189 1190 return true; 1191} 1192 1193bool ath9k_hw_check_alive(struct ath_hw *ah) 1194{ 1195 int count = 50; 1196 u32 reg; 1197 1198 if (AR_SREV_9285_10_OR_LATER(ah)) 1199 return true; 1200 1201 do { 1202 reg = REG_READ(ah, AR_OBS_BUS_1); 1203 1204 if ((reg & 0x7E7FFFEF) == 0x00702400) 1205 continue; 1206 1207 switch (reg & 0x7E000B00) { 1208 case 0x1E000000: 1209 case 0x52000B00: 1210 case 0x18000B00: 1211 continue; 1212 default: 1213 return true; 1214 } 1215 } while (count-- > 0); 1216 1217 return false; 1218} 1219EXPORT_SYMBOL(ath9k_hw_check_alive); 1220 1221int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1222 bool bChannelChange) 1223{ 1224 struct ath_common *common = ath9k_hw_common(ah); 1225 u32 saveLedState; 1226 struct ath9k_channel *curchan = ah->curchan; 1227 u32 saveDefAntenna; 1228 u32 macStaId1; 1229 u64 tsf = 0; 1230 int i, r; 1231 1232 ah->txchainmask = common->tx_chainmask; 1233 ah->rxchainmask = common->rx_chainmask; 1234 1235 if (!ah->chip_fullsleep) { 1236 ath9k_hw_abortpcurecv(ah); 1237 if (!ath9k_hw_stopdmarecv(ah)) 1238 ath_print(common, ATH_DBG_XMIT, 1239 "Failed to stop receive dma\n"); 1240 } 1241 1242 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1243 return -EIO; 1244 1245 if (curchan && !ah->chip_fullsleep) 1246 ath9k_hw_getnf(ah, curchan); 1247 1248 if (bChannelChange && 1249 (ah->chip_fullsleep != true) && 1250 (ah->curchan != NULL) && 1251 (chan->channel != ah->curchan->channel) && 1252 ((chan->channelFlags & CHANNEL_ALL) == 1253 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1254 !AR_SREV_9280(ah)) { 1255 1256 if (ath9k_hw_channel_change(ah, chan)) { 1257 ath9k_hw_loadnf(ah, ah->curchan); 1258 ath9k_hw_start_nfcal(ah); 1259 return 0; 1260 } 1261 } 1262 1263 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1264 if (saveDefAntenna == 0) 1265 saveDefAntenna = 1; 1266 1267 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1268 1269 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1270 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1271 tsf = ath9k_hw_gettsf64(ah); 1272 1273 saveLedState = REG_READ(ah, AR_CFG_LED) & 1274 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1275 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1276 1277 ath9k_hw_mark_phy_inactive(ah); 1278 1279 /* Only required on the first reset */ 1280 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1281 REG_WRITE(ah, 1282 AR9271_RESET_POWER_DOWN_CONTROL, 1283 AR9271_RADIO_RF_RST); 1284 udelay(50); 1285 } 1286 1287 if (!ath9k_hw_chip_reset(ah, chan)) { 1288 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); 1289 return -EINVAL; 1290 } 1291 1292 /* Only required on the first reset */ 1293 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1294 ah->htc_reset_init = false; 1295 REG_WRITE(ah, 1296 AR9271_RESET_POWER_DOWN_CONTROL, 1297 AR9271_GATE_MAC_CTL); 1298 udelay(50); 1299 } 1300 1301 /* Restore TSF */ 1302 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1303 ath9k_hw_settsf64(ah, tsf); 1304 1305 if (AR_SREV_9280_10_OR_LATER(ah)) 1306 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1307 1308 if (!AR_SREV_9300_20_OR_LATER(ah)) 1309 ar9002_hw_enable_async_fifo(ah); 1310 1311 r = ath9k_hw_process_ini(ah, chan); 1312 if (r) 1313 return r; 1314 1315 /* Setup MFP options for CCMP */ 1316 if (AR_SREV_9280_20_OR_LATER(ah)) { 1317 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1318 * frames when constructing CCMP AAD. */ 1319 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1320 0xc7ff); 1321 ah->sw_mgmt_crypto = false; 1322 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1323 /* Disable hardware crypto for management frames */ 1324 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1325 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1326 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1327 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1328 ah->sw_mgmt_crypto = true; 1329 } else 1330 ah->sw_mgmt_crypto = true; 1331 1332 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1333 ath9k_hw_set_delta_slope(ah, chan); 1334 1335 ath9k_hw_spur_mitigate_freq(ah, chan); 1336 ah->eep_ops->set_board_values(ah, chan); 1337 1338 ath9k_hw_set_operating_mode(ah, ah->opmode); 1339 1340 ENABLE_REGWRITE_BUFFER(ah); 1341 1342 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1343 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1344 | macStaId1 1345 | AR_STA_ID1_RTS_USE_DEF 1346 | (ah->config. 1347 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1348 | ah->sta_id1_defaults); 1349 ath_hw_setbssidmask(common); 1350 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1351 ath9k_hw_write_associd(ah); 1352 REG_WRITE(ah, AR_ISR, ~0); 1353 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1354 1355 REGWRITE_BUFFER_FLUSH(ah); 1356 DISABLE_REGWRITE_BUFFER(ah); 1357 1358 r = ath9k_hw_rf_set_freq(ah, chan); 1359 if (r) 1360 return r; 1361 1362 ENABLE_REGWRITE_BUFFER(ah); 1363 1364 for (i = 0; i < AR_NUM_DCU; i++) 1365 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1366 1367 REGWRITE_BUFFER_FLUSH(ah); 1368 DISABLE_REGWRITE_BUFFER(ah); 1369 1370 ah->intr_txqs = 0; 1371 for (i = 0; i < ah->caps.total_queues; i++) 1372 ath9k_hw_resettxqueue(ah, i); 1373 1374 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1375 ath9k_hw_ani_cache_ini_regs(ah); 1376 ath9k_hw_init_qos(ah); 1377 1378 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1379 ath9k_enable_rfkill(ah); 1380 1381 ath9k_hw_init_global_settings(ah); 1382 1383 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1384 ar9002_hw_update_async_fifo(ah); 1385 ar9002_hw_enable_wep_aggregation(ah); 1386 } 1387 1388 REG_WRITE(ah, AR_STA_ID1, 1389 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 1390 1391 ath9k_hw_set_dma(ah); 1392 1393 REG_WRITE(ah, AR_OBS, 8); 1394 1395 if (ah->config.rx_intr_mitigation) { 1396 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1397 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1398 } 1399 1400 if (ah->config.tx_intr_mitigation) { 1401 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1402 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1403 } 1404 1405 ath9k_hw_init_bb(ah, chan); 1406 1407 if (!ath9k_hw_init_cal(ah, chan)) 1408 return -EIO; 1409 1410 ENABLE_REGWRITE_BUFFER(ah); 1411 1412 ath9k_hw_restore_chainmask(ah); 1413 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1414 1415 REGWRITE_BUFFER_FLUSH(ah); 1416 DISABLE_REGWRITE_BUFFER(ah); 1417 1418 /* 1419 * For big endian systems turn on swapping for descriptors 1420 */ 1421 if (AR_SREV_9100(ah)) { 1422 u32 mask; 1423 mask = REG_READ(ah, AR_CFG); 1424 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1425 ath_print(common, ATH_DBG_RESET, 1426 "CFG Byte Swap Set 0x%x\n", mask); 1427 } else { 1428 mask = 1429 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1430 REG_WRITE(ah, AR_CFG, mask); 1431 ath_print(common, ATH_DBG_RESET, 1432 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1433 } 1434 } else { 1435 if (common->bus_ops->ath_bus_type == ATH_USB) { 1436 /* Configure AR9271 target WLAN */ 1437 if (AR_SREV_9271(ah)) 1438 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1439 else 1440 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1441 } 1442#ifdef __BIG_ENDIAN 1443 else 1444 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1445#endif 1446 } 1447 1448 if (ah->btcoex_hw.enabled) 1449 ath9k_hw_btcoex_enable(ah); 1450 1451 if (AR_SREV_9300_20_OR_LATER(ah)) { 1452 ath9k_hw_loadnf(ah, curchan); 1453 ath9k_hw_start_nfcal(ah); 1454 ar9003_hw_bb_watchdog_config(ah); 1455 } 1456 1457 return 0; 1458} 1459EXPORT_SYMBOL(ath9k_hw_reset); 1460 1461/************************/ 1462/* Key Cache Management */ 1463/************************/ 1464 1465bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) 1466{ 1467 u32 keyType; 1468 1469 if (entry >= ah->caps.keycache_size) { 1470 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1471 "keychache entry %u out of range\n", entry); 1472 return false; 1473 } 1474 1475 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 1476 1477 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 1478 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 1479 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 1480 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 1481 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 1482 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1483 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 1484 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 1485 1486 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 1487 u16 micentry = entry + 64; 1488 1489 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 1490 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 1491 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); 1492 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 1493 1494 } 1495 1496 return true; 1497} 1498EXPORT_SYMBOL(ath9k_hw_keyreset); 1499 1500bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) 1501{ 1502 u32 macHi, macLo; 1503 u32 unicast_flag = AR_KEYTABLE_VALID; 1504 1505 if (entry >= ah->caps.keycache_size) { 1506 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1507 "keychache entry %u out of range\n", entry); 1508 return false; 1509 } 1510 1511 if (mac != NULL) { 1512 /* 1513 * AR_KEYTABLE_VALID indicates that the address is a unicast 1514 * address, which must match the transmitter address for 1515 * decrypting frames. 1516 * Not setting this bit allows the hardware to use the key 1517 * for multicast frame decryption. 1518 */ 1519 if (mac[0] & 0x01) 1520 unicast_flag = 0; 1521 1522 macHi = (mac[5] << 8) | mac[4]; 1523 macLo = (mac[3] << 24) | 1524 (mac[2] << 16) | 1525 (mac[1] << 8) | 1526 mac[0]; 1527 macLo >>= 1; 1528 macLo |= (macHi & 1) << 31; 1529 macHi >>= 1; 1530 } else { 1531 macLo = macHi = 0; 1532 } 1533 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 1534 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag); 1535 1536 return true; 1537} 1538EXPORT_SYMBOL(ath9k_hw_keysetmac); 1539 1540bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, 1541 const struct ath9k_keyval *k, 1542 const u8 *mac) 1543{ 1544 const struct ath9k_hw_capabilities *pCap = &ah->caps; 1545 struct ath_common *common = ath9k_hw_common(ah); 1546 u32 key0, key1, key2, key3, key4; 1547 u32 keyType; 1548 1549 if (entry >= pCap->keycache_size) { 1550 ath_print(common, ATH_DBG_FATAL, 1551 "keycache entry %u out of range\n", entry); 1552 return false; 1553 } 1554 1555 switch (k->kv_type) { 1556 case ATH9K_CIPHER_AES_OCB: 1557 keyType = AR_KEYTABLE_TYPE_AES; 1558 break; 1559 case ATH9K_CIPHER_AES_CCM: 1560 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 1561 ath_print(common, ATH_DBG_ANY, 1562 "AES-CCM not supported by mac rev 0x%x\n", 1563 ah->hw_version.macRev); 1564 return false; 1565 } 1566 keyType = AR_KEYTABLE_TYPE_CCM; 1567 break; 1568 case ATH9K_CIPHER_TKIP: 1569 keyType = AR_KEYTABLE_TYPE_TKIP; 1570 if (ATH9K_IS_MIC_ENABLED(ah) 1571 && entry + 64 >= pCap->keycache_size) { 1572 ath_print(common, ATH_DBG_ANY, 1573 "entry %u inappropriate for TKIP\n", entry); 1574 return false; 1575 } 1576 break; 1577 case ATH9K_CIPHER_WEP: 1578 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 1579 ath_print(common, ATH_DBG_ANY, 1580 "WEP key length %u too small\n", k->kv_len); 1581 return false; 1582 } 1583 if (k->kv_len <= WLAN_KEY_LEN_WEP40) 1584 keyType = AR_KEYTABLE_TYPE_40; 1585 else if (k->kv_len <= WLAN_KEY_LEN_WEP104) 1586 keyType = AR_KEYTABLE_TYPE_104; 1587 else 1588 keyType = AR_KEYTABLE_TYPE_128; 1589 break; 1590 case ATH9K_CIPHER_CLR: 1591 keyType = AR_KEYTABLE_TYPE_CLR; 1592 break; 1593 default: 1594 ath_print(common, ATH_DBG_FATAL, 1595 "cipher %u not supported\n", k->kv_type); 1596 return false; 1597 } 1598 1599 key0 = get_unaligned_le32(k->kv_val + 0); 1600 key1 = get_unaligned_le16(k->kv_val + 4); 1601 key2 = get_unaligned_le32(k->kv_val + 6); 1602 key3 = get_unaligned_le16(k->kv_val + 10); 1603 key4 = get_unaligned_le32(k->kv_val + 12); 1604 if (k->kv_len <= WLAN_KEY_LEN_WEP104) 1605 key4 &= 0xff; 1606 1607 /* 1608 * Note: Key cache registers access special memory area that requires 1609 * two 32-bit writes to actually update the values in the internal 1610 * memory. Consequently, the exact order and pairs used here must be 1611 * maintained. 1612 */ 1613 1614 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 1615 u16 micentry = entry + 64; 1616 1617 /* 1618 * Write inverted key[47:0] first to avoid Michael MIC errors 1619 * on frames that could be sent or received at the same time. 1620 * The correct key will be written in the end once everything 1621 * else is ready. 1622 */ 1623 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); 1624 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); 1625 1626 /* Write key[95:48] */ 1627 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 1628 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 1629 1630 /* Write key[127:96] and key type */ 1631 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 1632 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 1633 1634 /* Write MAC address for the entry */ 1635 (void) ath9k_hw_keysetmac(ah, entry, mac); 1636 1637 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { 1638 /* 1639 * TKIP uses two key cache entries: 1640 * Michael MIC TX/RX keys in the same key cache entry 1641 * (idx = main index + 64): 1642 * key0 [31:0] = RX key [31:0] 1643 * key1 [15:0] = TX key [31:16] 1644 * key1 [31:16] = reserved 1645 * key2 [31:0] = RX key [63:32] 1646 * key3 [15:0] = TX key [15:0] 1647 * key3 [31:16] = reserved 1648 * key4 [31:0] = TX key [63:32] 1649 */ 1650 u32 mic0, mic1, mic2, mic3, mic4; 1651 1652 mic0 = get_unaligned_le32(k->kv_mic + 0); 1653 mic2 = get_unaligned_le32(k->kv_mic + 4); 1654 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; 1655 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; 1656 mic4 = get_unaligned_le32(k->kv_txmic + 4); 1657 1658 /* Write RX[31:0] and TX[31:16] */ 1659 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 1660 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); 1661 1662 /* Write RX[63:32] and TX[15:0] */ 1663 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 1664 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); 1665 1666 /* Write TX[63:32] and keyType(reserved) */ 1667 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); 1668 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 1669 AR_KEYTABLE_TYPE_CLR); 1670 1671 } else { 1672 /* 1673 * TKIP uses four key cache entries (two for group 1674 * keys): 1675 * Michael MIC TX/RX keys are in different key cache 1676 * entries (idx = main index + 64 for TX and 1677 * main index + 32 + 96 for RX): 1678 * key0 [31:0] = TX/RX MIC key [31:0] 1679 * key1 [31:0] = reserved 1680 * key2 [31:0] = TX/RX MIC key [63:32] 1681 * key3 [31:0] = reserved 1682 * key4 [31:0] = reserved 1683 * 1684 * Upper layer code will call this function separately 1685 * for TX and RX keys when these registers offsets are 1686 * used. 1687 */ 1688 u32 mic0, mic2; 1689 1690 mic0 = get_unaligned_le32(k->kv_mic + 0); 1691 mic2 = get_unaligned_le32(k->kv_mic + 4); 1692 1693 /* Write MIC key[31:0] */ 1694 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 1695 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 1696 1697 /* Write MIC key[63:32] */ 1698 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 1699 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 1700 1701 /* Write TX[63:32] and keyType(reserved) */ 1702 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); 1703 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 1704 AR_KEYTABLE_TYPE_CLR); 1705 } 1706 1707 /* MAC address registers are reserved for the MIC entry */ 1708 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); 1709 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); 1710 1711 /* 1712 * Write the correct (un-inverted) key[47:0] last to enable 1713 * TKIP now that all other registers are set with correct 1714 * values. 1715 */ 1716 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 1717 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 1718 } else { 1719 /* Write key[47:0] */ 1720 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 1721 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 1722 1723 /* Write key[95:48] */ 1724 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 1725 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 1726 1727 /* Write key[127:96] and key type */ 1728 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 1729 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 1730 1731 /* Write MAC address for the entry */ 1732 (void) ath9k_hw_keysetmac(ah, entry, mac); 1733 } 1734 1735 return true; 1736} 1737EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); 1738 1739bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) 1740{ 1741 if (entry < ah->caps.keycache_size) { 1742 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 1743 if (val & AR_KEYTABLE_VALID) 1744 return true; 1745 } 1746 return false; 1747} 1748EXPORT_SYMBOL(ath9k_hw_keyisvalid); 1749 1750/******************************/ 1751/* Power Management (Chipset) */ 1752/******************************/ 1753 1754/* 1755 * Notify Power Mgt is disabled in self-generated frames. 1756 * If requested, force chip to sleep. 1757 */ 1758static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1759{ 1760 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1761 if (setChip) { 1762 /* 1763 * Clear the RTC force wake bit to allow the 1764 * mac to go to sleep. 1765 */ 1766 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1767 AR_RTC_FORCE_WAKE_EN); 1768 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1769 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1770 1771 /* Shutdown chip. Active low */ 1772 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1773 REG_CLR_BIT(ah, (AR_RTC_RESET), 1774 AR_RTC_RESET_EN); 1775 } 1776 1777 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1778 if (AR_SREV_9300_20_OR_LATER(ah)) 1779 REG_WRITE(ah, AR_WA, 1780 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1781} 1782 1783/* 1784 * Notify Power Management is enabled in self-generating 1785 * frames. If request, set power mode of chip to 1786 * auto/normal. Duration in units of 128us (1/8 TU). 1787 */ 1788static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1789{ 1790 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1791 if (setChip) { 1792 struct ath9k_hw_capabilities *pCap = &ah->caps; 1793 1794 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1795 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1796 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1797 AR_RTC_FORCE_WAKE_ON_INT); 1798 } else { 1799 /* 1800 * Clear the RTC force wake bit to allow the 1801 * mac to go to sleep. 1802 */ 1803 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1804 AR_RTC_FORCE_WAKE_EN); 1805 } 1806 } 1807 1808 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1809 if (AR_SREV_9300_20_OR_LATER(ah)) 1810 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1811} 1812 1813static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1814{ 1815 u32 val; 1816 int i; 1817 1818 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1819 if (AR_SREV_9300_20_OR_LATER(ah)) { 1820 REG_WRITE(ah, AR_WA, ah->WARegVal); 1821 udelay(10); 1822 } 1823 1824 if (setChip) { 1825 if ((REG_READ(ah, AR_RTC_STATUS) & 1826 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1827 if (ath9k_hw_set_reset_reg(ah, 1828 ATH9K_RESET_POWER_ON) != true) { 1829 return false; 1830 } 1831 if (!AR_SREV_9300_20_OR_LATER(ah)) 1832 ath9k_hw_init_pll(ah, NULL); 1833 } 1834 if (AR_SREV_9100(ah)) 1835 REG_SET_BIT(ah, AR_RTC_RESET, 1836 AR_RTC_RESET_EN); 1837 1838 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1839 AR_RTC_FORCE_WAKE_EN); 1840 udelay(50); 1841 1842 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1843 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1844 if (val == AR_RTC_STATUS_ON) 1845 break; 1846 udelay(50); 1847 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1848 AR_RTC_FORCE_WAKE_EN); 1849 } 1850 if (i == 0) { 1851 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1852 "Failed to wakeup in %uus\n", 1853 POWER_UP_TIME / 20); 1854 return false; 1855 } 1856 } 1857 1858 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1859 1860 return true; 1861} 1862 1863bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1864{ 1865 struct ath_common *common = ath9k_hw_common(ah); 1866 int status = true, setChip = true; 1867 static const char *modes[] = { 1868 "AWAKE", 1869 "FULL-SLEEP", 1870 "NETWORK SLEEP", 1871 "UNDEFINED" 1872 }; 1873 1874 if (ah->power_mode == mode) 1875 return status; 1876 1877 ath_print(common, ATH_DBG_RESET, "%s -> %s\n", 1878 modes[ah->power_mode], modes[mode]); 1879 1880 switch (mode) { 1881 case ATH9K_PM_AWAKE: 1882 status = ath9k_hw_set_power_awake(ah, setChip); 1883 break; 1884 case ATH9K_PM_FULL_SLEEP: 1885 ath9k_set_power_sleep(ah, setChip); 1886 ah->chip_fullsleep = true; 1887 break; 1888 case ATH9K_PM_NETWORK_SLEEP: 1889 ath9k_set_power_network_sleep(ah, setChip); 1890 break; 1891 default: 1892 ath_print(common, ATH_DBG_FATAL, 1893 "Unknown power mode %u\n", mode); 1894 return false; 1895 } 1896 ah->power_mode = mode; 1897 1898 return status; 1899} 1900EXPORT_SYMBOL(ath9k_hw_setpower); 1901 1902/*******************/ 1903/* Beacon Handling */ 1904/*******************/ 1905 1906void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1907{ 1908 int flags = 0; 1909 1910 ah->beacon_interval = beacon_period; 1911 1912 ENABLE_REGWRITE_BUFFER(ah); 1913 1914 switch (ah->opmode) { 1915 case NL80211_IFTYPE_STATION: 1916 case NL80211_IFTYPE_MONITOR: 1917 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1918 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); 1919 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); 1920 flags |= AR_TBTT_TIMER_EN; 1921 break; 1922 case NL80211_IFTYPE_ADHOC: 1923 case NL80211_IFTYPE_MESH_POINT: 1924 REG_SET_BIT(ah, AR_TXCFG, 1925 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1926 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 1927 TU_TO_USEC(next_beacon + 1928 (ah->atim_window ? ah-> 1929 atim_window : 1))); 1930 flags |= AR_NDP_TIMER_EN; 1931 case NL80211_IFTYPE_AP: 1932 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1933 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 1934 TU_TO_USEC(next_beacon - 1935 ah->config. 1936 dma_beacon_response_time)); 1937 REG_WRITE(ah, AR_NEXT_SWBA, 1938 TU_TO_USEC(next_beacon - 1939 ah->config. 1940 sw_beacon_response_time)); 1941 flags |= 1942 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1943 break; 1944 default: 1945 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, 1946 "%s: unsupported opmode: %d\n", 1947 __func__, ah->opmode); 1948 return; 1949 break; 1950 } 1951 1952 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1953 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1954 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1955 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1956 1957 REGWRITE_BUFFER_FLUSH(ah); 1958 DISABLE_REGWRITE_BUFFER(ah); 1959 1960 beacon_period &= ~ATH9K_BEACON_ENA; 1961 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1962 ath9k_hw_reset_tsf(ah); 1963 } 1964 1965 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1966} 1967EXPORT_SYMBOL(ath9k_hw_beaconinit); 1968 1969void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1970 const struct ath9k_beacon_state *bs) 1971{ 1972 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 1973 struct ath9k_hw_capabilities *pCap = &ah->caps; 1974 struct ath_common *common = ath9k_hw_common(ah); 1975 1976 ENABLE_REGWRITE_BUFFER(ah); 1977 1978 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1979 1980 REG_WRITE(ah, AR_BEACON_PERIOD, 1981 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1982 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1983 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1984 1985 REGWRITE_BUFFER_FLUSH(ah); 1986 DISABLE_REGWRITE_BUFFER(ah); 1987 1988 REG_RMW_FIELD(ah, AR_RSSI_THR, 1989 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1990 1991 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 1992 1993 if (bs->bs_sleepduration > beaconintval) 1994 beaconintval = bs->bs_sleepduration; 1995 1996 dtimperiod = bs->bs_dtimperiod; 1997 if (bs->bs_sleepduration > dtimperiod) 1998 dtimperiod = bs->bs_sleepduration; 1999 2000 if (beaconintval == dtimperiod) 2001 nextTbtt = bs->bs_nextdtim; 2002 else 2003 nextTbtt = bs->bs_nexttbtt; 2004 2005 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2006 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 2007 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 2008 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 2009 2010 ENABLE_REGWRITE_BUFFER(ah); 2011 2012 REG_WRITE(ah, AR_NEXT_DTIM, 2013 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2014 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2015 2016 REG_WRITE(ah, AR_SLEEP1, 2017 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2018 | AR_SLEEP1_ASSUME_DTIM); 2019 2020 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2021 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2022 else 2023 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2024 2025 REG_WRITE(ah, AR_SLEEP2, 2026 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2027 2028 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2029 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2030 2031 REGWRITE_BUFFER_FLUSH(ah); 2032 DISABLE_REGWRITE_BUFFER(ah); 2033 2034 REG_SET_BIT(ah, AR_TIMER_MODE, 2035 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2036 AR_DTIM_TIMER_EN); 2037 2038 /* TSF Out of Range Threshold */ 2039 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2040} 2041EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2042 2043/*******************/ 2044/* HW Capabilities */ 2045/*******************/ 2046 2047int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2048{ 2049 struct ath9k_hw_capabilities *pCap = &ah->caps; 2050 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2051 struct ath_common *common = ath9k_hw_common(ah); 2052 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 2053 2054 u16 capField = 0, eeval; 2055 2056 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2057 regulatory->current_rd = eeval; 2058 2059 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 2060 if (AR_SREV_9285_10_OR_LATER(ah)) 2061 eeval |= AR9285_RDEXT_DEFAULT; 2062 regulatory->current_rd_ext = eeval; 2063 2064 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 2065 2066 if (ah->opmode != NL80211_IFTYPE_AP && 2067 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2068 if (regulatory->current_rd == 0x64 || 2069 regulatory->current_rd == 0x65) 2070 regulatory->current_rd += 5; 2071 else if (regulatory->current_rd == 0x41) 2072 regulatory->current_rd = 0x43; 2073 ath_print(common, ATH_DBG_REGULATORY, 2074 "regdomain mapped to 0x%x\n", regulatory->current_rd); 2075 } 2076 2077 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2078 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2079 ath_print(common, ATH_DBG_FATAL, 2080 "no band has been marked as supported in EEPROM.\n"); 2081 return -EINVAL; 2082 } 2083 2084 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); 2085 2086 if (eeval & AR5416_OPFLAGS_11A) { 2087 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 2088 if (ah->config.ht_enable) { 2089 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) 2090 set_bit(ATH9K_MODE_11NA_HT20, 2091 pCap->wireless_modes); 2092 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { 2093 set_bit(ATH9K_MODE_11NA_HT40PLUS, 2094 pCap->wireless_modes); 2095 set_bit(ATH9K_MODE_11NA_HT40MINUS, 2096 pCap->wireless_modes); 2097 } 2098 } 2099 } 2100 2101 if (eeval & AR5416_OPFLAGS_11G) { 2102 set_bit(ATH9K_MODE_11G, pCap->wireless_modes); 2103 if (ah->config.ht_enable) { 2104 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) 2105 set_bit(ATH9K_MODE_11NG_HT20, 2106 pCap->wireless_modes); 2107 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { 2108 set_bit(ATH9K_MODE_11NG_HT40PLUS, 2109 pCap->wireless_modes); 2110 set_bit(ATH9K_MODE_11NG_HT40MINUS, 2111 pCap->wireless_modes); 2112 } 2113 } 2114 } 2115 2116 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2117 /* 2118 * For AR9271 we will temporarilly uses the rx chainmax as read from 2119 * the EEPROM. 2120 */ 2121 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2122 !(eeval & AR5416_OPFLAGS_11A) && 2123 !(AR_SREV_9271(ah))) 2124 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2125 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2126 else 2127 /* Use rx_chainmask from EEPROM. */ 2128 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2129 2130 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 2131 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2132 2133 pCap->low_2ghz_chan = 2312; 2134 pCap->high_2ghz_chan = 2732; 2135 2136 pCap->low_5ghz_chan = 4920; 2137 pCap->high_5ghz_chan = 6100; 2138 2139 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; 2140 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; 2141 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; 2142 2143 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; 2144 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; 2145 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; 2146 2147 if (ah->config.ht_enable) 2148 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2149 else 2150 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2151 2152 pCap->hw_caps |= ATH9K_HW_CAP_GTT; 2153 pCap->hw_caps |= ATH9K_HW_CAP_VEOL; 2154 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; 2155 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; 2156 2157 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 2158 pCap->total_queues = 2159 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 2160 else 2161 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 2162 2163 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 2164 pCap->keycache_size = 2165 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 2166 else 2167 pCap->keycache_size = AR_KEYTABLE_SIZE; 2168 2169 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; 2170 2171 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 2172 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; 2173 else 2174 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 2175 2176 if (AR_SREV_9271(ah)) 2177 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2178 else if (AR_SREV_9285_10_OR_LATER(ah)) 2179 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2180 else if (AR_SREV_9280_10_OR_LATER(ah)) 2181 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2182 else 2183 pCap->num_gpio_pins = AR_NUM_GPIO; 2184 2185 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 2186 pCap->hw_caps |= ATH9K_HW_CAP_CST; 2187 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2188 } else { 2189 pCap->rts_aggr_limit = (8 * 1024); 2190 } 2191 2192 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 2193 2194#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2195 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2196 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2197 ah->rfkill_gpio = 2198 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2199 ah->rfkill_polarity = 2200 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2201 2202 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2203 } 2204#endif 2205 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2206 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2207 else 2208 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2209 2210 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2211 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2212 else 2213 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2214 2215 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2216 pCap->reg_cap = 2217 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2218 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2219 AR_EEPROM_EEREGCAP_EN_KK_U2 | 2220 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2221 } else { 2222 pCap->reg_cap = 2223 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2224 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2225 } 2226 2227 /* Advertise midband for AR5416 with FCC midband set in eeprom */ 2228 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && 2229 AR_SREV_5416(ah)) 2230 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2231 2232 pCap->num_antcfg_5ghz = 2233 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 2234 pCap->num_antcfg_2ghz = 2235 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 2236 2237 if (AR_SREV_9280_10_OR_LATER(ah) && 2238 ath9k_hw_btcoex_supported(ah)) { 2239 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 2240 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 2241 2242 if (AR_SREV_9285(ah)) { 2243 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2244 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; 2245 } else { 2246 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 2247 } 2248 } else { 2249 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2250 } 2251 2252 if (AR_SREV_9300_20_OR_LATER(ah)) { 2253 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC | 2254 ATH9K_HW_CAP_FASTCLOCK; 2255 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2256 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2257 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2258 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2259 pCap->txs_len = sizeof(struct ar9003_txs); 2260 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2261 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2262 } else { 2263 pCap->tx_desc_len = sizeof(struct ath_desc); 2264 if (AR_SREV_9280_20(ah) && 2265 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= 2266 AR5416_EEP_MINOR_VER_16) || 2267 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) 2268 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2269 } 2270 2271 if (AR_SREV_9300_20_OR_LATER(ah)) 2272 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2273 2274 if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah)) 2275 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2276 2277 return 0; 2278} 2279 2280/****************************/ 2281/* GPIO / RFKILL / Antennae */ 2282/****************************/ 2283 2284static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2285 u32 gpio, u32 type) 2286{ 2287 int addr; 2288 u32 gpio_shift, tmp; 2289 2290 if (gpio > 11) 2291 addr = AR_GPIO_OUTPUT_MUX3; 2292 else if (gpio > 5) 2293 addr = AR_GPIO_OUTPUT_MUX2; 2294 else 2295 addr = AR_GPIO_OUTPUT_MUX1; 2296 2297 gpio_shift = (gpio % 6) * 5; 2298 2299 if (AR_SREV_9280_20_OR_LATER(ah) 2300 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2301 REG_RMW(ah, addr, (type << gpio_shift), 2302 (0x1f << gpio_shift)); 2303 } else { 2304 tmp = REG_READ(ah, addr); 2305 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2306 tmp &= ~(0x1f << gpio_shift); 2307 tmp |= (type << gpio_shift); 2308 REG_WRITE(ah, addr, tmp); 2309 } 2310} 2311 2312void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2313{ 2314 u32 gpio_shift; 2315 2316 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2317 2318 gpio_shift = gpio << 1; 2319 2320 REG_RMW(ah, 2321 AR_GPIO_OE_OUT, 2322 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2323 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2324} 2325EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2326 2327u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2328{ 2329#define MS_REG_READ(x, y) \ 2330 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2331 2332 if (gpio >= ah->caps.num_gpio_pins) 2333 return 0xffffffff; 2334 2335 if (AR_SREV_9300_20_OR_LATER(ah)) 2336 return MS_REG_READ(AR9300, gpio) != 0; 2337 else if (AR_SREV_9271(ah)) 2338 return MS_REG_READ(AR9271, gpio) != 0; 2339 else if (AR_SREV_9287_10_OR_LATER(ah)) 2340 return MS_REG_READ(AR9287, gpio) != 0; 2341 else if (AR_SREV_9285_10_OR_LATER(ah)) 2342 return MS_REG_READ(AR9285, gpio) != 0; 2343 else if (AR_SREV_9280_10_OR_LATER(ah)) 2344 return MS_REG_READ(AR928X, gpio) != 0; 2345 else 2346 return MS_REG_READ(AR, gpio) != 0; 2347} 2348EXPORT_SYMBOL(ath9k_hw_gpio_get); 2349 2350void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2351 u32 ah_signal_type) 2352{ 2353 u32 gpio_shift; 2354 2355 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2356 2357 gpio_shift = 2 * gpio; 2358 2359 REG_RMW(ah, 2360 AR_GPIO_OE_OUT, 2361 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2362 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2363} 2364EXPORT_SYMBOL(ath9k_hw_cfg_output); 2365 2366void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2367{ 2368 if (AR_SREV_9271(ah)) 2369 val = ~val; 2370 2371 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2372 AR_GPIO_BIT(gpio)); 2373} 2374EXPORT_SYMBOL(ath9k_hw_set_gpio); 2375 2376u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2377{ 2378 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2379} 2380EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2381 2382void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2383{ 2384 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2385} 2386EXPORT_SYMBOL(ath9k_hw_setantenna); 2387 2388/*********************/ 2389/* General Operation */ 2390/*********************/ 2391 2392u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2393{ 2394 u32 bits = REG_READ(ah, AR_RX_FILTER); 2395 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2396 2397 if (phybits & AR_PHY_ERR_RADAR) 2398 bits |= ATH9K_RX_FILTER_PHYRADAR; 2399 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2400 bits |= ATH9K_RX_FILTER_PHYERR; 2401 2402 return bits; 2403} 2404EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2405 2406void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2407{ 2408 u32 phybits; 2409 2410 ENABLE_REGWRITE_BUFFER(ah); 2411 2412 REG_WRITE(ah, AR_RX_FILTER, bits); 2413 2414 phybits = 0; 2415 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2416 phybits |= AR_PHY_ERR_RADAR; 2417 if (bits & ATH9K_RX_FILTER_PHYERR) 2418 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2419 REG_WRITE(ah, AR_PHY_ERR, phybits); 2420 2421 if (phybits) 2422 REG_WRITE(ah, AR_RXCFG, 2423 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 2424 else 2425 REG_WRITE(ah, AR_RXCFG, 2426 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2427 2428 REGWRITE_BUFFER_FLUSH(ah); 2429 DISABLE_REGWRITE_BUFFER(ah); 2430} 2431EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2432 2433bool ath9k_hw_phy_disable(struct ath_hw *ah) 2434{ 2435 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2436 return false; 2437 2438 ath9k_hw_init_pll(ah, NULL); 2439 return true; 2440} 2441EXPORT_SYMBOL(ath9k_hw_phy_disable); 2442 2443bool ath9k_hw_disable(struct ath_hw *ah) 2444{ 2445 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2446 return false; 2447 2448 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2449 return false; 2450 2451 ath9k_hw_init_pll(ah, NULL); 2452 return true; 2453} 2454EXPORT_SYMBOL(ath9k_hw_disable); 2455 2456void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 2457{ 2458 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2459 struct ath9k_channel *chan = ah->curchan; 2460 struct ieee80211_channel *channel = chan->chan; 2461 2462 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 2463 2464 ah->eep_ops->set_txpower(ah, chan, 2465 ath9k_regd_get_ctl(regulatory, chan), 2466 channel->max_antenna_gain * 2, 2467 channel->max_power * 2, 2468 min((u32) MAX_RATE_POWER, 2469 (u32) regulatory->power_limit)); 2470} 2471EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2472 2473void ath9k_hw_setopmode(struct ath_hw *ah) 2474{ 2475 ath9k_hw_set_operating_mode(ah, ah->opmode); 2476} 2477EXPORT_SYMBOL(ath9k_hw_setopmode); 2478 2479void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2480{ 2481 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2482 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2483} 2484EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2485 2486void ath9k_hw_write_associd(struct ath_hw *ah) 2487{ 2488 struct ath_common *common = ath9k_hw_common(ah); 2489 2490 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2491 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2492 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2493} 2494EXPORT_SYMBOL(ath9k_hw_write_associd); 2495 2496#define ATH9K_MAX_TSF_READ 10 2497 2498u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2499{ 2500 u32 tsf_lower, tsf_upper1, tsf_upper2; 2501 int i; 2502 2503 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2504 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2505 tsf_lower = REG_READ(ah, AR_TSF_L32); 2506 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2507 if (tsf_upper2 == tsf_upper1) 2508 break; 2509 tsf_upper1 = tsf_upper2; 2510 } 2511 2512 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2513 2514 return (((u64)tsf_upper1 << 32) | tsf_lower); 2515} 2516EXPORT_SYMBOL(ath9k_hw_gettsf64); 2517 2518void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2519{ 2520 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2521 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2522} 2523EXPORT_SYMBOL(ath9k_hw_settsf64); 2524 2525void ath9k_hw_reset_tsf(struct ath_hw *ah) 2526{ 2527 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2528 AH_TSF_WRITE_TIMEOUT)) 2529 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 2530 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2531 2532 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2533} 2534EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2535 2536void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2537{ 2538 if (setting) 2539 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2540 else 2541 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2542} 2543EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2544 2545void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2546{ 2547 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2548 u32 macmode; 2549 2550 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2551 macmode = AR_2040_JOINED_RX_CLEAR; 2552 else 2553 macmode = 0; 2554 2555 REG_WRITE(ah, AR_2040_MODE, macmode); 2556} 2557 2558/* HW Generic timers configuration */ 2559 2560static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2561{ 2562 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2563 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2564 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2565 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2566 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2567 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2568 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2569 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2570 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2571 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2572 AR_NDP2_TIMER_MODE, 0x0002}, 2573 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2574 AR_NDP2_TIMER_MODE, 0x0004}, 2575 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2576 AR_NDP2_TIMER_MODE, 0x0008}, 2577 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2578 AR_NDP2_TIMER_MODE, 0x0010}, 2579 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2580 AR_NDP2_TIMER_MODE, 0x0020}, 2581 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2582 AR_NDP2_TIMER_MODE, 0x0040}, 2583 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2584 AR_NDP2_TIMER_MODE, 0x0080} 2585}; 2586 2587/* HW generic timer primitives */ 2588 2589/* compute and clear index of rightmost 1 */ 2590static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2591{ 2592 u32 b; 2593 2594 b = *mask; 2595 b &= (0-b); 2596 *mask &= ~b; 2597 b *= debruijn32; 2598 b >>= 27; 2599 2600 return timer_table->gen_timer_index[b]; 2601} 2602 2603u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2604{ 2605 return REG_READ(ah, AR_TSF_L32); 2606} 2607EXPORT_SYMBOL(ath9k_hw_gettsf32); 2608 2609struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2610 void (*trigger)(void *), 2611 void (*overflow)(void *), 2612 void *arg, 2613 u8 timer_index) 2614{ 2615 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2616 struct ath_gen_timer *timer; 2617 2618 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2619 2620 if (timer == NULL) { 2621 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2622 "Failed to allocate memory" 2623 "for hw timer[%d]\n", timer_index); 2624 return NULL; 2625 } 2626 2627 /* allocate a hardware generic timer slot */ 2628 timer_table->timers[timer_index] = timer; 2629 timer->index = timer_index; 2630 timer->trigger = trigger; 2631 timer->overflow = overflow; 2632 timer->arg = arg; 2633 2634 return timer; 2635} 2636EXPORT_SYMBOL(ath_gen_timer_alloc); 2637 2638void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2639 struct ath_gen_timer *timer, 2640 u32 timer_next, 2641 u32 timer_period) 2642{ 2643 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2644 u32 tsf; 2645 2646 BUG_ON(!timer_period); 2647 2648 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2649 2650 tsf = ath9k_hw_gettsf32(ah); 2651 2652 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2653 "curent tsf %x period %x" 2654 "timer_next %x\n", tsf, timer_period, timer_next); 2655 2656 /* 2657 * Pull timer_next forward if the current TSF already passed it 2658 * because of software latency 2659 */ 2660 if (timer_next < tsf) 2661 timer_next = tsf + timer_period; 2662 2663 /* 2664 * Program generic timer registers 2665 */ 2666 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2667 timer_next); 2668 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2669 timer_period); 2670 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2671 gen_tmr_configuration[timer->index].mode_mask); 2672 2673 /* Enable both trigger and thresh interrupt masks */ 2674 REG_SET_BIT(ah, AR_IMR_S5, 2675 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2676 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2677} 2678EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2679 2680void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2681{ 2682 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2683 2684 if ((timer->index < AR_FIRST_NDP_TIMER) || 2685 (timer->index >= ATH_MAX_GEN_TIMER)) { 2686 return; 2687 } 2688 2689 /* Clear generic timer enable bits. */ 2690 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2691 gen_tmr_configuration[timer->index].mode_mask); 2692 2693 /* Disable both trigger and thresh interrupt masks */ 2694 REG_CLR_BIT(ah, AR_IMR_S5, 2695 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2696 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2697 2698 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2699} 2700EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2701 2702void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2703{ 2704 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2705 2706 /* free the hardware generic timer slot */ 2707 timer_table->timers[timer->index] = NULL; 2708 kfree(timer); 2709} 2710EXPORT_SYMBOL(ath_gen_timer_free); 2711 2712/* 2713 * Generic Timer Interrupts handling 2714 */ 2715void ath_gen_timer_isr(struct ath_hw *ah) 2716{ 2717 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2718 struct ath_gen_timer *timer; 2719 struct ath_common *common = ath9k_hw_common(ah); 2720 u32 trigger_mask, thresh_mask, index; 2721 2722 /* get hardware generic timer interrupt status */ 2723 trigger_mask = ah->intr_gen_timer_trigger; 2724 thresh_mask = ah->intr_gen_timer_thresh; 2725 trigger_mask &= timer_table->timer_mask.val; 2726 thresh_mask &= timer_table->timer_mask.val; 2727 2728 trigger_mask &= ~thresh_mask; 2729 2730 while (thresh_mask) { 2731 index = rightmost_index(timer_table, &thresh_mask); 2732 timer = timer_table->timers[index]; 2733 BUG_ON(!timer); 2734 ath_print(common, ATH_DBG_HWTIMER, 2735 "TSF overflow for Gen timer %d\n", index); 2736 timer->overflow(timer->arg); 2737 } 2738 2739 while (trigger_mask) { 2740 index = rightmost_index(timer_table, &trigger_mask); 2741 timer = timer_table->timers[index]; 2742 BUG_ON(!timer); 2743 ath_print(common, ATH_DBG_HWTIMER, 2744 "Gen timer[%d] trigger\n", index); 2745 timer->trigger(timer->arg); 2746 } 2747} 2748EXPORT_SYMBOL(ath_gen_timer_isr); 2749 2750/********/ 2751/* HTC */ 2752/********/ 2753 2754void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2755{ 2756 ah->htc_reset_init = true; 2757} 2758EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2759 2760static struct { 2761 u32 version; 2762 const char * name; 2763} ath_mac_bb_names[] = { 2764 /* Devices with external radios */ 2765 { AR_SREV_VERSION_5416_PCI, "5416" }, 2766 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2767 { AR_SREV_VERSION_9100, "9100" }, 2768 { AR_SREV_VERSION_9160, "9160" }, 2769 /* Single-chip solutions */ 2770 { AR_SREV_VERSION_9280, "9280" }, 2771 { AR_SREV_VERSION_9285, "9285" }, 2772 { AR_SREV_VERSION_9287, "9287" }, 2773 { AR_SREV_VERSION_9271, "9271" }, 2774 { AR_SREV_VERSION_9300, "9300" }, 2775}; 2776 2777/* For devices with external radios */ 2778static struct { 2779 u16 version; 2780 const char * name; 2781} ath_rf_names[] = { 2782 { 0, "5133" }, 2783 { AR_RAD5133_SREV_MAJOR, "5133" }, 2784 { AR_RAD5122_SREV_MAJOR, "5122" }, 2785 { AR_RAD2133_SREV_MAJOR, "2133" }, 2786 { AR_RAD2122_SREV_MAJOR, "2122" } 2787}; 2788 2789/* 2790 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2791 */ 2792static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2793{ 2794 int i; 2795 2796 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2797 if (ath_mac_bb_names[i].version == mac_bb_version) { 2798 return ath_mac_bb_names[i].name; 2799 } 2800 } 2801 2802 return "????"; 2803} 2804 2805/* 2806 * Return the RF name. "????" is returned if the RF is unknown. 2807 * Used for devices with external radios. 2808 */ 2809static const char *ath9k_hw_rf_name(u16 rf_version) 2810{ 2811 int i; 2812 2813 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2814 if (ath_rf_names[i].version == rf_version) { 2815 return ath_rf_names[i].name; 2816 } 2817 } 2818 2819 return "????"; 2820} 2821 2822void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2823{ 2824 int used; 2825 2826 /* chipsets >= AR9280 are single-chip */ 2827 if (AR_SREV_9280_10_OR_LATER(ah)) { 2828 used = snprintf(hw_name, len, 2829 "Atheros AR%s Rev:%x", 2830 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2831 ah->hw_version.macRev); 2832 } 2833 else { 2834 used = snprintf(hw_name, len, 2835 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2836 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2837 ah->hw_version.macRev, 2838 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2839 AR_RADIO_SREV_MAJOR)), 2840 ah->hw_version.phyRev); 2841 } 2842 2843 hw_name[used] = '\0'; 2844} 2845EXPORT_SYMBOL(ath9k_hw_name); 2846