hw.c revision 882b709230246de3359b04b195ad3e80b93b73ef
1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <asm/unaligned.h> 19 20#include "ath9k.h" 21#include "initvals.h" 22 23static int btcoex_enable; 24module_param(btcoex_enable, bool, 0); 25MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support"); 26 27#define ATH9K_CLOCK_RATE_CCK 22 28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 30 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, 33 enum ath9k_ht_macmode macmode); 34static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 35 struct ar5416_eeprom_def *pEepData, 36 u32 reg, u32 value); 37static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); 38static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); 39 40/********************/ 41/* Helper Functions */ 42/********************/ 43 44static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks) 45{ 46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 47 48 if (!ah->curchan) /* should really check for CCK instead */ 49 return clks / ATH9K_CLOCK_RATE_CCK; 50 if (conf->channel->band == IEEE80211_BAND_2GHZ) 51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; 52 53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM; 54} 55 56static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks) 57{ 58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 59 60 if (conf_is_ht40(conf)) 61 return ath9k_hw_mac_usec(ah, clks) / 2; 62 else 63 return ath9k_hw_mac_usec(ah, clks); 64} 65 66static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) 67{ 68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 69 70 if (!ah->curchan) /* should really check for CCK instead */ 71 return usecs *ATH9K_CLOCK_RATE_CCK; 72 if (conf->channel->band == IEEE80211_BAND_2GHZ) 73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; 75} 76 77static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 78{ 79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 80 81 if (conf_is_ht40(conf)) 82 return ath9k_hw_mac_clks(ah, usecs) * 2; 83 else 84 return ath9k_hw_mac_clks(ah, usecs); 85} 86 87bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 88{ 89 int i; 90 91 BUG_ON(timeout < AH_TIME_QUANTUM); 92 93 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 94 if ((REG_READ(ah, reg) & mask) == val) 95 return true; 96 97 udelay(AH_TIME_QUANTUM); 98 } 99 100 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 102 timeout, reg, REG_READ(ah, reg), mask, val); 103 104 return false; 105} 106 107u32 ath9k_hw_reverse_bits(u32 val, u32 n) 108{ 109 u32 retval; 110 int i; 111 112 for (i = 0, retval = 0; i < n; i++) { 113 retval = (retval << 1) | (val & 1); 114 val >>= 1; 115 } 116 return retval; 117} 118 119bool ath9k_get_channel_edges(struct ath_hw *ah, 120 u16 flags, u16 *low, 121 u16 *high) 122{ 123 struct ath9k_hw_capabilities *pCap = &ah->caps; 124 125 if (flags & CHANNEL_5GHZ) { 126 *low = pCap->low_5ghz_chan; 127 *high = pCap->high_5ghz_chan; 128 return true; 129 } 130 if ((flags & CHANNEL_2GHZ)) { 131 *low = pCap->low_2ghz_chan; 132 *high = pCap->high_2ghz_chan; 133 return true; 134 } 135 return false; 136} 137 138u16 ath9k_hw_computetxtime(struct ath_hw *ah, 139 struct ath_rate_table *rates, 140 u32 frameLen, u16 rateix, 141 bool shortPreamble) 142{ 143 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 144 u32 kbps; 145 146 kbps = rates->info[rateix].ratekbps; 147 148 if (kbps == 0) 149 return 0; 150 151 switch (rates->info[rateix].phy) { 152 case WLAN_RC_PHY_CCK: 153 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 154 if (shortPreamble && rates->info[rateix].short_preamble) 155 phyTime >>= 1; 156 numBits = frameLen << 3; 157 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 158 break; 159 case WLAN_RC_PHY_OFDM: 160 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 161 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 162 numBits = OFDM_PLCP_BITS + (frameLen << 3); 163 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 164 txTime = OFDM_SIFS_TIME_QUARTER 165 + OFDM_PREAMBLE_TIME_QUARTER 166 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 167 } else if (ah->curchan && 168 IS_CHAN_HALF_RATE(ah->curchan)) { 169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 170 numBits = OFDM_PLCP_BITS + (frameLen << 3); 171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 172 txTime = OFDM_SIFS_TIME_HALF + 173 OFDM_PREAMBLE_TIME_HALF 174 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 175 } else { 176 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 177 numBits = OFDM_PLCP_BITS + (frameLen << 3); 178 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 179 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 180 + (numSymbols * OFDM_SYMBOL_TIME); 181 } 182 break; 183 default: 184 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 185 "Unknown phy %u (rate ix %u)\n", 186 rates->info[rateix].phy, rateix); 187 txTime = 0; 188 break; 189 } 190 191 return txTime; 192} 193 194void ath9k_hw_get_channel_centers(struct ath_hw *ah, 195 struct ath9k_channel *chan, 196 struct chan_centers *centers) 197{ 198 int8_t extoff; 199 200 if (!IS_CHAN_HT40(chan)) { 201 centers->ctl_center = centers->ext_center = 202 centers->synth_center = chan->channel; 203 return; 204 } 205 206 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 207 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 208 centers->synth_center = 209 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 210 extoff = 1; 211 } else { 212 centers->synth_center = 213 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 214 extoff = -1; 215 } 216 217 centers->ctl_center = 218 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 219 centers->ext_center = 220 centers->synth_center + (extoff * 221 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? 222 HT40_CHANNEL_CENTER_SHIFT : 15)); 223} 224 225/******************/ 226/* Chip Revisions */ 227/******************/ 228 229static void ath9k_hw_read_revisions(struct ath_hw *ah) 230{ 231 u32 val; 232 233 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 234 235 if (val == 0xFF) { 236 val = REG_READ(ah, AR_SREV); 237 ah->hw_version.macVersion = 238 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 239 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 240 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 241 } else { 242 if (!AR_SREV_9100(ah)) 243 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 244 245 ah->hw_version.macRev = val & AR_SREV_REVISION; 246 247 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 248 ah->is_pciexpress = true; 249 } 250} 251 252static int ath9k_hw_get_radiorev(struct ath_hw *ah) 253{ 254 u32 val; 255 int i; 256 257 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 258 259 for (i = 0; i < 8; i++) 260 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 261 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 262 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 263 264 return ath9k_hw_reverse_bits(val, 8); 265} 266 267/************************************/ 268/* HW Attach, Detach, Init Routines */ 269/************************************/ 270 271static void ath9k_hw_disablepcie(struct ath_hw *ah) 272{ 273 if (AR_SREV_9100(ah)) 274 return; 275 276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 285 286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 287} 288 289static bool ath9k_hw_chip_test(struct ath_hw *ah) 290{ 291 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 292 u32 regHold[2]; 293 u32 patternData[4] = { 0x55555555, 294 0xaaaaaaaa, 295 0x66666666, 296 0x99999999 }; 297 int i, j; 298 299 for (i = 0; i < 2; i++) { 300 u32 addr = regAddr[i]; 301 u32 wrData, rdData; 302 303 regHold[i] = REG_READ(ah, addr); 304 for (j = 0; j < 0x100; j++) { 305 wrData = (j << 16) | j; 306 REG_WRITE(ah, addr, wrData); 307 rdData = REG_READ(ah, addr); 308 if (rdData != wrData) { 309 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 310 "address test failed " 311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 312 addr, wrData, rdData); 313 return false; 314 } 315 } 316 for (j = 0; j < 4; j++) { 317 wrData = patternData[j]; 318 REG_WRITE(ah, addr, wrData); 319 rdData = REG_READ(ah, addr); 320 if (wrData != rdData) { 321 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 322 "address test failed " 323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 324 addr, wrData, rdData); 325 return false; 326 } 327 } 328 REG_WRITE(ah, regAddr[i], regHold[i]); 329 } 330 udelay(100); 331 332 return true; 333} 334 335static const char *ath9k_hw_devname(u16 devid) 336{ 337 switch (devid) { 338 case AR5416_DEVID_PCI: 339 return "Atheros 5416"; 340 case AR5416_DEVID_PCIE: 341 return "Atheros 5418"; 342 case AR9160_DEVID_PCI: 343 return "Atheros 9160"; 344 case AR5416_AR9100_DEVID: 345 return "Atheros 9100"; 346 case AR9280_DEVID_PCI: 347 case AR9280_DEVID_PCIE: 348 return "Atheros 9280"; 349 case AR9285_DEVID_PCIE: 350 return "Atheros 9285"; 351 } 352 353 return NULL; 354} 355 356static void ath9k_hw_set_defaults(struct ath_hw *ah) 357{ 358 int i; 359 360 ah->config.dma_beacon_response_time = 2; 361 ah->config.sw_beacon_response_time = 10; 362 ah->config.additional_swba_backoff = 0; 363 ah->config.ack_6mb = 0x0; 364 ah->config.cwm_ignore_extcca = 0; 365 ah->config.pcie_powersave_enable = 0; 366 ah->config.pcie_clock_req = 0; 367 ah->config.pcie_waen = 0; 368 ah->config.analog_shiftreg = 1; 369 ah->config.ht_enable = 1; 370 ah->config.ofdm_trig_low = 200; 371 ah->config.ofdm_trig_high = 500; 372 ah->config.cck_trig_high = 200; 373 ah->config.cck_trig_low = 100; 374 ah->config.enable_ani = 1; 375 ah->config.diversity_control = 0; 376 ah->config.antenna_switch_swap = 0; 377 378 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 379 ah->config.spurchans[i][0] = AR_NO_SPUR; 380 ah->config.spurchans[i][1] = AR_NO_SPUR; 381 } 382 383 ah->config.intr_mitigation = true; 384 385 /* 386 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 387 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 388 * This means we use it for all AR5416 devices, and the few 389 * minor PCI AR9280 devices out there. 390 * 391 * Serialization is required because these devices do not handle 392 * well the case of two concurrent reads/writes due to the latency 393 * involved. During one read/write another read/write can be issued 394 * on another CPU while the previous read/write may still be working 395 * on our hardware, if we hit this case the hardware poops in a loop. 396 * We prevent this by serializing reads and writes. 397 * 398 * This issue is not present on PCI-Express devices or pre-AR5416 399 * devices (legacy, 802.11abg). 400 */ 401 if (num_possible_cpus() > 1) 402 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 403} 404 405static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, 406 int *status) 407{ 408 struct ath_hw *ah; 409 410 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 411 if (ah == NULL) { 412 DPRINTF(sc, ATH_DBG_FATAL, 413 "Cannot allocate memory for state block\n"); 414 *status = -ENOMEM; 415 return NULL; 416 } 417 418 ah->ah_sc = sc; 419 ah->hw_version.magic = AR5416_MAGIC; 420 ah->regulatory.country_code = CTRY_DEFAULT; 421 ah->hw_version.devid = devid; 422 ah->hw_version.subvendorid = 0; 423 424 ah->ah_flags = 0; 425 if ((devid == AR5416_AR9100_DEVID)) 426 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 427 if (!AR_SREV_9100(ah)) 428 ah->ah_flags = AH_USE_EEPROM; 429 430 ah->regulatory.power_limit = MAX_RATE_POWER; 431 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; 432 ah->atim_window = 0; 433 ah->diversity_control = ah->config.diversity_control; 434 ah->antenna_switch_swap = 435 ah->config.antenna_switch_swap; 436 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 437 ah->beacon_interval = 100; 438 ah->enable_32kHz_clock = DONT_USE_32KHZ; 439 ah->slottime = (u32) -1; 440 ah->acktimeout = (u32) -1; 441 ah->ctstimeout = (u32) -1; 442 ah->globaltxtimeout = (u32) -1; 443 444 ah->gbeacon_rate = 0; 445 446 return ah; 447} 448 449static int ath9k_hw_rfattach(struct ath_hw *ah) 450{ 451 bool rfStatus = false; 452 int ecode = 0; 453 454 rfStatus = ath9k_hw_init_rf(ah, &ecode); 455 if (!rfStatus) { 456 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 457 "RF setup failed, status: %u\n", ecode); 458 return ecode; 459 } 460 461 return 0; 462} 463 464static int ath9k_hw_rf_claim(struct ath_hw *ah) 465{ 466 u32 val; 467 468 REG_WRITE(ah, AR_PHY(0), 0x00000007); 469 470 val = ath9k_hw_get_radiorev(ah); 471 switch (val & AR_RADIO_SREV_MAJOR) { 472 case 0: 473 val = AR_RAD5133_SREV_MAJOR; 474 break; 475 case AR_RAD5133_SREV_MAJOR: 476 case AR_RAD5122_SREV_MAJOR: 477 case AR_RAD2133_SREV_MAJOR: 478 case AR_RAD2122_SREV_MAJOR: 479 break; 480 default: 481 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 482 "Radio Chip Rev 0x%02X not supported\n", 483 val & AR_RADIO_SREV_MAJOR); 484 return -EOPNOTSUPP; 485 } 486 487 ah->hw_version.analog5GhzRev = val; 488 489 return 0; 490} 491 492static int ath9k_hw_init_macaddr(struct ath_hw *ah) 493{ 494 u32 sum; 495 int i; 496 u16 eeval; 497 498 sum = 0; 499 for (i = 0; i < 3; i++) { 500 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); 501 sum += eeval; 502 ah->macaddr[2 * i] = eeval >> 8; 503 ah->macaddr[2 * i + 1] = eeval & 0xff; 504 } 505 if (sum == 0 || sum == 0xffff * 3) 506 return -EADDRNOTAVAIL; 507 508 return 0; 509} 510 511static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) 512{ 513 u32 rxgain_type; 514 515 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { 516 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); 517 518 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 519 INIT_INI_ARRAY(&ah->iniModesRxGain, 520 ar9280Modes_backoff_13db_rxgain_9280_2, 521 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); 522 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 523 INIT_INI_ARRAY(&ah->iniModesRxGain, 524 ar9280Modes_backoff_23db_rxgain_9280_2, 525 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); 526 else 527 INIT_INI_ARRAY(&ah->iniModesRxGain, 528 ar9280Modes_original_rxgain_9280_2, 529 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 530 } else { 531 INIT_INI_ARRAY(&ah->iniModesRxGain, 532 ar9280Modes_original_rxgain_9280_2, 533 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 534 } 535} 536 537static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) 538{ 539 u32 txgain_type; 540 541 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { 542 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 543 544 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 545 INIT_INI_ARRAY(&ah->iniModesTxGain, 546 ar9280Modes_high_power_tx_gain_9280_2, 547 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); 548 else 549 INIT_INI_ARRAY(&ah->iniModesTxGain, 550 ar9280Modes_original_tx_gain_9280_2, 551 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 552 } else { 553 INIT_INI_ARRAY(&ah->iniModesTxGain, 554 ar9280Modes_original_tx_gain_9280_2, 555 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 556 } 557} 558 559static int ath9k_hw_post_attach(struct ath_hw *ah) 560{ 561 int ecode; 562 563 if (!ath9k_hw_chip_test(ah)) 564 return -ENODEV; 565 566 ecode = ath9k_hw_rf_claim(ah); 567 if (ecode != 0) 568 return ecode; 569 570 ecode = ath9k_hw_eeprom_attach(ah); 571 if (ecode != 0) 572 return ecode; 573 574 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n", 575 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah)); 576 577 ecode = ath9k_hw_rfattach(ah); 578 if (ecode != 0) 579 return ecode; 580 581 if (!AR_SREV_9100(ah)) { 582 ath9k_hw_ani_setup(ah); 583 ath9k_hw_ani_attach(ah); 584 } 585 586 return 0; 587} 588 589static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 590 int *status) 591{ 592 struct ath_hw *ah; 593 int ecode; 594 u32 i, j; 595 596 ah = ath9k_hw_newstate(devid, sc, status); 597 if (ah == NULL) 598 return NULL; 599 600 ath9k_hw_set_defaults(ah); 601 602 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 603 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n"); 604 ecode = -EIO; 605 goto bad; 606 } 607 608 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 609 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 610 ecode = -EIO; 611 goto bad; 612 } 613 614 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 615 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 616 (AR_SREV_9280(ah) && !ah->is_pciexpress)) { 617 ah->config.serialize_regmode = 618 SER_REG_MODE_ON; 619 } else { 620 ah->config.serialize_regmode = 621 SER_REG_MODE_OFF; 622 } 623 } 624 625 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n", 626 ah->config.serialize_regmode); 627 628 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && 629 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && 630 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) && 631 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { 632 DPRINTF(sc, ATH_DBG_FATAL, 633 "Mac Chip Rev 0x%02x.%x is not supported by " 634 "this driver\n", ah->hw_version.macVersion, 635 ah->hw_version.macRev); 636 ecode = -EOPNOTSUPP; 637 goto bad; 638 } 639 640 if (AR_SREV_9100(ah)) { 641 ah->iq_caldata.calData = &iq_cal_multi_sample; 642 ah->supp_cals = IQ_MISMATCH_CAL; 643 ah->is_pciexpress = false; 644 } 645 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 646 647 if (AR_SREV_9160_10_OR_LATER(ah)) { 648 if (AR_SREV_9280_10_OR_LATER(ah)) { 649 ah->iq_caldata.calData = &iq_cal_single_sample; 650 ah->adcgain_caldata.calData = 651 &adc_gain_cal_single_sample; 652 ah->adcdc_caldata.calData = 653 &adc_dc_cal_single_sample; 654 ah->adcdc_calinitdata.calData = 655 &adc_init_dc_cal; 656 } else { 657 ah->iq_caldata.calData = &iq_cal_multi_sample; 658 ah->adcgain_caldata.calData = 659 &adc_gain_cal_multi_sample; 660 ah->adcdc_caldata.calData = 661 &adc_dc_cal_multi_sample; 662 ah->adcdc_calinitdata.calData = 663 &adc_init_dc_cal; 664 } 665 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 666 } 667 668 ah->ani_function = ATH9K_ANI_ALL; 669 if (AR_SREV_9280_10_OR_LATER(ah)) 670 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 671 672 if (AR_SREV_9285_12_OR_LATER(ah)) { 673 674 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, 675 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 676 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, 677 ARRAY_SIZE(ar9285Common_9285_1_2), 2); 678 679 if (ah->config.pcie_clock_req) { 680 INIT_INI_ARRAY(&ah->iniPcieSerdes, 681 ar9285PciePhy_clkreq_off_L1_9285_1_2, 682 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); 683 } else { 684 INIT_INI_ARRAY(&ah->iniPcieSerdes, 685 ar9285PciePhy_clkreq_always_on_L1_9285_1_2, 686 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 687 2); 688 } 689 } else if (AR_SREV_9285_10_OR_LATER(ah)) { 690 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, 691 ARRAY_SIZE(ar9285Modes_9285), 6); 692 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, 693 ARRAY_SIZE(ar9285Common_9285), 2); 694 695 if (ah->config.pcie_clock_req) { 696 INIT_INI_ARRAY(&ah->iniPcieSerdes, 697 ar9285PciePhy_clkreq_off_L1_9285, 698 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); 699 } else { 700 INIT_INI_ARRAY(&ah->iniPcieSerdes, 701 ar9285PciePhy_clkreq_always_on_L1_9285, 702 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); 703 } 704 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 705 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, 706 ARRAY_SIZE(ar9280Modes_9280_2), 6); 707 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, 708 ARRAY_SIZE(ar9280Common_9280_2), 2); 709 710 if (ah->config.pcie_clock_req) { 711 INIT_INI_ARRAY(&ah->iniPcieSerdes, 712 ar9280PciePhy_clkreq_off_L1_9280, 713 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); 714 } else { 715 INIT_INI_ARRAY(&ah->iniPcieSerdes, 716 ar9280PciePhy_clkreq_always_on_L1_9280, 717 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); 718 } 719 INIT_INI_ARRAY(&ah->iniModesAdditional, 720 ar9280Modes_fast_clock_9280_2, 721 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 722 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 723 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, 724 ARRAY_SIZE(ar9280Modes_9280), 6); 725 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, 726 ARRAY_SIZE(ar9280Common_9280), 2); 727 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 728 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, 729 ARRAY_SIZE(ar5416Modes_9160), 6); 730 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, 731 ARRAY_SIZE(ar5416Common_9160), 2); 732 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, 733 ARRAY_SIZE(ar5416Bank0_9160), 2); 734 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, 735 ARRAY_SIZE(ar5416BB_RfGain_9160), 3); 736 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, 737 ARRAY_SIZE(ar5416Bank1_9160), 2); 738 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, 739 ARRAY_SIZE(ar5416Bank2_9160), 2); 740 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, 741 ARRAY_SIZE(ar5416Bank3_9160), 3); 742 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, 743 ARRAY_SIZE(ar5416Bank6_9160), 3); 744 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, 745 ARRAY_SIZE(ar5416Bank6TPC_9160), 3); 746 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, 747 ARRAY_SIZE(ar5416Bank7_9160), 2); 748 if (AR_SREV_9160_11(ah)) { 749 INIT_INI_ARRAY(&ah->iniAddac, 750 ar5416Addac_91601_1, 751 ARRAY_SIZE(ar5416Addac_91601_1), 2); 752 } else { 753 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, 754 ARRAY_SIZE(ar5416Addac_9160), 2); 755 } 756 } else if (AR_SREV_9100_OR_LATER(ah)) { 757 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, 758 ARRAY_SIZE(ar5416Modes_9100), 6); 759 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, 760 ARRAY_SIZE(ar5416Common_9100), 2); 761 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, 762 ARRAY_SIZE(ar5416Bank0_9100), 2); 763 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, 764 ARRAY_SIZE(ar5416BB_RfGain_9100), 3); 765 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, 766 ARRAY_SIZE(ar5416Bank1_9100), 2); 767 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, 768 ARRAY_SIZE(ar5416Bank2_9100), 2); 769 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, 770 ARRAY_SIZE(ar5416Bank3_9100), 3); 771 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, 772 ARRAY_SIZE(ar5416Bank6_9100), 3); 773 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, 774 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 775 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, 776 ARRAY_SIZE(ar5416Bank7_9100), 2); 777 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, 778 ARRAY_SIZE(ar5416Addac_9100), 2); 779 } else { 780 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, 781 ARRAY_SIZE(ar5416Modes), 6); 782 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, 783 ARRAY_SIZE(ar5416Common), 2); 784 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, 785 ARRAY_SIZE(ar5416Bank0), 2); 786 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, 787 ARRAY_SIZE(ar5416BB_RfGain), 3); 788 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, 789 ARRAY_SIZE(ar5416Bank1), 2); 790 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, 791 ARRAY_SIZE(ar5416Bank2), 2); 792 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, 793 ARRAY_SIZE(ar5416Bank3), 3); 794 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, 795 ARRAY_SIZE(ar5416Bank6), 3); 796 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, 797 ARRAY_SIZE(ar5416Bank6TPC), 3); 798 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, 799 ARRAY_SIZE(ar5416Bank7), 2); 800 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, 801 ARRAY_SIZE(ar5416Addac), 2); 802 } 803 804 if (ah->is_pciexpress) 805 ath9k_hw_configpcipowersave(ah, 0); 806 else 807 ath9k_hw_disablepcie(ah); 808 809 ecode = ath9k_hw_post_attach(ah); 810 if (ecode != 0) 811 goto bad; 812 813 if (AR_SREV_9285_12_OR_LATER(ah)) { 814 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 815 816 /* txgain table */ 817 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { 818 INIT_INI_ARRAY(&ah->iniModesTxGain, 819 ar9285Modes_high_power_tx_gain_9285_1_2, 820 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6); 821 } else { 822 INIT_INI_ARRAY(&ah->iniModesTxGain, 823 ar9285Modes_original_tx_gain_9285_1_2, 824 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6); 825 } 826 827 } 828 829 /* rxgain table */ 830 if (AR_SREV_9280_20(ah)) 831 ath9k_hw_init_rxgain_ini(ah); 832 833 /* txgain table */ 834 if (AR_SREV_9280_20(ah)) 835 ath9k_hw_init_txgain_ini(ah); 836 837 ath9k_hw_fill_cap_info(ah); 838 839 if ((ah->hw_version.devid == AR9280_DEVID_PCI) && 840 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) { 841 842 /* EEPROM Fixup */ 843 for (i = 0; i < ah->iniModes.ia_rows; i++) { 844 u32 reg = INI_RA(&ah->iniModes, i, 0); 845 846 for (j = 1; j < ah->iniModes.ia_columns; j++) { 847 u32 val = INI_RA(&ah->iniModes, i, j); 848 849 INI_RA(&ah->iniModes, i, j) = 850 ath9k_hw_ini_fixup(ah, 851 &ah->eeprom.def, 852 reg, val); 853 } 854 } 855 } 856 857 ecode = ath9k_hw_init_macaddr(ah); 858 if (ecode != 0) { 859 DPRINTF(sc, ATH_DBG_FATAL, 860 "Failed to initialize MAC address\n"); 861 goto bad; 862 } 863 864 if (AR_SREV_9285(ah)) 865 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 866 else 867 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 868 869 ath9k_init_nfcal_hist_buffer(ah); 870 871 return ah; 872bad: 873 if (ah) 874 ath9k_hw_detach(ah); 875 if (status) 876 *status = ecode; 877 878 return NULL; 879} 880 881static void ath9k_hw_init_bb(struct ath_hw *ah, 882 struct ath9k_channel *chan) 883{ 884 u32 synthDelay; 885 886 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 887 if (IS_CHAN_B(chan)) 888 synthDelay = (4 * synthDelay) / 22; 889 else 890 synthDelay /= 10; 891 892 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 893 894 udelay(synthDelay + BASE_ACTIVATE_DELAY); 895} 896 897static void ath9k_hw_init_qos(struct ath_hw *ah) 898{ 899 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 900 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 901 902 REG_WRITE(ah, AR_QOS_NO_ACK, 903 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 904 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 905 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 906 907 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 908 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 909 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 910 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 911 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 912} 913 914static void ath9k_hw_init_pll(struct ath_hw *ah, 915 struct ath9k_channel *chan) 916{ 917 u32 pll; 918 919 if (AR_SREV_9100(ah)) { 920 if (chan && IS_CHAN_5GHZ(chan)) 921 pll = 0x1450; 922 else 923 pll = 0x1458; 924 } else { 925 if (AR_SREV_9280_10_OR_LATER(ah)) { 926 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 927 928 if (chan && IS_CHAN_HALF_RATE(chan)) 929 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 930 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 931 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 932 933 if (chan && IS_CHAN_5GHZ(chan)) { 934 pll |= SM(0x28, AR_RTC_9160_PLL_DIV); 935 936 937 if (AR_SREV_9280_20(ah)) { 938 if (((chan->channel % 20) == 0) 939 || ((chan->channel % 10) == 0)) 940 pll = 0x2850; 941 else 942 pll = 0x142c; 943 } 944 } else { 945 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); 946 } 947 948 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 949 950 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 951 952 if (chan && IS_CHAN_HALF_RATE(chan)) 953 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 954 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 955 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 956 957 if (chan && IS_CHAN_5GHZ(chan)) 958 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 959 else 960 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 961 } else { 962 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 963 964 if (chan && IS_CHAN_HALF_RATE(chan)) 965 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 966 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 967 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 968 969 if (chan && IS_CHAN_5GHZ(chan)) 970 pll |= SM(0xa, AR_RTC_PLL_DIV); 971 else 972 pll |= SM(0xb, AR_RTC_PLL_DIV); 973 } 974 } 975 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 976 977 udelay(RTC_PLL_SETTLE_DELAY); 978 979 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 980} 981 982static void ath9k_hw_init_chain_masks(struct ath_hw *ah) 983{ 984 int rx_chainmask, tx_chainmask; 985 986 rx_chainmask = ah->rxchainmask; 987 tx_chainmask = ah->txchainmask; 988 989 switch (rx_chainmask) { 990 case 0x5: 991 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 992 AR_PHY_SWAP_ALT_CHAIN); 993 case 0x3: 994 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) { 995 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 996 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 997 break; 998 } 999 case 0x1: 1000 case 0x2: 1001 case 0x7: 1002 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1003 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1004 break; 1005 default: 1006 break; 1007 } 1008 1009 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 1010 if (tx_chainmask == 0x5) { 1011 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 1012 AR_PHY_SWAP_ALT_CHAIN); 1013 } 1014 if (AR_SREV_9100(ah)) 1015 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 1016 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1017} 1018 1019static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 1020 enum nl80211_iftype opmode) 1021{ 1022 ah->mask_reg = AR_IMR_TXERR | 1023 AR_IMR_TXURN | 1024 AR_IMR_RXERR | 1025 AR_IMR_RXORN | 1026 AR_IMR_BCNMISC; 1027 1028 if (ah->config.intr_mitigation) 1029 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 1030 else 1031 ah->mask_reg |= AR_IMR_RXOK; 1032 1033 ah->mask_reg |= AR_IMR_TXOK; 1034 1035 if (opmode == NL80211_IFTYPE_AP) 1036 ah->mask_reg |= AR_IMR_MIB; 1037 1038 REG_WRITE(ah, AR_IMR, ah->mask_reg); 1039 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); 1040 1041 if (!AR_SREV_9100(ah)) { 1042 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 1043 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 1044 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 1045 } 1046} 1047 1048static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1049{ 1050 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1051 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); 1052 ah->acktimeout = (u32) -1; 1053 return false; 1054 } else { 1055 REG_RMW_FIELD(ah, AR_TIME_OUT, 1056 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); 1057 ah->acktimeout = us; 1058 return true; 1059 } 1060} 1061 1062static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1063{ 1064 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1065 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); 1066 ah->ctstimeout = (u32) -1; 1067 return false; 1068 } else { 1069 REG_RMW_FIELD(ah, AR_TIME_OUT, 1070 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); 1071 ah->ctstimeout = us; 1072 return true; 1073 } 1074} 1075 1076static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1077{ 1078 if (tu > 0xFFFF) { 1079 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 1080 "bad global tx timeout %u\n", tu); 1081 ah->globaltxtimeout = (u32) -1; 1082 return false; 1083 } else { 1084 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1085 ah->globaltxtimeout = tu; 1086 return true; 1087 } 1088} 1089 1090static void ath9k_hw_init_user_settings(struct ath_hw *ah) 1091{ 1092 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 1093 ah->misc_mode); 1094 1095 if (ah->misc_mode != 0) 1096 REG_WRITE(ah, AR_PCU_MISC, 1097 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 1098 if (ah->slottime != (u32) -1) 1099 ath9k_hw_setslottime(ah, ah->slottime); 1100 if (ah->acktimeout != (u32) -1) 1101 ath9k_hw_set_ack_timeout(ah, ah->acktimeout); 1102 if (ah->ctstimeout != (u32) -1) 1103 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout); 1104 if (ah->globaltxtimeout != (u32) -1) 1105 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1106} 1107 1108const char *ath9k_hw_probe(u16 vendorid, u16 devid) 1109{ 1110 return vendorid == ATHEROS_VENDOR_ID ? 1111 ath9k_hw_devname(devid) : NULL; 1112} 1113 1114void ath9k_hw_detach(struct ath_hw *ah) 1115{ 1116 if (!AR_SREV_9100(ah)) 1117 ath9k_hw_ani_detach(ah); 1118 1119 ath9k_hw_rfdetach(ah); 1120 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1121 kfree(ah); 1122} 1123 1124struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error) 1125{ 1126 struct ath_hw *ah = NULL; 1127 1128 switch (devid) { 1129 case AR5416_DEVID_PCI: 1130 case AR5416_DEVID_PCIE: 1131 case AR5416_AR9100_DEVID: 1132 case AR9160_DEVID_PCI: 1133 case AR9280_DEVID_PCI: 1134 case AR9280_DEVID_PCIE: 1135 case AR9285_DEVID_PCIE: 1136 ah = ath9k_hw_do_attach(devid, sc, error); 1137 break; 1138 default: 1139 *error = -ENXIO; 1140 break; 1141 } 1142 1143 return ah; 1144} 1145 1146/*******/ 1147/* INI */ 1148/*******/ 1149 1150static void ath9k_hw_override_ini(struct ath_hw *ah, 1151 struct ath9k_channel *chan) 1152{ 1153 /* 1154 * Set the RX_ABORT and RX_DIS and clear if off only after 1155 * RXE is set for MAC. This prevents frames with corrupted 1156 * descriptor status. 1157 */ 1158 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 1159 1160 1161 if (!AR_SREV_5416_20_OR_LATER(ah) || 1162 AR_SREV_9280_10_OR_LATER(ah)) 1163 return; 1164 1165 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 1166} 1167 1168static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah, 1169 struct ar5416_eeprom_def *pEepData, 1170 u32 reg, u32 value) 1171{ 1172 struct base_eep_header *pBase = &(pEepData->baseEepHeader); 1173 1174 switch (ah->hw_version.devid) { 1175 case AR9280_DEVID_PCI: 1176 if (reg == 0x7894) { 1177 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1178 "ini VAL: %x EEPROM: %x\n", value, 1179 (pBase->version & 0xff)); 1180 1181 if ((pBase->version & 0xff) > 0x0a) { 1182 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1183 "PWDCLKIND: %d\n", 1184 pBase->pwdclkind); 1185 value &= ~AR_AN_TOP2_PWDCLKIND; 1186 value |= AR_AN_TOP2_PWDCLKIND & 1187 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); 1188 } else { 1189 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1190 "PWDCLKIND Earlier Rev\n"); 1191 } 1192 1193 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1194 "final ini VAL: %x\n", value); 1195 } 1196 break; 1197 } 1198 1199 return value; 1200} 1201 1202static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 1203 struct ar5416_eeprom_def *pEepData, 1204 u32 reg, u32 value) 1205{ 1206 if (ah->eep_map == EEP_MAP_4KBITS) 1207 return value; 1208 else 1209 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); 1210} 1211 1212static void ath9k_olc_init(struct ath_hw *ah) 1213{ 1214 u32 i; 1215 1216 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) 1217 ah->originalGain[i] = 1218 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), 1219 AR_PHY_TX_GAIN); 1220 ah->PDADCdelta = 0; 1221} 1222 1223static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, 1224 struct ath9k_channel *chan) 1225{ 1226 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1227 1228 if (IS_CHAN_B(chan)) 1229 ctl |= CTL_11B; 1230 else if (IS_CHAN_G(chan)) 1231 ctl |= CTL_11G; 1232 else 1233 ctl |= CTL_11A; 1234 1235 return ctl; 1236} 1237 1238static int ath9k_hw_process_ini(struct ath_hw *ah, 1239 struct ath9k_channel *chan, 1240 enum ath9k_ht_macmode macmode) 1241{ 1242 int i, regWrites = 0; 1243 struct ieee80211_channel *channel = chan->chan; 1244 u32 modesIndex, freqIndex; 1245 int status; 1246 1247 switch (chan->chanmode) { 1248 case CHANNEL_A: 1249 case CHANNEL_A_HT20: 1250 modesIndex = 1; 1251 freqIndex = 1; 1252 break; 1253 case CHANNEL_A_HT40PLUS: 1254 case CHANNEL_A_HT40MINUS: 1255 modesIndex = 2; 1256 freqIndex = 1; 1257 break; 1258 case CHANNEL_G: 1259 case CHANNEL_G_HT20: 1260 case CHANNEL_B: 1261 modesIndex = 4; 1262 freqIndex = 2; 1263 break; 1264 case CHANNEL_G_HT40PLUS: 1265 case CHANNEL_G_HT40MINUS: 1266 modesIndex = 3; 1267 freqIndex = 2; 1268 break; 1269 1270 default: 1271 return -EINVAL; 1272 } 1273 1274 REG_WRITE(ah, AR_PHY(0), 0x00000007); 1275 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 1276 ah->eep_ops->set_addac(ah, chan); 1277 1278 if (AR_SREV_5416_22_OR_LATER(ah)) { 1279 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 1280 } else { 1281 struct ar5416IniArray temp; 1282 u32 addacSize = 1283 sizeof(u32) * ah->iniAddac.ia_rows * 1284 ah->iniAddac.ia_columns; 1285 1286 memcpy(ah->addac5416_21, 1287 ah->iniAddac.ia_array, addacSize); 1288 1289 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; 1290 1291 temp.ia_array = ah->addac5416_21; 1292 temp.ia_columns = ah->iniAddac.ia_columns; 1293 temp.ia_rows = ah->iniAddac.ia_rows; 1294 REG_WRITE_ARRAY(&temp, 1, regWrites); 1295 } 1296 1297 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 1298 1299 for (i = 0; i < ah->iniModes.ia_rows; i++) { 1300 u32 reg = INI_RA(&ah->iniModes, i, 0); 1301 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 1302 1303 REG_WRITE(ah, reg, val); 1304 1305 if (reg >= 0x7800 && reg < 0x78a0 1306 && ah->config.analog_shiftreg) { 1307 udelay(100); 1308 } 1309 1310 DO_DELAY(regWrites); 1311 } 1312 1313 if (AR_SREV_9280(ah)) 1314 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 1315 1316 if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) && 1317 AR_SREV_9285_12_OR_LATER(ah))) 1318 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 1319 1320 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 1321 u32 reg = INI_RA(&ah->iniCommon, i, 0); 1322 u32 val = INI_RA(&ah->iniCommon, i, 1); 1323 1324 REG_WRITE(ah, reg, val); 1325 1326 if (reg >= 0x7800 && reg < 0x78a0 1327 && ah->config.analog_shiftreg) { 1328 udelay(100); 1329 } 1330 1331 DO_DELAY(regWrites); 1332 } 1333 1334 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1335 1336 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1337 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, 1338 regWrites); 1339 } 1340 1341 ath9k_hw_override_ini(ah, chan); 1342 ath9k_hw_set_regs(ah, chan, macmode); 1343 ath9k_hw_init_chain_masks(ah); 1344 1345 if (OLC_FOR_AR9280_20_LATER) 1346 ath9k_olc_init(ah); 1347 1348 status = ah->eep_ops->set_txpower(ah, chan, 1349 ath9k_regd_get_ctl(&ah->regulatory, chan), 1350 channel->max_antenna_gain * 2, 1351 channel->max_power * 2, 1352 min((u32) MAX_RATE_POWER, 1353 (u32) ah->regulatory.power_limit)); 1354 if (status != 0) { 1355 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1356 "Error initializing transmit power\n"); 1357 return -EIO; 1358 } 1359 1360 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1361 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1362 "ar5416SetRfRegs failed\n"); 1363 return -EIO; 1364 } 1365 1366 return 0; 1367} 1368 1369/****************************************/ 1370/* Reset and Channel Switching Routines */ 1371/****************************************/ 1372 1373static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 1374{ 1375 u32 rfMode = 0; 1376 1377 if (chan == NULL) 1378 return; 1379 1380 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 1381 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1382 1383 if (!AR_SREV_9280_10_OR_LATER(ah)) 1384 rfMode |= (IS_CHAN_5GHZ(chan)) ? 1385 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 1386 1387 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) 1388 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 1389 1390 REG_WRITE(ah, AR_PHY_MODE, rfMode); 1391} 1392 1393static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah) 1394{ 1395 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1396} 1397 1398static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1399{ 1400 u32 regval; 1401 1402 regval = REG_READ(ah, AR_AHB_MODE); 1403 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 1404 1405 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 1406 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 1407 1408 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1409 1410 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 1411 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 1412 1413 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1414 1415 if (AR_SREV_9285(ah)) { 1416 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1417 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1418 } else { 1419 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1420 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1421 } 1422} 1423 1424static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1425{ 1426 u32 val; 1427 1428 val = REG_READ(ah, AR_STA_ID1); 1429 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 1430 switch (opmode) { 1431 case NL80211_IFTYPE_AP: 1432 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 1433 | AR_STA_ID1_KSRCH_MODE); 1434 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1435 break; 1436 case NL80211_IFTYPE_ADHOC: 1437 case NL80211_IFTYPE_MESH_POINT: 1438 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 1439 | AR_STA_ID1_KSRCH_MODE); 1440 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1441 break; 1442 case NL80211_IFTYPE_STATION: 1443 case NL80211_IFTYPE_MONITOR: 1444 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 1445 break; 1446 } 1447} 1448 1449static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, 1450 u32 coef_scaled, 1451 u32 *coef_mantissa, 1452 u32 *coef_exponent) 1453{ 1454 u32 coef_exp, coef_man; 1455 1456 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1457 if ((coef_scaled >> coef_exp) & 0x1) 1458 break; 1459 1460 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1461 1462 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1463 1464 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1465 *coef_exponent = coef_exp - 16; 1466} 1467 1468static void ath9k_hw_set_delta_slope(struct ath_hw *ah, 1469 struct ath9k_channel *chan) 1470{ 1471 u32 coef_scaled, ds_coef_exp, ds_coef_man; 1472 u32 clockMhzScaled = 0x64000000; 1473 struct chan_centers centers; 1474 1475 if (IS_CHAN_HALF_RATE(chan)) 1476 clockMhzScaled = clockMhzScaled >> 1; 1477 else if (IS_CHAN_QUARTER_RATE(chan)) 1478 clockMhzScaled = clockMhzScaled >> 2; 1479 1480 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 1481 coef_scaled = clockMhzScaled / centers.synth_center; 1482 1483 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1484 &ds_coef_exp); 1485 1486 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1487 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 1488 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1489 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 1490 1491 coef_scaled = (9 * coef_scaled) / 10; 1492 1493 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1494 &ds_coef_exp); 1495 1496 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 1497 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 1498 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 1499 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 1500} 1501 1502static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1503{ 1504 u32 rst_flags; 1505 u32 tmpReg; 1506 1507 if (AR_SREV_9100(ah)) { 1508 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 1509 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 1510 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 1511 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 1512 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1513 } 1514 1515 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1516 AR_RTC_FORCE_WAKE_ON_INT); 1517 1518 if (AR_SREV_9100(ah)) { 1519 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1520 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1521 } else { 1522 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1523 if (tmpReg & 1524 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1525 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1526 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1527 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1528 } else { 1529 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1530 } 1531 1532 rst_flags = AR_RTC_RC_MAC_WARM; 1533 if (type == ATH9K_RESET_COLD) 1534 rst_flags |= AR_RTC_RC_MAC_COLD; 1535 } 1536 1537 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1538 udelay(50); 1539 1540 REG_WRITE(ah, AR_RTC_RC, 0); 1541 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1542 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 1543 "RTC stuck in MAC reset\n"); 1544 return false; 1545 } 1546 1547 if (!AR_SREV_9100(ah)) 1548 REG_WRITE(ah, AR_RC, 0); 1549 1550 ath9k_hw_init_pll(ah, NULL); 1551 1552 if (AR_SREV_9100(ah)) 1553 udelay(50); 1554 1555 return true; 1556} 1557 1558static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1559{ 1560 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1561 AR_RTC_FORCE_WAKE_ON_INT); 1562 1563 REG_WRITE(ah, AR_RTC_RESET, 0); 1564 udelay(2); 1565 REG_WRITE(ah, AR_RTC_RESET, 1); 1566 1567 if (!ath9k_hw_wait(ah, 1568 AR_RTC_STATUS, 1569 AR_RTC_STATUS_M, 1570 AR_RTC_STATUS_ON, 1571 AH_WAIT_TIMEOUT)) { 1572 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n"); 1573 return false; 1574 } 1575 1576 ath9k_hw_read_revisions(ah); 1577 1578 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1579} 1580 1581static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1582{ 1583 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1584 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1585 1586 switch (type) { 1587 case ATH9K_RESET_POWER_ON: 1588 return ath9k_hw_set_reset_power_on(ah); 1589 break; 1590 case ATH9K_RESET_WARM: 1591 case ATH9K_RESET_COLD: 1592 return ath9k_hw_set_reset(ah, type); 1593 break; 1594 default: 1595 return false; 1596 } 1597} 1598 1599static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, 1600 enum ath9k_ht_macmode macmode) 1601{ 1602 u32 phymode; 1603 u32 enableDacFifo = 0; 1604 1605 if (AR_SREV_9285_10_OR_LATER(ah)) 1606 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 1607 AR_PHY_FC_ENABLE_DAC_FIFO); 1608 1609 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 1610 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 1611 1612 if (IS_CHAN_HT40(chan)) { 1613 phymode |= AR_PHY_FC_DYN2040_EN; 1614 1615 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 1616 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1617 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1618 1619 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25) 1620 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 1621 } 1622 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1623 1624 ath9k_hw_set11nmac2040(ah, macmode); 1625 1626 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 1627 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 1628} 1629 1630static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1631 struct ath9k_channel *chan) 1632{ 1633 if (OLC_FOR_AR9280_20_LATER) { 1634 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1635 return false; 1636 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1637 return false; 1638 1639 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1640 return false; 1641 1642 ah->chip_fullsleep = false; 1643 ath9k_hw_init_pll(ah, chan); 1644 ath9k_hw_set_rfmode(ah, chan); 1645 1646 return true; 1647} 1648 1649static bool ath9k_hw_channel_change(struct ath_hw *ah, 1650 struct ath9k_channel *chan, 1651 enum ath9k_ht_macmode macmode) 1652{ 1653 struct ieee80211_channel *channel = chan->chan; 1654 u32 synthDelay, qnum; 1655 1656 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1657 if (ath9k_hw_numtxpending(ah, qnum)) { 1658 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 1659 "Transmit frames pending on queue %d\n", qnum); 1660 return false; 1661 } 1662 } 1663 1664 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1665 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1666 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { 1667 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1668 "Could not kill baseband RX\n"); 1669 return false; 1670 } 1671 1672 ath9k_hw_set_regs(ah, chan, macmode); 1673 1674 if (AR_SREV_9280_10_OR_LATER(ah)) { 1675 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { 1676 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1677 "Failed to set channel\n"); 1678 return false; 1679 } 1680 } else { 1681 if (!(ath9k_hw_set_channel(ah, chan))) { 1682 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1683 "Failed to set channel\n"); 1684 return false; 1685 } 1686 } 1687 1688 if (ah->eep_ops->set_txpower(ah, chan, 1689 ath9k_regd_get_ctl(&ah->regulatory, chan), 1690 channel->max_antenna_gain * 2, 1691 channel->max_power * 2, 1692 min((u32) MAX_RATE_POWER, 1693 (u32) ah->regulatory.power_limit)) != 0) { 1694 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1695 "Error initializing transmit power\n"); 1696 return false; 1697 } 1698 1699 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1700 if (IS_CHAN_B(chan)) 1701 synthDelay = (4 * synthDelay) / 22; 1702 else 1703 synthDelay /= 10; 1704 1705 udelay(synthDelay + BASE_ACTIVATE_DELAY); 1706 1707 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 1708 1709 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1710 ath9k_hw_set_delta_slope(ah, chan); 1711 1712 if (AR_SREV_9280_10_OR_LATER(ah)) 1713 ath9k_hw_9280_spur_mitigate(ah, chan); 1714 else 1715 ath9k_hw_spur_mitigate(ah, chan); 1716 1717 if (!chan->oneTimeCalsDone) 1718 chan->oneTimeCalsDone = true; 1719 1720 return true; 1721} 1722 1723static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) 1724{ 1725 int bb_spur = AR_NO_SPUR; 1726 int freq; 1727 int bin, cur_bin; 1728 int bb_spur_off, spur_subchannel_sd; 1729 int spur_freq_sd; 1730 int spur_delta_phase; 1731 int denominator; 1732 int upper, lower, cur_vit_mask; 1733 int tmp, newVal; 1734 int i; 1735 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 1736 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 1737 }; 1738 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 1739 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 1740 }; 1741 int inc[4] = { 0, 100, 0, 0 }; 1742 struct chan_centers centers; 1743 1744 int8_t mask_m[123]; 1745 int8_t mask_p[123]; 1746 int8_t mask_amt; 1747 int tmp_mask; 1748 int cur_bb_spur; 1749 bool is2GHz = IS_CHAN_2GHZ(chan); 1750 1751 memset(&mask_m, 0, sizeof(int8_t) * 123); 1752 memset(&mask_p, 0, sizeof(int8_t) * 123); 1753 1754 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 1755 freq = centers.synth_center; 1756 1757 ah->config.spurmode = SPUR_ENABLE_EEPROM; 1758 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 1759 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 1760 1761 if (is2GHz) 1762 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 1763 else 1764 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 1765 1766 if (AR_NO_SPUR == cur_bb_spur) 1767 break; 1768 cur_bb_spur = cur_bb_spur - freq; 1769 1770 if (IS_CHAN_HT40(chan)) { 1771 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 1772 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 1773 bb_spur = cur_bb_spur; 1774 break; 1775 } 1776 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 1777 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 1778 bb_spur = cur_bb_spur; 1779 break; 1780 } 1781 } 1782 1783 if (AR_NO_SPUR == bb_spur) { 1784 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, 1785 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 1786 return; 1787 } else { 1788 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, 1789 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 1790 } 1791 1792 bin = bb_spur * 320; 1793 1794 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 1795 1796 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 1797 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 1798 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 1799 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 1800 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); 1801 1802 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 1803 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 1804 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 1805 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 1806 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 1807 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 1808 1809 if (IS_CHAN_HT40(chan)) { 1810 if (bb_spur < 0) { 1811 spur_subchannel_sd = 1; 1812 bb_spur_off = bb_spur + 10; 1813 } else { 1814 spur_subchannel_sd = 0; 1815 bb_spur_off = bb_spur - 10; 1816 } 1817 } else { 1818 spur_subchannel_sd = 0; 1819 bb_spur_off = bb_spur; 1820 } 1821 1822 if (IS_CHAN_HT40(chan)) 1823 spur_delta_phase = 1824 ((bb_spur * 262144) / 1825 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 1826 else 1827 spur_delta_phase = 1828 ((bb_spur * 524288) / 1829 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 1830 1831 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40; 1832 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 1833 1834 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 1835 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 1836 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 1837 REG_WRITE(ah, AR_PHY_TIMING11, newVal); 1838 1839 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 1840 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 1841 1842 cur_bin = -6000; 1843 upper = bin + 100; 1844 lower = bin - 100; 1845 1846 for (i = 0; i < 4; i++) { 1847 int pilot_mask = 0; 1848 int chan_mask = 0; 1849 int bp = 0; 1850 for (bp = 0; bp < 30; bp++) { 1851 if ((cur_bin > lower) && (cur_bin < upper)) { 1852 pilot_mask = pilot_mask | 0x1 << bp; 1853 chan_mask = chan_mask | 0x1 << bp; 1854 } 1855 cur_bin += 100; 1856 } 1857 cur_bin += inc[i]; 1858 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 1859 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 1860 } 1861 1862 cur_vit_mask = 6100; 1863 upper = bin + 120; 1864 lower = bin - 120; 1865 1866 for (i = 0; i < 123; i++) { 1867 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 1868 1869 /* workaround for gcc bug #37014 */ 1870 volatile int tmp_v = abs(cur_vit_mask - bin); 1871 1872 if (tmp_v < 75) 1873 mask_amt = 1; 1874 else 1875 mask_amt = 0; 1876 if (cur_vit_mask < 0) 1877 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 1878 else 1879 mask_p[cur_vit_mask / 100] = mask_amt; 1880 } 1881 cur_vit_mask -= 100; 1882 } 1883 1884 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 1885 | (mask_m[48] << 26) | (mask_m[49] << 24) 1886 | (mask_m[50] << 22) | (mask_m[51] << 20) 1887 | (mask_m[52] << 18) | (mask_m[53] << 16) 1888 | (mask_m[54] << 14) | (mask_m[55] << 12) 1889 | (mask_m[56] << 10) | (mask_m[57] << 8) 1890 | (mask_m[58] << 6) | (mask_m[59] << 4) 1891 | (mask_m[60] << 2) | (mask_m[61] << 0); 1892 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 1893 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 1894 1895 tmp_mask = (mask_m[31] << 28) 1896 | (mask_m[32] << 26) | (mask_m[33] << 24) 1897 | (mask_m[34] << 22) | (mask_m[35] << 20) 1898 | (mask_m[36] << 18) | (mask_m[37] << 16) 1899 | (mask_m[48] << 14) | (mask_m[39] << 12) 1900 | (mask_m[40] << 10) | (mask_m[41] << 8) 1901 | (mask_m[42] << 6) | (mask_m[43] << 4) 1902 | (mask_m[44] << 2) | (mask_m[45] << 0); 1903 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 1904 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 1905 1906 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 1907 | (mask_m[18] << 26) | (mask_m[18] << 24) 1908 | (mask_m[20] << 22) | (mask_m[20] << 20) 1909 | (mask_m[22] << 18) | (mask_m[22] << 16) 1910 | (mask_m[24] << 14) | (mask_m[24] << 12) 1911 | (mask_m[25] << 10) | (mask_m[26] << 8) 1912 | (mask_m[27] << 6) | (mask_m[28] << 4) 1913 | (mask_m[29] << 2) | (mask_m[30] << 0); 1914 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 1915 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 1916 1917 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 1918 | (mask_m[2] << 26) | (mask_m[3] << 24) 1919 | (mask_m[4] << 22) | (mask_m[5] << 20) 1920 | (mask_m[6] << 18) | (mask_m[7] << 16) 1921 | (mask_m[8] << 14) | (mask_m[9] << 12) 1922 | (mask_m[10] << 10) | (mask_m[11] << 8) 1923 | (mask_m[12] << 6) | (mask_m[13] << 4) 1924 | (mask_m[14] << 2) | (mask_m[15] << 0); 1925 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 1926 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 1927 1928 tmp_mask = (mask_p[15] << 28) 1929 | (mask_p[14] << 26) | (mask_p[13] << 24) 1930 | (mask_p[12] << 22) | (mask_p[11] << 20) 1931 | (mask_p[10] << 18) | (mask_p[9] << 16) 1932 | (mask_p[8] << 14) | (mask_p[7] << 12) 1933 | (mask_p[6] << 10) | (mask_p[5] << 8) 1934 | (mask_p[4] << 6) | (mask_p[3] << 4) 1935 | (mask_p[2] << 2) | (mask_p[1] << 0); 1936 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 1937 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 1938 1939 tmp_mask = (mask_p[30] << 28) 1940 | (mask_p[29] << 26) | (mask_p[28] << 24) 1941 | (mask_p[27] << 22) | (mask_p[26] << 20) 1942 | (mask_p[25] << 18) | (mask_p[24] << 16) 1943 | (mask_p[23] << 14) | (mask_p[22] << 12) 1944 | (mask_p[21] << 10) | (mask_p[20] << 8) 1945 | (mask_p[19] << 6) | (mask_p[18] << 4) 1946 | (mask_p[17] << 2) | (mask_p[16] << 0); 1947 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 1948 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 1949 1950 tmp_mask = (mask_p[45] << 28) 1951 | (mask_p[44] << 26) | (mask_p[43] << 24) 1952 | (mask_p[42] << 22) | (mask_p[41] << 20) 1953 | (mask_p[40] << 18) | (mask_p[39] << 16) 1954 | (mask_p[38] << 14) | (mask_p[37] << 12) 1955 | (mask_p[36] << 10) | (mask_p[35] << 8) 1956 | (mask_p[34] << 6) | (mask_p[33] << 4) 1957 | (mask_p[32] << 2) | (mask_p[31] << 0); 1958 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 1959 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 1960 1961 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 1962 | (mask_p[59] << 26) | (mask_p[58] << 24) 1963 | (mask_p[57] << 22) | (mask_p[56] << 20) 1964 | (mask_p[55] << 18) | (mask_p[54] << 16) 1965 | (mask_p[53] << 14) | (mask_p[52] << 12) 1966 | (mask_p[51] << 10) | (mask_p[50] << 8) 1967 | (mask_p[49] << 6) | (mask_p[48] << 4) 1968 | (mask_p[47] << 2) | (mask_p[46] << 0); 1969 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 1970 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 1971} 1972 1973static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) 1974{ 1975 int bb_spur = AR_NO_SPUR; 1976 int bin, cur_bin; 1977 int spur_freq_sd; 1978 int spur_delta_phase; 1979 int denominator; 1980 int upper, lower, cur_vit_mask; 1981 int tmp, new; 1982 int i; 1983 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 1984 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 1985 }; 1986 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 1987 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 1988 }; 1989 int inc[4] = { 0, 100, 0, 0 }; 1990 1991 int8_t mask_m[123]; 1992 int8_t mask_p[123]; 1993 int8_t mask_amt; 1994 int tmp_mask; 1995 int cur_bb_spur; 1996 bool is2GHz = IS_CHAN_2GHZ(chan); 1997 1998 memset(&mask_m, 0, sizeof(int8_t) * 123); 1999 memset(&mask_p, 0, sizeof(int8_t) * 123); 2000 2001 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 2002 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 2003 if (AR_NO_SPUR == cur_bb_spur) 2004 break; 2005 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 2006 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 2007 bb_spur = cur_bb_spur; 2008 break; 2009 } 2010 } 2011 2012 if (AR_NO_SPUR == bb_spur) 2013 return; 2014 2015 bin = bb_spur * 32; 2016 2017 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 2018 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 2019 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 2020 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 2021 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 2022 2023 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 2024 2025 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 2026 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 2027 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 2028 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 2029 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 2030 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 2031 2032 spur_delta_phase = ((bb_spur * 524288) / 100) & 2033 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 2034 2035 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 2036 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 2037 2038 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 2039 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 2040 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 2041 REG_WRITE(ah, AR_PHY_TIMING11, new); 2042 2043 cur_bin = -6000; 2044 upper = bin + 100; 2045 lower = bin - 100; 2046 2047 for (i = 0; i < 4; i++) { 2048 int pilot_mask = 0; 2049 int chan_mask = 0; 2050 int bp = 0; 2051 for (bp = 0; bp < 30; bp++) { 2052 if ((cur_bin > lower) && (cur_bin < upper)) { 2053 pilot_mask = pilot_mask | 0x1 << bp; 2054 chan_mask = chan_mask | 0x1 << bp; 2055 } 2056 cur_bin += 100; 2057 } 2058 cur_bin += inc[i]; 2059 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 2060 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 2061 } 2062 2063 cur_vit_mask = 6100; 2064 upper = bin + 120; 2065 lower = bin - 120; 2066 2067 for (i = 0; i < 123; i++) { 2068 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 2069 2070 /* workaround for gcc bug #37014 */ 2071 volatile int tmp_v = abs(cur_vit_mask - bin); 2072 2073 if (tmp_v < 75) 2074 mask_amt = 1; 2075 else 2076 mask_amt = 0; 2077 if (cur_vit_mask < 0) 2078 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 2079 else 2080 mask_p[cur_vit_mask / 100] = mask_amt; 2081 } 2082 cur_vit_mask -= 100; 2083 } 2084 2085 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 2086 | (mask_m[48] << 26) | (mask_m[49] << 24) 2087 | (mask_m[50] << 22) | (mask_m[51] << 20) 2088 | (mask_m[52] << 18) | (mask_m[53] << 16) 2089 | (mask_m[54] << 14) | (mask_m[55] << 12) 2090 | (mask_m[56] << 10) | (mask_m[57] << 8) 2091 | (mask_m[58] << 6) | (mask_m[59] << 4) 2092 | (mask_m[60] << 2) | (mask_m[61] << 0); 2093 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 2094 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 2095 2096 tmp_mask = (mask_m[31] << 28) 2097 | (mask_m[32] << 26) | (mask_m[33] << 24) 2098 | (mask_m[34] << 22) | (mask_m[35] << 20) 2099 | (mask_m[36] << 18) | (mask_m[37] << 16) 2100 | (mask_m[48] << 14) | (mask_m[39] << 12) 2101 | (mask_m[40] << 10) | (mask_m[41] << 8) 2102 | (mask_m[42] << 6) | (mask_m[43] << 4) 2103 | (mask_m[44] << 2) | (mask_m[45] << 0); 2104 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 2105 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 2106 2107 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 2108 | (mask_m[18] << 26) | (mask_m[18] << 24) 2109 | (mask_m[20] << 22) | (mask_m[20] << 20) 2110 | (mask_m[22] << 18) | (mask_m[22] << 16) 2111 | (mask_m[24] << 14) | (mask_m[24] << 12) 2112 | (mask_m[25] << 10) | (mask_m[26] << 8) 2113 | (mask_m[27] << 6) | (mask_m[28] << 4) 2114 | (mask_m[29] << 2) | (mask_m[30] << 0); 2115 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 2116 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 2117 2118 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 2119 | (mask_m[2] << 26) | (mask_m[3] << 24) 2120 | (mask_m[4] << 22) | (mask_m[5] << 20) 2121 | (mask_m[6] << 18) | (mask_m[7] << 16) 2122 | (mask_m[8] << 14) | (mask_m[9] << 12) 2123 | (mask_m[10] << 10) | (mask_m[11] << 8) 2124 | (mask_m[12] << 6) | (mask_m[13] << 4) 2125 | (mask_m[14] << 2) | (mask_m[15] << 0); 2126 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 2127 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 2128 2129 tmp_mask = (mask_p[15] << 28) 2130 | (mask_p[14] << 26) | (mask_p[13] << 24) 2131 | (mask_p[12] << 22) | (mask_p[11] << 20) 2132 | (mask_p[10] << 18) | (mask_p[9] << 16) 2133 | (mask_p[8] << 14) | (mask_p[7] << 12) 2134 | (mask_p[6] << 10) | (mask_p[5] << 8) 2135 | (mask_p[4] << 6) | (mask_p[3] << 4) 2136 | (mask_p[2] << 2) | (mask_p[1] << 0); 2137 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 2138 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 2139 2140 tmp_mask = (mask_p[30] << 28) 2141 | (mask_p[29] << 26) | (mask_p[28] << 24) 2142 | (mask_p[27] << 22) | (mask_p[26] << 20) 2143 | (mask_p[25] << 18) | (mask_p[24] << 16) 2144 | (mask_p[23] << 14) | (mask_p[22] << 12) 2145 | (mask_p[21] << 10) | (mask_p[20] << 8) 2146 | (mask_p[19] << 6) | (mask_p[18] << 4) 2147 | (mask_p[17] << 2) | (mask_p[16] << 0); 2148 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 2149 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 2150 2151 tmp_mask = (mask_p[45] << 28) 2152 | (mask_p[44] << 26) | (mask_p[43] << 24) 2153 | (mask_p[42] << 22) | (mask_p[41] << 20) 2154 | (mask_p[40] << 18) | (mask_p[39] << 16) 2155 | (mask_p[38] << 14) | (mask_p[37] << 12) 2156 | (mask_p[36] << 10) | (mask_p[35] << 8) 2157 | (mask_p[34] << 6) | (mask_p[33] << 4) 2158 | (mask_p[32] << 2) | (mask_p[31] << 0); 2159 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 2160 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 2161 2162 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 2163 | (mask_p[59] << 26) | (mask_p[58] << 24) 2164 | (mask_p[57] << 22) | (mask_p[56] << 20) 2165 | (mask_p[55] << 18) | (mask_p[54] << 16) 2166 | (mask_p[53] << 14) | (mask_p[52] << 12) 2167 | (mask_p[51] << 10) | (mask_p[50] << 8) 2168 | (mask_p[49] << 6) | (mask_p[48] << 4) 2169 | (mask_p[47] << 2) | (mask_p[46] << 0); 2170 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 2171 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2172} 2173 2174int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 2175 bool bChannelChange) 2176{ 2177 u32 saveLedState; 2178 struct ath_softc *sc = ah->ah_sc; 2179 struct ath9k_channel *curchan = ah->curchan; 2180 u32 saveDefAntenna; 2181 u32 macStaId1; 2182 int i, rx_chainmask, r; 2183 2184 ah->extprotspacing = sc->ht_extprotspacing; 2185 ah->txchainmask = sc->tx_chainmask; 2186 ah->rxchainmask = sc->rx_chainmask; 2187 2188 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2189 return -EIO; 2190 2191 if (curchan) 2192 ath9k_hw_getnf(ah, curchan); 2193 2194 if (bChannelChange && 2195 (ah->chip_fullsleep != true) && 2196 (ah->curchan != NULL) && 2197 (chan->channel != ah->curchan->channel) && 2198 ((chan->channelFlags & CHANNEL_ALL) == 2199 (ah->curchan->channelFlags & CHANNEL_ALL)) && 2200 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && 2201 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) { 2202 2203 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) { 2204 ath9k_hw_loadnf(ah, ah->curchan); 2205 ath9k_hw_start_nfcal(ah); 2206 return 0; 2207 } 2208 } 2209 2210 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 2211 if (saveDefAntenna == 0) 2212 saveDefAntenna = 1; 2213 2214 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2215 2216 saveLedState = REG_READ(ah, AR_CFG_LED) & 2217 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 2218 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 2219 2220 ath9k_hw_mark_phy_inactive(ah); 2221 2222 if (!ath9k_hw_chip_reset(ah, chan)) { 2223 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n"); 2224 return -EINVAL; 2225 } 2226 2227 if (AR_SREV_9280_10_OR_LATER(ah)) 2228 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 2229 2230 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width); 2231 if (r) 2232 return r; 2233 2234 /* Setup MFP options for CCMP */ 2235 if (AR_SREV_9280_20_OR_LATER(ah)) { 2236 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 2237 * frames when constructing CCMP AAD. */ 2238 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 2239 0xc7ff); 2240 ah->sw_mgmt_crypto = false; 2241 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 2242 /* Disable hardware crypto for management frames */ 2243 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 2244 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2245 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 2246 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2247 ah->sw_mgmt_crypto = true; 2248 } else 2249 ah->sw_mgmt_crypto = true; 2250 2251 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2252 ath9k_hw_set_delta_slope(ah, chan); 2253 2254 if (AR_SREV_9280_10_OR_LATER(ah)) 2255 ath9k_hw_9280_spur_mitigate(ah, chan); 2256 else 2257 ath9k_hw_spur_mitigate(ah, chan); 2258 2259 ah->eep_ops->set_board_values(ah, chan); 2260 2261 ath9k_hw_decrease_chain_power(ah, chan); 2262 2263 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr)); 2264 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4) 2265 | macStaId1 2266 | AR_STA_ID1_RTS_USE_DEF 2267 | (ah->config. 2268 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 2269 | ah->sta_id1_defaults); 2270 ath9k_hw_set_operating_mode(ah, ah->opmode); 2271 2272 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); 2273 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4)); 2274 2275 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 2276 2277 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); 2278 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) | 2279 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2280 2281 REG_WRITE(ah, AR_ISR, ~0); 2282 2283 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2284 2285 if (AR_SREV_9280_10_OR_LATER(ah)) { 2286 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) 2287 return -EIO; 2288 } else { 2289 if (!(ath9k_hw_set_channel(ah, chan))) 2290 return -EIO; 2291 } 2292 2293 for (i = 0; i < AR_NUM_DCU; i++) 2294 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2295 2296 ah->intr_txqs = 0; 2297 for (i = 0; i < ah->caps.total_queues; i++) 2298 ath9k_hw_resettxqueue(ah, i); 2299 2300 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 2301 ath9k_hw_init_qos(ah); 2302 2303#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2304 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2305 ath9k_enable_rfkill(ah); 2306#endif 2307 ath9k_hw_init_user_settings(ah); 2308 2309 REG_WRITE(ah, AR_STA_ID1, 2310 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 2311 2312 ath9k_hw_set_dma(ah); 2313 2314 REG_WRITE(ah, AR_OBS, 8); 2315 2316 if (ah->config.intr_mitigation) { 2317 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2318 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2319 } 2320 2321 ath9k_hw_init_bb(ah, chan); 2322 2323 if (!ath9k_hw_init_cal(ah, chan)) 2324 return -EIO;; 2325 2326 rx_chainmask = ah->rxchainmask; 2327 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 2328 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 2329 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 2330 } 2331 2332 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2333 2334 if (AR_SREV_9100(ah)) { 2335 u32 mask; 2336 mask = REG_READ(ah, AR_CFG); 2337 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2338 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2339 "CFG Byte Swap Set 0x%x\n", mask); 2340 } else { 2341 mask = 2342 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2343 REG_WRITE(ah, AR_CFG, mask); 2344 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2345 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 2346 } 2347 } else { 2348#ifdef __BIG_ENDIAN 2349 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2350#endif 2351 } 2352 2353 return 0; 2354} 2355 2356/************************/ 2357/* Key Cache Management */ 2358/************************/ 2359 2360bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) 2361{ 2362 u32 keyType; 2363 2364 if (entry >= ah->caps.keycache_size) { 2365 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2366 "keychache entry %u out of range\n", entry); 2367 return false; 2368 } 2369 2370 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 2371 2372 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 2373 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 2374 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 2375 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 2376 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 2377 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 2378 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 2379 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 2380 2381 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 2382 u16 micentry = entry + 64; 2383 2384 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 2385 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 2386 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); 2387 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 2388 2389 } 2390 2391 if (ah->curchan == NULL) 2392 return true; 2393 2394 return true; 2395} 2396 2397bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) 2398{ 2399 u32 macHi, macLo; 2400 2401 if (entry >= ah->caps.keycache_size) { 2402 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2403 "keychache entry %u out of range\n", entry); 2404 return false; 2405 } 2406 2407 if (mac != NULL) { 2408 macHi = (mac[5] << 8) | mac[4]; 2409 macLo = (mac[3] << 24) | 2410 (mac[2] << 16) | 2411 (mac[1] << 8) | 2412 mac[0]; 2413 macLo >>= 1; 2414 macLo |= (macHi & 1) << 31; 2415 macHi >>= 1; 2416 } else { 2417 macLo = macHi = 0; 2418 } 2419 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 2420 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); 2421 2422 return true; 2423} 2424 2425bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, 2426 const struct ath9k_keyval *k, 2427 const u8 *mac) 2428{ 2429 const struct ath9k_hw_capabilities *pCap = &ah->caps; 2430 u32 key0, key1, key2, key3, key4; 2431 u32 keyType; 2432 2433 if (entry >= pCap->keycache_size) { 2434 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2435 "keycache entry %u out of range\n", entry); 2436 return false; 2437 } 2438 2439 switch (k->kv_type) { 2440 case ATH9K_CIPHER_AES_OCB: 2441 keyType = AR_KEYTABLE_TYPE_AES; 2442 break; 2443 case ATH9K_CIPHER_AES_CCM: 2444 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2445 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2446 "AES-CCM not supported by mac rev 0x%x\n", 2447 ah->hw_version.macRev); 2448 return false; 2449 } 2450 keyType = AR_KEYTABLE_TYPE_CCM; 2451 break; 2452 case ATH9K_CIPHER_TKIP: 2453 keyType = AR_KEYTABLE_TYPE_TKIP; 2454 if (ATH9K_IS_MIC_ENABLED(ah) 2455 && entry + 64 >= pCap->keycache_size) { 2456 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2457 "entry %u inappropriate for TKIP\n", entry); 2458 return false; 2459 } 2460 break; 2461 case ATH9K_CIPHER_WEP: 2462 if (k->kv_len < LEN_WEP40) { 2463 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2464 "WEP key length %u too small\n", k->kv_len); 2465 return false; 2466 } 2467 if (k->kv_len <= LEN_WEP40) 2468 keyType = AR_KEYTABLE_TYPE_40; 2469 else if (k->kv_len <= LEN_WEP104) 2470 keyType = AR_KEYTABLE_TYPE_104; 2471 else 2472 keyType = AR_KEYTABLE_TYPE_128; 2473 break; 2474 case ATH9K_CIPHER_CLR: 2475 keyType = AR_KEYTABLE_TYPE_CLR; 2476 break; 2477 default: 2478 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2479 "cipher %u not supported\n", k->kv_type); 2480 return false; 2481 } 2482 2483 key0 = get_unaligned_le32(k->kv_val + 0); 2484 key1 = get_unaligned_le16(k->kv_val + 4); 2485 key2 = get_unaligned_le32(k->kv_val + 6); 2486 key3 = get_unaligned_le16(k->kv_val + 10); 2487 key4 = get_unaligned_le32(k->kv_val + 12); 2488 if (k->kv_len <= LEN_WEP104) 2489 key4 &= 0xff; 2490 2491 /* 2492 * Note: Key cache registers access special memory area that requires 2493 * two 32-bit writes to actually update the values in the internal 2494 * memory. Consequently, the exact order and pairs used here must be 2495 * maintained. 2496 */ 2497 2498 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 2499 u16 micentry = entry + 64; 2500 2501 /* 2502 * Write inverted key[47:0] first to avoid Michael MIC errors 2503 * on frames that could be sent or received at the same time. 2504 * The correct key will be written in the end once everything 2505 * else is ready. 2506 */ 2507 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); 2508 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); 2509 2510 /* Write key[95:48] */ 2511 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 2512 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 2513 2514 /* Write key[127:96] and key type */ 2515 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 2516 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2517 2518 /* Write MAC address for the entry */ 2519 (void) ath9k_hw_keysetmac(ah, entry, mac); 2520 2521 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { 2522 /* 2523 * TKIP uses two key cache entries: 2524 * Michael MIC TX/RX keys in the same key cache entry 2525 * (idx = main index + 64): 2526 * key0 [31:0] = RX key [31:0] 2527 * key1 [15:0] = TX key [31:16] 2528 * key1 [31:16] = reserved 2529 * key2 [31:0] = RX key [63:32] 2530 * key3 [15:0] = TX key [15:0] 2531 * key3 [31:16] = reserved 2532 * key4 [31:0] = TX key [63:32] 2533 */ 2534 u32 mic0, mic1, mic2, mic3, mic4; 2535 2536 mic0 = get_unaligned_le32(k->kv_mic + 0); 2537 mic2 = get_unaligned_le32(k->kv_mic + 4); 2538 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; 2539 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; 2540 mic4 = get_unaligned_le32(k->kv_txmic + 4); 2541 2542 /* Write RX[31:0] and TX[31:16] */ 2543 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 2544 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); 2545 2546 /* Write RX[63:32] and TX[15:0] */ 2547 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 2548 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); 2549 2550 /* Write TX[63:32] and keyType(reserved) */ 2551 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); 2552 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 2553 AR_KEYTABLE_TYPE_CLR); 2554 2555 } else { 2556 /* 2557 * TKIP uses four key cache entries (two for group 2558 * keys): 2559 * Michael MIC TX/RX keys are in different key cache 2560 * entries (idx = main index + 64 for TX and 2561 * main index + 32 + 96 for RX): 2562 * key0 [31:0] = TX/RX MIC key [31:0] 2563 * key1 [31:0] = reserved 2564 * key2 [31:0] = TX/RX MIC key [63:32] 2565 * key3 [31:0] = reserved 2566 * key4 [31:0] = reserved 2567 * 2568 * Upper layer code will call this function separately 2569 * for TX and RX keys when these registers offsets are 2570 * used. 2571 */ 2572 u32 mic0, mic2; 2573 2574 mic0 = get_unaligned_le32(k->kv_mic + 0); 2575 mic2 = get_unaligned_le32(k->kv_mic + 4); 2576 2577 /* Write MIC key[31:0] */ 2578 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 2579 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 2580 2581 /* Write MIC key[63:32] */ 2582 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 2583 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 2584 2585 /* Write TX[63:32] and keyType(reserved) */ 2586 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); 2587 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 2588 AR_KEYTABLE_TYPE_CLR); 2589 } 2590 2591 /* MAC address registers are reserved for the MIC entry */ 2592 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); 2593 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); 2594 2595 /* 2596 * Write the correct (un-inverted) key[47:0] last to enable 2597 * TKIP now that all other registers are set with correct 2598 * values. 2599 */ 2600 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 2601 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 2602 } else { 2603 /* Write key[47:0] */ 2604 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 2605 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 2606 2607 /* Write key[95:48] */ 2608 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 2609 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 2610 2611 /* Write key[127:96] and key type */ 2612 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 2613 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2614 2615 /* Write MAC address for the entry */ 2616 (void) ath9k_hw_keysetmac(ah, entry, mac); 2617 } 2618 2619 return true; 2620} 2621 2622bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) 2623{ 2624 if (entry < ah->caps.keycache_size) { 2625 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 2626 if (val & AR_KEYTABLE_VALID) 2627 return true; 2628 } 2629 return false; 2630} 2631 2632/******************************/ 2633/* Power Management (Chipset) */ 2634/******************************/ 2635 2636static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 2637{ 2638 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2639 if (setChip) { 2640 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2641 AR_RTC_FORCE_WAKE_EN); 2642 if (!AR_SREV_9100(ah)) 2643 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2644 2645 REG_CLR_BIT(ah, (AR_RTC_RESET), 2646 AR_RTC_RESET_EN); 2647 } 2648} 2649 2650static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 2651{ 2652 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2653 if (setChip) { 2654 struct ath9k_hw_capabilities *pCap = &ah->caps; 2655 2656 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2657 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2658 AR_RTC_FORCE_WAKE_ON_INT); 2659 } else { 2660 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2661 AR_RTC_FORCE_WAKE_EN); 2662 } 2663 } 2664} 2665 2666static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 2667{ 2668 u32 val; 2669 int i; 2670 2671 if (setChip) { 2672 if ((REG_READ(ah, AR_RTC_STATUS) & 2673 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2674 if (ath9k_hw_set_reset_reg(ah, 2675 ATH9K_RESET_POWER_ON) != true) { 2676 return false; 2677 } 2678 } 2679 if (AR_SREV_9100(ah)) 2680 REG_SET_BIT(ah, AR_RTC_RESET, 2681 AR_RTC_RESET_EN); 2682 2683 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2684 AR_RTC_FORCE_WAKE_EN); 2685 udelay(50); 2686 2687 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2688 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2689 if (val == AR_RTC_STATUS_ON) 2690 break; 2691 udelay(50); 2692 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2693 AR_RTC_FORCE_WAKE_EN); 2694 } 2695 if (i == 0) { 2696 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2697 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20); 2698 return false; 2699 } 2700 } 2701 2702 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2703 2704 return true; 2705} 2706 2707bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2708{ 2709 int status = true, setChip = true; 2710 static const char *modes[] = { 2711 "AWAKE", 2712 "FULL-SLEEP", 2713 "NETWORK SLEEP", 2714 "UNDEFINED" 2715 }; 2716 2717 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n", 2718 modes[ah->power_mode], modes[mode]); 2719 2720 switch (mode) { 2721 case ATH9K_PM_AWAKE: 2722 status = ath9k_hw_set_power_awake(ah, setChip); 2723 break; 2724 case ATH9K_PM_FULL_SLEEP: 2725 ath9k_set_power_sleep(ah, setChip); 2726 ah->chip_fullsleep = true; 2727 break; 2728 case ATH9K_PM_NETWORK_SLEEP: 2729 ath9k_set_power_network_sleep(ah, setChip); 2730 break; 2731 default: 2732 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2733 "Unknown power mode %u\n", mode); 2734 return false; 2735 } 2736 ah->power_mode = mode; 2737 2738 return status; 2739} 2740 2741/* 2742 * Helper for ASPM support. 2743 * 2744 * Disable PLL when in L0s as well as receiver clock when in L1. 2745 * This power saving option must be enabled through the SerDes. 2746 * 2747 * Programming the SerDes must go through the same 288 bit serial shift 2748 * register as the other analog registers. Hence the 9 writes. 2749 */ 2750void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) 2751{ 2752 u8 i; 2753 2754 if (ah->is_pciexpress != true) 2755 return; 2756 2757 /* Do not touch SerDes registers */ 2758 if (ah->config.pcie_powersave_enable == 2) 2759 return; 2760 2761 /* Nothing to do on restore for 11N */ 2762 if (restore) 2763 return; 2764 2765 if (AR_SREV_9280_20_OR_LATER(ah)) { 2766 /* 2767 * AR9280 2.0 or later chips use SerDes values from the 2768 * initvals.h initialized depending on chipset during 2769 * ath9k_hw_do_attach() 2770 */ 2771 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { 2772 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), 2773 INI_RA(&ah->iniPcieSerdes, i, 1)); 2774 } 2775 } else if (AR_SREV_9280(ah) && 2776 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { 2777 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); 2778 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2779 2780 /* RX shut off when elecidle is asserted */ 2781 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); 2782 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); 2783 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); 2784 2785 /* Shut off CLKREQ active in L1 */ 2786 if (ah->config.pcie_clock_req) 2787 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); 2788 else 2789 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); 2790 2791 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 2792 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 2793 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); 2794 2795 /* Load the new settings */ 2796 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 2797 2798 } else { 2799 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 2800 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2801 2802 /* RX shut off when elecidle is asserted */ 2803 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 2804 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 2805 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 2806 2807 /* 2808 * Ignore ah->ah_config.pcie_clock_req setting for 2809 * pre-AR9280 11n 2810 */ 2811 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 2812 2813 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 2814 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 2815 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 2816 2817 /* Load the new settings */ 2818 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 2819 } 2820 2821 udelay(1000); 2822 2823 /* set bit 19 to allow forcing of pcie core into L1 state */ 2824 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 2825 2826 /* Several PCIe massages to ensure proper behaviour */ 2827 if (ah->config.pcie_waen) { 2828 REG_WRITE(ah, AR_WA, ah->config.pcie_waen); 2829 } else { 2830 if (AR_SREV_9285(ah)) 2831 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); 2832 /* 2833 * On AR9280 chips bit 22 of 0x4004 needs to be set to 2834 * otherwise card may disappear. 2835 */ 2836 else if (AR_SREV_9280(ah)) 2837 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 2838 else 2839 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 2840 } 2841} 2842 2843/**********************/ 2844/* Interrupt Handling */ 2845/**********************/ 2846 2847bool ath9k_hw_intrpend(struct ath_hw *ah) 2848{ 2849 u32 host_isr; 2850 2851 if (AR_SREV_9100(ah)) 2852 return true; 2853 2854 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); 2855 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) 2856 return true; 2857 2858 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); 2859 if ((host_isr & AR_INTR_SYNC_DEFAULT) 2860 && (host_isr != AR_INTR_SPURIOUS)) 2861 return true; 2862 2863 return false; 2864} 2865 2866bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) 2867{ 2868 u32 isr = 0; 2869 u32 mask2 = 0; 2870 struct ath9k_hw_capabilities *pCap = &ah->caps; 2871 u32 sync_cause = 0; 2872 bool fatal_int = false; 2873 2874 if (!AR_SREV_9100(ah)) { 2875 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2876 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 2877 == AR_RTC_STATUS_ON) { 2878 isr = REG_READ(ah, AR_ISR); 2879 } 2880 } 2881 2882 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & 2883 AR_INTR_SYNC_DEFAULT; 2884 2885 *masked = 0; 2886 2887 if (!isr && !sync_cause) 2888 return false; 2889 } else { 2890 *masked = 0; 2891 isr = REG_READ(ah, AR_ISR); 2892 } 2893 2894 if (isr) { 2895 if (isr & AR_ISR_BCNMISC) { 2896 u32 isr2; 2897 isr2 = REG_READ(ah, AR_ISR_S2); 2898 if (isr2 & AR_ISR_S2_TIM) 2899 mask2 |= ATH9K_INT_TIM; 2900 if (isr2 & AR_ISR_S2_DTIM) 2901 mask2 |= ATH9K_INT_DTIM; 2902 if (isr2 & AR_ISR_S2_DTIMSYNC) 2903 mask2 |= ATH9K_INT_DTIMSYNC; 2904 if (isr2 & (AR_ISR_S2_CABEND)) 2905 mask2 |= ATH9K_INT_CABEND; 2906 if (isr2 & AR_ISR_S2_GTT) 2907 mask2 |= ATH9K_INT_GTT; 2908 if (isr2 & AR_ISR_S2_CST) 2909 mask2 |= ATH9K_INT_CST; 2910 if (isr2 & AR_ISR_S2_TSFOOR) 2911 mask2 |= ATH9K_INT_TSFOOR; 2912 } 2913 2914 isr = REG_READ(ah, AR_ISR_RAC); 2915 if (isr == 0xffffffff) { 2916 *masked = 0; 2917 return false; 2918 } 2919 2920 *masked = isr & ATH9K_INT_COMMON; 2921 2922 if (ah->config.intr_mitigation) { 2923 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2924 *masked |= ATH9K_INT_RX; 2925 } 2926 2927 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 2928 *masked |= ATH9K_INT_RX; 2929 if (isr & 2930 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | 2931 AR_ISR_TXEOL)) { 2932 u32 s0_s, s1_s; 2933 2934 *masked |= ATH9K_INT_TX; 2935 2936 s0_s = REG_READ(ah, AR_ISR_S0_S); 2937 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); 2938 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); 2939 2940 s1_s = REG_READ(ah, AR_ISR_S1_S); 2941 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); 2942 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); 2943 } 2944 2945 if (isr & AR_ISR_RXORN) { 2946 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2947 "receive FIFO overrun interrupt\n"); 2948 } 2949 2950 if (!AR_SREV_9100(ah)) { 2951 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2952 u32 isr5 = REG_READ(ah, AR_ISR_S5_S); 2953 if (isr5 & AR_ISR_S5_TIM_TIMER) 2954 *masked |= ATH9K_INT_TIM_TIMER; 2955 } 2956 } 2957 2958 *masked |= mask2; 2959 } 2960 2961 if (AR_SREV_9100(ah)) 2962 return true; 2963 2964 if (sync_cause) { 2965 fatal_int = 2966 (sync_cause & 2967 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) 2968 ? true : false; 2969 2970 if (fatal_int) { 2971 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 2972 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2973 "received PCI FATAL interrupt\n"); 2974 } 2975 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 2976 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2977 "received PCI PERR interrupt\n"); 2978 } 2979 *masked |= ATH9K_INT_FATAL; 2980 } 2981 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 2982 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2983 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); 2984 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 2985 REG_WRITE(ah, AR_RC, 0); 2986 *masked |= ATH9K_INT_FATAL; 2987 } 2988 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 2989 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2990 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 2991 } 2992 2993 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 2994 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 2995 } 2996 2997 return true; 2998} 2999 3000enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah) 3001{ 3002 return ah->mask_reg; 3003} 3004 3005enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) 3006{ 3007 u32 omask = ah->mask_reg; 3008 u32 mask, mask2; 3009 struct ath9k_hw_capabilities *pCap = &ah->caps; 3010 3011 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 3012 3013 if (omask & ATH9K_INT_GLOBAL) { 3014 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n"); 3015 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 3016 (void) REG_READ(ah, AR_IER); 3017 if (!AR_SREV_9100(ah)) { 3018 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 3019 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); 3020 3021 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 3022 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); 3023 } 3024 } 3025 3026 mask = ints & ATH9K_INT_COMMON; 3027 mask2 = 0; 3028 3029 if (ints & ATH9K_INT_TX) { 3030 if (ah->txok_interrupt_mask) 3031 mask |= AR_IMR_TXOK; 3032 if (ah->txdesc_interrupt_mask) 3033 mask |= AR_IMR_TXDESC; 3034 if (ah->txerr_interrupt_mask) 3035 mask |= AR_IMR_TXERR; 3036 if (ah->txeol_interrupt_mask) 3037 mask |= AR_IMR_TXEOL; 3038 } 3039 if (ints & ATH9K_INT_RX) { 3040 mask |= AR_IMR_RXERR; 3041 if (ah->config.intr_mitigation) 3042 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 3043 else 3044 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 3045 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 3046 mask |= AR_IMR_GENTMR; 3047 } 3048 3049 if (ints & (ATH9K_INT_BMISC)) { 3050 mask |= AR_IMR_BCNMISC; 3051 if (ints & ATH9K_INT_TIM) 3052 mask2 |= AR_IMR_S2_TIM; 3053 if (ints & ATH9K_INT_DTIM) 3054 mask2 |= AR_IMR_S2_DTIM; 3055 if (ints & ATH9K_INT_DTIMSYNC) 3056 mask2 |= AR_IMR_S2_DTIMSYNC; 3057 if (ints & ATH9K_INT_CABEND) 3058 mask2 |= AR_IMR_S2_CABEND; 3059 if (ints & ATH9K_INT_TSFOOR) 3060 mask2 |= AR_IMR_S2_TSFOOR; 3061 } 3062 3063 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { 3064 mask |= AR_IMR_BCNMISC; 3065 if (ints & ATH9K_INT_GTT) 3066 mask2 |= AR_IMR_S2_GTT; 3067 if (ints & ATH9K_INT_CST) 3068 mask2 |= AR_IMR_S2_CST; 3069 } 3070 3071 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); 3072 REG_WRITE(ah, AR_IMR, mask); 3073 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 3074 AR_IMR_S2_DTIM | 3075 AR_IMR_S2_DTIMSYNC | 3076 AR_IMR_S2_CABEND | 3077 AR_IMR_S2_CABTO | 3078 AR_IMR_S2_TSFOOR | 3079 AR_IMR_S2_GTT | AR_IMR_S2_CST); 3080 REG_WRITE(ah, AR_IMR_S2, mask | mask2); 3081 ah->mask_reg = ints; 3082 3083 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 3084 if (ints & ATH9K_INT_TIM_TIMER) 3085 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 3086 else 3087 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 3088 } 3089 3090 if (ints & ATH9K_INT_GLOBAL) { 3091 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n"); 3092 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 3093 if (!AR_SREV_9100(ah)) { 3094 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 3095 AR_INTR_MAC_IRQ); 3096 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 3097 3098 3099 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 3100 AR_INTR_SYNC_DEFAULT); 3101 REG_WRITE(ah, AR_INTR_SYNC_MASK, 3102 AR_INTR_SYNC_DEFAULT); 3103 } 3104 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 3105 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 3106 } 3107 3108 return omask; 3109} 3110 3111/*******************/ 3112/* Beacon Handling */ 3113/*******************/ 3114 3115void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 3116{ 3117 int flags = 0; 3118 3119 ah->beacon_interval = beacon_period; 3120 3121 switch (ah->opmode) { 3122 case NL80211_IFTYPE_STATION: 3123 case NL80211_IFTYPE_MONITOR: 3124 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 3125 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); 3126 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); 3127 flags |= AR_TBTT_TIMER_EN; 3128 break; 3129 case NL80211_IFTYPE_ADHOC: 3130 case NL80211_IFTYPE_MESH_POINT: 3131 REG_SET_BIT(ah, AR_TXCFG, 3132 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 3133 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 3134 TU_TO_USEC(next_beacon + 3135 (ah->atim_window ? ah-> 3136 atim_window : 1))); 3137 flags |= AR_NDP_TIMER_EN; 3138 case NL80211_IFTYPE_AP: 3139 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 3140 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 3141 TU_TO_USEC(next_beacon - 3142 ah->config. 3143 dma_beacon_response_time)); 3144 REG_WRITE(ah, AR_NEXT_SWBA, 3145 TU_TO_USEC(next_beacon - 3146 ah->config. 3147 sw_beacon_response_time)); 3148 flags |= 3149 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 3150 break; 3151 default: 3152 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, 3153 "%s: unsupported opmode: %d\n", 3154 __func__, ah->opmode); 3155 return; 3156 break; 3157 } 3158 3159 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 3160 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 3161 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 3162 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 3163 3164 beacon_period &= ~ATH9K_BEACON_ENA; 3165 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 3166 beacon_period &= ~ATH9K_BEACON_RESET_TSF; 3167 ath9k_hw_reset_tsf(ah); 3168 } 3169 3170 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3171} 3172 3173void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 3174 const struct ath9k_beacon_state *bs) 3175{ 3176 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3177 struct ath9k_hw_capabilities *pCap = &ah->caps; 3178 3179 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 3180 3181 REG_WRITE(ah, AR_BEACON_PERIOD, 3182 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 3183 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 3184 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 3185 3186 REG_RMW_FIELD(ah, AR_RSSI_THR, 3187 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 3188 3189 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 3190 3191 if (bs->bs_sleepduration > beaconintval) 3192 beaconintval = bs->bs_sleepduration; 3193 3194 dtimperiod = bs->bs_dtimperiod; 3195 if (bs->bs_sleepduration > dtimperiod) 3196 dtimperiod = bs->bs_sleepduration; 3197 3198 if (beaconintval == dtimperiod) 3199 nextTbtt = bs->bs_nextdtim; 3200 else 3201 nextTbtt = bs->bs_nexttbtt; 3202 3203 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 3204 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 3205 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 3206 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 3207 3208 REG_WRITE(ah, AR_NEXT_DTIM, 3209 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3210 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 3211 3212 REG_WRITE(ah, AR_SLEEP1, 3213 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 3214 | AR_SLEEP1_ASSUME_DTIM); 3215 3216 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 3217 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 3218 else 3219 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 3220 3221 REG_WRITE(ah, AR_SLEEP2, 3222 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 3223 3224 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 3225 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 3226 3227 REG_SET_BIT(ah, AR_TIMER_MODE, 3228 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 3229 AR_DTIM_TIMER_EN); 3230 3231 /* TSF Out of Range Threshold */ 3232 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 3233} 3234 3235/*******************/ 3236/* HW Capabilities */ 3237/*******************/ 3238 3239void ath9k_hw_fill_cap_info(struct ath_hw *ah) 3240{ 3241 struct ath9k_hw_capabilities *pCap = &ah->caps; 3242 u16 capField = 0, eeval; 3243 3244 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 3245 ah->regulatory.current_rd = eeval; 3246 3247 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 3248 if (AR_SREV_9285_10_OR_LATER(ah)) 3249 eeval |= AR9285_RDEXT_DEFAULT; 3250 ah->regulatory.current_rd_ext = eeval; 3251 3252 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 3253 3254 if (ah->opmode != NL80211_IFTYPE_AP && 3255 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 3256 if (ah->regulatory.current_rd == 0x64 || 3257 ah->regulatory.current_rd == 0x65) 3258 ah->regulatory.current_rd += 5; 3259 else if (ah->regulatory.current_rd == 0x41) 3260 ah->regulatory.current_rd = 0x43; 3261 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 3262 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd); 3263 } 3264 3265 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 3266 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); 3267 3268 if (eeval & AR5416_OPFLAGS_11A) { 3269 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 3270 if (ah->config.ht_enable) { 3271 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) 3272 set_bit(ATH9K_MODE_11NA_HT20, 3273 pCap->wireless_modes); 3274 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { 3275 set_bit(ATH9K_MODE_11NA_HT40PLUS, 3276 pCap->wireless_modes); 3277 set_bit(ATH9K_MODE_11NA_HT40MINUS, 3278 pCap->wireless_modes); 3279 } 3280 } 3281 } 3282 3283 if (eeval & AR5416_OPFLAGS_11G) { 3284 set_bit(ATH9K_MODE_11B, pCap->wireless_modes); 3285 set_bit(ATH9K_MODE_11G, pCap->wireless_modes); 3286 if (ah->config.ht_enable) { 3287 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) 3288 set_bit(ATH9K_MODE_11NG_HT20, 3289 pCap->wireless_modes); 3290 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { 3291 set_bit(ATH9K_MODE_11NG_HT40PLUS, 3292 pCap->wireless_modes); 3293 set_bit(ATH9K_MODE_11NG_HT40MINUS, 3294 pCap->wireless_modes); 3295 } 3296 } 3297 } 3298 3299 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 3300 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 3301 !(eeval & AR5416_OPFLAGS_11A)) 3302 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 3303 else 3304 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 3305 3306 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 3307 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 3308 3309 pCap->low_2ghz_chan = 2312; 3310 pCap->high_2ghz_chan = 2732; 3311 3312 pCap->low_5ghz_chan = 4920; 3313 pCap->high_5ghz_chan = 6100; 3314 3315 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; 3316 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; 3317 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; 3318 3319 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; 3320 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; 3321 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; 3322 3323 if (ah->config.ht_enable) 3324 pCap->hw_caps |= ATH9K_HW_CAP_HT; 3325 else 3326 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 3327 3328 pCap->hw_caps |= ATH9K_HW_CAP_GTT; 3329 pCap->hw_caps |= ATH9K_HW_CAP_VEOL; 3330 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; 3331 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; 3332 3333 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 3334 pCap->total_queues = 3335 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 3336 else 3337 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 3338 3339 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 3340 pCap->keycache_size = 3341 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 3342 else 3343 pCap->keycache_size = AR_KEYTABLE_SIZE; 3344 3345 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; 3346 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 3347 3348 if (AR_SREV_9285_10_OR_LATER(ah)) 3349 pCap->num_gpio_pins = AR9285_NUM_GPIO; 3350 else if (AR_SREV_9280_10_OR_LATER(ah)) 3351 pCap->num_gpio_pins = AR928X_NUM_GPIO; 3352 else 3353 pCap->num_gpio_pins = AR_NUM_GPIO; 3354 3355 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 3356 pCap->hw_caps |= ATH9K_HW_CAP_CST; 3357 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 3358 } else { 3359 pCap->rts_aggr_limit = (8 * 1024); 3360 } 3361 3362 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 3363 3364#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3365 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 3366 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 3367 ah->rfkill_gpio = 3368 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 3369 ah->rfkill_polarity = 3370 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 3371 3372 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 3373 } 3374#endif 3375 3376 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || 3377 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) || 3378 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) || 3379 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) || 3380 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) || 3381 (ah->hw_version.macVersion == AR_SREV_VERSION_9285)) 3382 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 3383 else 3384 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 3385 3386 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 3387 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 3388 else 3389 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 3390 3391 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 3392 pCap->reg_cap = 3393 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3394 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 3395 AR_EEPROM_EEREGCAP_EN_KK_U2 | 3396 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 3397 } else { 3398 pCap->reg_cap = 3399 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3400 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 3401 } 3402 3403 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 3404 3405 pCap->num_antcfg_5ghz = 3406 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 3407 pCap->num_antcfg_2ghz = 3408 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 3409 3410 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) { 3411 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX; 3412 ah->btactive_gpio = 6; 3413 ah->wlanactive_gpio = 5; 3414 } 3415} 3416 3417bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3418 u32 capability, u32 *result) 3419{ 3420 switch (type) { 3421 case ATH9K_CAP_CIPHER: 3422 switch (capability) { 3423 case ATH9K_CIPHER_AES_CCM: 3424 case ATH9K_CIPHER_AES_OCB: 3425 case ATH9K_CIPHER_TKIP: 3426 case ATH9K_CIPHER_WEP: 3427 case ATH9K_CIPHER_MIC: 3428 case ATH9K_CIPHER_CLR: 3429 return true; 3430 default: 3431 return false; 3432 } 3433 case ATH9K_CAP_TKIP_MIC: 3434 switch (capability) { 3435 case 0: 3436 return true; 3437 case 1: 3438 return (ah->sta_id1_defaults & 3439 AR_STA_ID1_CRPT_MIC_ENABLE) ? true : 3440 false; 3441 } 3442 case ATH9K_CAP_TKIP_SPLIT: 3443 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 3444 false : true; 3445 case ATH9K_CAP_DIVERSITY: 3446 return (REG_READ(ah, AR_PHY_CCK_DETECT) & 3447 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 3448 true : false; 3449 case ATH9K_CAP_MCAST_KEYSRCH: 3450 switch (capability) { 3451 case 0: 3452 return true; 3453 case 1: 3454 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 3455 return false; 3456 } else { 3457 return (ah->sta_id1_defaults & 3458 AR_STA_ID1_MCAST_KSRCH) ? true : 3459 false; 3460 } 3461 } 3462 return false; 3463 case ATH9K_CAP_TXPOW: 3464 switch (capability) { 3465 case 0: 3466 return 0; 3467 case 1: 3468 *result = ah->regulatory.power_limit; 3469 return 0; 3470 case 2: 3471 *result = ah->regulatory.max_power_level; 3472 return 0; 3473 case 3: 3474 *result = ah->regulatory.tp_scale; 3475 return 0; 3476 } 3477 return false; 3478 case ATH9K_CAP_DS: 3479 return (AR_SREV_9280_20_OR_LATER(ah) && 3480 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) 3481 ? false : true; 3482 default: 3483 return false; 3484 } 3485} 3486 3487bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3488 u32 capability, u32 setting, int *status) 3489{ 3490 u32 v; 3491 3492 switch (type) { 3493 case ATH9K_CAP_TKIP_MIC: 3494 if (setting) 3495 ah->sta_id1_defaults |= 3496 AR_STA_ID1_CRPT_MIC_ENABLE; 3497 else 3498 ah->sta_id1_defaults &= 3499 ~AR_STA_ID1_CRPT_MIC_ENABLE; 3500 return true; 3501 case ATH9K_CAP_DIVERSITY: 3502 v = REG_READ(ah, AR_PHY_CCK_DETECT); 3503 if (setting) 3504 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 3505 else 3506 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 3507 REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 3508 return true; 3509 case ATH9K_CAP_MCAST_KEYSRCH: 3510 if (setting) 3511 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 3512 else 3513 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 3514 return true; 3515 default: 3516 return false; 3517 } 3518} 3519 3520/****************************/ 3521/* GPIO / RFKILL / Antennae */ 3522/****************************/ 3523 3524static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 3525 u32 gpio, u32 type) 3526{ 3527 int addr; 3528 u32 gpio_shift, tmp; 3529 3530 if (gpio > 11) 3531 addr = AR_GPIO_OUTPUT_MUX3; 3532 else if (gpio > 5) 3533 addr = AR_GPIO_OUTPUT_MUX2; 3534 else 3535 addr = AR_GPIO_OUTPUT_MUX1; 3536 3537 gpio_shift = (gpio % 6) * 5; 3538 3539 if (AR_SREV_9280_20_OR_LATER(ah) 3540 || (addr != AR_GPIO_OUTPUT_MUX1)) { 3541 REG_RMW(ah, addr, (type << gpio_shift), 3542 (0x1f << gpio_shift)); 3543 } else { 3544 tmp = REG_READ(ah, addr); 3545 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 3546 tmp &= ~(0x1f << gpio_shift); 3547 tmp |= (type << gpio_shift); 3548 REG_WRITE(ah, addr, tmp); 3549 } 3550} 3551 3552void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 3553{ 3554 u32 gpio_shift; 3555 3556 ASSERT(gpio < ah->caps.num_gpio_pins); 3557 3558 gpio_shift = gpio << 1; 3559 3560 REG_RMW(ah, 3561 AR_GPIO_OE_OUT, 3562 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 3563 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3564} 3565 3566u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 3567{ 3568#define MS_REG_READ(x, y) \ 3569 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 3570 3571 if (gpio >= ah->caps.num_gpio_pins) 3572 return 0xffffffff; 3573 3574 if (AR_SREV_9285_10_OR_LATER(ah)) 3575 return MS_REG_READ(AR9285, gpio) != 0; 3576 else if (AR_SREV_9280_10_OR_LATER(ah)) 3577 return MS_REG_READ(AR928X, gpio) != 0; 3578 else 3579 return MS_REG_READ(AR, gpio) != 0; 3580} 3581 3582void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 3583 u32 ah_signal_type) 3584{ 3585 u32 gpio_shift; 3586 3587 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 3588 3589 gpio_shift = 2 * gpio; 3590 3591 REG_RMW(ah, 3592 AR_GPIO_OE_OUT, 3593 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 3594 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3595} 3596 3597void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 3598{ 3599 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 3600 AR_GPIO_BIT(gpio)); 3601} 3602 3603#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3604void ath9k_enable_rfkill(struct ath_hw *ah) 3605{ 3606 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 3607 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 3608 3609 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, 3610 AR_GPIO_INPUT_MUX2_RFSILENT); 3611 3612 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 3613 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 3614} 3615#endif 3616 3617u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 3618{ 3619 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 3620} 3621 3622void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 3623{ 3624 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 3625} 3626 3627bool ath9k_hw_setantennaswitch(struct ath_hw *ah, 3628 enum ath9k_ant_setting settings, 3629 struct ath9k_channel *chan, 3630 u8 *tx_chainmask, 3631 u8 *rx_chainmask, 3632 u8 *antenna_cfgd) 3633{ 3634 static u8 tx_chainmask_cfg, rx_chainmask_cfg; 3635 3636 if (AR_SREV_9280(ah)) { 3637 if (!tx_chainmask_cfg) { 3638 3639 tx_chainmask_cfg = *tx_chainmask; 3640 rx_chainmask_cfg = *rx_chainmask; 3641 } 3642 3643 switch (settings) { 3644 case ATH9K_ANT_FIXED_A: 3645 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK; 3646 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK; 3647 *antenna_cfgd = true; 3648 break; 3649 case ATH9K_ANT_FIXED_B: 3650 if (ah->caps.tx_chainmask > 3651 ATH9K_ANTENNA1_CHAINMASK) { 3652 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; 3653 } 3654 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK; 3655 *antenna_cfgd = true; 3656 break; 3657 case ATH9K_ANT_VARIABLE: 3658 *tx_chainmask = tx_chainmask_cfg; 3659 *rx_chainmask = rx_chainmask_cfg; 3660 *antenna_cfgd = true; 3661 break; 3662 default: 3663 break; 3664 } 3665 } else { 3666 ah->diversity_control = settings; 3667 } 3668 3669 return true; 3670} 3671 3672/*********************/ 3673/* General Operation */ 3674/*********************/ 3675 3676u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 3677{ 3678 u32 bits = REG_READ(ah, AR_RX_FILTER); 3679 u32 phybits = REG_READ(ah, AR_PHY_ERR); 3680 3681 if (phybits & AR_PHY_ERR_RADAR) 3682 bits |= ATH9K_RX_FILTER_PHYRADAR; 3683 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 3684 bits |= ATH9K_RX_FILTER_PHYERR; 3685 3686 return bits; 3687} 3688 3689void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 3690{ 3691 u32 phybits; 3692 3693 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR); 3694 phybits = 0; 3695 if (bits & ATH9K_RX_FILTER_PHYRADAR) 3696 phybits |= AR_PHY_ERR_RADAR; 3697 if (bits & ATH9K_RX_FILTER_PHYERR) 3698 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 3699 REG_WRITE(ah, AR_PHY_ERR, phybits); 3700 3701 if (phybits) 3702 REG_WRITE(ah, AR_RXCFG, 3703 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 3704 else 3705 REG_WRITE(ah, AR_RXCFG, 3706 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 3707} 3708 3709bool ath9k_hw_phy_disable(struct ath_hw *ah) 3710{ 3711 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); 3712} 3713 3714bool ath9k_hw_disable(struct ath_hw *ah) 3715{ 3716 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 3717 return false; 3718 3719 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); 3720} 3721 3722bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 3723{ 3724 struct ath9k_channel *chan = ah->curchan; 3725 struct ieee80211_channel *channel = chan->chan; 3726 3727 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER); 3728 3729 if (ah->eep_ops->set_txpower(ah, chan, 3730 ath9k_regd_get_ctl(&ah->regulatory, chan), 3731 channel->max_antenna_gain * 2, 3732 channel->max_power * 2, 3733 min((u32) MAX_RATE_POWER, 3734 (u32) ah->regulatory.power_limit)) != 0) 3735 return false; 3736 3737 return true; 3738} 3739 3740void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) 3741{ 3742 memcpy(ah->macaddr, mac, ETH_ALEN); 3743} 3744 3745void ath9k_hw_setopmode(struct ath_hw *ah) 3746{ 3747 ath9k_hw_set_operating_mode(ah, ah->opmode); 3748} 3749 3750void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 3751{ 3752 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 3753 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 3754} 3755 3756void ath9k_hw_setbssidmask(struct ath_softc *sc) 3757{ 3758 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); 3759 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4)); 3760} 3761 3762void ath9k_hw_write_associd(struct ath_softc *sc) 3763{ 3764 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); 3765 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) | 3766 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 3767} 3768 3769u64 ath9k_hw_gettsf64(struct ath_hw *ah) 3770{ 3771 u64 tsf; 3772 3773 tsf = REG_READ(ah, AR_TSF_U32); 3774 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); 3775 3776 return tsf; 3777} 3778 3779void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 3780{ 3781 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3782 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3783} 3784 3785void ath9k_hw_reset_tsf(struct ath_hw *ah) 3786{ 3787 int count; 3788 3789 count = 0; 3790 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 3791 count++; 3792 if (count > 10) { 3793 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 3794 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 3795 break; 3796 } 3797 udelay(10); 3798 } 3799 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3800} 3801 3802bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 3803{ 3804 if (setting) 3805 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 3806 else 3807 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 3808 3809 return true; 3810} 3811 3812bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 3813{ 3814 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 3815 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); 3816 ah->slottime = (u32) -1; 3817 return false; 3818 } else { 3819 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); 3820 ah->slottime = us; 3821 return true; 3822 } 3823} 3824 3825void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode) 3826{ 3827 u32 macmode; 3828 3829 if (mode == ATH9K_HT_MACMODE_2040 && 3830 !ah->config.cwm_ignore_extcca) 3831 macmode = AR_2040_JOINED_RX_CLEAR; 3832 else 3833 macmode = 0; 3834 3835 REG_WRITE(ah, AR_2040_MODE, macmode); 3836} 3837 3838/***************************/ 3839/* Bluetooth Coexistence */ 3840/***************************/ 3841 3842void ath9k_hw_btcoex_enable(struct ath_hw *ah) 3843{ 3844 /* connect bt_active to baseband */ 3845 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, 3846 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 3847 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 3848 3849 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 3850 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 3851 3852 /* Set input mux for bt_active to gpio pin */ 3853 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 3854 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 3855 ah->btactive_gpio); 3856 3857 /* Configure the desired gpio port for input */ 3858 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio); 3859 3860 /* Configure the desired GPIO port for TX_FRAME output */ 3861 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio, 3862 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 3863} 3864