hw.c revision bde748a40d4d5a9915def6772e208848c105e616
1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <asm/unaligned.h> 19 20#include "hw.h" 21#include "rc.h" 22#include "initvals.h" 23 24#define ATH9K_CLOCK_RATE_CCK 22 25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 27 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan); 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 31 struct ar5416_eeprom_def *pEepData, 32 u32 reg, u32 value); 33 34MODULE_AUTHOR("Atheros Communications"); 35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 36MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 37MODULE_LICENSE("Dual BSD/GPL"); 38 39static int __init ath9k_init(void) 40{ 41 return 0; 42} 43module_init(ath9k_init); 44 45static void __exit ath9k_exit(void) 46{ 47 return; 48} 49module_exit(ath9k_exit); 50 51/********************/ 52/* Helper Functions */ 53/********************/ 54 55static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) 56{ 57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 58 59 if (!ah->curchan) /* should really check for CCK instead */ 60 return usecs *ATH9K_CLOCK_RATE_CCK; 61 if (conf->channel->band == IEEE80211_BAND_2GHZ) 62 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 63 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; 64} 65 66static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 67{ 68 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 69 70 if (conf_is_ht40(conf)) 71 return ath9k_hw_mac_clks(ah, usecs) * 2; 72 else 73 return ath9k_hw_mac_clks(ah, usecs); 74} 75 76bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 77{ 78 int i; 79 80 BUG_ON(timeout < AH_TIME_QUANTUM); 81 82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 83 if ((REG_READ(ah, reg) & mask) == val) 84 return true; 85 86 udelay(AH_TIME_QUANTUM); 87 } 88 89 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, 90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 91 timeout, reg, REG_READ(ah, reg), mask, val); 92 93 return false; 94} 95EXPORT_SYMBOL(ath9k_hw_wait); 96 97u32 ath9k_hw_reverse_bits(u32 val, u32 n) 98{ 99 u32 retval; 100 int i; 101 102 for (i = 0, retval = 0; i < n; i++) { 103 retval = (retval << 1) | (val & 1); 104 val >>= 1; 105 } 106 return retval; 107} 108 109bool ath9k_get_channel_edges(struct ath_hw *ah, 110 u16 flags, u16 *low, 111 u16 *high) 112{ 113 struct ath9k_hw_capabilities *pCap = &ah->caps; 114 115 if (flags & CHANNEL_5GHZ) { 116 *low = pCap->low_5ghz_chan; 117 *high = pCap->high_5ghz_chan; 118 return true; 119 } 120 if ((flags & CHANNEL_2GHZ)) { 121 *low = pCap->low_2ghz_chan; 122 *high = pCap->high_2ghz_chan; 123 return true; 124 } 125 return false; 126} 127 128u16 ath9k_hw_computetxtime(struct ath_hw *ah, 129 u8 phy, int kbps, 130 u32 frameLen, u16 rateix, 131 bool shortPreamble) 132{ 133 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 134 135 if (kbps == 0) 136 return 0; 137 138 switch (phy) { 139 case WLAN_RC_PHY_CCK: 140 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 141 if (shortPreamble) 142 phyTime >>= 1; 143 numBits = frameLen << 3; 144 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 145 break; 146 case WLAN_RC_PHY_OFDM: 147 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 148 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 149 numBits = OFDM_PLCP_BITS + (frameLen << 3); 150 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 151 txTime = OFDM_SIFS_TIME_QUARTER 152 + OFDM_PREAMBLE_TIME_QUARTER 153 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 154 } else if (ah->curchan && 155 IS_CHAN_HALF_RATE(ah->curchan)) { 156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 157 numBits = OFDM_PLCP_BITS + (frameLen << 3); 158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 159 txTime = OFDM_SIFS_TIME_HALF + 160 OFDM_PREAMBLE_TIME_HALF 161 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 162 } else { 163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 164 numBits = OFDM_PLCP_BITS + (frameLen << 3); 165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 166 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 167 + (numSymbols * OFDM_SYMBOL_TIME); 168 } 169 break; 170 default: 171 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 172 "Unknown phy %u (rate ix %u)\n", phy, rateix); 173 txTime = 0; 174 break; 175 } 176 177 return txTime; 178} 179EXPORT_SYMBOL(ath9k_hw_computetxtime); 180 181void ath9k_hw_get_channel_centers(struct ath_hw *ah, 182 struct ath9k_channel *chan, 183 struct chan_centers *centers) 184{ 185 int8_t extoff; 186 187 if (!IS_CHAN_HT40(chan)) { 188 centers->ctl_center = centers->ext_center = 189 centers->synth_center = chan->channel; 190 return; 191 } 192 193 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 194 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 195 centers->synth_center = 196 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 197 extoff = 1; 198 } else { 199 centers->synth_center = 200 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 201 extoff = -1; 202 } 203 204 centers->ctl_center = 205 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 206 /* 25 MHz spacing is supported by hw but not on upper layers */ 207 centers->ext_center = 208 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 209} 210 211/******************/ 212/* Chip Revisions */ 213/******************/ 214 215static void ath9k_hw_read_revisions(struct ath_hw *ah) 216{ 217 u32 val; 218 219 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 220 221 if (val == 0xFF) { 222 val = REG_READ(ah, AR_SREV); 223 ah->hw_version.macVersion = 224 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 225 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 226 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 227 } else { 228 if (!AR_SREV_9100(ah)) 229 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 230 231 ah->hw_version.macRev = val & AR_SREV_REVISION; 232 233 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 234 ah->is_pciexpress = true; 235 } 236} 237 238static int ath9k_hw_get_radiorev(struct ath_hw *ah) 239{ 240 u32 val; 241 int i; 242 243 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 244 245 for (i = 0; i < 8; i++) 246 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 247 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 248 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 249 250 return ath9k_hw_reverse_bits(val, 8); 251} 252 253/************************************/ 254/* HW Attach, Detach, Init Routines */ 255/************************************/ 256 257static void ath9k_hw_disablepcie(struct ath_hw *ah) 258{ 259 if (AR_SREV_9100(ah)) 260 return; 261 262 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 263 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 264 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 265 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 266 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 267 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 268 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 269 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 270 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 271 272 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 273} 274 275static bool ath9k_hw_chip_test(struct ath_hw *ah) 276{ 277 struct ath_common *common = ath9k_hw_common(ah); 278 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 279 u32 regHold[2]; 280 u32 patternData[4] = { 0x55555555, 281 0xaaaaaaaa, 282 0x66666666, 283 0x99999999 }; 284 int i, j; 285 286 for (i = 0; i < 2; i++) { 287 u32 addr = regAddr[i]; 288 u32 wrData, rdData; 289 290 regHold[i] = REG_READ(ah, addr); 291 for (j = 0; j < 0x100; j++) { 292 wrData = (j << 16) | j; 293 REG_WRITE(ah, addr, wrData); 294 rdData = REG_READ(ah, addr); 295 if (rdData != wrData) { 296 ath_print(common, ATH_DBG_FATAL, 297 "address test failed " 298 "addr: 0x%08x - wr:0x%08x != " 299 "rd:0x%08x\n", 300 addr, wrData, rdData); 301 return false; 302 } 303 } 304 for (j = 0; j < 4; j++) { 305 wrData = patternData[j]; 306 REG_WRITE(ah, addr, wrData); 307 rdData = REG_READ(ah, addr); 308 if (wrData != rdData) { 309 ath_print(common, ATH_DBG_FATAL, 310 "address test failed " 311 "addr: 0x%08x - wr:0x%08x != " 312 "rd:0x%08x\n", 313 addr, wrData, rdData); 314 return false; 315 } 316 } 317 REG_WRITE(ah, regAddr[i], regHold[i]); 318 } 319 udelay(100); 320 321 return true; 322} 323 324static void ath9k_hw_init_config(struct ath_hw *ah) 325{ 326 int i; 327 328 ah->config.dma_beacon_response_time = 2; 329 ah->config.sw_beacon_response_time = 10; 330 ah->config.additional_swba_backoff = 0; 331 ah->config.ack_6mb = 0x0; 332 ah->config.cwm_ignore_extcca = 0; 333 ah->config.pcie_powersave_enable = 0; 334 ah->config.pcie_clock_req = 0; 335 ah->config.pcie_waen = 0; 336 ah->config.analog_shiftreg = 1; 337 ah->config.ofdm_trig_low = 200; 338 ah->config.ofdm_trig_high = 500; 339 ah->config.cck_trig_high = 200; 340 ah->config.cck_trig_low = 100; 341 ah->config.enable_ani = 1; 342 343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 344 ah->config.spurchans[i][0] = AR_NO_SPUR; 345 ah->config.spurchans[i][1] = AR_NO_SPUR; 346 } 347 348 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 349 ah->config.ht_enable = 1; 350 else 351 ah->config.ht_enable = 0; 352 353 ah->config.rx_intr_mitigation = true; 354 355 /* 356 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 357 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 358 * This means we use it for all AR5416 devices, and the few 359 * minor PCI AR9280 devices out there. 360 * 361 * Serialization is required because these devices do not handle 362 * well the case of two concurrent reads/writes due to the latency 363 * involved. During one read/write another read/write can be issued 364 * on another CPU while the previous read/write may still be working 365 * on our hardware, if we hit this case the hardware poops in a loop. 366 * We prevent this by serializing reads and writes. 367 * 368 * This issue is not present on PCI-Express devices or pre-AR5416 369 * devices (legacy, 802.11abg). 370 */ 371 if (num_possible_cpus() > 1) 372 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 373} 374EXPORT_SYMBOL(ath9k_hw_init); 375 376static void ath9k_hw_init_defaults(struct ath_hw *ah) 377{ 378 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 379 380 regulatory->country_code = CTRY_DEFAULT; 381 regulatory->power_limit = MAX_RATE_POWER; 382 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 383 384 ah->hw_version.magic = AR5416_MAGIC; 385 ah->hw_version.subvendorid = 0; 386 387 ah->ah_flags = 0; 388 if (ah->hw_version.devid == AR5416_AR9100_DEVID) 389 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 390 if (!AR_SREV_9100(ah)) 391 ah->ah_flags = AH_USE_EEPROM; 392 393 ah->atim_window = 0; 394 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 395 ah->beacon_interval = 100; 396 ah->enable_32kHz_clock = DONT_USE_32KHZ; 397 ah->slottime = (u32) -1; 398 ah->globaltxtimeout = (u32) -1; 399 ah->power_mode = ATH9K_PM_UNDEFINED; 400} 401 402static int ath9k_hw_rf_claim(struct ath_hw *ah) 403{ 404 u32 val; 405 406 REG_WRITE(ah, AR_PHY(0), 0x00000007); 407 408 val = ath9k_hw_get_radiorev(ah); 409 switch (val & AR_RADIO_SREV_MAJOR) { 410 case 0: 411 val = AR_RAD5133_SREV_MAJOR; 412 break; 413 case AR_RAD5133_SREV_MAJOR: 414 case AR_RAD5122_SREV_MAJOR: 415 case AR_RAD2133_SREV_MAJOR: 416 case AR_RAD2122_SREV_MAJOR: 417 break; 418 default: 419 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 420 "Radio Chip Rev 0x%02X not supported\n", 421 val & AR_RADIO_SREV_MAJOR); 422 return -EOPNOTSUPP; 423 } 424 425 ah->hw_version.analog5GhzRev = val; 426 427 return 0; 428} 429 430static int ath9k_hw_init_macaddr(struct ath_hw *ah) 431{ 432 struct ath_common *common = ath9k_hw_common(ah); 433 u32 sum; 434 int i; 435 u16 eeval; 436 437 sum = 0; 438 for (i = 0; i < 3; i++) { 439 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); 440 sum += eeval; 441 common->macaddr[2 * i] = eeval >> 8; 442 common->macaddr[2 * i + 1] = eeval & 0xff; 443 } 444 if (sum == 0 || sum == 0xffff * 3) 445 return -EADDRNOTAVAIL; 446 447 return 0; 448} 449 450static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) 451{ 452 u32 rxgain_type; 453 454 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { 455 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); 456 457 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 458 INIT_INI_ARRAY(&ah->iniModesRxGain, 459 ar9280Modes_backoff_13db_rxgain_9280_2, 460 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); 461 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 462 INIT_INI_ARRAY(&ah->iniModesRxGain, 463 ar9280Modes_backoff_23db_rxgain_9280_2, 464 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); 465 else 466 INIT_INI_ARRAY(&ah->iniModesRxGain, 467 ar9280Modes_original_rxgain_9280_2, 468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 469 } else { 470 INIT_INI_ARRAY(&ah->iniModesRxGain, 471 ar9280Modes_original_rxgain_9280_2, 472 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 473 } 474} 475 476static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) 477{ 478 u32 txgain_type; 479 480 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { 481 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 482 483 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 484 INIT_INI_ARRAY(&ah->iniModesTxGain, 485 ar9280Modes_high_power_tx_gain_9280_2, 486 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); 487 else 488 INIT_INI_ARRAY(&ah->iniModesTxGain, 489 ar9280Modes_original_tx_gain_9280_2, 490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 491 } else { 492 INIT_INI_ARRAY(&ah->iniModesTxGain, 493 ar9280Modes_original_tx_gain_9280_2, 494 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 495 } 496} 497 498static int ath9k_hw_post_init(struct ath_hw *ah) 499{ 500 int ecode; 501 502 if (!AR_SREV_9271(ah)) { 503 if (!ath9k_hw_chip_test(ah)) 504 return -ENODEV; 505 } 506 507 ecode = ath9k_hw_rf_claim(ah); 508 if (ecode != 0) 509 return ecode; 510 511 ecode = ath9k_hw_eeprom_init(ah); 512 if (ecode != 0) 513 return ecode; 514 515 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, 516 "Eeprom VER: %d, REV: %d\n", 517 ah->eep_ops->get_eeprom_ver(ah), 518 ah->eep_ops->get_eeprom_rev(ah)); 519 520 if (!AR_SREV_9280_10_OR_LATER(ah)) { 521 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 522 if (ecode) { 523 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 524 "Failed allocating banks for " 525 "external radio\n"); 526 return ecode; 527 } 528 } 529 530 if (!AR_SREV_9100(ah)) { 531 ath9k_hw_ani_setup(ah); 532 ath9k_hw_ani_init(ah); 533 } 534 535 return 0; 536} 537 538static bool ath9k_hw_devid_supported(u16 devid) 539{ 540 switch (devid) { 541 case AR5416_DEVID_PCI: 542 case AR5416_DEVID_PCIE: 543 case AR5416_AR9100_DEVID: 544 case AR9160_DEVID_PCI: 545 case AR9280_DEVID_PCI: 546 case AR9280_DEVID_PCIE: 547 case AR9285_DEVID_PCIE: 548 case AR5416_DEVID_AR9287_PCI: 549 case AR5416_DEVID_AR9287_PCIE: 550 case AR2427_DEVID_PCIE: 551 return true; 552 default: 553 break; 554 } 555 return false; 556} 557 558static bool ath9k_hw_macversion_supported(u32 macversion) 559{ 560 switch (macversion) { 561 case AR_SREV_VERSION_5416_PCI: 562 case AR_SREV_VERSION_5416_PCIE: 563 case AR_SREV_VERSION_9160: 564 case AR_SREV_VERSION_9100: 565 case AR_SREV_VERSION_9280: 566 case AR_SREV_VERSION_9285: 567 case AR_SREV_VERSION_9287: 568 case AR_SREV_VERSION_9271: 569 return true; 570 default: 571 break; 572 } 573 return false; 574} 575 576static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 577{ 578 if (AR_SREV_9160_10_OR_LATER(ah)) { 579 if (AR_SREV_9280_10_OR_LATER(ah)) { 580 ah->iq_caldata.calData = &iq_cal_single_sample; 581 ah->adcgain_caldata.calData = 582 &adc_gain_cal_single_sample; 583 ah->adcdc_caldata.calData = 584 &adc_dc_cal_single_sample; 585 ah->adcdc_calinitdata.calData = 586 &adc_init_dc_cal; 587 } else { 588 ah->iq_caldata.calData = &iq_cal_multi_sample; 589 ah->adcgain_caldata.calData = 590 &adc_gain_cal_multi_sample; 591 ah->adcdc_caldata.calData = 592 &adc_dc_cal_multi_sample; 593 ah->adcdc_calinitdata.calData = 594 &adc_init_dc_cal; 595 } 596 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 597 } 598} 599 600static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 601{ 602 if (AR_SREV_9271(ah)) { 603 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, 604 ARRAY_SIZE(ar9271Modes_9271), 6); 605 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, 606 ARRAY_SIZE(ar9271Common_9271), 2); 607 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, 608 ar9271Common_normal_cck_fir_coeff_9271, 609 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2); 610 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271, 611 ar9271Common_japan_2484_cck_fir_coeff_9271, 612 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); 613 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, 614 ar9271Modes_9271_1_0_only, 615 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); 616 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, 617 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6); 618 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271, 619 ar9271Modes_high_power_tx_gain_9271, 620 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6); 621 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, 622 ar9271Modes_normal_power_tx_gain_9271, 623 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6); 624 return; 625 } 626 627 if (AR_SREV_9287_11_OR_LATER(ah)) { 628 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, 629 ARRAY_SIZE(ar9287Modes_9287_1_1), 6); 630 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, 631 ARRAY_SIZE(ar9287Common_9287_1_1), 2); 632 if (ah->config.pcie_clock_req) 633 INIT_INI_ARRAY(&ah->iniPcieSerdes, 634 ar9287PciePhy_clkreq_off_L1_9287_1_1, 635 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2); 636 else 637 INIT_INI_ARRAY(&ah->iniPcieSerdes, 638 ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 639 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), 640 2); 641 } else if (AR_SREV_9287_10_OR_LATER(ah)) { 642 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0, 643 ARRAY_SIZE(ar9287Modes_9287_1_0), 6); 644 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0, 645 ARRAY_SIZE(ar9287Common_9287_1_0), 2); 646 647 if (ah->config.pcie_clock_req) 648 INIT_INI_ARRAY(&ah->iniPcieSerdes, 649 ar9287PciePhy_clkreq_off_L1_9287_1_0, 650 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2); 651 else 652 INIT_INI_ARRAY(&ah->iniPcieSerdes, 653 ar9287PciePhy_clkreq_always_on_L1_9287_1_0, 654 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0), 655 2); 656 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 657 658 659 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, 660 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 661 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, 662 ARRAY_SIZE(ar9285Common_9285_1_2), 2); 663 664 if (ah->config.pcie_clock_req) { 665 INIT_INI_ARRAY(&ah->iniPcieSerdes, 666 ar9285PciePhy_clkreq_off_L1_9285_1_2, 667 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); 668 } else { 669 INIT_INI_ARRAY(&ah->iniPcieSerdes, 670 ar9285PciePhy_clkreq_always_on_L1_9285_1_2, 671 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 672 2); 673 } 674 } else if (AR_SREV_9285_10_OR_LATER(ah)) { 675 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, 676 ARRAY_SIZE(ar9285Modes_9285), 6); 677 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, 678 ARRAY_SIZE(ar9285Common_9285), 2); 679 680 if (ah->config.pcie_clock_req) { 681 INIT_INI_ARRAY(&ah->iniPcieSerdes, 682 ar9285PciePhy_clkreq_off_L1_9285, 683 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); 684 } else { 685 INIT_INI_ARRAY(&ah->iniPcieSerdes, 686 ar9285PciePhy_clkreq_always_on_L1_9285, 687 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); 688 } 689 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 690 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, 691 ARRAY_SIZE(ar9280Modes_9280_2), 6); 692 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, 693 ARRAY_SIZE(ar9280Common_9280_2), 2); 694 695 if (ah->config.pcie_clock_req) { 696 INIT_INI_ARRAY(&ah->iniPcieSerdes, 697 ar9280PciePhy_clkreq_off_L1_9280, 698 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); 699 } else { 700 INIT_INI_ARRAY(&ah->iniPcieSerdes, 701 ar9280PciePhy_clkreq_always_on_L1_9280, 702 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); 703 } 704 INIT_INI_ARRAY(&ah->iniModesAdditional, 705 ar9280Modes_fast_clock_9280_2, 706 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 707 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 708 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, 709 ARRAY_SIZE(ar9280Modes_9280), 6); 710 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, 711 ARRAY_SIZE(ar9280Common_9280), 2); 712 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 713 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, 714 ARRAY_SIZE(ar5416Modes_9160), 6); 715 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, 716 ARRAY_SIZE(ar5416Common_9160), 2); 717 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, 718 ARRAY_SIZE(ar5416Bank0_9160), 2); 719 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, 720 ARRAY_SIZE(ar5416BB_RfGain_9160), 3); 721 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, 722 ARRAY_SIZE(ar5416Bank1_9160), 2); 723 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, 724 ARRAY_SIZE(ar5416Bank2_9160), 2); 725 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, 726 ARRAY_SIZE(ar5416Bank3_9160), 3); 727 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, 728 ARRAY_SIZE(ar5416Bank6_9160), 3); 729 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, 730 ARRAY_SIZE(ar5416Bank6TPC_9160), 3); 731 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, 732 ARRAY_SIZE(ar5416Bank7_9160), 2); 733 if (AR_SREV_9160_11(ah)) { 734 INIT_INI_ARRAY(&ah->iniAddac, 735 ar5416Addac_91601_1, 736 ARRAY_SIZE(ar5416Addac_91601_1), 2); 737 } else { 738 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, 739 ARRAY_SIZE(ar5416Addac_9160), 2); 740 } 741 } else if (AR_SREV_9100_OR_LATER(ah)) { 742 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, 743 ARRAY_SIZE(ar5416Modes_9100), 6); 744 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, 745 ARRAY_SIZE(ar5416Common_9100), 2); 746 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, 747 ARRAY_SIZE(ar5416Bank0_9100), 2); 748 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, 749 ARRAY_SIZE(ar5416BB_RfGain_9100), 3); 750 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, 751 ARRAY_SIZE(ar5416Bank1_9100), 2); 752 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, 753 ARRAY_SIZE(ar5416Bank2_9100), 2); 754 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, 755 ARRAY_SIZE(ar5416Bank3_9100), 3); 756 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, 757 ARRAY_SIZE(ar5416Bank6_9100), 3); 758 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, 759 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 760 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, 761 ARRAY_SIZE(ar5416Bank7_9100), 2); 762 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, 763 ARRAY_SIZE(ar5416Addac_9100), 2); 764 } else { 765 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, 766 ARRAY_SIZE(ar5416Modes), 6); 767 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, 768 ARRAY_SIZE(ar5416Common), 2); 769 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, 770 ARRAY_SIZE(ar5416Bank0), 2); 771 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, 772 ARRAY_SIZE(ar5416BB_RfGain), 3); 773 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, 774 ARRAY_SIZE(ar5416Bank1), 2); 775 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, 776 ARRAY_SIZE(ar5416Bank2), 2); 777 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, 778 ARRAY_SIZE(ar5416Bank3), 3); 779 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, 780 ARRAY_SIZE(ar5416Bank6), 3); 781 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, 782 ARRAY_SIZE(ar5416Bank6TPC), 3); 783 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, 784 ARRAY_SIZE(ar5416Bank7), 2); 785 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, 786 ARRAY_SIZE(ar5416Addac), 2); 787 } 788} 789 790static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 791{ 792 if (AR_SREV_9287_11_OR_LATER(ah)) 793 INIT_INI_ARRAY(&ah->iniModesRxGain, 794 ar9287Modes_rx_gain_9287_1_1, 795 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); 796 else if (AR_SREV_9287_10(ah)) 797 INIT_INI_ARRAY(&ah->iniModesRxGain, 798 ar9287Modes_rx_gain_9287_1_0, 799 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6); 800 else if (AR_SREV_9280_20(ah)) 801 ath9k_hw_init_rxgain_ini(ah); 802 803 if (AR_SREV_9287_11_OR_LATER(ah)) { 804 INIT_INI_ARRAY(&ah->iniModesTxGain, 805 ar9287Modes_tx_gain_9287_1_1, 806 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); 807 } else if (AR_SREV_9287_10(ah)) { 808 INIT_INI_ARRAY(&ah->iniModesTxGain, 809 ar9287Modes_tx_gain_9287_1_0, 810 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6); 811 } else if (AR_SREV_9280_20(ah)) { 812 ath9k_hw_init_txgain_ini(ah); 813 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 814 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 815 816 /* txgain table */ 817 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { 818 if (AR_SREV_9285E_20(ah)) { 819 INIT_INI_ARRAY(&ah->iniModesTxGain, 820 ar9285Modes_XE2_0_high_power, 821 ARRAY_SIZE( 822 ar9285Modes_XE2_0_high_power), 6); 823 } else { 824 INIT_INI_ARRAY(&ah->iniModesTxGain, 825 ar9285Modes_high_power_tx_gain_9285_1_2, 826 ARRAY_SIZE( 827 ar9285Modes_high_power_tx_gain_9285_1_2), 6); 828 } 829 } else { 830 if (AR_SREV_9285E_20(ah)) { 831 INIT_INI_ARRAY(&ah->iniModesTxGain, 832 ar9285Modes_XE2_0_normal_power, 833 ARRAY_SIZE( 834 ar9285Modes_XE2_0_normal_power), 6); 835 } else { 836 INIT_INI_ARRAY(&ah->iniModesTxGain, 837 ar9285Modes_original_tx_gain_9285_1_2, 838 ARRAY_SIZE( 839 ar9285Modes_original_tx_gain_9285_1_2), 6); 840 } 841 } 842 } 843} 844 845static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah) 846{ 847 u32 i, j; 848 849 if (ah->hw_version.devid == AR9280_DEVID_PCI) { 850 851 /* EEPROM Fixup */ 852 for (i = 0; i < ah->iniModes.ia_rows; i++) { 853 u32 reg = INI_RA(&ah->iniModes, i, 0); 854 855 for (j = 1; j < ah->iniModes.ia_columns; j++) { 856 u32 val = INI_RA(&ah->iniModes, i, j); 857 858 INI_RA(&ah->iniModes, i, j) = 859 ath9k_hw_ini_fixup(ah, 860 &ah->eeprom.def, 861 reg, val); 862 } 863 } 864 } 865} 866 867int ath9k_hw_init(struct ath_hw *ah) 868{ 869 struct ath_common *common = ath9k_hw_common(ah); 870 int r = 0; 871 872 if (common->bus_ops->ath_bus_type != ATH_USB) { 873 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) { 874 ath_print(common, ATH_DBG_FATAL, 875 "Unsupported device ID: 0x%0x\n", 876 ah->hw_version.devid); 877 return -EOPNOTSUPP; 878 } 879 } 880 881 ath9k_hw_init_defaults(ah); 882 ath9k_hw_init_config(ah); 883 884 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 885 ath_print(common, ATH_DBG_FATAL, 886 "Couldn't reset chip\n"); 887 return -EIO; 888 } 889 890 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 891 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 892 return -EIO; 893 } 894 895 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 896 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 897 (AR_SREV_9280(ah) && !ah->is_pciexpress)) { 898 ah->config.serialize_regmode = 899 SER_REG_MODE_ON; 900 } else { 901 ah->config.serialize_regmode = 902 SER_REG_MODE_OFF; 903 } 904 } 905 906 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 907 ah->config.serialize_regmode); 908 909 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 910 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 911 else 912 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 913 914 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { 915 ath_print(common, ATH_DBG_FATAL, 916 "Mac Chip Rev 0x%02x.%x is not supported by " 917 "this driver\n", ah->hw_version.macVersion, 918 ah->hw_version.macRev); 919 return -EOPNOTSUPP; 920 } 921 922 if (AR_SREV_9100(ah)) { 923 ah->iq_caldata.calData = &iq_cal_multi_sample; 924 ah->supp_cals = IQ_MISMATCH_CAL; 925 ah->is_pciexpress = false; 926 } 927 928 if (AR_SREV_9271(ah)) 929 ah->is_pciexpress = false; 930 931 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 932 933 ath9k_hw_init_cal_settings(ah); 934 935 ah->ani_function = ATH9K_ANI_ALL; 936 if (AR_SREV_9280_10_OR_LATER(ah)) { 937 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 938 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel; 939 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate; 940 } else { 941 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel; 942 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate; 943 } 944 945 ath9k_hw_init_mode_regs(ah); 946 947 if (ah->is_pciexpress) 948 ath9k_hw_configpcipowersave(ah, 0, 0); 949 else 950 ath9k_hw_disablepcie(ah); 951 952 /* Support for Japan ch.14 (2484) spread */ 953 if (AR_SREV_9287_11_OR_LATER(ah)) { 954 INIT_INI_ARRAY(&ah->iniCckfirNormal, 955 ar9287Common_normal_cck_fir_coeff_92871_1, 956 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2); 957 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 958 ar9287Common_japan_2484_cck_fir_coeff_92871_1, 959 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2); 960 } 961 962 r = ath9k_hw_post_init(ah); 963 if (r) 964 return r; 965 966 ath9k_hw_init_mode_gain_regs(ah); 967 r = ath9k_hw_fill_cap_info(ah); 968 if (r) 969 return r; 970 971 ath9k_hw_init_eeprom_fix(ah); 972 973 r = ath9k_hw_init_macaddr(ah); 974 if (r) { 975 ath_print(common, ATH_DBG_FATAL, 976 "Failed to initialize MAC address\n"); 977 return r; 978 } 979 980 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 981 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 982 else 983 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 984 985 ath9k_init_nfcal_hist_buffer(ah); 986 987 common->state = ATH_HW_INITIALIZED; 988 989 return 0; 990} 991 992static void ath9k_hw_init_bb(struct ath_hw *ah, 993 struct ath9k_channel *chan) 994{ 995 u32 synthDelay; 996 997 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 998 if (IS_CHAN_B(chan)) 999 synthDelay = (4 * synthDelay) / 22; 1000 else 1001 synthDelay /= 10; 1002 1003 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 1004 1005 udelay(synthDelay + BASE_ACTIVATE_DELAY); 1006} 1007 1008static void ath9k_hw_init_qos(struct ath_hw *ah) 1009{ 1010 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 1011 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 1012 1013 REG_WRITE(ah, AR_QOS_NO_ACK, 1014 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 1015 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 1016 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 1017 1018 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 1019 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 1020 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 1021 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 1022 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 1023} 1024 1025static void ath9k_hw_init_pll(struct ath_hw *ah, 1026 struct ath9k_channel *chan) 1027{ 1028 u32 pll; 1029 1030 if (AR_SREV_9100(ah)) { 1031 if (chan && IS_CHAN_5GHZ(chan)) 1032 pll = 0x1450; 1033 else 1034 pll = 0x1458; 1035 } else { 1036 if (AR_SREV_9280_10_OR_LATER(ah)) { 1037 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 1038 1039 if (chan && IS_CHAN_HALF_RATE(chan)) 1040 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 1041 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1042 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 1043 1044 if (chan && IS_CHAN_5GHZ(chan)) { 1045 pll |= SM(0x28, AR_RTC_9160_PLL_DIV); 1046 1047 1048 if (AR_SREV_9280_20(ah)) { 1049 if (((chan->channel % 20) == 0) 1050 || ((chan->channel % 10) == 0)) 1051 pll = 0x2850; 1052 else 1053 pll = 0x142c; 1054 } 1055 } else { 1056 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); 1057 } 1058 1059 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1060 1061 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 1062 1063 if (chan && IS_CHAN_HALF_RATE(chan)) 1064 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 1065 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1066 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 1067 1068 if (chan && IS_CHAN_5GHZ(chan)) 1069 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 1070 else 1071 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 1072 } else { 1073 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 1074 1075 if (chan && IS_CHAN_HALF_RATE(chan)) 1076 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1077 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1078 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1079 1080 if (chan && IS_CHAN_5GHZ(chan)) 1081 pll |= SM(0xa, AR_RTC_PLL_DIV); 1082 else 1083 pll |= SM(0xb, AR_RTC_PLL_DIV); 1084 } 1085 } 1086 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1087 1088 /* Switch the core clock for ar9271 to 117Mhz */ 1089 if (AR_SREV_9271(ah)) { 1090 udelay(500); 1091 REG_WRITE(ah, 0x50040, 0x304); 1092 } 1093 1094 udelay(RTC_PLL_SETTLE_DELAY); 1095 1096 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 1097} 1098 1099static void ath9k_hw_init_chain_masks(struct ath_hw *ah) 1100{ 1101 int rx_chainmask, tx_chainmask; 1102 1103 rx_chainmask = ah->rxchainmask; 1104 tx_chainmask = ah->txchainmask; 1105 1106 switch (rx_chainmask) { 1107 case 0x5: 1108 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 1109 AR_PHY_SWAP_ALT_CHAIN); 1110 case 0x3: 1111 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 1112 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 1113 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 1114 break; 1115 } 1116 case 0x1: 1117 case 0x2: 1118 case 0x7: 1119 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1120 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1121 break; 1122 default: 1123 break; 1124 } 1125 1126 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 1127 if (tx_chainmask == 0x5) { 1128 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 1129 AR_PHY_SWAP_ALT_CHAIN); 1130 } 1131 if (AR_SREV_9100(ah)) 1132 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 1133 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1134} 1135 1136static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 1137 enum nl80211_iftype opmode) 1138{ 1139 u32 imr_reg = AR_IMR_TXERR | 1140 AR_IMR_TXURN | 1141 AR_IMR_RXERR | 1142 AR_IMR_RXORN | 1143 AR_IMR_BCNMISC; 1144 1145 if (ah->config.rx_intr_mitigation) 1146 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 1147 else 1148 imr_reg |= AR_IMR_RXOK; 1149 1150 imr_reg |= AR_IMR_TXOK; 1151 1152 if (opmode == NL80211_IFTYPE_AP) 1153 imr_reg |= AR_IMR_MIB; 1154 1155 REG_WRITE(ah, AR_IMR, imr_reg); 1156 ah->imrs2_reg |= AR_IMR_S2_GTT; 1157 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 1158 1159 if (!AR_SREV_9100(ah)) { 1160 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 1161 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 1162 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 1163 } 1164} 1165 1166static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 1167{ 1168 u32 val = ath9k_hw_mac_to_clks(ah, us); 1169 val = min(val, (u32) 0xFFFF); 1170 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1171} 1172 1173static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1174{ 1175 u32 val = ath9k_hw_mac_to_clks(ah, us); 1176 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1177 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1178} 1179 1180static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1181{ 1182 u32 val = ath9k_hw_mac_to_clks(ah, us); 1183 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1184 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1185} 1186 1187static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1188{ 1189 if (tu > 0xFFFF) { 1190 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 1191 "bad global tx timeout %u\n", tu); 1192 ah->globaltxtimeout = (u32) -1; 1193 return false; 1194 } else { 1195 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1196 ah->globaltxtimeout = tu; 1197 return true; 1198 } 1199} 1200 1201void ath9k_hw_init_global_settings(struct ath_hw *ah) 1202{ 1203 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 1204 int acktimeout; 1205 int slottime; 1206 int sifstime; 1207 1208 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 1209 ah->misc_mode); 1210 1211 if (ah->misc_mode != 0) 1212 REG_WRITE(ah, AR_PCU_MISC, 1213 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 1214 1215 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 1216 sifstime = 16; 1217 else 1218 sifstime = 10; 1219 1220 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1221 slottime = ah->slottime + 3 * ah->coverage_class; 1222 acktimeout = slottime + sifstime; 1223 1224 /* 1225 * Workaround for early ACK timeouts, add an offset to match the 1226 * initval's 64us ack timeout value. 1227 * This was initially only meant to work around an issue with delayed 1228 * BA frames in some implementations, but it has been found to fix ACK 1229 * timeout issues in other cases as well. 1230 */ 1231 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 1232 acktimeout += 64 - sifstime - ah->slottime; 1233 1234 ath9k_hw_setslottime(ah, slottime); 1235 ath9k_hw_set_ack_timeout(ah, acktimeout); 1236 ath9k_hw_set_cts_timeout(ah, acktimeout); 1237 if (ah->globaltxtimeout != (u32) -1) 1238 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1239} 1240EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1241 1242void ath9k_hw_deinit(struct ath_hw *ah) 1243{ 1244 struct ath_common *common = ath9k_hw_common(ah); 1245 1246 if (common->state < ATH_HW_INITIALIZED) 1247 goto free_hw; 1248 1249 if (!AR_SREV_9100(ah)) 1250 ath9k_hw_ani_disable(ah); 1251 1252 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1253 1254free_hw: 1255 if (!AR_SREV_9280_10_OR_LATER(ah)) 1256 ath9k_hw_rf_free_ext_banks(ah); 1257} 1258EXPORT_SYMBOL(ath9k_hw_deinit); 1259 1260/*******/ 1261/* INI */ 1262/*******/ 1263 1264static void ath9k_hw_override_ini(struct ath_hw *ah, 1265 struct ath9k_channel *chan) 1266{ 1267 u32 val; 1268 1269 /* 1270 * Set the RX_ABORT and RX_DIS and clear if off only after 1271 * RXE is set for MAC. This prevents frames with corrupted 1272 * descriptor status. 1273 */ 1274 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 1275 1276 if (AR_SREV_9280_10_OR_LATER(ah)) { 1277 val = REG_READ(ah, AR_PCU_MISC_MODE2); 1278 1279 if (!AR_SREV_9271(ah)) 1280 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 1281 1282 if (AR_SREV_9287_10_OR_LATER(ah)) 1283 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 1284 1285 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 1286 } 1287 1288 if (!AR_SREV_5416_20_OR_LATER(ah) || 1289 AR_SREV_9280_10_OR_LATER(ah)) 1290 return; 1291 /* 1292 * Disable BB clock gating 1293 * Necessary to avoid issues on AR5416 2.0 1294 */ 1295 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 1296 1297 /* 1298 * Disable RIFS search on some chips to avoid baseband 1299 * hang issues. 1300 */ 1301 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 1302 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 1303 val &= ~AR_PHY_RIFS_INIT_DELAY; 1304 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 1305 } 1306} 1307 1308static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah, 1309 struct ar5416_eeprom_def *pEepData, 1310 u32 reg, u32 value) 1311{ 1312 struct base_eep_header *pBase = &(pEepData->baseEepHeader); 1313 struct ath_common *common = ath9k_hw_common(ah); 1314 1315 switch (ah->hw_version.devid) { 1316 case AR9280_DEVID_PCI: 1317 if (reg == 0x7894) { 1318 ath_print(common, ATH_DBG_EEPROM, 1319 "ini VAL: %x EEPROM: %x\n", value, 1320 (pBase->version & 0xff)); 1321 1322 if ((pBase->version & 0xff) > 0x0a) { 1323 ath_print(common, ATH_DBG_EEPROM, 1324 "PWDCLKIND: %d\n", 1325 pBase->pwdclkind); 1326 value &= ~AR_AN_TOP2_PWDCLKIND; 1327 value |= AR_AN_TOP2_PWDCLKIND & 1328 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); 1329 } else { 1330 ath_print(common, ATH_DBG_EEPROM, 1331 "PWDCLKIND Earlier Rev\n"); 1332 } 1333 1334 ath_print(common, ATH_DBG_EEPROM, 1335 "final ini VAL: %x\n", value); 1336 } 1337 break; 1338 } 1339 1340 return value; 1341} 1342 1343static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 1344 struct ar5416_eeprom_def *pEepData, 1345 u32 reg, u32 value) 1346{ 1347 if (ah->eep_map == EEP_MAP_4KBITS) 1348 return value; 1349 else 1350 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); 1351} 1352 1353static void ath9k_olc_init(struct ath_hw *ah) 1354{ 1355 u32 i; 1356 1357 if (OLC_FOR_AR9287_10_LATER) { 1358 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, 1359 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); 1360 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0, 1361 AR9287_AN_TXPC0_TXPCMODE, 1362 AR9287_AN_TXPC0_TXPCMODE_S, 1363 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); 1364 udelay(100); 1365 } else { 1366 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) 1367 ah->originalGain[i] = 1368 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), 1369 AR_PHY_TX_GAIN); 1370 ah->PDADCdelta = 0; 1371 } 1372} 1373 1374static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, 1375 struct ath9k_channel *chan) 1376{ 1377 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1378 1379 if (IS_CHAN_B(chan)) 1380 ctl |= CTL_11B; 1381 else if (IS_CHAN_G(chan)) 1382 ctl |= CTL_11G; 1383 else 1384 ctl |= CTL_11A; 1385 1386 return ctl; 1387} 1388 1389static int ath9k_hw_process_ini(struct ath_hw *ah, 1390 struct ath9k_channel *chan) 1391{ 1392 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1393 int i, regWrites = 0; 1394 struct ieee80211_channel *channel = chan->chan; 1395 u32 modesIndex, freqIndex; 1396 1397 switch (chan->chanmode) { 1398 case CHANNEL_A: 1399 case CHANNEL_A_HT20: 1400 modesIndex = 1; 1401 freqIndex = 1; 1402 break; 1403 case CHANNEL_A_HT40PLUS: 1404 case CHANNEL_A_HT40MINUS: 1405 modesIndex = 2; 1406 freqIndex = 1; 1407 break; 1408 case CHANNEL_G: 1409 case CHANNEL_G_HT20: 1410 case CHANNEL_B: 1411 modesIndex = 4; 1412 freqIndex = 2; 1413 break; 1414 case CHANNEL_G_HT40PLUS: 1415 case CHANNEL_G_HT40MINUS: 1416 modesIndex = 3; 1417 freqIndex = 2; 1418 break; 1419 1420 default: 1421 return -EINVAL; 1422 } 1423 1424 /* Set correct baseband to analog shift setting to access analog chips */ 1425 REG_WRITE(ah, AR_PHY(0), 0x00000007); 1426 1427 /* Write ADDAC shifts */ 1428 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 1429 ah->eep_ops->set_addac(ah, chan); 1430 1431 if (AR_SREV_5416_22_OR_LATER(ah)) { 1432 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 1433 } else { 1434 struct ar5416IniArray temp; 1435 u32 addacSize = 1436 sizeof(u32) * ah->iniAddac.ia_rows * 1437 ah->iniAddac.ia_columns; 1438 1439 /* For AR5416 2.0/2.1 */ 1440 memcpy(ah->addac5416_21, 1441 ah->iniAddac.ia_array, addacSize); 1442 1443 /* override CLKDRV value at [row, column] = [31, 1] */ 1444 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; 1445 1446 temp.ia_array = ah->addac5416_21; 1447 temp.ia_columns = ah->iniAddac.ia_columns; 1448 temp.ia_rows = ah->iniAddac.ia_rows; 1449 REG_WRITE_ARRAY(&temp, 1, regWrites); 1450 } 1451 1452 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 1453 1454 for (i = 0; i < ah->iniModes.ia_rows; i++) { 1455 u32 reg = INI_RA(&ah->iniModes, i, 0); 1456 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 1457 1458 REG_WRITE(ah, reg, val); 1459 1460 if (reg >= 0x7800 && reg < 0x78a0 1461 && ah->config.analog_shiftreg) { 1462 udelay(100); 1463 } 1464 1465 DO_DELAY(regWrites); 1466 } 1467 1468 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah)) 1469 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 1470 1471 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 1472 AR_SREV_9287_10_OR_LATER(ah)) 1473 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 1474 1475 if (AR_SREV_9271_10(ah)) 1476 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only, 1477 modesIndex, regWrites); 1478 1479 /* Write common array parameters */ 1480 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 1481 u32 reg = INI_RA(&ah->iniCommon, i, 0); 1482 u32 val = INI_RA(&ah->iniCommon, i, 1); 1483 1484 REG_WRITE(ah, reg, val); 1485 1486 if (reg >= 0x7800 && reg < 0x78a0 1487 && ah->config.analog_shiftreg) { 1488 udelay(100); 1489 } 1490 1491 DO_DELAY(regWrites); 1492 } 1493 1494 if (AR_SREV_9271(ah)) { 1495 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1) 1496 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271, 1497 modesIndex, regWrites); 1498 else 1499 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, 1500 modesIndex, regWrites); 1501 } 1502 1503 ath9k_hw_write_regs(ah, freqIndex, regWrites); 1504 1505 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1506 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, 1507 regWrites); 1508 } 1509 1510 ath9k_hw_override_ini(ah, chan); 1511 ath9k_hw_set_regs(ah, chan); 1512 ath9k_hw_init_chain_masks(ah); 1513 1514 if (OLC_FOR_AR9280_20_LATER) 1515 ath9k_olc_init(ah); 1516 1517 /* Set TX power */ 1518 ah->eep_ops->set_txpower(ah, chan, 1519 ath9k_regd_get_ctl(regulatory, chan), 1520 channel->max_antenna_gain * 2, 1521 channel->max_power * 2, 1522 min((u32) MAX_RATE_POWER, 1523 (u32) regulatory->power_limit)); 1524 1525 /* Write analog registers */ 1526 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1527 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1528 "ar5416SetRfRegs failed\n"); 1529 return -EIO; 1530 } 1531 1532 return 0; 1533} 1534 1535/****************************************/ 1536/* Reset and Channel Switching Routines */ 1537/****************************************/ 1538 1539static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 1540{ 1541 u32 rfMode = 0; 1542 1543 if (chan == NULL) 1544 return; 1545 1546 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 1547 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1548 1549 if (!AR_SREV_9280_10_OR_LATER(ah)) 1550 rfMode |= (IS_CHAN_5GHZ(chan)) ? 1551 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 1552 1553 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) 1554 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 1555 1556 REG_WRITE(ah, AR_PHY_MODE, rfMode); 1557} 1558 1559static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah) 1560{ 1561 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1562} 1563 1564static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1565{ 1566 u32 regval; 1567 1568 /* 1569 * set AHB_MODE not to do cacheline prefetches 1570 */ 1571 regval = REG_READ(ah, AR_AHB_MODE); 1572 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 1573 1574 /* 1575 * let mac dma reads be in 128 byte chunks 1576 */ 1577 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 1578 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 1579 1580 /* 1581 * Restore TX Trigger Level to its pre-reset value. 1582 * The initial value depends on whether aggregation is enabled, and is 1583 * adjusted whenever underruns are detected. 1584 */ 1585 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1586 1587 /* 1588 * let mac dma writes be in 128 byte chunks 1589 */ 1590 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 1591 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 1592 1593 /* 1594 * Setup receive FIFO threshold to hold off TX activities 1595 */ 1596 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1597 1598 /* 1599 * reduce the number of usable entries in PCU TXBUF to avoid 1600 * wrap around issues. 1601 */ 1602 if (AR_SREV_9285(ah)) { 1603 /* For AR9285 the number of Fifos are reduced to half. 1604 * So set the usable tx buf size also to half to 1605 * avoid data/delimiter underruns 1606 */ 1607 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1608 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1609 } else if (!AR_SREV_9271(ah)) { 1610 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1611 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1612 } 1613} 1614 1615static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1616{ 1617 u32 val; 1618 1619 val = REG_READ(ah, AR_STA_ID1); 1620 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 1621 switch (opmode) { 1622 case NL80211_IFTYPE_AP: 1623 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 1624 | AR_STA_ID1_KSRCH_MODE); 1625 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1626 break; 1627 case NL80211_IFTYPE_ADHOC: 1628 case NL80211_IFTYPE_MESH_POINT: 1629 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 1630 | AR_STA_ID1_KSRCH_MODE); 1631 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1632 break; 1633 case NL80211_IFTYPE_STATION: 1634 case NL80211_IFTYPE_MONITOR: 1635 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 1636 break; 1637 } 1638} 1639 1640static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, 1641 u32 coef_scaled, 1642 u32 *coef_mantissa, 1643 u32 *coef_exponent) 1644{ 1645 u32 coef_exp, coef_man; 1646 1647 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1648 if ((coef_scaled >> coef_exp) & 0x1) 1649 break; 1650 1651 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1652 1653 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1654 1655 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1656 *coef_exponent = coef_exp - 16; 1657} 1658 1659static void ath9k_hw_set_delta_slope(struct ath_hw *ah, 1660 struct ath9k_channel *chan) 1661{ 1662 u32 coef_scaled, ds_coef_exp, ds_coef_man; 1663 u32 clockMhzScaled = 0x64000000; 1664 struct chan_centers centers; 1665 1666 if (IS_CHAN_HALF_RATE(chan)) 1667 clockMhzScaled = clockMhzScaled >> 1; 1668 else if (IS_CHAN_QUARTER_RATE(chan)) 1669 clockMhzScaled = clockMhzScaled >> 2; 1670 1671 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 1672 coef_scaled = clockMhzScaled / centers.synth_center; 1673 1674 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1675 &ds_coef_exp); 1676 1677 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1678 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 1679 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1680 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 1681 1682 coef_scaled = (9 * coef_scaled) / 10; 1683 1684 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1685 &ds_coef_exp); 1686 1687 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 1688 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 1689 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 1690 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 1691} 1692 1693static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1694{ 1695 u32 rst_flags; 1696 u32 tmpReg; 1697 1698 if (AR_SREV_9100(ah)) { 1699 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 1700 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 1701 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 1702 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 1703 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1704 } 1705 1706 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1707 AR_RTC_FORCE_WAKE_ON_INT); 1708 1709 if (AR_SREV_9100(ah)) { 1710 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1711 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1712 } else { 1713 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1714 if (tmpReg & 1715 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1716 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1717 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1718 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1719 } else { 1720 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1721 } 1722 1723 rst_flags = AR_RTC_RC_MAC_WARM; 1724 if (type == ATH9K_RESET_COLD) 1725 rst_flags |= AR_RTC_RC_MAC_COLD; 1726 } 1727 1728 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1729 udelay(50); 1730 1731 REG_WRITE(ah, AR_RTC_RC, 0); 1732 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1733 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1734 "RTC stuck in MAC reset\n"); 1735 return false; 1736 } 1737 1738 if (!AR_SREV_9100(ah)) 1739 REG_WRITE(ah, AR_RC, 0); 1740 1741 if (AR_SREV_9100(ah)) 1742 udelay(50); 1743 1744 return true; 1745} 1746 1747static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1748{ 1749 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1750 AR_RTC_FORCE_WAKE_ON_INT); 1751 1752 if (!AR_SREV_9100(ah)) 1753 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1754 1755 REG_WRITE(ah, AR_RTC_RESET, 0); 1756 udelay(2); 1757 1758 if (!AR_SREV_9100(ah)) 1759 REG_WRITE(ah, AR_RC, 0); 1760 1761 REG_WRITE(ah, AR_RTC_RESET, 1); 1762 1763 if (!ath9k_hw_wait(ah, 1764 AR_RTC_STATUS, 1765 AR_RTC_STATUS_M, 1766 AR_RTC_STATUS_ON, 1767 AH_WAIT_TIMEOUT)) { 1768 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1769 "RTC not waking up\n"); 1770 return false; 1771 } 1772 1773 ath9k_hw_read_revisions(ah); 1774 1775 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1776} 1777 1778static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1779{ 1780 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1781 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1782 1783 switch (type) { 1784 case ATH9K_RESET_POWER_ON: 1785 return ath9k_hw_set_reset_power_on(ah); 1786 case ATH9K_RESET_WARM: 1787 case ATH9K_RESET_COLD: 1788 return ath9k_hw_set_reset(ah, type); 1789 default: 1790 return false; 1791 } 1792} 1793 1794static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan) 1795{ 1796 u32 phymode; 1797 u32 enableDacFifo = 0; 1798 1799 if (AR_SREV_9285_10_OR_LATER(ah)) 1800 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 1801 AR_PHY_FC_ENABLE_DAC_FIFO); 1802 1803 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 1804 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 1805 1806 if (IS_CHAN_HT40(chan)) { 1807 phymode |= AR_PHY_FC_DYN2040_EN; 1808 1809 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 1810 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1811 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1812 1813 } 1814 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1815 1816 ath9k_hw_set11nmac2040(ah); 1817 1818 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 1819 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 1820} 1821 1822static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1823 struct ath9k_channel *chan) 1824{ 1825 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1826 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1827 return false; 1828 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1829 return false; 1830 1831 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1832 return false; 1833 1834 ah->chip_fullsleep = false; 1835 ath9k_hw_init_pll(ah, chan); 1836 ath9k_hw_set_rfmode(ah, chan); 1837 1838 return true; 1839} 1840 1841static bool ath9k_hw_channel_change(struct ath_hw *ah, 1842 struct ath9k_channel *chan) 1843{ 1844 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1845 struct ath_common *common = ath9k_hw_common(ah); 1846 struct ieee80211_channel *channel = chan->chan; 1847 u32 synthDelay, qnum; 1848 int r; 1849 1850 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1851 if (ath9k_hw_numtxpending(ah, qnum)) { 1852 ath_print(common, ATH_DBG_QUEUE, 1853 "Transmit frames pending on " 1854 "queue %d\n", qnum); 1855 return false; 1856 } 1857 } 1858 1859 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1860 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1861 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { 1862 ath_print(common, ATH_DBG_FATAL, 1863 "Could not kill baseband RX\n"); 1864 return false; 1865 } 1866 1867 ath9k_hw_set_regs(ah, chan); 1868 1869 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1870 if (r) { 1871 ath_print(common, ATH_DBG_FATAL, 1872 "Failed to set channel\n"); 1873 return false; 1874 } 1875 1876 ah->eep_ops->set_txpower(ah, chan, 1877 ath9k_regd_get_ctl(regulatory, chan), 1878 channel->max_antenna_gain * 2, 1879 channel->max_power * 2, 1880 min((u32) MAX_RATE_POWER, 1881 (u32) regulatory->power_limit)); 1882 1883 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1884 if (IS_CHAN_B(chan)) 1885 synthDelay = (4 * synthDelay) / 22; 1886 else 1887 synthDelay /= 10; 1888 1889 udelay(synthDelay + BASE_ACTIVATE_DELAY); 1890 1891 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 1892 1893 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1894 ath9k_hw_set_delta_slope(ah, chan); 1895 1896 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1897 1898 if (!chan->oneTimeCalsDone) 1899 chan->oneTimeCalsDone = true; 1900 1901 return true; 1902} 1903 1904static void ath9k_enable_rfkill(struct ath_hw *ah) 1905{ 1906 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1907 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 1908 1909 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, 1910 AR_GPIO_INPUT_MUX2_RFSILENT); 1911 1912 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1913 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 1914} 1915 1916int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1917 bool bChannelChange) 1918{ 1919 struct ath_common *common = ath9k_hw_common(ah); 1920 u32 saveLedState; 1921 struct ath9k_channel *curchan = ah->curchan; 1922 u32 saveDefAntenna; 1923 u32 macStaId1; 1924 u64 tsf = 0; 1925 int i, rx_chainmask, r; 1926 1927 ah->txchainmask = common->tx_chainmask; 1928 ah->rxchainmask = common->rx_chainmask; 1929 1930 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1931 return -EIO; 1932 1933 if (curchan && !ah->chip_fullsleep) 1934 ath9k_hw_getnf(ah, curchan); 1935 1936 if (bChannelChange && 1937 (ah->chip_fullsleep != true) && 1938 (ah->curchan != NULL) && 1939 (chan->channel != ah->curchan->channel) && 1940 ((chan->channelFlags & CHANNEL_ALL) == 1941 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1942 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || 1943 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { 1944 1945 if (ath9k_hw_channel_change(ah, chan)) { 1946 ath9k_hw_loadnf(ah, ah->curchan); 1947 ath9k_hw_start_nfcal(ah); 1948 return 0; 1949 } 1950 } 1951 1952 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1953 if (saveDefAntenna == 0) 1954 saveDefAntenna = 1; 1955 1956 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1957 1958 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1959 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1960 tsf = ath9k_hw_gettsf64(ah); 1961 1962 saveLedState = REG_READ(ah, AR_CFG_LED) & 1963 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1964 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1965 1966 ath9k_hw_mark_phy_inactive(ah); 1967 1968 /* Only required on the first reset */ 1969 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1970 REG_WRITE(ah, 1971 AR9271_RESET_POWER_DOWN_CONTROL, 1972 AR9271_RADIO_RF_RST); 1973 udelay(50); 1974 } 1975 1976 if (!ath9k_hw_chip_reset(ah, chan)) { 1977 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); 1978 return -EINVAL; 1979 } 1980 1981 /* Only required on the first reset */ 1982 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1983 ah->htc_reset_init = false; 1984 REG_WRITE(ah, 1985 AR9271_RESET_POWER_DOWN_CONTROL, 1986 AR9271_GATE_MAC_CTL); 1987 udelay(50); 1988 } 1989 1990 /* Restore TSF */ 1991 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1992 ath9k_hw_settsf64(ah, tsf); 1993 1994 if (AR_SREV_9280_10_OR_LATER(ah)) 1995 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1996 1997 if (AR_SREV_9287_12_OR_LATER(ah)) { 1998 /* Enable ASYNC FIFO */ 1999 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 2000 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 2001 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 2002 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 2003 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 2004 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 2005 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 2006 } 2007 r = ath9k_hw_process_ini(ah, chan); 2008 if (r) 2009 return r; 2010 2011 /* Setup MFP options for CCMP */ 2012 if (AR_SREV_9280_20_OR_LATER(ah)) { 2013 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 2014 * frames when constructing CCMP AAD. */ 2015 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 2016 0xc7ff); 2017 ah->sw_mgmt_crypto = false; 2018 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 2019 /* Disable hardware crypto for management frames */ 2020 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 2021 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2022 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 2023 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2024 ah->sw_mgmt_crypto = true; 2025 } else 2026 ah->sw_mgmt_crypto = true; 2027 2028 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2029 ath9k_hw_set_delta_slope(ah, chan); 2030 2031 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 2032 ah->eep_ops->set_board_values(ah, chan); 2033 2034 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 2035 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 2036 | macStaId1 2037 | AR_STA_ID1_RTS_USE_DEF 2038 | (ah->config. 2039 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 2040 | ah->sta_id1_defaults); 2041 ath9k_hw_set_operating_mode(ah, ah->opmode); 2042 2043 ath_hw_setbssidmask(common); 2044 2045 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 2046 2047 ath9k_hw_write_associd(ah); 2048 2049 REG_WRITE(ah, AR_ISR, ~0); 2050 2051 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2052 2053 r = ah->ath9k_hw_rf_set_freq(ah, chan); 2054 if (r) 2055 return r; 2056 2057 for (i = 0; i < AR_NUM_DCU; i++) 2058 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2059 2060 ah->intr_txqs = 0; 2061 for (i = 0; i < ah->caps.total_queues; i++) 2062 ath9k_hw_resettxqueue(ah, i); 2063 2064 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 2065 ath9k_hw_init_qos(ah); 2066 2067 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2068 ath9k_enable_rfkill(ah); 2069 2070 ath9k_hw_init_global_settings(ah); 2071 2072 if (AR_SREV_9287_12_OR_LATER(ah)) { 2073 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 2074 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 2075 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 2076 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 2077 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 2078 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 2079 2080 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 2081 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 2082 2083 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 2084 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 2085 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 2086 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 2087 } 2088 if (AR_SREV_9287_12_OR_LATER(ah)) { 2089 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 2090 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 2091 } 2092 2093 REG_WRITE(ah, AR_STA_ID1, 2094 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 2095 2096 ath9k_hw_set_dma(ah); 2097 2098 REG_WRITE(ah, AR_OBS, 8); 2099 2100 if (ah->config.rx_intr_mitigation) { 2101 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2102 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2103 } 2104 2105 ath9k_hw_init_bb(ah, chan); 2106 2107 if (!ath9k_hw_init_cal(ah, chan)) 2108 return -EIO; 2109 2110 rx_chainmask = ah->rxchainmask; 2111 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 2112 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 2113 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 2114 } 2115 2116 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2117 2118 /* 2119 * For big endian systems turn on swapping for descriptors 2120 */ 2121 if (AR_SREV_9100(ah)) { 2122 u32 mask; 2123 mask = REG_READ(ah, AR_CFG); 2124 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2125 ath_print(common, ATH_DBG_RESET, 2126 "CFG Byte Swap Set 0x%x\n", mask); 2127 } else { 2128 mask = 2129 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2130 REG_WRITE(ah, AR_CFG, mask); 2131 ath_print(common, ATH_DBG_RESET, 2132 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 2133 } 2134 } else { 2135 /* Configure AR9271 target WLAN */ 2136 if (AR_SREV_9271(ah)) 2137 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2138#ifdef __BIG_ENDIAN 2139 else 2140 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2141#endif 2142 } 2143 2144 if (ah->btcoex_hw.enabled) 2145 ath9k_hw_btcoex_enable(ah); 2146 2147 return 0; 2148} 2149EXPORT_SYMBOL(ath9k_hw_reset); 2150 2151/************************/ 2152/* Key Cache Management */ 2153/************************/ 2154 2155bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) 2156{ 2157 u32 keyType; 2158 2159 if (entry >= ah->caps.keycache_size) { 2160 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2161 "keychache entry %u out of range\n", entry); 2162 return false; 2163 } 2164 2165 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 2166 2167 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 2168 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 2169 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 2170 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 2171 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 2172 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 2173 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 2174 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 2175 2176 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 2177 u16 micentry = entry + 64; 2178 2179 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 2180 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 2181 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); 2182 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 2183 2184 } 2185 2186 return true; 2187} 2188EXPORT_SYMBOL(ath9k_hw_keyreset); 2189 2190bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) 2191{ 2192 u32 macHi, macLo; 2193 2194 if (entry >= ah->caps.keycache_size) { 2195 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2196 "keychache entry %u out of range\n", entry); 2197 return false; 2198 } 2199 2200 if (mac != NULL) { 2201 macHi = (mac[5] << 8) | mac[4]; 2202 macLo = (mac[3] << 24) | 2203 (mac[2] << 16) | 2204 (mac[1] << 8) | 2205 mac[0]; 2206 macLo >>= 1; 2207 macLo |= (macHi & 1) << 31; 2208 macHi >>= 1; 2209 } else { 2210 macLo = macHi = 0; 2211 } 2212 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 2213 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); 2214 2215 return true; 2216} 2217EXPORT_SYMBOL(ath9k_hw_keysetmac); 2218 2219bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, 2220 const struct ath9k_keyval *k, 2221 const u8 *mac) 2222{ 2223 const struct ath9k_hw_capabilities *pCap = &ah->caps; 2224 struct ath_common *common = ath9k_hw_common(ah); 2225 u32 key0, key1, key2, key3, key4; 2226 u32 keyType; 2227 2228 if (entry >= pCap->keycache_size) { 2229 ath_print(common, ATH_DBG_FATAL, 2230 "keycache entry %u out of range\n", entry); 2231 return false; 2232 } 2233 2234 switch (k->kv_type) { 2235 case ATH9K_CIPHER_AES_OCB: 2236 keyType = AR_KEYTABLE_TYPE_AES; 2237 break; 2238 case ATH9K_CIPHER_AES_CCM: 2239 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2240 ath_print(common, ATH_DBG_ANY, 2241 "AES-CCM not supported by mac rev 0x%x\n", 2242 ah->hw_version.macRev); 2243 return false; 2244 } 2245 keyType = AR_KEYTABLE_TYPE_CCM; 2246 break; 2247 case ATH9K_CIPHER_TKIP: 2248 keyType = AR_KEYTABLE_TYPE_TKIP; 2249 if (ATH9K_IS_MIC_ENABLED(ah) 2250 && entry + 64 >= pCap->keycache_size) { 2251 ath_print(common, ATH_DBG_ANY, 2252 "entry %u inappropriate for TKIP\n", entry); 2253 return false; 2254 } 2255 break; 2256 case ATH9K_CIPHER_WEP: 2257 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 2258 ath_print(common, ATH_DBG_ANY, 2259 "WEP key length %u too small\n", k->kv_len); 2260 return false; 2261 } 2262 if (k->kv_len <= WLAN_KEY_LEN_WEP40) 2263 keyType = AR_KEYTABLE_TYPE_40; 2264 else if (k->kv_len <= WLAN_KEY_LEN_WEP104) 2265 keyType = AR_KEYTABLE_TYPE_104; 2266 else 2267 keyType = AR_KEYTABLE_TYPE_128; 2268 break; 2269 case ATH9K_CIPHER_CLR: 2270 keyType = AR_KEYTABLE_TYPE_CLR; 2271 break; 2272 default: 2273 ath_print(common, ATH_DBG_FATAL, 2274 "cipher %u not supported\n", k->kv_type); 2275 return false; 2276 } 2277 2278 key0 = get_unaligned_le32(k->kv_val + 0); 2279 key1 = get_unaligned_le16(k->kv_val + 4); 2280 key2 = get_unaligned_le32(k->kv_val + 6); 2281 key3 = get_unaligned_le16(k->kv_val + 10); 2282 key4 = get_unaligned_le32(k->kv_val + 12); 2283 if (k->kv_len <= WLAN_KEY_LEN_WEP104) 2284 key4 &= 0xff; 2285 2286 /* 2287 * Note: Key cache registers access special memory area that requires 2288 * two 32-bit writes to actually update the values in the internal 2289 * memory. Consequently, the exact order and pairs used here must be 2290 * maintained. 2291 */ 2292 2293 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 2294 u16 micentry = entry + 64; 2295 2296 /* 2297 * Write inverted key[47:0] first to avoid Michael MIC errors 2298 * on frames that could be sent or received at the same time. 2299 * The correct key will be written in the end once everything 2300 * else is ready. 2301 */ 2302 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); 2303 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); 2304 2305 /* Write key[95:48] */ 2306 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 2307 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 2308 2309 /* Write key[127:96] and key type */ 2310 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 2311 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2312 2313 /* Write MAC address for the entry */ 2314 (void) ath9k_hw_keysetmac(ah, entry, mac); 2315 2316 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { 2317 /* 2318 * TKIP uses two key cache entries: 2319 * Michael MIC TX/RX keys in the same key cache entry 2320 * (idx = main index + 64): 2321 * key0 [31:0] = RX key [31:0] 2322 * key1 [15:0] = TX key [31:16] 2323 * key1 [31:16] = reserved 2324 * key2 [31:0] = RX key [63:32] 2325 * key3 [15:0] = TX key [15:0] 2326 * key3 [31:16] = reserved 2327 * key4 [31:0] = TX key [63:32] 2328 */ 2329 u32 mic0, mic1, mic2, mic3, mic4; 2330 2331 mic0 = get_unaligned_le32(k->kv_mic + 0); 2332 mic2 = get_unaligned_le32(k->kv_mic + 4); 2333 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; 2334 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; 2335 mic4 = get_unaligned_le32(k->kv_txmic + 4); 2336 2337 /* Write RX[31:0] and TX[31:16] */ 2338 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 2339 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); 2340 2341 /* Write RX[63:32] and TX[15:0] */ 2342 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 2343 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); 2344 2345 /* Write TX[63:32] and keyType(reserved) */ 2346 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); 2347 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 2348 AR_KEYTABLE_TYPE_CLR); 2349 2350 } else { 2351 /* 2352 * TKIP uses four key cache entries (two for group 2353 * keys): 2354 * Michael MIC TX/RX keys are in different key cache 2355 * entries (idx = main index + 64 for TX and 2356 * main index + 32 + 96 for RX): 2357 * key0 [31:0] = TX/RX MIC key [31:0] 2358 * key1 [31:0] = reserved 2359 * key2 [31:0] = TX/RX MIC key [63:32] 2360 * key3 [31:0] = reserved 2361 * key4 [31:0] = reserved 2362 * 2363 * Upper layer code will call this function separately 2364 * for TX and RX keys when these registers offsets are 2365 * used. 2366 */ 2367 u32 mic0, mic2; 2368 2369 mic0 = get_unaligned_le32(k->kv_mic + 0); 2370 mic2 = get_unaligned_le32(k->kv_mic + 4); 2371 2372 /* Write MIC key[31:0] */ 2373 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 2374 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 2375 2376 /* Write MIC key[63:32] */ 2377 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 2378 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 2379 2380 /* Write TX[63:32] and keyType(reserved) */ 2381 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); 2382 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 2383 AR_KEYTABLE_TYPE_CLR); 2384 } 2385 2386 /* MAC address registers are reserved for the MIC entry */ 2387 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); 2388 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); 2389 2390 /* 2391 * Write the correct (un-inverted) key[47:0] last to enable 2392 * TKIP now that all other registers are set with correct 2393 * values. 2394 */ 2395 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 2396 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 2397 } else { 2398 /* Write key[47:0] */ 2399 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 2400 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 2401 2402 /* Write key[95:48] */ 2403 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 2404 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 2405 2406 /* Write key[127:96] and key type */ 2407 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 2408 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2409 2410 /* Write MAC address for the entry */ 2411 (void) ath9k_hw_keysetmac(ah, entry, mac); 2412 } 2413 2414 return true; 2415} 2416EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); 2417 2418bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) 2419{ 2420 if (entry < ah->caps.keycache_size) { 2421 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 2422 if (val & AR_KEYTABLE_VALID) 2423 return true; 2424 } 2425 return false; 2426} 2427EXPORT_SYMBOL(ath9k_hw_keyisvalid); 2428 2429/******************************/ 2430/* Power Management (Chipset) */ 2431/******************************/ 2432 2433static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 2434{ 2435 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2436 if (setChip) { 2437 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2438 AR_RTC_FORCE_WAKE_EN); 2439 if (!AR_SREV_9100(ah)) 2440 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2441 2442 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 2443 REG_CLR_BIT(ah, (AR_RTC_RESET), 2444 AR_RTC_RESET_EN); 2445 } 2446} 2447 2448static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 2449{ 2450 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2451 if (setChip) { 2452 struct ath9k_hw_capabilities *pCap = &ah->caps; 2453 2454 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2455 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2456 AR_RTC_FORCE_WAKE_ON_INT); 2457 } else { 2458 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2459 AR_RTC_FORCE_WAKE_EN); 2460 } 2461 } 2462} 2463 2464static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 2465{ 2466 u32 val; 2467 int i; 2468 2469 if (setChip) { 2470 if ((REG_READ(ah, AR_RTC_STATUS) & 2471 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2472 if (ath9k_hw_set_reset_reg(ah, 2473 ATH9K_RESET_POWER_ON) != true) { 2474 return false; 2475 } 2476 ath9k_hw_init_pll(ah, NULL); 2477 } 2478 if (AR_SREV_9100(ah)) 2479 REG_SET_BIT(ah, AR_RTC_RESET, 2480 AR_RTC_RESET_EN); 2481 2482 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2483 AR_RTC_FORCE_WAKE_EN); 2484 udelay(50); 2485 2486 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2487 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2488 if (val == AR_RTC_STATUS_ON) 2489 break; 2490 udelay(50); 2491 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2492 AR_RTC_FORCE_WAKE_EN); 2493 } 2494 if (i == 0) { 2495 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2496 "Failed to wakeup in %uus\n", 2497 POWER_UP_TIME / 20); 2498 return false; 2499 } 2500 } 2501 2502 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2503 2504 return true; 2505} 2506 2507bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2508{ 2509 struct ath_common *common = ath9k_hw_common(ah); 2510 int status = true, setChip = true; 2511 static const char *modes[] = { 2512 "AWAKE", 2513 "FULL-SLEEP", 2514 "NETWORK SLEEP", 2515 "UNDEFINED" 2516 }; 2517 2518 if (ah->power_mode == mode) 2519 return status; 2520 2521 ath_print(common, ATH_DBG_RESET, "%s -> %s\n", 2522 modes[ah->power_mode], modes[mode]); 2523 2524 switch (mode) { 2525 case ATH9K_PM_AWAKE: 2526 status = ath9k_hw_set_power_awake(ah, setChip); 2527 break; 2528 case ATH9K_PM_FULL_SLEEP: 2529 ath9k_set_power_sleep(ah, setChip); 2530 ah->chip_fullsleep = true; 2531 break; 2532 case ATH9K_PM_NETWORK_SLEEP: 2533 ath9k_set_power_network_sleep(ah, setChip); 2534 break; 2535 default: 2536 ath_print(common, ATH_DBG_FATAL, 2537 "Unknown power mode %u\n", mode); 2538 return false; 2539 } 2540 ah->power_mode = mode; 2541 2542 return status; 2543} 2544EXPORT_SYMBOL(ath9k_hw_setpower); 2545 2546/* 2547 * Helper for ASPM support. 2548 * 2549 * Disable PLL when in L0s as well as receiver clock when in L1. 2550 * This power saving option must be enabled through the SerDes. 2551 * 2552 * Programming the SerDes must go through the same 288 bit serial shift 2553 * register as the other analog registers. Hence the 9 writes. 2554 */ 2555void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off) 2556{ 2557 u8 i; 2558 u32 val; 2559 2560 if (ah->is_pciexpress != true) 2561 return; 2562 2563 /* Do not touch SerDes registers */ 2564 if (ah->config.pcie_powersave_enable == 2) 2565 return; 2566 2567 /* Nothing to do on restore for 11N */ 2568 if (!restore) { 2569 if (AR_SREV_9280_20_OR_LATER(ah)) { 2570 /* 2571 * AR9280 2.0 or later chips use SerDes values from the 2572 * initvals.h initialized depending on chipset during 2573 * ath9k_hw_init() 2574 */ 2575 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { 2576 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), 2577 INI_RA(&ah->iniPcieSerdes, i, 1)); 2578 } 2579 } else if (AR_SREV_9280(ah) && 2580 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { 2581 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); 2582 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2583 2584 /* RX shut off when elecidle is asserted */ 2585 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); 2586 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); 2587 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); 2588 2589 /* Shut off CLKREQ active in L1 */ 2590 if (ah->config.pcie_clock_req) 2591 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); 2592 else 2593 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); 2594 2595 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 2596 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 2597 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); 2598 2599 /* Load the new settings */ 2600 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 2601 2602 } else { 2603 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 2604 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2605 2606 /* RX shut off when elecidle is asserted */ 2607 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 2608 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 2609 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 2610 2611 /* 2612 * Ignore ah->ah_config.pcie_clock_req setting for 2613 * pre-AR9280 11n 2614 */ 2615 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 2616 2617 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 2618 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 2619 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 2620 2621 /* Load the new settings */ 2622 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 2623 } 2624 2625 udelay(1000); 2626 2627 /* set bit 19 to allow forcing of pcie core into L1 state */ 2628 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 2629 2630 /* Several PCIe massages to ensure proper behaviour */ 2631 if (ah->config.pcie_waen) { 2632 val = ah->config.pcie_waen; 2633 if (!power_off) 2634 val &= (~AR_WA_D3_L1_DISABLE); 2635 } else { 2636 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || 2637 AR_SREV_9287(ah)) { 2638 val = AR9285_WA_DEFAULT; 2639 if (!power_off) 2640 val &= (~AR_WA_D3_L1_DISABLE); 2641 } else if (AR_SREV_9280(ah)) { 2642 /* 2643 * On AR9280 chips bit 22 of 0x4004 needs to be 2644 * set otherwise card may disappear. 2645 */ 2646 val = AR9280_WA_DEFAULT; 2647 if (!power_off) 2648 val &= (~AR_WA_D3_L1_DISABLE); 2649 } else 2650 val = AR_WA_DEFAULT; 2651 } 2652 2653 REG_WRITE(ah, AR_WA, val); 2654 } 2655 2656 if (power_off) { 2657 /* 2658 * Set PCIe workaround bits 2659 * bit 14 in WA register (disable L1) should only 2660 * be set when device enters D3 and be cleared 2661 * when device comes back to D0. 2662 */ 2663 if (ah->config.pcie_waen) { 2664 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) 2665 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); 2666 } else { 2667 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) || 2668 AR_SREV_9287(ah)) && 2669 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || 2670 (AR_SREV_9280(ah) && 2671 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { 2672 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); 2673 } 2674 } 2675 } 2676} 2677EXPORT_SYMBOL(ath9k_hw_configpcipowersave); 2678 2679/**********************/ 2680/* Interrupt Handling */ 2681/**********************/ 2682 2683bool ath9k_hw_intrpend(struct ath_hw *ah) 2684{ 2685 u32 host_isr; 2686 2687 if (AR_SREV_9100(ah)) 2688 return true; 2689 2690 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); 2691 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) 2692 return true; 2693 2694 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); 2695 if ((host_isr & AR_INTR_SYNC_DEFAULT) 2696 && (host_isr != AR_INTR_SPURIOUS)) 2697 return true; 2698 2699 return false; 2700} 2701EXPORT_SYMBOL(ath9k_hw_intrpend); 2702 2703bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) 2704{ 2705 u32 isr = 0; 2706 u32 mask2 = 0; 2707 struct ath9k_hw_capabilities *pCap = &ah->caps; 2708 u32 sync_cause = 0; 2709 bool fatal_int = false; 2710 struct ath_common *common = ath9k_hw_common(ah); 2711 2712 if (!AR_SREV_9100(ah)) { 2713 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2714 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 2715 == AR_RTC_STATUS_ON) { 2716 isr = REG_READ(ah, AR_ISR); 2717 } 2718 } 2719 2720 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & 2721 AR_INTR_SYNC_DEFAULT; 2722 2723 *masked = 0; 2724 2725 if (!isr && !sync_cause) 2726 return false; 2727 } else { 2728 *masked = 0; 2729 isr = REG_READ(ah, AR_ISR); 2730 } 2731 2732 if (isr) { 2733 if (isr & AR_ISR_BCNMISC) { 2734 u32 isr2; 2735 isr2 = REG_READ(ah, AR_ISR_S2); 2736 if (isr2 & AR_ISR_S2_TIM) 2737 mask2 |= ATH9K_INT_TIM; 2738 if (isr2 & AR_ISR_S2_DTIM) 2739 mask2 |= ATH9K_INT_DTIM; 2740 if (isr2 & AR_ISR_S2_DTIMSYNC) 2741 mask2 |= ATH9K_INT_DTIMSYNC; 2742 if (isr2 & (AR_ISR_S2_CABEND)) 2743 mask2 |= ATH9K_INT_CABEND; 2744 if (isr2 & AR_ISR_S2_GTT) 2745 mask2 |= ATH9K_INT_GTT; 2746 if (isr2 & AR_ISR_S2_CST) 2747 mask2 |= ATH9K_INT_CST; 2748 if (isr2 & AR_ISR_S2_TSFOOR) 2749 mask2 |= ATH9K_INT_TSFOOR; 2750 } 2751 2752 isr = REG_READ(ah, AR_ISR_RAC); 2753 if (isr == 0xffffffff) { 2754 *masked = 0; 2755 return false; 2756 } 2757 2758 *masked = isr & ATH9K_INT_COMMON; 2759 2760 if (ah->config.rx_intr_mitigation) { 2761 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2762 *masked |= ATH9K_INT_RX; 2763 } 2764 2765 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 2766 *masked |= ATH9K_INT_RX; 2767 if (isr & 2768 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | 2769 AR_ISR_TXEOL)) { 2770 u32 s0_s, s1_s; 2771 2772 *masked |= ATH9K_INT_TX; 2773 2774 s0_s = REG_READ(ah, AR_ISR_S0_S); 2775 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); 2776 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); 2777 2778 s1_s = REG_READ(ah, AR_ISR_S1_S); 2779 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); 2780 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); 2781 } 2782 2783 if (isr & AR_ISR_RXORN) { 2784 ath_print(common, ATH_DBG_INTERRUPT, 2785 "receive FIFO overrun interrupt\n"); 2786 } 2787 2788 if (!AR_SREV_9100(ah)) { 2789 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2790 u32 isr5 = REG_READ(ah, AR_ISR_S5_S); 2791 if (isr5 & AR_ISR_S5_TIM_TIMER) 2792 *masked |= ATH9K_INT_TIM_TIMER; 2793 } 2794 } 2795 2796 *masked |= mask2; 2797 } 2798 2799 if (AR_SREV_9100(ah)) 2800 return true; 2801 2802 if (isr & AR_ISR_GENTMR) { 2803 u32 s5_s; 2804 2805 s5_s = REG_READ(ah, AR_ISR_S5_S); 2806 if (isr & AR_ISR_GENTMR) { 2807 ah->intr_gen_timer_trigger = 2808 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); 2809 2810 ah->intr_gen_timer_thresh = 2811 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH); 2812 2813 if (ah->intr_gen_timer_trigger) 2814 *masked |= ATH9K_INT_GENTIMER; 2815 2816 } 2817 } 2818 2819 if (sync_cause) { 2820 fatal_int = 2821 (sync_cause & 2822 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) 2823 ? true : false; 2824 2825 if (fatal_int) { 2826 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 2827 ath_print(common, ATH_DBG_ANY, 2828 "received PCI FATAL interrupt\n"); 2829 } 2830 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 2831 ath_print(common, ATH_DBG_ANY, 2832 "received PCI PERR interrupt\n"); 2833 } 2834 *masked |= ATH9K_INT_FATAL; 2835 } 2836 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 2837 ath_print(common, ATH_DBG_INTERRUPT, 2838 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); 2839 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 2840 REG_WRITE(ah, AR_RC, 0); 2841 *masked |= ATH9K_INT_FATAL; 2842 } 2843 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 2844 ath_print(common, ATH_DBG_INTERRUPT, 2845 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 2846 } 2847 2848 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 2849 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 2850 } 2851 2852 return true; 2853} 2854EXPORT_SYMBOL(ath9k_hw_getisr); 2855 2856enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) 2857{ 2858 enum ath9k_int omask = ah->imask; 2859 u32 mask, mask2; 2860 struct ath9k_hw_capabilities *pCap = &ah->caps; 2861 struct ath_common *common = ath9k_hw_common(ah); 2862 2863 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 2864 2865 if (omask & ATH9K_INT_GLOBAL) { 2866 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n"); 2867 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 2868 (void) REG_READ(ah, AR_IER); 2869 if (!AR_SREV_9100(ah)) { 2870 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 2871 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); 2872 2873 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 2874 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); 2875 } 2876 } 2877 2878 mask = ints & ATH9K_INT_COMMON; 2879 mask2 = 0; 2880 2881 if (ints & ATH9K_INT_TX) { 2882 if (ah->txok_interrupt_mask) 2883 mask |= AR_IMR_TXOK; 2884 if (ah->txdesc_interrupt_mask) 2885 mask |= AR_IMR_TXDESC; 2886 if (ah->txerr_interrupt_mask) 2887 mask |= AR_IMR_TXERR; 2888 if (ah->txeol_interrupt_mask) 2889 mask |= AR_IMR_TXEOL; 2890 } 2891 if (ints & ATH9K_INT_RX) { 2892 mask |= AR_IMR_RXERR; 2893 if (ah->config.rx_intr_mitigation) 2894 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 2895 else 2896 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 2897 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 2898 mask |= AR_IMR_GENTMR; 2899 } 2900 2901 if (ints & (ATH9K_INT_BMISC)) { 2902 mask |= AR_IMR_BCNMISC; 2903 if (ints & ATH9K_INT_TIM) 2904 mask2 |= AR_IMR_S2_TIM; 2905 if (ints & ATH9K_INT_DTIM) 2906 mask2 |= AR_IMR_S2_DTIM; 2907 if (ints & ATH9K_INT_DTIMSYNC) 2908 mask2 |= AR_IMR_S2_DTIMSYNC; 2909 if (ints & ATH9K_INT_CABEND) 2910 mask2 |= AR_IMR_S2_CABEND; 2911 if (ints & ATH9K_INT_TSFOOR) 2912 mask2 |= AR_IMR_S2_TSFOOR; 2913 } 2914 2915 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { 2916 mask |= AR_IMR_BCNMISC; 2917 if (ints & ATH9K_INT_GTT) 2918 mask2 |= AR_IMR_S2_GTT; 2919 if (ints & ATH9K_INT_CST) 2920 mask2 |= AR_IMR_S2_CST; 2921 } 2922 2923 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); 2924 REG_WRITE(ah, AR_IMR, mask); 2925 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2926 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2927 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2928 ah->imrs2_reg |= mask2; 2929 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 2930 2931 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2932 if (ints & ATH9K_INT_TIM_TIMER) 2933 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2934 else 2935 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2936 } 2937 2938 if (ints & ATH9K_INT_GLOBAL) { 2939 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n"); 2940 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 2941 if (!AR_SREV_9100(ah)) { 2942 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 2943 AR_INTR_MAC_IRQ); 2944 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2945 2946 2947 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 2948 AR_INTR_SYNC_DEFAULT); 2949 REG_WRITE(ah, AR_INTR_SYNC_MASK, 2950 AR_INTR_SYNC_DEFAULT); 2951 } 2952 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 2953 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 2954 } 2955 2956 return omask; 2957} 2958EXPORT_SYMBOL(ath9k_hw_set_interrupts); 2959 2960/*******************/ 2961/* Beacon Handling */ 2962/*******************/ 2963 2964void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2965{ 2966 int flags = 0; 2967 2968 ah->beacon_interval = beacon_period; 2969 2970 switch (ah->opmode) { 2971 case NL80211_IFTYPE_STATION: 2972 case NL80211_IFTYPE_MONITOR: 2973 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 2974 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); 2975 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); 2976 flags |= AR_TBTT_TIMER_EN; 2977 break; 2978 case NL80211_IFTYPE_ADHOC: 2979 case NL80211_IFTYPE_MESH_POINT: 2980 REG_SET_BIT(ah, AR_TXCFG, 2981 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2982 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 2983 TU_TO_USEC(next_beacon + 2984 (ah->atim_window ? ah-> 2985 atim_window : 1))); 2986 flags |= AR_NDP_TIMER_EN; 2987 case NL80211_IFTYPE_AP: 2988 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 2989 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 2990 TU_TO_USEC(next_beacon - 2991 ah->config. 2992 dma_beacon_response_time)); 2993 REG_WRITE(ah, AR_NEXT_SWBA, 2994 TU_TO_USEC(next_beacon - 2995 ah->config. 2996 sw_beacon_response_time)); 2997 flags |= 2998 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2999 break; 3000 default: 3001 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, 3002 "%s: unsupported opmode: %d\n", 3003 __func__, ah->opmode); 3004 return; 3005 break; 3006 } 3007 3008 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 3009 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 3010 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 3011 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 3012 3013 beacon_period &= ~ATH9K_BEACON_ENA; 3014 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 3015 ath9k_hw_reset_tsf(ah); 3016 } 3017 3018 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3019} 3020EXPORT_SYMBOL(ath9k_hw_beaconinit); 3021 3022void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 3023 const struct ath9k_beacon_state *bs) 3024{ 3025 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3026 struct ath9k_hw_capabilities *pCap = &ah->caps; 3027 struct ath_common *common = ath9k_hw_common(ah); 3028 3029 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 3030 3031 REG_WRITE(ah, AR_BEACON_PERIOD, 3032 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 3033 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 3034 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 3035 3036 REG_RMW_FIELD(ah, AR_RSSI_THR, 3037 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 3038 3039 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 3040 3041 if (bs->bs_sleepduration > beaconintval) 3042 beaconintval = bs->bs_sleepduration; 3043 3044 dtimperiod = bs->bs_dtimperiod; 3045 if (bs->bs_sleepduration > dtimperiod) 3046 dtimperiod = bs->bs_sleepduration; 3047 3048 if (beaconintval == dtimperiod) 3049 nextTbtt = bs->bs_nextdtim; 3050 else 3051 nextTbtt = bs->bs_nexttbtt; 3052 3053 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 3054 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 3055 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 3056 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 3057 3058 REG_WRITE(ah, AR_NEXT_DTIM, 3059 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3060 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 3061 3062 REG_WRITE(ah, AR_SLEEP1, 3063 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 3064 | AR_SLEEP1_ASSUME_DTIM); 3065 3066 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 3067 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 3068 else 3069 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 3070 3071 REG_WRITE(ah, AR_SLEEP2, 3072 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 3073 3074 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 3075 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 3076 3077 REG_SET_BIT(ah, AR_TIMER_MODE, 3078 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 3079 AR_DTIM_TIMER_EN); 3080 3081 /* TSF Out of Range Threshold */ 3082 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 3083} 3084EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 3085 3086/*******************/ 3087/* HW Capabilities */ 3088/*******************/ 3089 3090int ath9k_hw_fill_cap_info(struct ath_hw *ah) 3091{ 3092 struct ath9k_hw_capabilities *pCap = &ah->caps; 3093 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 3094 struct ath_common *common = ath9k_hw_common(ah); 3095 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 3096 3097 u16 capField = 0, eeval; 3098 3099 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 3100 regulatory->current_rd = eeval; 3101 3102 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 3103 if (AR_SREV_9285_10_OR_LATER(ah)) 3104 eeval |= AR9285_RDEXT_DEFAULT; 3105 regulatory->current_rd_ext = eeval; 3106 3107 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 3108 3109 if (ah->opmode != NL80211_IFTYPE_AP && 3110 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 3111 if (regulatory->current_rd == 0x64 || 3112 regulatory->current_rd == 0x65) 3113 regulatory->current_rd += 5; 3114 else if (regulatory->current_rd == 0x41) 3115 regulatory->current_rd = 0x43; 3116 ath_print(common, ATH_DBG_REGULATORY, 3117 "regdomain mapped to 0x%x\n", regulatory->current_rd); 3118 } 3119 3120 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 3121 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 3122 ath_print(common, ATH_DBG_FATAL, 3123 "no band has been marked as supported in EEPROM.\n"); 3124 return -EINVAL; 3125 } 3126 3127 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); 3128 3129 if (eeval & AR5416_OPFLAGS_11A) { 3130 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 3131 if (ah->config.ht_enable) { 3132 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) 3133 set_bit(ATH9K_MODE_11NA_HT20, 3134 pCap->wireless_modes); 3135 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { 3136 set_bit(ATH9K_MODE_11NA_HT40PLUS, 3137 pCap->wireless_modes); 3138 set_bit(ATH9K_MODE_11NA_HT40MINUS, 3139 pCap->wireless_modes); 3140 } 3141 } 3142 } 3143 3144 if (eeval & AR5416_OPFLAGS_11G) { 3145 set_bit(ATH9K_MODE_11G, pCap->wireless_modes); 3146 if (ah->config.ht_enable) { 3147 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) 3148 set_bit(ATH9K_MODE_11NG_HT20, 3149 pCap->wireless_modes); 3150 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { 3151 set_bit(ATH9K_MODE_11NG_HT40PLUS, 3152 pCap->wireless_modes); 3153 set_bit(ATH9K_MODE_11NG_HT40MINUS, 3154 pCap->wireless_modes); 3155 } 3156 } 3157 } 3158 3159 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 3160 /* 3161 * For AR9271 we will temporarilly uses the rx chainmax as read from 3162 * the EEPROM. 3163 */ 3164 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 3165 !(eeval & AR5416_OPFLAGS_11A) && 3166 !(AR_SREV_9271(ah))) 3167 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 3168 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 3169 else 3170 /* Use rx_chainmask from EEPROM. */ 3171 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 3172 3173 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 3174 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 3175 3176 pCap->low_2ghz_chan = 2312; 3177 pCap->high_2ghz_chan = 2732; 3178 3179 pCap->low_5ghz_chan = 4920; 3180 pCap->high_5ghz_chan = 6100; 3181 3182 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; 3183 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; 3184 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; 3185 3186 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; 3187 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; 3188 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; 3189 3190 if (ah->config.ht_enable) 3191 pCap->hw_caps |= ATH9K_HW_CAP_HT; 3192 else 3193 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 3194 3195 pCap->hw_caps |= ATH9K_HW_CAP_GTT; 3196 pCap->hw_caps |= ATH9K_HW_CAP_VEOL; 3197 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; 3198 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; 3199 3200 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 3201 pCap->total_queues = 3202 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 3203 else 3204 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 3205 3206 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 3207 pCap->keycache_size = 3208 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 3209 else 3210 pCap->keycache_size = AR_KEYTABLE_SIZE; 3211 3212 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; 3213 3214 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 3215 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; 3216 else 3217 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 3218 3219 if (AR_SREV_9271(ah)) 3220 pCap->num_gpio_pins = AR9271_NUM_GPIO; 3221 else if (AR_SREV_9285_10_OR_LATER(ah)) 3222 pCap->num_gpio_pins = AR9285_NUM_GPIO; 3223 else if (AR_SREV_9280_10_OR_LATER(ah)) 3224 pCap->num_gpio_pins = AR928X_NUM_GPIO; 3225 else 3226 pCap->num_gpio_pins = AR_NUM_GPIO; 3227 3228 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 3229 pCap->hw_caps |= ATH9K_HW_CAP_CST; 3230 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 3231 } else { 3232 pCap->rts_aggr_limit = (8 * 1024); 3233 } 3234 3235 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 3236 3237#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3238 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 3239 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 3240 ah->rfkill_gpio = 3241 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 3242 ah->rfkill_polarity = 3243 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 3244 3245 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 3246 } 3247#endif 3248 if (AR_SREV_9271(ah)) 3249 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 3250 else 3251 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 3252 3253 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 3254 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 3255 else 3256 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 3257 3258 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 3259 pCap->reg_cap = 3260 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3261 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 3262 AR_EEPROM_EEREGCAP_EN_KK_U2 | 3263 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 3264 } else { 3265 pCap->reg_cap = 3266 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3267 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 3268 } 3269 3270 /* Advertise midband for AR5416 with FCC midband set in eeprom */ 3271 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && 3272 AR_SREV_5416(ah)) 3273 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 3274 3275 pCap->num_antcfg_5ghz = 3276 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 3277 pCap->num_antcfg_2ghz = 3278 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 3279 3280 if (AR_SREV_9280_10_OR_LATER(ah) && 3281 ath9k_hw_btcoex_supported(ah)) { 3282 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 3283 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 3284 3285 if (AR_SREV_9285(ah)) { 3286 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 3287 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; 3288 } else { 3289 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 3290 } 3291 } else { 3292 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 3293 } 3294 3295 return 0; 3296} 3297 3298bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3299 u32 capability, u32 *result) 3300{ 3301 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 3302 switch (type) { 3303 case ATH9K_CAP_CIPHER: 3304 switch (capability) { 3305 case ATH9K_CIPHER_AES_CCM: 3306 case ATH9K_CIPHER_AES_OCB: 3307 case ATH9K_CIPHER_TKIP: 3308 case ATH9K_CIPHER_WEP: 3309 case ATH9K_CIPHER_MIC: 3310 case ATH9K_CIPHER_CLR: 3311 return true; 3312 default: 3313 return false; 3314 } 3315 case ATH9K_CAP_TKIP_MIC: 3316 switch (capability) { 3317 case 0: 3318 return true; 3319 case 1: 3320 return (ah->sta_id1_defaults & 3321 AR_STA_ID1_CRPT_MIC_ENABLE) ? true : 3322 false; 3323 } 3324 case ATH9K_CAP_TKIP_SPLIT: 3325 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 3326 false : true; 3327 case ATH9K_CAP_DIVERSITY: 3328 return (REG_READ(ah, AR_PHY_CCK_DETECT) & 3329 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 3330 true : false; 3331 case ATH9K_CAP_MCAST_KEYSRCH: 3332 switch (capability) { 3333 case 0: 3334 return true; 3335 case 1: 3336 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 3337 return false; 3338 } else { 3339 return (ah->sta_id1_defaults & 3340 AR_STA_ID1_MCAST_KSRCH) ? true : 3341 false; 3342 } 3343 } 3344 return false; 3345 case ATH9K_CAP_TXPOW: 3346 switch (capability) { 3347 case 0: 3348 return 0; 3349 case 1: 3350 *result = regulatory->power_limit; 3351 return 0; 3352 case 2: 3353 *result = regulatory->max_power_level; 3354 return 0; 3355 case 3: 3356 *result = regulatory->tp_scale; 3357 return 0; 3358 } 3359 return false; 3360 case ATH9K_CAP_DS: 3361 return (AR_SREV_9280_20_OR_LATER(ah) && 3362 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) 3363 ? false : true; 3364 default: 3365 return false; 3366 } 3367} 3368EXPORT_SYMBOL(ath9k_hw_getcapability); 3369 3370bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3371 u32 capability, u32 setting, int *status) 3372{ 3373 u32 v; 3374 3375 switch (type) { 3376 case ATH9K_CAP_TKIP_MIC: 3377 if (setting) 3378 ah->sta_id1_defaults |= 3379 AR_STA_ID1_CRPT_MIC_ENABLE; 3380 else 3381 ah->sta_id1_defaults &= 3382 ~AR_STA_ID1_CRPT_MIC_ENABLE; 3383 return true; 3384 case ATH9K_CAP_DIVERSITY: 3385 v = REG_READ(ah, AR_PHY_CCK_DETECT); 3386 if (setting) 3387 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 3388 else 3389 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 3390 REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 3391 return true; 3392 case ATH9K_CAP_MCAST_KEYSRCH: 3393 if (setting) 3394 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 3395 else 3396 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 3397 return true; 3398 default: 3399 return false; 3400 } 3401} 3402EXPORT_SYMBOL(ath9k_hw_setcapability); 3403 3404/****************************/ 3405/* GPIO / RFKILL / Antennae */ 3406/****************************/ 3407 3408static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 3409 u32 gpio, u32 type) 3410{ 3411 int addr; 3412 u32 gpio_shift, tmp; 3413 3414 if (gpio > 11) 3415 addr = AR_GPIO_OUTPUT_MUX3; 3416 else if (gpio > 5) 3417 addr = AR_GPIO_OUTPUT_MUX2; 3418 else 3419 addr = AR_GPIO_OUTPUT_MUX1; 3420 3421 gpio_shift = (gpio % 6) * 5; 3422 3423 if (AR_SREV_9280_20_OR_LATER(ah) 3424 || (addr != AR_GPIO_OUTPUT_MUX1)) { 3425 REG_RMW(ah, addr, (type << gpio_shift), 3426 (0x1f << gpio_shift)); 3427 } else { 3428 tmp = REG_READ(ah, addr); 3429 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 3430 tmp &= ~(0x1f << gpio_shift); 3431 tmp |= (type << gpio_shift); 3432 REG_WRITE(ah, addr, tmp); 3433 } 3434} 3435 3436void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 3437{ 3438 u32 gpio_shift; 3439 3440 BUG_ON(gpio >= ah->caps.num_gpio_pins); 3441 3442 gpio_shift = gpio << 1; 3443 3444 REG_RMW(ah, 3445 AR_GPIO_OE_OUT, 3446 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 3447 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3448} 3449EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 3450 3451u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 3452{ 3453#define MS_REG_READ(x, y) \ 3454 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 3455 3456 if (gpio >= ah->caps.num_gpio_pins) 3457 return 0xffffffff; 3458 3459 if (AR_SREV_9271(ah)) 3460 return MS_REG_READ(AR9271, gpio) != 0; 3461 else if (AR_SREV_9287_10_OR_LATER(ah)) 3462 return MS_REG_READ(AR9287, gpio) != 0; 3463 else if (AR_SREV_9285_10_OR_LATER(ah)) 3464 return MS_REG_READ(AR9285, gpio) != 0; 3465 else if (AR_SREV_9280_10_OR_LATER(ah)) 3466 return MS_REG_READ(AR928X, gpio) != 0; 3467 else 3468 return MS_REG_READ(AR, gpio) != 0; 3469} 3470EXPORT_SYMBOL(ath9k_hw_gpio_get); 3471 3472void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 3473 u32 ah_signal_type) 3474{ 3475 u32 gpio_shift; 3476 3477 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 3478 3479 gpio_shift = 2 * gpio; 3480 3481 REG_RMW(ah, 3482 AR_GPIO_OE_OUT, 3483 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 3484 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3485} 3486EXPORT_SYMBOL(ath9k_hw_cfg_output); 3487 3488void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 3489{ 3490 if (AR_SREV_9271(ah)) 3491 val = ~val; 3492 3493 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 3494 AR_GPIO_BIT(gpio)); 3495} 3496EXPORT_SYMBOL(ath9k_hw_set_gpio); 3497 3498u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 3499{ 3500 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 3501} 3502EXPORT_SYMBOL(ath9k_hw_getdefantenna); 3503 3504void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 3505{ 3506 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 3507} 3508EXPORT_SYMBOL(ath9k_hw_setantenna); 3509 3510/*********************/ 3511/* General Operation */ 3512/*********************/ 3513 3514u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 3515{ 3516 u32 bits = REG_READ(ah, AR_RX_FILTER); 3517 u32 phybits = REG_READ(ah, AR_PHY_ERR); 3518 3519 if (phybits & AR_PHY_ERR_RADAR) 3520 bits |= ATH9K_RX_FILTER_PHYRADAR; 3521 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 3522 bits |= ATH9K_RX_FILTER_PHYERR; 3523 3524 return bits; 3525} 3526EXPORT_SYMBOL(ath9k_hw_getrxfilter); 3527 3528void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 3529{ 3530 u32 phybits; 3531 3532 REG_WRITE(ah, AR_RX_FILTER, bits); 3533 3534 phybits = 0; 3535 if (bits & ATH9K_RX_FILTER_PHYRADAR) 3536 phybits |= AR_PHY_ERR_RADAR; 3537 if (bits & ATH9K_RX_FILTER_PHYERR) 3538 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 3539 REG_WRITE(ah, AR_PHY_ERR, phybits); 3540 3541 if (phybits) 3542 REG_WRITE(ah, AR_RXCFG, 3543 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 3544 else 3545 REG_WRITE(ah, AR_RXCFG, 3546 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 3547} 3548EXPORT_SYMBOL(ath9k_hw_setrxfilter); 3549 3550bool ath9k_hw_phy_disable(struct ath_hw *ah) 3551{ 3552 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 3553 return false; 3554 3555 ath9k_hw_init_pll(ah, NULL); 3556 return true; 3557} 3558EXPORT_SYMBOL(ath9k_hw_phy_disable); 3559 3560bool ath9k_hw_disable(struct ath_hw *ah) 3561{ 3562 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 3563 return false; 3564 3565 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 3566 return false; 3567 3568 ath9k_hw_init_pll(ah, NULL); 3569 return true; 3570} 3571EXPORT_SYMBOL(ath9k_hw_disable); 3572 3573void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 3574{ 3575 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 3576 struct ath9k_channel *chan = ah->curchan; 3577 struct ieee80211_channel *channel = chan->chan; 3578 3579 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 3580 3581 ah->eep_ops->set_txpower(ah, chan, 3582 ath9k_regd_get_ctl(regulatory, chan), 3583 channel->max_antenna_gain * 2, 3584 channel->max_power * 2, 3585 min((u32) MAX_RATE_POWER, 3586 (u32) regulatory->power_limit)); 3587} 3588EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 3589 3590void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) 3591{ 3592 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN); 3593} 3594EXPORT_SYMBOL(ath9k_hw_setmac); 3595 3596void ath9k_hw_setopmode(struct ath_hw *ah) 3597{ 3598 ath9k_hw_set_operating_mode(ah, ah->opmode); 3599} 3600EXPORT_SYMBOL(ath9k_hw_setopmode); 3601 3602void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 3603{ 3604 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 3605 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 3606} 3607EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 3608 3609void ath9k_hw_write_associd(struct ath_hw *ah) 3610{ 3611 struct ath_common *common = ath9k_hw_common(ah); 3612 3613 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 3614 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 3615 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 3616} 3617EXPORT_SYMBOL(ath9k_hw_write_associd); 3618 3619u64 ath9k_hw_gettsf64(struct ath_hw *ah) 3620{ 3621 u64 tsf; 3622 3623 tsf = REG_READ(ah, AR_TSF_U32); 3624 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); 3625 3626 return tsf; 3627} 3628EXPORT_SYMBOL(ath9k_hw_gettsf64); 3629 3630void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 3631{ 3632 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3633 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3634} 3635EXPORT_SYMBOL(ath9k_hw_settsf64); 3636 3637void ath9k_hw_reset_tsf(struct ath_hw *ah) 3638{ 3639 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 3640 AH_TSF_WRITE_TIMEOUT)) 3641 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 3642 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 3643 3644 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3645} 3646EXPORT_SYMBOL(ath9k_hw_reset_tsf); 3647 3648void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 3649{ 3650 if (setting) 3651 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 3652 else 3653 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 3654} 3655EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 3656 3657/* 3658 * Extend 15-bit time stamp from rx descriptor to 3659 * a full 64-bit TSF using the current h/w TSF. 3660*/ 3661u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp) 3662{ 3663 u64 tsf; 3664 3665 tsf = ath9k_hw_gettsf64(ah); 3666 if ((tsf & 0x7fff) < rstamp) 3667 tsf -= 0x8000; 3668 return (tsf & ~0x7fff) | rstamp; 3669} 3670EXPORT_SYMBOL(ath9k_hw_extend_tsf); 3671 3672void ath9k_hw_set11nmac2040(struct ath_hw *ah) 3673{ 3674 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 3675 u32 macmode; 3676 3677 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 3678 macmode = AR_2040_JOINED_RX_CLEAR; 3679 else 3680 macmode = 0; 3681 3682 REG_WRITE(ah, AR_2040_MODE, macmode); 3683} 3684 3685/* HW Generic timers configuration */ 3686 3687static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 3688{ 3689 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3690 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3691 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3692 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3693 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3694 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3695 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3696 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3697 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 3698 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 3699 AR_NDP2_TIMER_MODE, 0x0002}, 3700 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 3701 AR_NDP2_TIMER_MODE, 0x0004}, 3702 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 3703 AR_NDP2_TIMER_MODE, 0x0008}, 3704 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 3705 AR_NDP2_TIMER_MODE, 0x0010}, 3706 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 3707 AR_NDP2_TIMER_MODE, 0x0020}, 3708 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 3709 AR_NDP2_TIMER_MODE, 0x0040}, 3710 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 3711 AR_NDP2_TIMER_MODE, 0x0080} 3712}; 3713 3714/* HW generic timer primitives */ 3715 3716/* compute and clear index of rightmost 1 */ 3717static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 3718{ 3719 u32 b; 3720 3721 b = *mask; 3722 b &= (0-b); 3723 *mask &= ~b; 3724 b *= debruijn32; 3725 b >>= 27; 3726 3727 return timer_table->gen_timer_index[b]; 3728} 3729 3730u32 ath9k_hw_gettsf32(struct ath_hw *ah) 3731{ 3732 return REG_READ(ah, AR_TSF_L32); 3733} 3734EXPORT_SYMBOL(ath9k_hw_gettsf32); 3735 3736struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3737 void (*trigger)(void *), 3738 void (*overflow)(void *), 3739 void *arg, 3740 u8 timer_index) 3741{ 3742 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3743 struct ath_gen_timer *timer; 3744 3745 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3746 3747 if (timer == NULL) { 3748 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 3749 "Failed to allocate memory" 3750 "for hw timer[%d]\n", timer_index); 3751 return NULL; 3752 } 3753 3754 /* allocate a hardware generic timer slot */ 3755 timer_table->timers[timer_index] = timer; 3756 timer->index = timer_index; 3757 timer->trigger = trigger; 3758 timer->overflow = overflow; 3759 timer->arg = arg; 3760 3761 return timer; 3762} 3763EXPORT_SYMBOL(ath_gen_timer_alloc); 3764 3765void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3766 struct ath_gen_timer *timer, 3767 u32 timer_next, 3768 u32 timer_period) 3769{ 3770 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3771 u32 tsf; 3772 3773 BUG_ON(!timer_period); 3774 3775 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 3776 3777 tsf = ath9k_hw_gettsf32(ah); 3778 3779 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 3780 "curent tsf %x period %x" 3781 "timer_next %x\n", tsf, timer_period, timer_next); 3782 3783 /* 3784 * Pull timer_next forward if the current TSF already passed it 3785 * because of software latency 3786 */ 3787 if (timer_next < tsf) 3788 timer_next = tsf + timer_period; 3789 3790 /* 3791 * Program generic timer registers 3792 */ 3793 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3794 timer_next); 3795 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3796 timer_period); 3797 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3798 gen_tmr_configuration[timer->index].mode_mask); 3799 3800 /* Enable both trigger and thresh interrupt masks */ 3801 REG_SET_BIT(ah, AR_IMR_S5, 3802 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3803 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3804} 3805EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3806 3807void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3808{ 3809 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3810 3811 if ((timer->index < AR_FIRST_NDP_TIMER) || 3812 (timer->index >= ATH_MAX_GEN_TIMER)) { 3813 return; 3814 } 3815 3816 /* Clear generic timer enable bits. */ 3817 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3818 gen_tmr_configuration[timer->index].mode_mask); 3819 3820 /* Disable both trigger and thresh interrupt masks */ 3821 REG_CLR_BIT(ah, AR_IMR_S5, 3822 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3823 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3824 3825 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3826} 3827EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3828 3829void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3830{ 3831 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3832 3833 /* free the hardware generic timer slot */ 3834 timer_table->timers[timer->index] = NULL; 3835 kfree(timer); 3836} 3837EXPORT_SYMBOL(ath_gen_timer_free); 3838 3839/* 3840 * Generic Timer Interrupts handling 3841 */ 3842void ath_gen_timer_isr(struct ath_hw *ah) 3843{ 3844 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3845 struct ath_gen_timer *timer; 3846 struct ath_common *common = ath9k_hw_common(ah); 3847 u32 trigger_mask, thresh_mask, index; 3848 3849 /* get hardware generic timer interrupt status */ 3850 trigger_mask = ah->intr_gen_timer_trigger; 3851 thresh_mask = ah->intr_gen_timer_thresh; 3852 trigger_mask &= timer_table->timer_mask.val; 3853 thresh_mask &= timer_table->timer_mask.val; 3854 3855 trigger_mask &= ~thresh_mask; 3856 3857 while (thresh_mask) { 3858 index = rightmost_index(timer_table, &thresh_mask); 3859 timer = timer_table->timers[index]; 3860 BUG_ON(!timer); 3861 ath_print(common, ATH_DBG_HWTIMER, 3862 "TSF overflow for Gen timer %d\n", index); 3863 timer->overflow(timer->arg); 3864 } 3865 3866 while (trigger_mask) { 3867 index = rightmost_index(timer_table, &trigger_mask); 3868 timer = timer_table->timers[index]; 3869 BUG_ON(!timer); 3870 ath_print(common, ATH_DBG_HWTIMER, 3871 "Gen timer[%d] trigger\n", index); 3872 timer->trigger(timer->arg); 3873 } 3874} 3875EXPORT_SYMBOL(ath_gen_timer_isr); 3876 3877/********/ 3878/* HTC */ 3879/********/ 3880 3881void ath9k_hw_htc_resetinit(struct ath_hw *ah) 3882{ 3883 ah->htc_reset_init = true; 3884} 3885EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 3886 3887static struct { 3888 u32 version; 3889 const char * name; 3890} ath_mac_bb_names[] = { 3891 /* Devices with external radios */ 3892 { AR_SREV_VERSION_5416_PCI, "5416" }, 3893 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3894 { AR_SREV_VERSION_9100, "9100" }, 3895 { AR_SREV_VERSION_9160, "9160" }, 3896 /* Single-chip solutions */ 3897 { AR_SREV_VERSION_9280, "9280" }, 3898 { AR_SREV_VERSION_9285, "9285" }, 3899 { AR_SREV_VERSION_9287, "9287" }, 3900 { AR_SREV_VERSION_9271, "9271" }, 3901}; 3902 3903/* For devices with external radios */ 3904static struct { 3905 u16 version; 3906 const char * name; 3907} ath_rf_names[] = { 3908 { 0, "5133" }, 3909 { AR_RAD5133_SREV_MAJOR, "5133" }, 3910 { AR_RAD5122_SREV_MAJOR, "5122" }, 3911 { AR_RAD2133_SREV_MAJOR, "2133" }, 3912 { AR_RAD2122_SREV_MAJOR, "2122" } 3913}; 3914 3915/* 3916 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3917 */ 3918static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3919{ 3920 int i; 3921 3922 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3923 if (ath_mac_bb_names[i].version == mac_bb_version) { 3924 return ath_mac_bb_names[i].name; 3925 } 3926 } 3927 3928 return "????"; 3929} 3930 3931/* 3932 * Return the RF name. "????" is returned if the RF is unknown. 3933 * Used for devices with external radios. 3934 */ 3935static const char *ath9k_hw_rf_name(u16 rf_version) 3936{ 3937 int i; 3938 3939 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3940 if (ath_rf_names[i].version == rf_version) { 3941 return ath_rf_names[i].name; 3942 } 3943 } 3944 3945 return "????"; 3946} 3947 3948void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3949{ 3950 int used; 3951 3952 /* chipsets >= AR9280 are single-chip */ 3953 if (AR_SREV_9280_10_OR_LATER(ah)) { 3954 used = snprintf(hw_name, len, 3955 "Atheros AR%s Rev:%x", 3956 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3957 ah->hw_version.macRev); 3958 } 3959 else { 3960 used = snprintf(hw_name, len, 3961 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3962 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3963 ah->hw_version.macRev, 3964 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3965 AR_RADIO_SREV_MAJOR)), 3966 ah->hw_version.phyRev); 3967 } 3968 3969 hw_name[used] = '\0'; 3970} 3971EXPORT_SYMBOL(ath9k_hw_name); 3972