hw.c revision c774d57fd47c71675bb8c41a4dc2aafd78baa39d
1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <linux/module.h> 20#include <linux/time.h> 21#include <linux/bitops.h> 22#include <asm/unaligned.h> 23 24#include "hw.h" 25#include "hw-ops.h" 26#include "ar9003_mac.h" 27#include "ar9003_mci.h" 28#include "ar9003_phy.h" 29#include "ath9k.h" 30 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32 33MODULE_AUTHOR("Atheros Communications"); 34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 36MODULE_LICENSE("Dual BSD/GPL"); 37 38static void ath9k_hw_set_clockrate(struct ath_hw *ah) 39{ 40 struct ath_common *common = ath9k_hw_common(ah); 41 struct ath9k_channel *chan = ah->curchan; 42 unsigned int clockrate; 43 44 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 45 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 46 clockrate = 117; 47 else if (!chan) /* should really check for CCK instead */ 48 clockrate = ATH9K_CLOCK_RATE_CCK; 49 else if (IS_CHAN_2GHZ(chan)) 50 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 51 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 52 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 53 else 54 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 55 56 if (chan) { 57 if (IS_CHAN_HT40(chan)) 58 clockrate *= 2; 59 if (IS_CHAN_HALF_RATE(chan)) 60 clockrate /= 2; 61 if (IS_CHAN_QUARTER_RATE(chan)) 62 clockrate /= 4; 63 } 64 65 common->clockrate = clockrate; 66} 67 68static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 69{ 70 struct ath_common *common = ath9k_hw_common(ah); 71 72 return usecs * common->clockrate; 73} 74 75bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 76{ 77 int i; 78 79 BUG_ON(timeout < AH_TIME_QUANTUM); 80 81 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 82 if ((REG_READ(ah, reg) & mask) == val) 83 return true; 84 85 udelay(AH_TIME_QUANTUM); 86 } 87 88 ath_dbg(ath9k_hw_common(ah), ANY, 89 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 90 timeout, reg, REG_READ(ah, reg), mask, val); 91 92 return false; 93} 94EXPORT_SYMBOL(ath9k_hw_wait); 95 96void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 97 int hw_delay) 98{ 99 hw_delay /= 10; 100 101 if (IS_CHAN_HALF_RATE(chan)) 102 hw_delay *= 2; 103 else if (IS_CHAN_QUARTER_RATE(chan)) 104 hw_delay *= 4; 105 106 udelay(hw_delay + BASE_ACTIVATE_DELAY); 107} 108 109void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 110 int column, unsigned int *writecnt) 111{ 112 int r; 113 114 ENABLE_REGWRITE_BUFFER(ah); 115 for (r = 0; r < array->ia_rows; r++) { 116 REG_WRITE(ah, INI_RA(array, r, 0), 117 INI_RA(array, r, column)); 118 DO_DELAY(*writecnt); 119 } 120 REGWRITE_BUFFER_FLUSH(ah); 121} 122 123u32 ath9k_hw_reverse_bits(u32 val, u32 n) 124{ 125 u32 retval; 126 int i; 127 128 for (i = 0, retval = 0; i < n; i++) { 129 retval = (retval << 1) | (val & 1); 130 val >>= 1; 131 } 132 return retval; 133} 134 135u16 ath9k_hw_computetxtime(struct ath_hw *ah, 136 u8 phy, int kbps, 137 u32 frameLen, u16 rateix, 138 bool shortPreamble) 139{ 140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 141 142 if (kbps == 0) 143 return 0; 144 145 switch (phy) { 146 case WLAN_RC_PHY_CCK: 147 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 148 if (shortPreamble) 149 phyTime >>= 1; 150 numBits = frameLen << 3; 151 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 152 break; 153 case WLAN_RC_PHY_OFDM: 154 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 155 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 156 numBits = OFDM_PLCP_BITS + (frameLen << 3); 157 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 158 txTime = OFDM_SIFS_TIME_QUARTER 159 + OFDM_PREAMBLE_TIME_QUARTER 160 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 161 } else if (ah->curchan && 162 IS_CHAN_HALF_RATE(ah->curchan)) { 163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 164 numBits = OFDM_PLCP_BITS + (frameLen << 3); 165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 166 txTime = OFDM_SIFS_TIME_HALF + 167 OFDM_PREAMBLE_TIME_HALF 168 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 169 } else { 170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 171 numBits = OFDM_PLCP_BITS + (frameLen << 3); 172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 173 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 174 + (numSymbols * OFDM_SYMBOL_TIME); 175 } 176 break; 177 default: 178 ath_err(ath9k_hw_common(ah), 179 "Unknown phy %u (rate ix %u)\n", phy, rateix); 180 txTime = 0; 181 break; 182 } 183 184 return txTime; 185} 186EXPORT_SYMBOL(ath9k_hw_computetxtime); 187 188void ath9k_hw_get_channel_centers(struct ath_hw *ah, 189 struct ath9k_channel *chan, 190 struct chan_centers *centers) 191{ 192 int8_t extoff; 193 194 if (!IS_CHAN_HT40(chan)) { 195 centers->ctl_center = centers->ext_center = 196 centers->synth_center = chan->channel; 197 return; 198 } 199 200 if (IS_CHAN_HT40PLUS(chan)) { 201 centers->synth_center = 202 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 203 extoff = 1; 204 } else { 205 centers->synth_center = 206 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 207 extoff = -1; 208 } 209 210 centers->ctl_center = 211 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 212 /* 25 MHz spacing is supported by hw but not on upper layers */ 213 centers->ext_center = 214 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 215} 216 217/******************/ 218/* Chip Revisions */ 219/******************/ 220 221static void ath9k_hw_read_revisions(struct ath_hw *ah) 222{ 223 u32 val; 224 225 switch (ah->hw_version.devid) { 226 case AR5416_AR9100_DEVID: 227 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 228 break; 229 case AR9300_DEVID_AR9330: 230 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 231 if (ah->get_mac_revision) { 232 ah->hw_version.macRev = ah->get_mac_revision(); 233 } else { 234 val = REG_READ(ah, AR_SREV); 235 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 236 } 237 return; 238 case AR9300_DEVID_AR9340: 239 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 240 val = REG_READ(ah, AR_SREV); 241 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 242 return; 243 case AR9300_DEVID_QCA955X: 244 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 245 return; 246 case AR9300_DEVID_AR953X: 247 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 248 if (ah->get_mac_revision) 249 ah->hw_version.macRev = ah->get_mac_revision(); 250 return; 251 } 252 253 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 254 255 if (val == 0xFF) { 256 val = REG_READ(ah, AR_SREV); 257 ah->hw_version.macVersion = 258 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 259 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 260 261 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 262 ah->is_pciexpress = true; 263 else 264 ah->is_pciexpress = (val & 265 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 266 } else { 267 if (!AR_SREV_9100(ah)) 268 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 269 270 ah->hw_version.macRev = val & AR_SREV_REVISION; 271 272 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 273 ah->is_pciexpress = true; 274 } 275} 276 277/************************************/ 278/* HW Attach, Detach, Init Routines */ 279/************************************/ 280 281static void ath9k_hw_disablepcie(struct ath_hw *ah) 282{ 283 if (!AR_SREV_5416(ah)) 284 return; 285 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 293 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 294 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 295 296 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 297} 298 299/* This should work for all families including legacy */ 300static bool ath9k_hw_chip_test(struct ath_hw *ah) 301{ 302 struct ath_common *common = ath9k_hw_common(ah); 303 u32 regAddr[2] = { AR_STA_ID0 }; 304 u32 regHold[2]; 305 static const u32 patternData[4] = { 306 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 307 }; 308 int i, j, loop_max; 309 310 if (!AR_SREV_9300_20_OR_LATER(ah)) { 311 loop_max = 2; 312 regAddr[1] = AR_PHY_BASE + (8 << 2); 313 } else 314 loop_max = 1; 315 316 for (i = 0; i < loop_max; i++) { 317 u32 addr = regAddr[i]; 318 u32 wrData, rdData; 319 320 regHold[i] = REG_READ(ah, addr); 321 for (j = 0; j < 0x100; j++) { 322 wrData = (j << 16) | j; 323 REG_WRITE(ah, addr, wrData); 324 rdData = REG_READ(ah, addr); 325 if (rdData != wrData) { 326 ath_err(common, 327 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 328 addr, wrData, rdData); 329 return false; 330 } 331 } 332 for (j = 0; j < 4; j++) { 333 wrData = patternData[j]; 334 REG_WRITE(ah, addr, wrData); 335 rdData = REG_READ(ah, addr); 336 if (wrData != rdData) { 337 ath_err(common, 338 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 339 addr, wrData, rdData); 340 return false; 341 } 342 } 343 REG_WRITE(ah, regAddr[i], regHold[i]); 344 } 345 udelay(100); 346 347 return true; 348} 349 350static void ath9k_hw_init_config(struct ath_hw *ah) 351{ 352 struct ath_common *common = ath9k_hw_common(ah); 353 354 ah->config.dma_beacon_response_time = 1; 355 ah->config.sw_beacon_response_time = 6; 356 ah->config.cwm_ignore_extcca = 0; 357 ah->config.analog_shiftreg = 1; 358 359 ah->config.rx_intr_mitigation = true; 360 361 if (AR_SREV_9300_20_OR_LATER(ah)) { 362 ah->config.rimt_last = 500; 363 ah->config.rimt_first = 2000; 364 } else { 365 ah->config.rimt_last = 250; 366 ah->config.rimt_first = 700; 367 } 368 369 /* 370 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 371 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 372 * This means we use it for all AR5416 devices, and the few 373 * minor PCI AR9280 devices out there. 374 * 375 * Serialization is required because these devices do not handle 376 * well the case of two concurrent reads/writes due to the latency 377 * involved. During one read/write another read/write can be issued 378 * on another CPU while the previous read/write may still be working 379 * on our hardware, if we hit this case the hardware poops in a loop. 380 * We prevent this by serializing reads and writes. 381 * 382 * This issue is not present on PCI-Express devices or pre-AR5416 383 * devices (legacy, 802.11abg). 384 */ 385 if (num_possible_cpus() > 1) 386 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 387 388 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 389 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 390 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 391 !ah->is_pciexpress)) { 392 ah->config.serialize_regmode = SER_REG_MODE_ON; 393 } else { 394 ah->config.serialize_regmode = SER_REG_MODE_OFF; 395 } 396 } 397 398 ath_dbg(common, RESET, "serialize_regmode is %d\n", 399 ah->config.serialize_regmode); 400 401 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 402 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 403 else 404 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 405} 406 407static void ath9k_hw_init_defaults(struct ath_hw *ah) 408{ 409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 410 411 regulatory->country_code = CTRY_DEFAULT; 412 regulatory->power_limit = MAX_RATE_POWER; 413 414 ah->hw_version.magic = AR5416_MAGIC; 415 ah->hw_version.subvendorid = 0; 416 417 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 418 AR_STA_ID1_MCAST_KSRCH; 419 if (AR_SREV_9100(ah)) 420 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 421 422 ah->slottime = ATH9K_SLOT_TIME_9; 423 ah->globaltxtimeout = (u32) -1; 424 ah->power_mode = ATH9K_PM_UNDEFINED; 425 ah->htc_reset_init = true; 426 427 ah->ani_function = ATH9K_ANI_ALL; 428 if (!AR_SREV_9300_20_OR_LATER(ah)) 429 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 430 431 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 432 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 433 else 434 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 435} 436 437static int ath9k_hw_init_macaddr(struct ath_hw *ah) 438{ 439 struct ath_common *common = ath9k_hw_common(ah); 440 u32 sum; 441 int i; 442 u16 eeval; 443 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 444 445 sum = 0; 446 for (i = 0; i < 3; i++) { 447 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 448 sum += eeval; 449 common->macaddr[2 * i] = eeval >> 8; 450 common->macaddr[2 * i + 1] = eeval & 0xff; 451 } 452 if (sum == 0 || sum == 0xffff * 3) 453 return -EADDRNOTAVAIL; 454 455 return 0; 456} 457 458static int ath9k_hw_post_init(struct ath_hw *ah) 459{ 460 struct ath_common *common = ath9k_hw_common(ah); 461 int ecode; 462 463 if (common->bus_ops->ath_bus_type != ATH_USB) { 464 if (!ath9k_hw_chip_test(ah)) 465 return -ENODEV; 466 } 467 468 if (!AR_SREV_9300_20_OR_LATER(ah)) { 469 ecode = ar9002_hw_rf_claim(ah); 470 if (ecode != 0) 471 return ecode; 472 } 473 474 ecode = ath9k_hw_eeprom_init(ah); 475 if (ecode != 0) 476 return ecode; 477 478 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 479 ah->eep_ops->get_eeprom_ver(ah), 480 ah->eep_ops->get_eeprom_rev(ah)); 481 482 ath9k_hw_ani_init(ah); 483 484 /* 485 * EEPROM needs to be initialized before we do this. 486 * This is required for regulatory compliance. 487 */ 488 if (AR_SREV_9300_20_OR_LATER(ah)) { 489 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 490 if ((regdmn & 0xF0) == CTL_FCC) { 491 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 492 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 493 } 494 } 495 496 return 0; 497} 498 499static int ath9k_hw_attach_ops(struct ath_hw *ah) 500{ 501 if (!AR_SREV_9300_20_OR_LATER(ah)) 502 return ar9002_hw_attach_ops(ah); 503 504 ar9003_hw_attach_ops(ah); 505 return 0; 506} 507 508/* Called for all hardware families */ 509static int __ath9k_hw_init(struct ath_hw *ah) 510{ 511 struct ath_common *common = ath9k_hw_common(ah); 512 int r = 0; 513 514 ath9k_hw_read_revisions(ah); 515 516 switch (ah->hw_version.macVersion) { 517 case AR_SREV_VERSION_5416_PCI: 518 case AR_SREV_VERSION_5416_PCIE: 519 case AR_SREV_VERSION_9160: 520 case AR_SREV_VERSION_9100: 521 case AR_SREV_VERSION_9280: 522 case AR_SREV_VERSION_9285: 523 case AR_SREV_VERSION_9287: 524 case AR_SREV_VERSION_9271: 525 case AR_SREV_VERSION_9300: 526 case AR_SREV_VERSION_9330: 527 case AR_SREV_VERSION_9485: 528 case AR_SREV_VERSION_9340: 529 case AR_SREV_VERSION_9462: 530 case AR_SREV_VERSION_9550: 531 case AR_SREV_VERSION_9565: 532 case AR_SREV_VERSION_9531: 533 break; 534 default: 535 ath_err(common, 536 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 537 ah->hw_version.macVersion, ah->hw_version.macRev); 538 return -EOPNOTSUPP; 539 } 540 541 /* 542 * Read back AR_WA into a permanent copy and set bits 14 and 17. 543 * We need to do this to avoid RMW of this register. We cannot 544 * read the reg when chip is asleep. 545 */ 546 if (AR_SREV_9300_20_OR_LATER(ah)) { 547 ah->WARegVal = REG_READ(ah, AR_WA); 548 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 549 AR_WA_ASPM_TIMER_BASED_DISABLE); 550 } 551 552 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 553 ath_err(common, "Couldn't reset chip\n"); 554 return -EIO; 555 } 556 557 if (AR_SREV_9565(ah)) { 558 ah->WARegVal |= AR_WA_BIT22; 559 REG_WRITE(ah, AR_WA, ah->WARegVal); 560 } 561 562 ath9k_hw_init_defaults(ah); 563 ath9k_hw_init_config(ah); 564 565 r = ath9k_hw_attach_ops(ah); 566 if (r) 567 return r; 568 569 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 570 ath_err(common, "Couldn't wakeup chip\n"); 571 return -EIO; 572 } 573 574 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 575 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 576 ah->is_pciexpress = false; 577 578 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 579 ath9k_hw_init_cal_settings(ah); 580 581 if (!ah->is_pciexpress) 582 ath9k_hw_disablepcie(ah); 583 584 r = ath9k_hw_post_init(ah); 585 if (r) 586 return r; 587 588 ath9k_hw_init_mode_gain_regs(ah); 589 r = ath9k_hw_fill_cap_info(ah); 590 if (r) 591 return r; 592 593 r = ath9k_hw_init_macaddr(ah); 594 if (r) { 595 ath_err(common, "Failed to initialize MAC address\n"); 596 return r; 597 } 598 599 ath9k_hw_init_hang_checks(ah); 600 601 common->state = ATH_HW_INITIALIZED; 602 603 return 0; 604} 605 606int ath9k_hw_init(struct ath_hw *ah) 607{ 608 int ret; 609 struct ath_common *common = ath9k_hw_common(ah); 610 611 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 612 switch (ah->hw_version.devid) { 613 case AR5416_DEVID_PCI: 614 case AR5416_DEVID_PCIE: 615 case AR5416_AR9100_DEVID: 616 case AR9160_DEVID_PCI: 617 case AR9280_DEVID_PCI: 618 case AR9280_DEVID_PCIE: 619 case AR9285_DEVID_PCIE: 620 case AR9287_DEVID_PCI: 621 case AR9287_DEVID_PCIE: 622 case AR2427_DEVID_PCIE: 623 case AR9300_DEVID_PCIE: 624 case AR9300_DEVID_AR9485_PCIE: 625 case AR9300_DEVID_AR9330: 626 case AR9300_DEVID_AR9340: 627 case AR9300_DEVID_QCA955X: 628 case AR9300_DEVID_AR9580: 629 case AR9300_DEVID_AR9462: 630 case AR9485_DEVID_AR1111: 631 case AR9300_DEVID_AR9565: 632 case AR9300_DEVID_AR953X: 633 break; 634 default: 635 if (common->bus_ops->ath_bus_type == ATH_USB) 636 break; 637 ath_err(common, "Hardware device ID 0x%04x not supported\n", 638 ah->hw_version.devid); 639 return -EOPNOTSUPP; 640 } 641 642 ret = __ath9k_hw_init(ah); 643 if (ret) { 644 ath_err(common, 645 "Unable to initialize hardware; initialization status: %d\n", 646 ret); 647 return ret; 648 } 649 650 ath_dynack_init(ah); 651 652 return 0; 653} 654EXPORT_SYMBOL(ath9k_hw_init); 655 656static void ath9k_hw_init_qos(struct ath_hw *ah) 657{ 658 ENABLE_REGWRITE_BUFFER(ah); 659 660 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 661 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 662 663 REG_WRITE(ah, AR_QOS_NO_ACK, 664 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 665 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 666 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 667 668 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 669 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 670 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 671 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 672 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 673 674 REGWRITE_BUFFER_FLUSH(ah); 675} 676 677u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 678{ 679 struct ath_common *common = ath9k_hw_common(ah); 680 int i = 0; 681 682 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 683 udelay(100); 684 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 685 686 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 687 688 udelay(100); 689 690 if (WARN_ON_ONCE(i >= 100)) { 691 ath_err(common, "PLL4 meaurement not done\n"); 692 break; 693 } 694 695 i++; 696 } 697 698 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 699} 700EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 701 702static void ath9k_hw_init_pll(struct ath_hw *ah, 703 struct ath9k_channel *chan) 704{ 705 u32 pll; 706 707 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 708 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 709 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 710 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 712 AR_CH0_DPLL2_KD, 0x40); 713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 714 AR_CH0_DPLL2_KI, 0x4); 715 716 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 717 AR_CH0_BB_DPLL1_REFDIV, 0x5); 718 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 719 AR_CH0_BB_DPLL1_NINI, 0x58); 720 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 721 AR_CH0_BB_DPLL1_NFRAC, 0x0); 722 723 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 724 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 725 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 726 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 727 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 728 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 729 730 /* program BB PLL phase_shift to 0x6 */ 731 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 732 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 733 734 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 735 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 736 udelay(1000); 737 } else if (AR_SREV_9330(ah)) { 738 u32 ddr_dpll2, pll_control2, kd; 739 740 if (ah->is_clk_25mhz) { 741 ddr_dpll2 = 0x18e82f01; 742 pll_control2 = 0xe04a3d; 743 kd = 0x1d; 744 } else { 745 ddr_dpll2 = 0x19e82f01; 746 pll_control2 = 0x886666; 747 kd = 0x3d; 748 } 749 750 /* program DDR PLL ki and kd value */ 751 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 752 753 /* program DDR PLL phase_shift */ 754 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 755 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 756 757 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 758 udelay(1000); 759 760 /* program refdiv, nint, frac to RTC register */ 761 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 762 763 /* program BB PLL kd and ki value */ 764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 766 767 /* program BB PLL phase_shift */ 768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 769 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 770 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 771 u32 regval, pll2_divint, pll2_divfrac, refdiv; 772 773 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 774 udelay(1000); 775 776 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 777 udelay(100); 778 779 if (ah->is_clk_25mhz) { 780 if (AR_SREV_9531(ah)) { 781 pll2_divint = 0x1c; 782 pll2_divfrac = 0xa3d2; 783 refdiv = 1; 784 } else { 785 pll2_divint = 0x54; 786 pll2_divfrac = 0x1eb85; 787 refdiv = 3; 788 } 789 } else { 790 if (AR_SREV_9340(ah)) { 791 pll2_divint = 88; 792 pll2_divfrac = 0; 793 refdiv = 5; 794 } else { 795 pll2_divint = 0x11; 796 pll2_divfrac = 797 AR_SREV_9531(ah) ? 0x26665 : 0x26666; 798 refdiv = 1; 799 } 800 } 801 802 regval = REG_READ(ah, AR_PHY_PLL_MODE); 803 if (AR_SREV_9531(ah)) 804 regval |= (0x1 << 22); 805 else 806 regval |= (0x1 << 16); 807 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 808 udelay(100); 809 810 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 811 (pll2_divint << 18) | pll2_divfrac); 812 udelay(100); 813 814 regval = REG_READ(ah, AR_PHY_PLL_MODE); 815 if (AR_SREV_9340(ah)) 816 regval = (regval & 0x80071fff) | 817 (0x1 << 30) | 818 (0x1 << 13) | 819 (0x4 << 26) | 820 (0x18 << 19); 821 else if (AR_SREV_9531(ah)) 822 regval = (regval & 0x01c00fff) | 823 (0x1 << 31) | 824 (0x2 << 29) | 825 (0xa << 25) | 826 (0x1 << 19) | 827 (0x6 << 12); 828 else 829 regval = (regval & 0x80071fff) | 830 (0x3 << 30) | 831 (0x1 << 13) | 832 (0x4 << 26) | 833 (0x60 << 19); 834 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 835 836 if (AR_SREV_9531(ah)) 837 REG_WRITE(ah, AR_PHY_PLL_MODE, 838 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 839 else 840 REG_WRITE(ah, AR_PHY_PLL_MODE, 841 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 842 843 udelay(1000); 844 } 845 846 pll = ath9k_hw_compute_pll_control(ah, chan); 847 if (AR_SREV_9565(ah)) 848 pll |= 0x40000; 849 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 850 851 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 852 AR_SREV_9550(ah)) 853 udelay(1000); 854 855 /* Switch the core clock for ar9271 to 117Mhz */ 856 if (AR_SREV_9271(ah)) { 857 udelay(500); 858 REG_WRITE(ah, 0x50040, 0x304); 859 } 860 861 udelay(RTC_PLL_SETTLE_DELAY); 862 863 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 864 865 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 866 if (ah->is_clk_25mhz) { 867 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 868 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 869 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 870 } else { 871 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 872 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 873 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 874 } 875 udelay(100); 876 } 877} 878 879static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 880 enum nl80211_iftype opmode) 881{ 882 u32 sync_default = AR_INTR_SYNC_DEFAULT; 883 u32 imr_reg = AR_IMR_TXERR | 884 AR_IMR_TXURN | 885 AR_IMR_RXERR | 886 AR_IMR_RXORN | 887 AR_IMR_BCNMISC; 888 889 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) 890 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 891 892 if (AR_SREV_9300_20_OR_LATER(ah)) { 893 imr_reg |= AR_IMR_RXOK_HP; 894 if (ah->config.rx_intr_mitigation) 895 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 896 else 897 imr_reg |= AR_IMR_RXOK_LP; 898 899 } else { 900 if (ah->config.rx_intr_mitigation) 901 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 902 else 903 imr_reg |= AR_IMR_RXOK; 904 } 905 906 if (ah->config.tx_intr_mitigation) 907 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 908 else 909 imr_reg |= AR_IMR_TXOK; 910 911 ENABLE_REGWRITE_BUFFER(ah); 912 913 REG_WRITE(ah, AR_IMR, imr_reg); 914 ah->imrs2_reg |= AR_IMR_S2_GTT; 915 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 916 917 if (!AR_SREV_9100(ah)) { 918 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 919 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 920 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 921 } 922 923 REGWRITE_BUFFER_FLUSH(ah); 924 925 if (AR_SREV_9300_20_OR_LATER(ah)) { 926 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 927 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 928 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 929 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 930 } 931} 932 933static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 934{ 935 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 936 val = min(val, (u32) 0xFFFF); 937 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 938} 939 940void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 941{ 942 u32 val = ath9k_hw_mac_to_clks(ah, us); 943 val = min(val, (u32) 0xFFFF); 944 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 945} 946 947void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 948{ 949 u32 val = ath9k_hw_mac_to_clks(ah, us); 950 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 951 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 952} 953 954void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 955{ 956 u32 val = ath9k_hw_mac_to_clks(ah, us); 957 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 958 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 959} 960 961static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 962{ 963 if (tu > 0xFFFF) { 964 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 965 tu); 966 ah->globaltxtimeout = (u32) -1; 967 return false; 968 } else { 969 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 970 ah->globaltxtimeout = tu; 971 return true; 972 } 973} 974 975void ath9k_hw_init_global_settings(struct ath_hw *ah) 976{ 977 struct ath_common *common = ath9k_hw_common(ah); 978 const struct ath9k_channel *chan = ah->curchan; 979 int acktimeout, ctstimeout, ack_offset = 0; 980 int slottime; 981 int sifstime; 982 int rx_lat = 0, tx_lat = 0, eifs = 0; 983 u32 reg; 984 985 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 986 ah->misc_mode); 987 988 if (!chan) 989 return; 990 991 if (ah->misc_mode != 0) 992 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 993 994 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 995 rx_lat = 41; 996 else 997 rx_lat = 37; 998 tx_lat = 54; 999 1000 if (IS_CHAN_5GHZ(chan)) 1001 sifstime = 16; 1002 else 1003 sifstime = 10; 1004 1005 if (IS_CHAN_HALF_RATE(chan)) { 1006 eifs = 175; 1007 rx_lat *= 2; 1008 tx_lat *= 2; 1009 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1010 tx_lat += 11; 1011 1012 sifstime = 32; 1013 ack_offset = 16; 1014 slottime = 13; 1015 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1016 eifs = 340; 1017 rx_lat = (rx_lat * 4) - 1; 1018 tx_lat *= 4; 1019 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1020 tx_lat += 22; 1021 1022 sifstime = 64; 1023 ack_offset = 32; 1024 slottime = 21; 1025 } else { 1026 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1027 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1028 reg = AR_USEC_ASYNC_FIFO; 1029 } else { 1030 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1031 common->clockrate; 1032 reg = REG_READ(ah, AR_USEC); 1033 } 1034 rx_lat = MS(reg, AR_USEC_RX_LAT); 1035 tx_lat = MS(reg, AR_USEC_TX_LAT); 1036 1037 slottime = ah->slottime; 1038 } 1039 1040 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1041 slottime += 3 * ah->coverage_class; 1042 acktimeout = slottime + sifstime + ack_offset; 1043 ctstimeout = acktimeout; 1044 1045 /* 1046 * Workaround for early ACK timeouts, add an offset to match the 1047 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1048 * This was initially only meant to work around an issue with delayed 1049 * BA frames in some implementations, but it has been found to fix ACK 1050 * timeout issues in other cases as well. 1051 */ 1052 if (IS_CHAN_2GHZ(chan) && 1053 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1054 acktimeout += 64 - sifstime - ah->slottime; 1055 ctstimeout += 48 - sifstime - ah->slottime; 1056 } 1057 1058 ath9k_hw_set_sifs_time(ah, sifstime); 1059 ath9k_hw_setslottime(ah, slottime); 1060 ath9k_hw_set_ack_timeout(ah, acktimeout); 1061 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1062 if (ah->globaltxtimeout != (u32) -1) 1063 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1064 1065 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1066 REG_RMW(ah, AR_USEC, 1067 (common->clockrate - 1) | 1068 SM(rx_lat, AR_USEC_RX_LAT) | 1069 SM(tx_lat, AR_USEC_TX_LAT), 1070 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1071 1072} 1073EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1074 1075void ath9k_hw_deinit(struct ath_hw *ah) 1076{ 1077 struct ath_common *common = ath9k_hw_common(ah); 1078 1079 if (common->state < ATH_HW_INITIALIZED) 1080 return; 1081 1082 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1083} 1084EXPORT_SYMBOL(ath9k_hw_deinit); 1085 1086/*******/ 1087/* INI */ 1088/*******/ 1089 1090u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1091{ 1092 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1093 1094 if (IS_CHAN_2GHZ(chan)) 1095 ctl |= CTL_11G; 1096 else 1097 ctl |= CTL_11A; 1098 1099 return ctl; 1100} 1101 1102/****************************************/ 1103/* Reset and Channel Switching Routines */ 1104/****************************************/ 1105 1106static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1107{ 1108 struct ath_common *common = ath9k_hw_common(ah); 1109 int txbuf_size; 1110 1111 ENABLE_REGWRITE_BUFFER(ah); 1112 1113 /* 1114 * set AHB_MODE not to do cacheline prefetches 1115 */ 1116 if (!AR_SREV_9300_20_OR_LATER(ah)) 1117 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1118 1119 /* 1120 * let mac dma reads be in 128 byte chunks 1121 */ 1122 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1123 1124 REGWRITE_BUFFER_FLUSH(ah); 1125 1126 /* 1127 * Restore TX Trigger Level to its pre-reset value. 1128 * The initial value depends on whether aggregation is enabled, and is 1129 * adjusted whenever underruns are detected. 1130 */ 1131 if (!AR_SREV_9300_20_OR_LATER(ah)) 1132 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1133 1134 ENABLE_REGWRITE_BUFFER(ah); 1135 1136 /* 1137 * let mac dma writes be in 128 byte chunks 1138 */ 1139 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1140 1141 /* 1142 * Setup receive FIFO threshold to hold off TX activities 1143 */ 1144 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1145 1146 if (AR_SREV_9300_20_OR_LATER(ah)) { 1147 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1148 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1149 1150 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1151 ah->caps.rx_status_len); 1152 } 1153 1154 /* 1155 * reduce the number of usable entries in PCU TXBUF to avoid 1156 * wrap around issues. 1157 */ 1158 if (AR_SREV_9285(ah)) { 1159 /* For AR9285 the number of Fifos are reduced to half. 1160 * So set the usable tx buf size also to half to 1161 * avoid data/delimiter underruns 1162 */ 1163 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1164 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1165 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1166 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1167 } else { 1168 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1169 } 1170 1171 if (!AR_SREV_9271(ah)) 1172 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1173 1174 REGWRITE_BUFFER_FLUSH(ah); 1175 1176 if (AR_SREV_9300_20_OR_LATER(ah)) 1177 ath9k_hw_reset_txstatus_ring(ah); 1178} 1179 1180static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1181{ 1182 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1183 u32 set = AR_STA_ID1_KSRCH_MODE; 1184 1185 switch (opmode) { 1186 case NL80211_IFTYPE_ADHOC: 1187 set |= AR_STA_ID1_ADHOC; 1188 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1189 break; 1190 case NL80211_IFTYPE_MESH_POINT: 1191 case NL80211_IFTYPE_AP: 1192 set |= AR_STA_ID1_STA_AP; 1193 /* fall through */ 1194 case NL80211_IFTYPE_STATION: 1195 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1196 break; 1197 default: 1198 if (!ah->is_monitoring) 1199 set = 0; 1200 break; 1201 } 1202 REG_RMW(ah, AR_STA_ID1, set, mask); 1203} 1204 1205void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1206 u32 *coef_mantissa, u32 *coef_exponent) 1207{ 1208 u32 coef_exp, coef_man; 1209 1210 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1211 if ((coef_scaled >> coef_exp) & 0x1) 1212 break; 1213 1214 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1215 1216 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1217 1218 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1219 *coef_exponent = coef_exp - 16; 1220} 1221 1222/* AR9330 WAR: 1223 * call external reset function to reset WMAC if: 1224 * - doing a cold reset 1225 * - we have pending frames in the TX queues. 1226 */ 1227static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1228{ 1229 int i, npend = 0; 1230 1231 for (i = 0; i < AR_NUM_QCU; i++) { 1232 npend = ath9k_hw_numtxpending(ah, i); 1233 if (npend) 1234 break; 1235 } 1236 1237 if (ah->external_reset && 1238 (npend || type == ATH9K_RESET_COLD)) { 1239 int reset_err = 0; 1240 1241 ath_dbg(ath9k_hw_common(ah), RESET, 1242 "reset MAC via external reset\n"); 1243 1244 reset_err = ah->external_reset(); 1245 if (reset_err) { 1246 ath_err(ath9k_hw_common(ah), 1247 "External reset failed, err=%d\n", 1248 reset_err); 1249 return false; 1250 } 1251 1252 REG_WRITE(ah, AR_RTC_RESET, 1); 1253 } 1254 1255 return true; 1256} 1257 1258static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1259{ 1260 u32 rst_flags; 1261 u32 tmpReg; 1262 1263 if (AR_SREV_9100(ah)) { 1264 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1265 AR_RTC_DERIVED_CLK_PERIOD, 1); 1266 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1267 } 1268 1269 ENABLE_REGWRITE_BUFFER(ah); 1270 1271 if (AR_SREV_9300_20_OR_LATER(ah)) { 1272 REG_WRITE(ah, AR_WA, ah->WARegVal); 1273 udelay(10); 1274 } 1275 1276 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1277 AR_RTC_FORCE_WAKE_ON_INT); 1278 1279 if (AR_SREV_9100(ah)) { 1280 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1281 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1282 } else { 1283 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1284 if (AR_SREV_9340(ah)) 1285 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1286 else 1287 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1288 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1289 1290 if (tmpReg) { 1291 u32 val; 1292 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1293 1294 val = AR_RC_HOSTIF; 1295 if (!AR_SREV_9300_20_OR_LATER(ah)) 1296 val |= AR_RC_AHB; 1297 REG_WRITE(ah, AR_RC, val); 1298 1299 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1300 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1301 1302 rst_flags = AR_RTC_RC_MAC_WARM; 1303 if (type == ATH9K_RESET_COLD) 1304 rst_flags |= AR_RTC_RC_MAC_COLD; 1305 } 1306 1307 if (AR_SREV_9330(ah)) { 1308 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1309 return false; 1310 } 1311 1312 if (ath9k_hw_mci_is_enabled(ah)) 1313 ar9003_mci_check_gpm_offset(ah); 1314 1315 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1316 1317 REGWRITE_BUFFER_FLUSH(ah); 1318 1319 if (AR_SREV_9300_20_OR_LATER(ah)) 1320 udelay(50); 1321 else if (AR_SREV_9100(ah)) 1322 mdelay(10); 1323 else 1324 udelay(100); 1325 1326 REG_WRITE(ah, AR_RTC_RC, 0); 1327 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1328 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1329 return false; 1330 } 1331 1332 if (!AR_SREV_9100(ah)) 1333 REG_WRITE(ah, AR_RC, 0); 1334 1335 if (AR_SREV_9100(ah)) 1336 udelay(50); 1337 1338 return true; 1339} 1340 1341static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1342{ 1343 ENABLE_REGWRITE_BUFFER(ah); 1344 1345 if (AR_SREV_9300_20_OR_LATER(ah)) { 1346 REG_WRITE(ah, AR_WA, ah->WARegVal); 1347 udelay(10); 1348 } 1349 1350 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1351 AR_RTC_FORCE_WAKE_ON_INT); 1352 1353 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1354 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1355 1356 REG_WRITE(ah, AR_RTC_RESET, 0); 1357 1358 REGWRITE_BUFFER_FLUSH(ah); 1359 1360 udelay(2); 1361 1362 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1363 REG_WRITE(ah, AR_RC, 0); 1364 1365 REG_WRITE(ah, AR_RTC_RESET, 1); 1366 1367 if (!ath9k_hw_wait(ah, 1368 AR_RTC_STATUS, 1369 AR_RTC_STATUS_M, 1370 AR_RTC_STATUS_ON, 1371 AH_WAIT_TIMEOUT)) { 1372 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1373 return false; 1374 } 1375 1376 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1377} 1378 1379static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1380{ 1381 bool ret = false; 1382 1383 if (AR_SREV_9300_20_OR_LATER(ah)) { 1384 REG_WRITE(ah, AR_WA, ah->WARegVal); 1385 udelay(10); 1386 } 1387 1388 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1389 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1390 1391 if (!ah->reset_power_on) 1392 type = ATH9K_RESET_POWER_ON; 1393 1394 switch (type) { 1395 case ATH9K_RESET_POWER_ON: 1396 ret = ath9k_hw_set_reset_power_on(ah); 1397 if (ret) 1398 ah->reset_power_on = true; 1399 break; 1400 case ATH9K_RESET_WARM: 1401 case ATH9K_RESET_COLD: 1402 ret = ath9k_hw_set_reset(ah, type); 1403 break; 1404 default: 1405 break; 1406 } 1407 1408 return ret; 1409} 1410 1411static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1412 struct ath9k_channel *chan) 1413{ 1414 int reset_type = ATH9K_RESET_WARM; 1415 1416 if (AR_SREV_9280(ah)) { 1417 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1418 reset_type = ATH9K_RESET_POWER_ON; 1419 else 1420 reset_type = ATH9K_RESET_COLD; 1421 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1422 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1423 reset_type = ATH9K_RESET_COLD; 1424 1425 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1426 return false; 1427 1428 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1429 return false; 1430 1431 ah->chip_fullsleep = false; 1432 1433 if (AR_SREV_9330(ah)) 1434 ar9003_hw_internal_regulator_apply(ah); 1435 ath9k_hw_init_pll(ah, chan); 1436 1437 return true; 1438} 1439 1440static bool ath9k_hw_channel_change(struct ath_hw *ah, 1441 struct ath9k_channel *chan) 1442{ 1443 struct ath_common *common = ath9k_hw_common(ah); 1444 struct ath9k_hw_capabilities *pCap = &ah->caps; 1445 bool band_switch = false, mode_diff = false; 1446 u8 ini_reloaded = 0; 1447 u32 qnum; 1448 int r; 1449 1450 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1451 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1452 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1453 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1454 } 1455 1456 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1457 if (ath9k_hw_numtxpending(ah, qnum)) { 1458 ath_dbg(common, QUEUE, 1459 "Transmit frames pending on queue %d\n", qnum); 1460 return false; 1461 } 1462 } 1463 1464 if (!ath9k_hw_rfbus_req(ah)) { 1465 ath_err(common, "Could not kill baseband RX\n"); 1466 return false; 1467 } 1468 1469 if (band_switch || mode_diff) { 1470 ath9k_hw_mark_phy_inactive(ah); 1471 udelay(5); 1472 1473 if (band_switch) 1474 ath9k_hw_init_pll(ah, chan); 1475 1476 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1477 ath_err(common, "Failed to do fast channel change\n"); 1478 return false; 1479 } 1480 } 1481 1482 ath9k_hw_set_channel_regs(ah, chan); 1483 1484 r = ath9k_hw_rf_set_freq(ah, chan); 1485 if (r) { 1486 ath_err(common, "Failed to set channel\n"); 1487 return false; 1488 } 1489 ath9k_hw_set_clockrate(ah); 1490 ath9k_hw_apply_txpower(ah, chan, false); 1491 1492 ath9k_hw_set_delta_slope(ah, chan); 1493 ath9k_hw_spur_mitigate_freq(ah, chan); 1494 1495 if (band_switch || ini_reloaded) 1496 ah->eep_ops->set_board_values(ah, chan); 1497 1498 ath9k_hw_init_bb(ah, chan); 1499 ath9k_hw_rfbus_done(ah); 1500 1501 if (band_switch || ini_reloaded) { 1502 ah->ah_flags |= AH_FASTCC; 1503 ath9k_hw_init_cal(ah, chan); 1504 ah->ah_flags &= ~AH_FASTCC; 1505 } 1506 1507 return true; 1508} 1509 1510static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1511{ 1512 u32 gpio_mask = ah->gpio_mask; 1513 int i; 1514 1515 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1516 if (!(gpio_mask & 1)) 1517 continue; 1518 1519 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1520 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1521 } 1522} 1523 1524void ath9k_hw_check_nav(struct ath_hw *ah) 1525{ 1526 struct ath_common *common = ath9k_hw_common(ah); 1527 u32 val; 1528 1529 val = REG_READ(ah, AR_NAV); 1530 if (val != 0xdeadbeef && val > 0x7fff) { 1531 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1532 REG_WRITE(ah, AR_NAV, 0); 1533 } 1534} 1535EXPORT_SYMBOL(ath9k_hw_check_nav); 1536 1537bool ath9k_hw_check_alive(struct ath_hw *ah) 1538{ 1539 int count = 50; 1540 u32 reg, last_val; 1541 1542 if (AR_SREV_9300(ah)) 1543 return !ath9k_hw_detect_mac_hang(ah); 1544 1545 if (AR_SREV_9285_12_OR_LATER(ah)) 1546 return true; 1547 1548 last_val = REG_READ(ah, AR_OBS_BUS_1); 1549 do { 1550 reg = REG_READ(ah, AR_OBS_BUS_1); 1551 if (reg != last_val) 1552 return true; 1553 1554 udelay(1); 1555 last_val = reg; 1556 if ((reg & 0x7E7FFFEF) == 0x00702400) 1557 continue; 1558 1559 switch (reg & 0x7E000B00) { 1560 case 0x1E000000: 1561 case 0x52000B00: 1562 case 0x18000B00: 1563 continue; 1564 default: 1565 return true; 1566 } 1567 } while (count-- > 0); 1568 1569 return false; 1570} 1571EXPORT_SYMBOL(ath9k_hw_check_alive); 1572 1573static void ath9k_hw_init_mfp(struct ath_hw *ah) 1574{ 1575 /* Setup MFP options for CCMP */ 1576 if (AR_SREV_9280_20_OR_LATER(ah)) { 1577 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1578 * frames when constructing CCMP AAD. */ 1579 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1580 0xc7ff); 1581 ah->sw_mgmt_crypto = false; 1582 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1583 /* Disable hardware crypto for management frames */ 1584 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1585 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1586 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1587 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1588 ah->sw_mgmt_crypto = true; 1589 } else { 1590 ah->sw_mgmt_crypto = true; 1591 } 1592} 1593 1594static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1595 u32 macStaId1, u32 saveDefAntenna) 1596{ 1597 struct ath_common *common = ath9k_hw_common(ah); 1598 1599 ENABLE_REGWRITE_BUFFER(ah); 1600 1601 REG_RMW(ah, AR_STA_ID1, macStaId1 1602 | AR_STA_ID1_RTS_USE_DEF 1603 | ah->sta_id1_defaults, 1604 ~AR_STA_ID1_SADH_MASK); 1605 ath_hw_setbssidmask(common); 1606 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1607 ath9k_hw_write_associd(ah); 1608 REG_WRITE(ah, AR_ISR, ~0); 1609 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1610 1611 REGWRITE_BUFFER_FLUSH(ah); 1612 1613 ath9k_hw_set_operating_mode(ah, ah->opmode); 1614} 1615 1616static void ath9k_hw_init_queues(struct ath_hw *ah) 1617{ 1618 int i; 1619 1620 ENABLE_REGWRITE_BUFFER(ah); 1621 1622 for (i = 0; i < AR_NUM_DCU; i++) 1623 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1624 1625 REGWRITE_BUFFER_FLUSH(ah); 1626 1627 ah->intr_txqs = 0; 1628 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1629 ath9k_hw_resettxqueue(ah, i); 1630} 1631 1632/* 1633 * For big endian systems turn on swapping for descriptors 1634 */ 1635static void ath9k_hw_init_desc(struct ath_hw *ah) 1636{ 1637 struct ath_common *common = ath9k_hw_common(ah); 1638 1639 if (AR_SREV_9100(ah)) { 1640 u32 mask; 1641 mask = REG_READ(ah, AR_CFG); 1642 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1643 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1644 mask); 1645 } else { 1646 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1647 REG_WRITE(ah, AR_CFG, mask); 1648 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1649 REG_READ(ah, AR_CFG)); 1650 } 1651 } else { 1652 if (common->bus_ops->ath_bus_type == ATH_USB) { 1653 /* Configure AR9271 target WLAN */ 1654 if (AR_SREV_9271(ah)) 1655 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1656 else 1657 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1658 } 1659#ifdef __BIG_ENDIAN 1660 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1661 AR_SREV_9550(ah) || AR_SREV_9531(ah)) 1662 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1663 else 1664 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1665#endif 1666 } 1667} 1668 1669/* 1670 * Fast channel change: 1671 * (Change synthesizer based on channel freq without resetting chip) 1672 */ 1673static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1674{ 1675 struct ath_common *common = ath9k_hw_common(ah); 1676 struct ath9k_hw_capabilities *pCap = &ah->caps; 1677 int ret; 1678 1679 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1680 goto fail; 1681 1682 if (ah->chip_fullsleep) 1683 goto fail; 1684 1685 if (!ah->curchan) 1686 goto fail; 1687 1688 if (chan->channel == ah->curchan->channel) 1689 goto fail; 1690 1691 if ((ah->curchan->channelFlags | chan->channelFlags) & 1692 (CHANNEL_HALF | CHANNEL_QUARTER)) 1693 goto fail; 1694 1695 /* 1696 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1697 */ 1698 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1699 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1700 goto fail; 1701 1702 if (!ath9k_hw_check_alive(ah)) 1703 goto fail; 1704 1705 /* 1706 * For AR9462, make sure that calibration data for 1707 * re-using are present. 1708 */ 1709 if (AR_SREV_9462(ah) && (ah->caldata && 1710 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1711 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1712 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1713 goto fail; 1714 1715 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1716 ah->curchan->channel, chan->channel); 1717 1718 ret = ath9k_hw_channel_change(ah, chan); 1719 if (!ret) 1720 goto fail; 1721 1722 if (ath9k_hw_mci_is_enabled(ah)) 1723 ar9003_mci_2g5g_switch(ah, false); 1724 1725 ath9k_hw_loadnf(ah, ah->curchan); 1726 ath9k_hw_start_nfcal(ah, true); 1727 1728 if (AR_SREV_9271(ah)) 1729 ar9002_hw_load_ani_reg(ah, chan); 1730 1731 return 0; 1732fail: 1733 return -EINVAL; 1734} 1735 1736u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1737{ 1738 struct timespec ts; 1739 s64 usec; 1740 1741 if (!cur) { 1742 getrawmonotonic(&ts); 1743 cur = &ts; 1744 } 1745 1746 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1747 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1748 1749 return (u32) usec; 1750} 1751EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1752 1753int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1754 struct ath9k_hw_cal_data *caldata, bool fastcc) 1755{ 1756 struct ath_common *common = ath9k_hw_common(ah); 1757 u32 saveLedState; 1758 u32 saveDefAntenna; 1759 u32 macStaId1; 1760 u64 tsf = 0; 1761 s64 usec = 0; 1762 int r; 1763 bool start_mci_reset = false; 1764 bool save_fullsleep = ah->chip_fullsleep; 1765 1766 if (ath9k_hw_mci_is_enabled(ah)) { 1767 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1768 if (start_mci_reset) 1769 return 0; 1770 } 1771 1772 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1773 return -EIO; 1774 1775 if (ah->curchan && !ah->chip_fullsleep) 1776 ath9k_hw_getnf(ah, ah->curchan); 1777 1778 ah->caldata = caldata; 1779 if (caldata && (chan->channel != caldata->channel || 1780 chan->channelFlags != caldata->channelFlags)) { 1781 /* Operating channel changed, reset channel calibration data */ 1782 memset(caldata, 0, sizeof(*caldata)); 1783 ath9k_init_nfcal_hist_buffer(ah, chan); 1784 } else if (caldata) { 1785 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1786 } 1787 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1788 1789 if (fastcc) { 1790 r = ath9k_hw_do_fastcc(ah, chan); 1791 if (!r) 1792 return r; 1793 } 1794 1795 if (ath9k_hw_mci_is_enabled(ah)) 1796 ar9003_mci_stop_bt(ah, save_fullsleep); 1797 1798 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1799 if (saveDefAntenna == 0) 1800 saveDefAntenna = 1; 1801 1802 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1803 1804 /* Save TSF before chip reset, a cold reset clears it */ 1805 tsf = ath9k_hw_gettsf64(ah); 1806 usec = ktime_to_us(ktime_get_raw()); 1807 1808 saveLedState = REG_READ(ah, AR_CFG_LED) & 1809 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1810 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1811 1812 ath9k_hw_mark_phy_inactive(ah); 1813 1814 ah->paprd_table_write_done = false; 1815 1816 /* Only required on the first reset */ 1817 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1818 REG_WRITE(ah, 1819 AR9271_RESET_POWER_DOWN_CONTROL, 1820 AR9271_RADIO_RF_RST); 1821 udelay(50); 1822 } 1823 1824 if (!ath9k_hw_chip_reset(ah, chan)) { 1825 ath_err(common, "Chip reset failed\n"); 1826 return -EINVAL; 1827 } 1828 1829 /* Only required on the first reset */ 1830 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1831 ah->htc_reset_init = false; 1832 REG_WRITE(ah, 1833 AR9271_RESET_POWER_DOWN_CONTROL, 1834 AR9271_GATE_MAC_CTL); 1835 udelay(50); 1836 } 1837 1838 /* Restore TSF */ 1839 usec = ktime_to_us(ktime_get_raw()) - usec; 1840 ath9k_hw_settsf64(ah, tsf + usec); 1841 1842 if (AR_SREV_9280_20_OR_LATER(ah)) 1843 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1844 1845 if (!AR_SREV_9300_20_OR_LATER(ah)) 1846 ar9002_hw_enable_async_fifo(ah); 1847 1848 r = ath9k_hw_process_ini(ah, chan); 1849 if (r) 1850 return r; 1851 1852 ath9k_hw_set_rfmode(ah, chan); 1853 1854 if (ath9k_hw_mci_is_enabled(ah)) 1855 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1856 1857 /* 1858 * Some AR91xx SoC devices frequently fail to accept TSF writes 1859 * right after the chip reset. When that happens, write a new 1860 * value after the initvals have been applied, with an offset 1861 * based on measured time difference 1862 */ 1863 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1864 tsf += 1500; 1865 ath9k_hw_settsf64(ah, tsf); 1866 } 1867 1868 ath9k_hw_init_mfp(ah); 1869 1870 ath9k_hw_set_delta_slope(ah, chan); 1871 ath9k_hw_spur_mitigate_freq(ah, chan); 1872 ah->eep_ops->set_board_values(ah, chan); 1873 1874 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1875 1876 r = ath9k_hw_rf_set_freq(ah, chan); 1877 if (r) 1878 return r; 1879 1880 ath9k_hw_set_clockrate(ah); 1881 1882 ath9k_hw_init_queues(ah); 1883 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1884 ath9k_hw_ani_cache_ini_regs(ah); 1885 ath9k_hw_init_qos(ah); 1886 1887 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1888 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1889 1890 ath9k_hw_init_global_settings(ah); 1891 1892 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1893 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1894 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1895 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1896 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1897 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1898 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1899 } 1900 1901 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1902 1903 ath9k_hw_set_dma(ah); 1904 1905 if (!ath9k_hw_mci_is_enabled(ah)) 1906 REG_WRITE(ah, AR_OBS, 8); 1907 1908 if (ah->config.rx_intr_mitigation) { 1909 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 1910 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 1911 } 1912 1913 if (ah->config.tx_intr_mitigation) { 1914 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1915 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1916 } 1917 1918 ath9k_hw_init_bb(ah, chan); 1919 1920 if (caldata) { 1921 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 1922 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 1923 } 1924 if (!ath9k_hw_init_cal(ah, chan)) 1925 return -EIO; 1926 1927 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1928 return -EIO; 1929 1930 ENABLE_REGWRITE_BUFFER(ah); 1931 1932 ath9k_hw_restore_chainmask(ah); 1933 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1934 1935 REGWRITE_BUFFER_FLUSH(ah); 1936 1937 ath9k_hw_init_desc(ah); 1938 1939 if (ath9k_hw_btcoex_is_enabled(ah)) 1940 ath9k_hw_btcoex_enable(ah); 1941 1942 if (ath9k_hw_mci_is_enabled(ah)) 1943 ar9003_mci_check_bt(ah); 1944 1945 ath9k_hw_loadnf(ah, chan); 1946 ath9k_hw_start_nfcal(ah, true); 1947 1948 if (AR_SREV_9300_20_OR_LATER(ah)) 1949 ar9003_hw_bb_watchdog_config(ah); 1950 1951 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 1952 ar9003_hw_disable_phy_restart(ah); 1953 1954 ath9k_hw_apply_gpio_override(ah); 1955 1956 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 1957 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 1958 1959 if (ah->hw->conf.radar_enabled) { 1960 /* set HW specific DFS configuration */ 1961 ath9k_hw_set_radar_params(ah); 1962 } 1963 1964 return 0; 1965} 1966EXPORT_SYMBOL(ath9k_hw_reset); 1967 1968/******************************/ 1969/* Power Management (Chipset) */ 1970/******************************/ 1971 1972/* 1973 * Notify Power Mgt is disabled in self-generated frames. 1974 * If requested, force chip to sleep. 1975 */ 1976static void ath9k_set_power_sleep(struct ath_hw *ah) 1977{ 1978 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1979 1980 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 1981 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 1982 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 1983 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 1984 /* xxx Required for WLAN only case ? */ 1985 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 1986 udelay(100); 1987 } 1988 1989 /* 1990 * Clear the RTC force wake bit to allow the 1991 * mac to go to sleep. 1992 */ 1993 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1994 1995 if (ath9k_hw_mci_is_enabled(ah)) 1996 udelay(100); 1997 1998 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1999 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2000 2001 /* Shutdown chip. Active low */ 2002 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2003 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2004 udelay(2); 2005 } 2006 2007 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2008 if (AR_SREV_9300_20_OR_LATER(ah)) 2009 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2010} 2011 2012/* 2013 * Notify Power Management is enabled in self-generating 2014 * frames. If request, set power mode of chip to 2015 * auto/normal. Duration in units of 128us (1/8 TU). 2016 */ 2017static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2018{ 2019 struct ath9k_hw_capabilities *pCap = &ah->caps; 2020 2021 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2022 2023 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2024 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2025 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2026 AR_RTC_FORCE_WAKE_ON_INT); 2027 } else { 2028 2029 /* When chip goes into network sleep, it could be waken 2030 * up by MCI_INT interrupt caused by BT's HW messages 2031 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2032 * rate (~100us). This will cause chip to leave and 2033 * re-enter network sleep mode frequently, which in 2034 * consequence will have WLAN MCI HW to generate lots of 2035 * SYS_WAKING and SYS_SLEEPING messages which will make 2036 * BT CPU to busy to process. 2037 */ 2038 if (ath9k_hw_mci_is_enabled(ah)) 2039 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2040 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2041 /* 2042 * Clear the RTC force wake bit to allow the 2043 * mac to go to sleep. 2044 */ 2045 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2046 2047 if (ath9k_hw_mci_is_enabled(ah)) 2048 udelay(30); 2049 } 2050 2051 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2052 if (AR_SREV_9300_20_OR_LATER(ah)) 2053 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2054} 2055 2056static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2057{ 2058 u32 val; 2059 int i; 2060 2061 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2062 if (AR_SREV_9300_20_OR_LATER(ah)) { 2063 REG_WRITE(ah, AR_WA, ah->WARegVal); 2064 udelay(10); 2065 } 2066 2067 if ((REG_READ(ah, AR_RTC_STATUS) & 2068 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2069 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2070 return false; 2071 } 2072 if (!AR_SREV_9300_20_OR_LATER(ah)) 2073 ath9k_hw_init_pll(ah, NULL); 2074 } 2075 if (AR_SREV_9100(ah)) 2076 REG_SET_BIT(ah, AR_RTC_RESET, 2077 AR_RTC_RESET_EN); 2078 2079 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2080 AR_RTC_FORCE_WAKE_EN); 2081 if (AR_SREV_9100(ah)) 2082 mdelay(10); 2083 else 2084 udelay(50); 2085 2086 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2087 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2088 if (val == AR_RTC_STATUS_ON) 2089 break; 2090 udelay(50); 2091 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2092 AR_RTC_FORCE_WAKE_EN); 2093 } 2094 if (i == 0) { 2095 ath_err(ath9k_hw_common(ah), 2096 "Failed to wakeup in %uus\n", 2097 POWER_UP_TIME / 20); 2098 return false; 2099 } 2100 2101 if (ath9k_hw_mci_is_enabled(ah)) 2102 ar9003_mci_set_power_awake(ah); 2103 2104 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2105 2106 return true; 2107} 2108 2109bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2110{ 2111 struct ath_common *common = ath9k_hw_common(ah); 2112 int status = true; 2113 static const char *modes[] = { 2114 "AWAKE", 2115 "FULL-SLEEP", 2116 "NETWORK SLEEP", 2117 "UNDEFINED" 2118 }; 2119 2120 if (ah->power_mode == mode) 2121 return status; 2122 2123 ath_dbg(common, RESET, "%s -> %s\n", 2124 modes[ah->power_mode], modes[mode]); 2125 2126 switch (mode) { 2127 case ATH9K_PM_AWAKE: 2128 status = ath9k_hw_set_power_awake(ah); 2129 break; 2130 case ATH9K_PM_FULL_SLEEP: 2131 if (ath9k_hw_mci_is_enabled(ah)) 2132 ar9003_mci_set_full_sleep(ah); 2133 2134 ath9k_set_power_sleep(ah); 2135 ah->chip_fullsleep = true; 2136 break; 2137 case ATH9K_PM_NETWORK_SLEEP: 2138 ath9k_set_power_network_sleep(ah); 2139 break; 2140 default: 2141 ath_err(common, "Unknown power mode %u\n", mode); 2142 return false; 2143 } 2144 ah->power_mode = mode; 2145 2146 /* 2147 * XXX: If this warning never comes up after a while then 2148 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2149 * ath9k_hw_setpower() return type void. 2150 */ 2151 2152 if (!(ah->ah_flags & AH_UNPLUGGED)) 2153 ATH_DBG_WARN_ON_ONCE(!status); 2154 2155 return status; 2156} 2157EXPORT_SYMBOL(ath9k_hw_setpower); 2158 2159/*******************/ 2160/* Beacon Handling */ 2161/*******************/ 2162 2163void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2164{ 2165 int flags = 0; 2166 2167 ENABLE_REGWRITE_BUFFER(ah); 2168 2169 switch (ah->opmode) { 2170 case NL80211_IFTYPE_ADHOC: 2171 REG_SET_BIT(ah, AR_TXCFG, 2172 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2173 case NL80211_IFTYPE_MESH_POINT: 2174 case NL80211_IFTYPE_AP: 2175 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2176 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2177 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2178 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2179 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2180 flags |= 2181 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2182 break; 2183 default: 2184 ath_dbg(ath9k_hw_common(ah), BEACON, 2185 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2186 return; 2187 break; 2188 } 2189 2190 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2191 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2192 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2193 2194 REGWRITE_BUFFER_FLUSH(ah); 2195 2196 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2197} 2198EXPORT_SYMBOL(ath9k_hw_beaconinit); 2199 2200void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2201 const struct ath9k_beacon_state *bs) 2202{ 2203 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2204 struct ath9k_hw_capabilities *pCap = &ah->caps; 2205 struct ath_common *common = ath9k_hw_common(ah); 2206 2207 ENABLE_REGWRITE_BUFFER(ah); 2208 2209 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2210 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2211 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2212 2213 REGWRITE_BUFFER_FLUSH(ah); 2214 2215 REG_RMW_FIELD(ah, AR_RSSI_THR, 2216 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2217 2218 beaconintval = bs->bs_intval; 2219 2220 if (bs->bs_sleepduration > beaconintval) 2221 beaconintval = bs->bs_sleepduration; 2222 2223 dtimperiod = bs->bs_dtimperiod; 2224 if (bs->bs_sleepduration > dtimperiod) 2225 dtimperiod = bs->bs_sleepduration; 2226 2227 if (beaconintval == dtimperiod) 2228 nextTbtt = bs->bs_nextdtim; 2229 else 2230 nextTbtt = bs->bs_nexttbtt; 2231 2232 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2233 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2234 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2235 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2236 2237 ENABLE_REGWRITE_BUFFER(ah); 2238 2239 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2240 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2241 2242 REG_WRITE(ah, AR_SLEEP1, 2243 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2244 | AR_SLEEP1_ASSUME_DTIM); 2245 2246 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2247 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2248 else 2249 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2250 2251 REG_WRITE(ah, AR_SLEEP2, 2252 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2253 2254 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2255 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2256 2257 REGWRITE_BUFFER_FLUSH(ah); 2258 2259 REG_SET_BIT(ah, AR_TIMER_MODE, 2260 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2261 AR_DTIM_TIMER_EN); 2262 2263 /* TSF Out of Range Threshold */ 2264 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2265} 2266EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2267 2268/*******************/ 2269/* HW Capabilities */ 2270/*******************/ 2271 2272static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2273{ 2274 eeprom_chainmask &= chip_chainmask; 2275 if (eeprom_chainmask) 2276 return eeprom_chainmask; 2277 else 2278 return chip_chainmask; 2279} 2280 2281/** 2282 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2283 * @ah: the atheros hardware data structure 2284 * 2285 * We enable DFS support upstream on chipsets which have passed a series 2286 * of tests. The testing requirements are going to be documented. Desired 2287 * test requirements are documented at: 2288 * 2289 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2290 * 2291 * Once a new chipset gets properly tested an individual commit can be used 2292 * to document the testing for DFS for that chipset. 2293 */ 2294static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2295{ 2296 2297 switch (ah->hw_version.macVersion) { 2298 /* for temporary testing DFS with 9280 */ 2299 case AR_SREV_VERSION_9280: 2300 /* AR9580 will likely be our first target to get testing on */ 2301 case AR_SREV_VERSION_9580: 2302 return true; 2303 default: 2304 return false; 2305 } 2306} 2307 2308int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2309{ 2310 struct ath9k_hw_capabilities *pCap = &ah->caps; 2311 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2312 struct ath_common *common = ath9k_hw_common(ah); 2313 unsigned int chip_chainmask; 2314 2315 u16 eeval; 2316 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2317 2318 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2319 regulatory->current_rd = eeval; 2320 2321 if (ah->opmode != NL80211_IFTYPE_AP && 2322 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2323 if (regulatory->current_rd == 0x64 || 2324 regulatory->current_rd == 0x65) 2325 regulatory->current_rd += 5; 2326 else if (regulatory->current_rd == 0x41) 2327 regulatory->current_rd = 0x43; 2328 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2329 regulatory->current_rd); 2330 } 2331 2332 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2333 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2334 ath_err(common, 2335 "no band has been marked as supported in EEPROM\n"); 2336 return -EINVAL; 2337 } 2338 2339 if (eeval & AR5416_OPFLAGS_11A) 2340 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2341 2342 if (eeval & AR5416_OPFLAGS_11G) 2343 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2344 2345 if (AR_SREV_9485(ah) || 2346 AR_SREV_9285(ah) || 2347 AR_SREV_9330(ah) || 2348 AR_SREV_9565(ah)) 2349 chip_chainmask = 1; 2350 else if (AR_SREV_9462(ah)) 2351 chip_chainmask = 3; 2352 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2353 chip_chainmask = 7; 2354 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2355 chip_chainmask = 3; 2356 else 2357 chip_chainmask = 7; 2358 2359 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2360 /* 2361 * For AR9271 we will temporarilly uses the rx chainmax as read from 2362 * the EEPROM. 2363 */ 2364 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2365 !(eeval & AR5416_OPFLAGS_11A) && 2366 !(AR_SREV_9271(ah))) 2367 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2368 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2369 else if (AR_SREV_9100(ah)) 2370 pCap->rx_chainmask = 0x7; 2371 else 2372 /* Use rx_chainmask from EEPROM. */ 2373 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2374 2375 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2376 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2377 ah->txchainmask = pCap->tx_chainmask; 2378 ah->rxchainmask = pCap->rx_chainmask; 2379 2380 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2381 2382 /* enable key search for every frame in an aggregate */ 2383 if (AR_SREV_9300_20_OR_LATER(ah)) 2384 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2385 2386 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2387 2388 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2389 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2390 else 2391 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2392 2393 if (AR_SREV_9271(ah)) 2394 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2395 else if (AR_DEVID_7010(ah)) 2396 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2397 else if (AR_SREV_9300_20_OR_LATER(ah)) 2398 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2399 else if (AR_SREV_9287_11_OR_LATER(ah)) 2400 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2401 else if (AR_SREV_9285_12_OR_LATER(ah)) 2402 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2403 else if (AR_SREV_9280_20_OR_LATER(ah)) 2404 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2405 else 2406 pCap->num_gpio_pins = AR_NUM_GPIO; 2407 2408 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2409 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2410 else 2411 pCap->rts_aggr_limit = (8 * 1024); 2412 2413#ifdef CONFIG_ATH9K_RFKILL 2414 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2415 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2416 ah->rfkill_gpio = 2417 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2418 ah->rfkill_polarity = 2419 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2420 2421 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2422 } 2423#endif 2424 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2425 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2426 else 2427 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2428 2429 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2430 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2431 else 2432 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2433 2434 if (AR_SREV_9300_20_OR_LATER(ah)) { 2435 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2436 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2437 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2438 2439 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2440 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2441 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2442 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2443 pCap->txs_len = sizeof(struct ar9003_txs); 2444 } else { 2445 pCap->tx_desc_len = sizeof(struct ath_desc); 2446 if (AR_SREV_9280_20(ah)) 2447 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2448 } 2449 2450 if (AR_SREV_9300_20_OR_LATER(ah)) 2451 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2452 2453 if (AR_SREV_9300_20_OR_LATER(ah)) 2454 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2455 2456 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2457 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2458 2459 if (AR_SREV_9285(ah)) { 2460 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2461 ant_div_ctl1 = 2462 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2463 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2464 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2465 ath_info(common, "Enable LNA combining\n"); 2466 } 2467 } 2468 } 2469 2470 if (AR_SREV_9300_20_OR_LATER(ah)) { 2471 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2472 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2473 } 2474 2475 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2476 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2477 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2478 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2479 ath_info(common, "Enable LNA combining\n"); 2480 } 2481 } 2482 2483 if (ath9k_hw_dfs_tested(ah)) 2484 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2485 2486 tx_chainmask = pCap->tx_chainmask; 2487 rx_chainmask = pCap->rx_chainmask; 2488 while (tx_chainmask || rx_chainmask) { 2489 if (tx_chainmask & BIT(0)) 2490 pCap->max_txchains++; 2491 if (rx_chainmask & BIT(0)) 2492 pCap->max_rxchains++; 2493 2494 tx_chainmask >>= 1; 2495 rx_chainmask >>= 1; 2496 } 2497 2498 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2499 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2500 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2501 2502 if (AR_SREV_9462_20_OR_LATER(ah)) 2503 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2504 } 2505 2506 if (AR_SREV_9462(ah)) 2507 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE; 2508 2509 if (AR_SREV_9300_20_OR_LATER(ah) && 2510 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2511 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2512 2513 return 0; 2514} 2515 2516/****************************/ 2517/* GPIO / RFKILL / Antennae */ 2518/****************************/ 2519 2520static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2521 u32 gpio, u32 type) 2522{ 2523 int addr; 2524 u32 gpio_shift, tmp; 2525 2526 if (gpio > 11) 2527 addr = AR_GPIO_OUTPUT_MUX3; 2528 else if (gpio > 5) 2529 addr = AR_GPIO_OUTPUT_MUX2; 2530 else 2531 addr = AR_GPIO_OUTPUT_MUX1; 2532 2533 gpio_shift = (gpio % 6) * 5; 2534 2535 if (AR_SREV_9280_20_OR_LATER(ah) 2536 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2537 REG_RMW(ah, addr, (type << gpio_shift), 2538 (0x1f << gpio_shift)); 2539 } else { 2540 tmp = REG_READ(ah, addr); 2541 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2542 tmp &= ~(0x1f << gpio_shift); 2543 tmp |= (type << gpio_shift); 2544 REG_WRITE(ah, addr, tmp); 2545 } 2546} 2547 2548void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2549{ 2550 u32 gpio_shift; 2551 2552 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2553 2554 if (AR_DEVID_7010(ah)) { 2555 gpio_shift = gpio; 2556 REG_RMW(ah, AR7010_GPIO_OE, 2557 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2558 (AR7010_GPIO_OE_MASK << gpio_shift)); 2559 return; 2560 } 2561 2562 gpio_shift = gpio << 1; 2563 REG_RMW(ah, 2564 AR_GPIO_OE_OUT, 2565 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2566 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2567} 2568EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2569 2570u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2571{ 2572#define MS_REG_READ(x, y) \ 2573 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2574 2575 if (gpio >= ah->caps.num_gpio_pins) 2576 return 0xffffffff; 2577 2578 if (AR_DEVID_7010(ah)) { 2579 u32 val; 2580 val = REG_READ(ah, AR7010_GPIO_IN); 2581 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2582 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2583 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2584 AR_GPIO_BIT(gpio)) != 0; 2585 else if (AR_SREV_9271(ah)) 2586 return MS_REG_READ(AR9271, gpio) != 0; 2587 else if (AR_SREV_9287_11_OR_LATER(ah)) 2588 return MS_REG_READ(AR9287, gpio) != 0; 2589 else if (AR_SREV_9285_12_OR_LATER(ah)) 2590 return MS_REG_READ(AR9285, gpio) != 0; 2591 else if (AR_SREV_9280_20_OR_LATER(ah)) 2592 return MS_REG_READ(AR928X, gpio) != 0; 2593 else 2594 return MS_REG_READ(AR, gpio) != 0; 2595} 2596EXPORT_SYMBOL(ath9k_hw_gpio_get); 2597 2598void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2599 u32 ah_signal_type) 2600{ 2601 u32 gpio_shift; 2602 2603 if (AR_DEVID_7010(ah)) { 2604 gpio_shift = gpio; 2605 REG_RMW(ah, AR7010_GPIO_OE, 2606 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2607 (AR7010_GPIO_OE_MASK << gpio_shift)); 2608 return; 2609 } 2610 2611 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2612 gpio_shift = 2 * gpio; 2613 REG_RMW(ah, 2614 AR_GPIO_OE_OUT, 2615 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2616 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2617} 2618EXPORT_SYMBOL(ath9k_hw_cfg_output); 2619 2620void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2621{ 2622 if (AR_DEVID_7010(ah)) { 2623 val = val ? 0 : 1; 2624 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2625 AR_GPIO_BIT(gpio)); 2626 return; 2627 } 2628 2629 if (AR_SREV_9271(ah)) 2630 val = ~val; 2631 2632 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2633 AR_GPIO_BIT(gpio)); 2634} 2635EXPORT_SYMBOL(ath9k_hw_set_gpio); 2636 2637void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2638{ 2639 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2640} 2641EXPORT_SYMBOL(ath9k_hw_setantenna); 2642 2643/*********************/ 2644/* General Operation */ 2645/*********************/ 2646 2647u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2648{ 2649 u32 bits = REG_READ(ah, AR_RX_FILTER); 2650 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2651 2652 if (phybits & AR_PHY_ERR_RADAR) 2653 bits |= ATH9K_RX_FILTER_PHYRADAR; 2654 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2655 bits |= ATH9K_RX_FILTER_PHYERR; 2656 2657 return bits; 2658} 2659EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2660 2661void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2662{ 2663 u32 phybits; 2664 2665 ENABLE_REGWRITE_BUFFER(ah); 2666 2667 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2668 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2669 2670 REG_WRITE(ah, AR_RX_FILTER, bits); 2671 2672 phybits = 0; 2673 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2674 phybits |= AR_PHY_ERR_RADAR; 2675 if (bits & ATH9K_RX_FILTER_PHYERR) 2676 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2677 REG_WRITE(ah, AR_PHY_ERR, phybits); 2678 2679 if (phybits) 2680 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2681 else 2682 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2683 2684 REGWRITE_BUFFER_FLUSH(ah); 2685} 2686EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2687 2688bool ath9k_hw_phy_disable(struct ath_hw *ah) 2689{ 2690 if (ath9k_hw_mci_is_enabled(ah)) 2691 ar9003_mci_bt_gain_ctrl(ah); 2692 2693 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2694 return false; 2695 2696 ath9k_hw_init_pll(ah, NULL); 2697 ah->htc_reset_init = true; 2698 return true; 2699} 2700EXPORT_SYMBOL(ath9k_hw_phy_disable); 2701 2702bool ath9k_hw_disable(struct ath_hw *ah) 2703{ 2704 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2705 return false; 2706 2707 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2708 return false; 2709 2710 ath9k_hw_init_pll(ah, NULL); 2711 return true; 2712} 2713EXPORT_SYMBOL(ath9k_hw_disable); 2714 2715static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2716{ 2717 enum eeprom_param gain_param; 2718 2719 if (IS_CHAN_2GHZ(chan)) 2720 gain_param = EEP_ANTENNA_GAIN_2G; 2721 else 2722 gain_param = EEP_ANTENNA_GAIN_5G; 2723 2724 return ah->eep_ops->get_eeprom(ah, gain_param); 2725} 2726 2727void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2728 bool test) 2729{ 2730 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2731 struct ieee80211_channel *channel; 2732 int chan_pwr, new_pwr, max_gain; 2733 int ant_gain, ant_reduction = 0; 2734 2735 if (!chan) 2736 return; 2737 2738 channel = chan->chan; 2739 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2740 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2741 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2742 2743 ant_gain = get_antenna_gain(ah, chan); 2744 if (ant_gain > max_gain) 2745 ant_reduction = ant_gain - max_gain; 2746 2747 ah->eep_ops->set_txpower(ah, chan, 2748 ath9k_regd_get_ctl(reg, chan), 2749 ant_reduction, new_pwr, test); 2750} 2751 2752void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2753{ 2754 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2755 struct ath9k_channel *chan = ah->curchan; 2756 struct ieee80211_channel *channel = chan->chan; 2757 2758 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2759 if (test) 2760 channel->max_power = MAX_RATE_POWER / 2; 2761 2762 ath9k_hw_apply_txpower(ah, chan, test); 2763 2764 if (test) 2765 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2766} 2767EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2768 2769void ath9k_hw_setopmode(struct ath_hw *ah) 2770{ 2771 ath9k_hw_set_operating_mode(ah, ah->opmode); 2772} 2773EXPORT_SYMBOL(ath9k_hw_setopmode); 2774 2775void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2776{ 2777 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2778 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2779} 2780EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2781 2782void ath9k_hw_write_associd(struct ath_hw *ah) 2783{ 2784 struct ath_common *common = ath9k_hw_common(ah); 2785 2786 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2787 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2788 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2789} 2790EXPORT_SYMBOL(ath9k_hw_write_associd); 2791 2792#define ATH9K_MAX_TSF_READ 10 2793 2794u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2795{ 2796 u32 tsf_lower, tsf_upper1, tsf_upper2; 2797 int i; 2798 2799 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2800 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2801 tsf_lower = REG_READ(ah, AR_TSF_L32); 2802 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2803 if (tsf_upper2 == tsf_upper1) 2804 break; 2805 tsf_upper1 = tsf_upper2; 2806 } 2807 2808 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2809 2810 return (((u64)tsf_upper1 << 32) | tsf_lower); 2811} 2812EXPORT_SYMBOL(ath9k_hw_gettsf64); 2813 2814void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2815{ 2816 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2817 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2818} 2819EXPORT_SYMBOL(ath9k_hw_settsf64); 2820 2821void ath9k_hw_reset_tsf(struct ath_hw *ah) 2822{ 2823 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2824 AH_TSF_WRITE_TIMEOUT)) 2825 ath_dbg(ath9k_hw_common(ah), RESET, 2826 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2827 2828 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2829} 2830EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2831 2832void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2833{ 2834 if (set) 2835 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2836 else 2837 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2838} 2839EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2840 2841void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 2842{ 2843 u32 macmode; 2844 2845 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 2846 macmode = AR_2040_JOINED_RX_CLEAR; 2847 else 2848 macmode = 0; 2849 2850 REG_WRITE(ah, AR_2040_MODE, macmode); 2851} 2852 2853/* HW Generic timers configuration */ 2854 2855static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2856{ 2857 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2858 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2859 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2860 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2861 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2862 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2863 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2864 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2865 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2866 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2867 AR_NDP2_TIMER_MODE, 0x0002}, 2868 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2869 AR_NDP2_TIMER_MODE, 0x0004}, 2870 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2871 AR_NDP2_TIMER_MODE, 0x0008}, 2872 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2873 AR_NDP2_TIMER_MODE, 0x0010}, 2874 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2875 AR_NDP2_TIMER_MODE, 0x0020}, 2876 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2877 AR_NDP2_TIMER_MODE, 0x0040}, 2878 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2879 AR_NDP2_TIMER_MODE, 0x0080} 2880}; 2881 2882/* HW generic timer primitives */ 2883 2884u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2885{ 2886 return REG_READ(ah, AR_TSF_L32); 2887} 2888EXPORT_SYMBOL(ath9k_hw_gettsf32); 2889 2890struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2891 void (*trigger)(void *), 2892 void (*overflow)(void *), 2893 void *arg, 2894 u8 timer_index) 2895{ 2896 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2897 struct ath_gen_timer *timer; 2898 2899 if ((timer_index < AR_FIRST_NDP_TIMER) || 2900 (timer_index >= ATH_MAX_GEN_TIMER)) 2901 return NULL; 2902 2903 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2904 if (timer == NULL) 2905 return NULL; 2906 2907 /* allocate a hardware generic timer slot */ 2908 timer_table->timers[timer_index] = timer; 2909 timer->index = timer_index; 2910 timer->trigger = trigger; 2911 timer->overflow = overflow; 2912 timer->arg = arg; 2913 2914 return timer; 2915} 2916EXPORT_SYMBOL(ath_gen_timer_alloc); 2917 2918void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2919 struct ath_gen_timer *timer, 2920 u32 timer_next, 2921 u32 timer_period) 2922{ 2923 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2924 u32 mask = 0; 2925 2926 timer_table->timer_mask |= BIT(timer->index); 2927 2928 /* 2929 * Program generic timer registers 2930 */ 2931 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2932 timer_next); 2933 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2934 timer_period); 2935 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2936 gen_tmr_configuration[timer->index].mode_mask); 2937 2938 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2939 /* 2940 * Starting from AR9462, each generic timer can select which tsf 2941 * to use. But we still follow the old rule, 0 - 7 use tsf and 2942 * 8 - 15 use tsf2. 2943 */ 2944 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 2945 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2946 (1 << timer->index)); 2947 else 2948 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2949 (1 << timer->index)); 2950 } 2951 2952 if (timer->trigger) 2953 mask |= SM(AR_GENTMR_BIT(timer->index), 2954 AR_IMR_S5_GENTIMER_TRIG); 2955 if (timer->overflow) 2956 mask |= SM(AR_GENTMR_BIT(timer->index), 2957 AR_IMR_S5_GENTIMER_THRESH); 2958 2959 REG_SET_BIT(ah, AR_IMR_S5, mask); 2960 2961 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 2962 ah->imask |= ATH9K_INT_GENTIMER; 2963 ath9k_hw_set_interrupts(ah); 2964 } 2965} 2966EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2967 2968void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2969{ 2970 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2971 2972 /* Clear generic timer enable bits. */ 2973 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2974 gen_tmr_configuration[timer->index].mode_mask); 2975 2976 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2977 /* 2978 * Need to switch back to TSF if it was using TSF2. 2979 */ 2980 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 2981 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2982 (1 << timer->index)); 2983 } 2984 } 2985 2986 /* Disable both trigger and thresh interrupt masks */ 2987 REG_CLR_BIT(ah, AR_IMR_S5, 2988 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2989 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2990 2991 timer_table->timer_mask &= ~BIT(timer->index); 2992 2993 if (timer_table->timer_mask == 0) { 2994 ah->imask &= ~ATH9K_INT_GENTIMER; 2995 ath9k_hw_set_interrupts(ah); 2996 } 2997} 2998EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2999 3000void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3001{ 3002 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3003 3004 /* free the hardware generic timer slot */ 3005 timer_table->timers[timer->index] = NULL; 3006 kfree(timer); 3007} 3008EXPORT_SYMBOL(ath_gen_timer_free); 3009 3010/* 3011 * Generic Timer Interrupts handling 3012 */ 3013void ath_gen_timer_isr(struct ath_hw *ah) 3014{ 3015 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3016 struct ath_gen_timer *timer; 3017 unsigned long trigger_mask, thresh_mask; 3018 unsigned int index; 3019 3020 /* get hardware generic timer interrupt status */ 3021 trigger_mask = ah->intr_gen_timer_trigger; 3022 thresh_mask = ah->intr_gen_timer_thresh; 3023 trigger_mask &= timer_table->timer_mask; 3024 thresh_mask &= timer_table->timer_mask; 3025 3026 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3027 timer = timer_table->timers[index]; 3028 if (!timer) 3029 continue; 3030 if (!timer->overflow) 3031 continue; 3032 3033 trigger_mask &= ~BIT(index); 3034 timer->overflow(timer->arg); 3035 } 3036 3037 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3038 timer = timer_table->timers[index]; 3039 if (!timer) 3040 continue; 3041 if (!timer->trigger) 3042 continue; 3043 timer->trigger(timer->arg); 3044 } 3045} 3046EXPORT_SYMBOL(ath_gen_timer_isr); 3047 3048/********/ 3049/* HTC */ 3050/********/ 3051 3052static struct { 3053 u32 version; 3054 const char * name; 3055} ath_mac_bb_names[] = { 3056 /* Devices with external radios */ 3057 { AR_SREV_VERSION_5416_PCI, "5416" }, 3058 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3059 { AR_SREV_VERSION_9100, "9100" }, 3060 { AR_SREV_VERSION_9160, "9160" }, 3061 /* Single-chip solutions */ 3062 { AR_SREV_VERSION_9280, "9280" }, 3063 { AR_SREV_VERSION_9285, "9285" }, 3064 { AR_SREV_VERSION_9287, "9287" }, 3065 { AR_SREV_VERSION_9271, "9271" }, 3066 { AR_SREV_VERSION_9300, "9300" }, 3067 { AR_SREV_VERSION_9330, "9330" }, 3068 { AR_SREV_VERSION_9340, "9340" }, 3069 { AR_SREV_VERSION_9485, "9485" }, 3070 { AR_SREV_VERSION_9462, "9462" }, 3071 { AR_SREV_VERSION_9550, "9550" }, 3072 { AR_SREV_VERSION_9565, "9565" }, 3073 { AR_SREV_VERSION_9531, "9531" }, 3074}; 3075 3076/* For devices with external radios */ 3077static struct { 3078 u16 version; 3079 const char * name; 3080} ath_rf_names[] = { 3081 { 0, "5133" }, 3082 { AR_RAD5133_SREV_MAJOR, "5133" }, 3083 { AR_RAD5122_SREV_MAJOR, "5122" }, 3084 { AR_RAD2133_SREV_MAJOR, "2133" }, 3085 { AR_RAD2122_SREV_MAJOR, "2122" } 3086}; 3087 3088/* 3089 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3090 */ 3091static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3092{ 3093 int i; 3094 3095 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3096 if (ath_mac_bb_names[i].version == mac_bb_version) { 3097 return ath_mac_bb_names[i].name; 3098 } 3099 } 3100 3101 return "????"; 3102} 3103 3104/* 3105 * Return the RF name. "????" is returned if the RF is unknown. 3106 * Used for devices with external radios. 3107 */ 3108static const char *ath9k_hw_rf_name(u16 rf_version) 3109{ 3110 int i; 3111 3112 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3113 if (ath_rf_names[i].version == rf_version) { 3114 return ath_rf_names[i].name; 3115 } 3116 } 3117 3118 return "????"; 3119} 3120 3121void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3122{ 3123 int used; 3124 3125 /* chipsets >= AR9280 are single-chip */ 3126 if (AR_SREV_9280_20_OR_LATER(ah)) { 3127 used = scnprintf(hw_name, len, 3128 "Atheros AR%s Rev:%x", 3129 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3130 ah->hw_version.macRev); 3131 } 3132 else { 3133 used = scnprintf(hw_name, len, 3134 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3135 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3136 ah->hw_version.macRev, 3137 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3138 & AR_RADIO_SREV_MAJOR)), 3139 ah->hw_version.phyRev); 3140 } 3141 3142 hw_name[used] = '\0'; 3143} 3144EXPORT_SYMBOL(ath9k_hw_name); 3145