hw.c revision d1ae25a0174938f03e28dee8f3269a826fc1bec5
1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <linux/module.h> 20#include <asm/unaligned.h> 21 22#include "hw.h" 23#include "hw-ops.h" 24#include "rc.h" 25#include "ar9003_mac.h" 26#include "ar9003_mci.h" 27#include "ar9003_phy.h" 28#include "debug.h" 29#include "ath9k.h" 30 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32 33MODULE_AUTHOR("Atheros Communications"); 34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 36MODULE_LICENSE("Dual BSD/GPL"); 37 38static int __init ath9k_init(void) 39{ 40 return 0; 41} 42module_init(ath9k_init); 43 44static void __exit ath9k_exit(void) 45{ 46 return; 47} 48module_exit(ath9k_exit); 49 50/* Private hardware callbacks */ 51 52static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 53{ 54 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 55} 56 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 58 struct ath9k_channel *chan) 59{ 60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 61} 62 63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 64{ 65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 66 return; 67 68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 69} 70 71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 72{ 73 /* You will not have this callback if using the old ANI */ 74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 75 return; 76 77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 78} 79 80/********************/ 81/* Helper Functions */ 82/********************/ 83 84#ifdef CONFIG_ATH9K_DEBUGFS 85 86void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause) 87{ 88 struct ath_softc *sc = common->priv; 89 if (sync_cause) 90 sc->debug.stats.istats.sync_cause_all++; 91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ) 92 sc->debug.stats.istats.sync_rtc_irq++; 93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ) 94 sc->debug.stats.istats.sync_mac_irq++; 95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS) 96 sc->debug.stats.istats.eeprom_illegal_access++; 97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT) 98 sc->debug.stats.istats.apb_timeout++; 99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT) 100 sc->debug.stats.istats.pci_mode_conflict++; 101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) 102 sc->debug.stats.istats.host1_fatal++; 103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) 104 sc->debug.stats.istats.host1_perr++; 105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR) 106 sc->debug.stats.istats.trcv_fifo_perr++; 107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP) 108 sc->debug.stats.istats.radm_cpl_ep++; 109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT) 110 sc->debug.stats.istats.radm_cpl_dllp_abort++; 111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT) 112 sc->debug.stats.istats.radm_cpl_tlp_abort++; 113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR) 114 sc->debug.stats.istats.radm_cpl_ecrc_err++; 115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) 116 sc->debug.stats.istats.radm_cpl_timeout++; 117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 118 sc->debug.stats.istats.local_timeout++; 119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS) 120 sc->debug.stats.istats.pm_access++; 121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE) 122 sc->debug.stats.istats.mac_awake++; 123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP) 124 sc->debug.stats.istats.mac_asleep++; 125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS) 126 sc->debug.stats.istats.mac_sleep_access++; 127} 128#endif 129 130 131static void ath9k_hw_set_clockrate(struct ath_hw *ah) 132{ 133 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 134 struct ath_common *common = ath9k_hw_common(ah); 135 unsigned int clockrate; 136 137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 139 clockrate = 117; 140 else if (!ah->curchan) /* should really check for CCK instead */ 141 clockrate = ATH9K_CLOCK_RATE_CCK; 142 else if (conf->chandef.chan->band == IEEE80211_BAND_2GHZ) 143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 146 else 147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 148 149 if (conf_is_ht40(conf)) 150 clockrate *= 2; 151 152 if (ah->curchan) { 153 if (IS_CHAN_HALF_RATE(ah->curchan)) 154 clockrate /= 2; 155 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 156 clockrate /= 4; 157 } 158 159 common->clockrate = clockrate; 160} 161 162static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 163{ 164 struct ath_common *common = ath9k_hw_common(ah); 165 166 return usecs * common->clockrate; 167} 168 169bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 170{ 171 int i; 172 173 BUG_ON(timeout < AH_TIME_QUANTUM); 174 175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 176 if ((REG_READ(ah, reg) & mask) == val) 177 return true; 178 179 udelay(AH_TIME_QUANTUM); 180 } 181 182 ath_dbg(ath9k_hw_common(ah), ANY, 183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 184 timeout, reg, REG_READ(ah, reg), mask, val); 185 186 return false; 187} 188EXPORT_SYMBOL(ath9k_hw_wait); 189 190void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 191 int hw_delay) 192{ 193 if (IS_CHAN_B(chan)) 194 hw_delay = (4 * hw_delay) / 22; 195 else 196 hw_delay /= 10; 197 198 if (IS_CHAN_HALF_RATE(chan)) 199 hw_delay *= 2; 200 else if (IS_CHAN_QUARTER_RATE(chan)) 201 hw_delay *= 4; 202 203 udelay(hw_delay + BASE_ACTIVATE_DELAY); 204} 205 206void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 207 int column, unsigned int *writecnt) 208{ 209 int r; 210 211 ENABLE_REGWRITE_BUFFER(ah); 212 for (r = 0; r < array->ia_rows; r++) { 213 REG_WRITE(ah, INI_RA(array, r, 0), 214 INI_RA(array, r, column)); 215 DO_DELAY(*writecnt); 216 } 217 REGWRITE_BUFFER_FLUSH(ah); 218} 219 220u32 ath9k_hw_reverse_bits(u32 val, u32 n) 221{ 222 u32 retval; 223 int i; 224 225 for (i = 0, retval = 0; i < n; i++) { 226 retval = (retval << 1) | (val & 1); 227 val >>= 1; 228 } 229 return retval; 230} 231 232u16 ath9k_hw_computetxtime(struct ath_hw *ah, 233 u8 phy, int kbps, 234 u32 frameLen, u16 rateix, 235 bool shortPreamble) 236{ 237 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 238 239 if (kbps == 0) 240 return 0; 241 242 switch (phy) { 243 case WLAN_RC_PHY_CCK: 244 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 245 if (shortPreamble) 246 phyTime >>= 1; 247 numBits = frameLen << 3; 248 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 249 break; 250 case WLAN_RC_PHY_OFDM: 251 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 252 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 253 numBits = OFDM_PLCP_BITS + (frameLen << 3); 254 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 255 txTime = OFDM_SIFS_TIME_QUARTER 256 + OFDM_PREAMBLE_TIME_QUARTER 257 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 258 } else if (ah->curchan && 259 IS_CHAN_HALF_RATE(ah->curchan)) { 260 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 261 numBits = OFDM_PLCP_BITS + (frameLen << 3); 262 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 263 txTime = OFDM_SIFS_TIME_HALF + 264 OFDM_PREAMBLE_TIME_HALF 265 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 266 } else { 267 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 268 numBits = OFDM_PLCP_BITS + (frameLen << 3); 269 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 270 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 271 + (numSymbols * OFDM_SYMBOL_TIME); 272 } 273 break; 274 default: 275 ath_err(ath9k_hw_common(ah), 276 "Unknown phy %u (rate ix %u)\n", phy, rateix); 277 txTime = 0; 278 break; 279 } 280 281 return txTime; 282} 283EXPORT_SYMBOL(ath9k_hw_computetxtime); 284 285void ath9k_hw_get_channel_centers(struct ath_hw *ah, 286 struct ath9k_channel *chan, 287 struct chan_centers *centers) 288{ 289 int8_t extoff; 290 291 if (!IS_CHAN_HT40(chan)) { 292 centers->ctl_center = centers->ext_center = 293 centers->synth_center = chan->channel; 294 return; 295 } 296 297 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 298 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 299 centers->synth_center = 300 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 301 extoff = 1; 302 } else { 303 centers->synth_center = 304 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 305 extoff = -1; 306 } 307 308 centers->ctl_center = 309 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 310 /* 25 MHz spacing is supported by hw but not on upper layers */ 311 centers->ext_center = 312 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 313} 314 315/******************/ 316/* Chip Revisions */ 317/******************/ 318 319static void ath9k_hw_read_revisions(struct ath_hw *ah) 320{ 321 u32 val; 322 323 switch (ah->hw_version.devid) { 324 case AR5416_AR9100_DEVID: 325 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 326 break; 327 case AR9300_DEVID_AR9330: 328 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 329 if (ah->get_mac_revision) { 330 ah->hw_version.macRev = ah->get_mac_revision(); 331 } else { 332 val = REG_READ(ah, AR_SREV); 333 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 334 } 335 return; 336 case AR9300_DEVID_AR9340: 337 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 338 val = REG_READ(ah, AR_SREV); 339 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 340 return; 341 case AR9300_DEVID_QCA955X: 342 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 343 return; 344 } 345 346 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 347 348 if (val == 0xFF) { 349 val = REG_READ(ah, AR_SREV); 350 ah->hw_version.macVersion = 351 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 352 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 353 354 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 355 ah->is_pciexpress = true; 356 else 357 ah->is_pciexpress = (val & 358 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 359 } else { 360 if (!AR_SREV_9100(ah)) 361 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 362 363 ah->hw_version.macRev = val & AR_SREV_REVISION; 364 365 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 366 ah->is_pciexpress = true; 367 } 368} 369 370/************************************/ 371/* HW Attach, Detach, Init Routines */ 372/************************************/ 373 374static void ath9k_hw_disablepcie(struct ath_hw *ah) 375{ 376 if (!AR_SREV_5416(ah)) 377 return; 378 379 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 380 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 381 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 382 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 383 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 384 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 385 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 386 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 387 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 388 389 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 390} 391 392/* This should work for all families including legacy */ 393static bool ath9k_hw_chip_test(struct ath_hw *ah) 394{ 395 struct ath_common *common = ath9k_hw_common(ah); 396 u32 regAddr[2] = { AR_STA_ID0 }; 397 u32 regHold[2]; 398 static const u32 patternData[4] = { 399 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 400 }; 401 int i, j, loop_max; 402 403 if (!AR_SREV_9300_20_OR_LATER(ah)) { 404 loop_max = 2; 405 regAddr[1] = AR_PHY_BASE + (8 << 2); 406 } else 407 loop_max = 1; 408 409 for (i = 0; i < loop_max; i++) { 410 u32 addr = regAddr[i]; 411 u32 wrData, rdData; 412 413 regHold[i] = REG_READ(ah, addr); 414 for (j = 0; j < 0x100; j++) { 415 wrData = (j << 16) | j; 416 REG_WRITE(ah, addr, wrData); 417 rdData = REG_READ(ah, addr); 418 if (rdData != wrData) { 419 ath_err(common, 420 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 421 addr, wrData, rdData); 422 return false; 423 } 424 } 425 for (j = 0; j < 4; j++) { 426 wrData = patternData[j]; 427 REG_WRITE(ah, addr, wrData); 428 rdData = REG_READ(ah, addr); 429 if (wrData != rdData) { 430 ath_err(common, 431 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 432 addr, wrData, rdData); 433 return false; 434 } 435 } 436 REG_WRITE(ah, regAddr[i], regHold[i]); 437 } 438 udelay(100); 439 440 return true; 441} 442 443static void ath9k_hw_init_config(struct ath_hw *ah) 444{ 445 int i; 446 447 ah->config.dma_beacon_response_time = 1; 448 ah->config.sw_beacon_response_time = 6; 449 ah->config.additional_swba_backoff = 0; 450 ah->config.ack_6mb = 0x0; 451 ah->config.cwm_ignore_extcca = 0; 452 ah->config.pcie_clock_req = 0; 453 ah->config.analog_shiftreg = 1; 454 455 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 456 ah->config.spurchans[i][0] = AR_NO_SPUR; 457 ah->config.spurchans[i][1] = AR_NO_SPUR; 458 } 459 460 ah->config.rx_intr_mitigation = true; 461 ah->config.pcieSerDesWrite = true; 462 463 /* 464 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 465 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 466 * This means we use it for all AR5416 devices, and the few 467 * minor PCI AR9280 devices out there. 468 * 469 * Serialization is required because these devices do not handle 470 * well the case of two concurrent reads/writes due to the latency 471 * involved. During one read/write another read/write can be issued 472 * on another CPU while the previous read/write may still be working 473 * on our hardware, if we hit this case the hardware poops in a loop. 474 * We prevent this by serializing reads and writes. 475 * 476 * This issue is not present on PCI-Express devices or pre-AR5416 477 * devices (legacy, 802.11abg). 478 */ 479 if (num_possible_cpus() > 1) 480 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 481} 482 483static void ath9k_hw_init_defaults(struct ath_hw *ah) 484{ 485 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 486 487 regulatory->country_code = CTRY_DEFAULT; 488 regulatory->power_limit = MAX_RATE_POWER; 489 490 ah->hw_version.magic = AR5416_MAGIC; 491 ah->hw_version.subvendorid = 0; 492 493 ah->atim_window = 0; 494 ah->sta_id1_defaults = 495 AR_STA_ID1_CRPT_MIC_ENABLE | 496 AR_STA_ID1_MCAST_KSRCH; 497 if (AR_SREV_9100(ah)) 498 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 499 ah->slottime = ATH9K_SLOT_TIME_9; 500 ah->globaltxtimeout = (u32) -1; 501 ah->power_mode = ATH9K_PM_UNDEFINED; 502 ah->htc_reset_init = true; 503} 504 505static int ath9k_hw_init_macaddr(struct ath_hw *ah) 506{ 507 struct ath_common *common = ath9k_hw_common(ah); 508 u32 sum; 509 int i; 510 u16 eeval; 511 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 512 513 sum = 0; 514 for (i = 0; i < 3; i++) { 515 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 516 sum += eeval; 517 common->macaddr[2 * i] = eeval >> 8; 518 common->macaddr[2 * i + 1] = eeval & 0xff; 519 } 520 if (sum == 0 || sum == 0xffff * 3) 521 return -EADDRNOTAVAIL; 522 523 return 0; 524} 525 526static int ath9k_hw_post_init(struct ath_hw *ah) 527{ 528 struct ath_common *common = ath9k_hw_common(ah); 529 int ecode; 530 531 if (common->bus_ops->ath_bus_type != ATH_USB) { 532 if (!ath9k_hw_chip_test(ah)) 533 return -ENODEV; 534 } 535 536 if (!AR_SREV_9300_20_OR_LATER(ah)) { 537 ecode = ar9002_hw_rf_claim(ah); 538 if (ecode != 0) 539 return ecode; 540 } 541 542 ecode = ath9k_hw_eeprom_init(ah); 543 if (ecode != 0) 544 return ecode; 545 546 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 547 ah->eep_ops->get_eeprom_ver(ah), 548 ah->eep_ops->get_eeprom_rev(ah)); 549 550 ath9k_hw_ani_init(ah); 551 552 return 0; 553} 554 555static int ath9k_hw_attach_ops(struct ath_hw *ah) 556{ 557 if (!AR_SREV_9300_20_OR_LATER(ah)) 558 return ar9002_hw_attach_ops(ah); 559 560 ar9003_hw_attach_ops(ah); 561 return 0; 562} 563 564/* Called for all hardware families */ 565static int __ath9k_hw_init(struct ath_hw *ah) 566{ 567 struct ath_common *common = ath9k_hw_common(ah); 568 int r = 0; 569 570 ath9k_hw_read_revisions(ah); 571 572 /* 573 * Read back AR_WA into a permanent copy and set bits 14 and 17. 574 * We need to do this to avoid RMW of this register. We cannot 575 * read the reg when chip is asleep. 576 */ 577 ah->WARegVal = REG_READ(ah, AR_WA); 578 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 579 AR_WA_ASPM_TIMER_BASED_DISABLE); 580 581 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 582 ath_err(common, "Couldn't reset chip\n"); 583 return -EIO; 584 } 585 586 if (AR_SREV_9462(ah)) 587 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 588 589 if (AR_SREV_9565(ah)) { 590 ah->WARegVal |= AR_WA_BIT22; 591 REG_WRITE(ah, AR_WA, ah->WARegVal); 592 } 593 594 ath9k_hw_init_defaults(ah); 595 ath9k_hw_init_config(ah); 596 597 r = ath9k_hw_attach_ops(ah); 598 if (r) 599 return r; 600 601 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 602 ath_err(common, "Couldn't wakeup chip\n"); 603 return -EIO; 604 } 605 606 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 607 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 608 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 609 !ah->is_pciexpress)) { 610 ah->config.serialize_regmode = 611 SER_REG_MODE_ON; 612 } else { 613 ah->config.serialize_regmode = 614 SER_REG_MODE_OFF; 615 } 616 } 617 618 ath_dbg(common, RESET, "serialize_regmode is %d\n", 619 ah->config.serialize_regmode); 620 621 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 622 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 623 else 624 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 625 626 switch (ah->hw_version.macVersion) { 627 case AR_SREV_VERSION_5416_PCI: 628 case AR_SREV_VERSION_5416_PCIE: 629 case AR_SREV_VERSION_9160: 630 case AR_SREV_VERSION_9100: 631 case AR_SREV_VERSION_9280: 632 case AR_SREV_VERSION_9285: 633 case AR_SREV_VERSION_9287: 634 case AR_SREV_VERSION_9271: 635 case AR_SREV_VERSION_9300: 636 case AR_SREV_VERSION_9330: 637 case AR_SREV_VERSION_9485: 638 case AR_SREV_VERSION_9340: 639 case AR_SREV_VERSION_9462: 640 case AR_SREV_VERSION_9550: 641 case AR_SREV_VERSION_9565: 642 break; 643 default: 644 ath_err(common, 645 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 646 ah->hw_version.macVersion, ah->hw_version.macRev); 647 return -EOPNOTSUPP; 648 } 649 650 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 651 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 652 ah->is_pciexpress = false; 653 654 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 655 ath9k_hw_init_cal_settings(ah); 656 657 ah->ani_function = ATH9K_ANI_ALL; 658 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 659 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 660 if (!AR_SREV_9300_20_OR_LATER(ah)) 661 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 662 663 if (!ah->is_pciexpress) 664 ath9k_hw_disablepcie(ah); 665 666 r = ath9k_hw_post_init(ah); 667 if (r) 668 return r; 669 670 ath9k_hw_init_mode_gain_regs(ah); 671 r = ath9k_hw_fill_cap_info(ah); 672 if (r) 673 return r; 674 675 r = ath9k_hw_init_macaddr(ah); 676 if (r) { 677 ath_err(common, "Failed to initialize MAC address\n"); 678 return r; 679 } 680 681 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 682 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 683 else 684 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 685 686 if (AR_SREV_9330(ah)) 687 ah->bb_watchdog_timeout_ms = 85; 688 else 689 ah->bb_watchdog_timeout_ms = 25; 690 691 common->state = ATH_HW_INITIALIZED; 692 693 return 0; 694} 695 696int ath9k_hw_init(struct ath_hw *ah) 697{ 698 int ret; 699 struct ath_common *common = ath9k_hw_common(ah); 700 701 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 702 switch (ah->hw_version.devid) { 703 case AR5416_DEVID_PCI: 704 case AR5416_DEVID_PCIE: 705 case AR5416_AR9100_DEVID: 706 case AR9160_DEVID_PCI: 707 case AR9280_DEVID_PCI: 708 case AR9280_DEVID_PCIE: 709 case AR9285_DEVID_PCIE: 710 case AR9287_DEVID_PCI: 711 case AR9287_DEVID_PCIE: 712 case AR2427_DEVID_PCIE: 713 case AR9300_DEVID_PCIE: 714 case AR9300_DEVID_AR9485_PCIE: 715 case AR9300_DEVID_AR9330: 716 case AR9300_DEVID_AR9340: 717 case AR9300_DEVID_QCA955X: 718 case AR9300_DEVID_AR9580: 719 case AR9300_DEVID_AR9462: 720 case AR9485_DEVID_AR1111: 721 case AR9300_DEVID_AR9565: 722 break; 723 default: 724 if (common->bus_ops->ath_bus_type == ATH_USB) 725 break; 726 ath_err(common, "Hardware device ID 0x%04x not supported\n", 727 ah->hw_version.devid); 728 return -EOPNOTSUPP; 729 } 730 731 ret = __ath9k_hw_init(ah); 732 if (ret) { 733 ath_err(common, 734 "Unable to initialize hardware; initialization status: %d\n", 735 ret); 736 return ret; 737 } 738 739 return 0; 740} 741EXPORT_SYMBOL(ath9k_hw_init); 742 743static void ath9k_hw_init_qos(struct ath_hw *ah) 744{ 745 ENABLE_REGWRITE_BUFFER(ah); 746 747 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 748 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 749 750 REG_WRITE(ah, AR_QOS_NO_ACK, 751 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 752 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 753 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 754 755 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 756 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 757 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 758 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 759 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 760 761 REGWRITE_BUFFER_FLUSH(ah); 762} 763 764u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 765{ 766 struct ath_common *common = ath9k_hw_common(ah); 767 int i = 0; 768 769 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 770 udelay(100); 771 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 772 773 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 774 775 udelay(100); 776 777 if (WARN_ON_ONCE(i >= 100)) { 778 ath_err(common, "PLL4 meaurement not done\n"); 779 break; 780 } 781 782 i++; 783 } 784 785 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 786} 787EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 788 789static void ath9k_hw_init_pll(struct ath_hw *ah, 790 struct ath9k_channel *chan) 791{ 792 u32 pll; 793 794 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 795 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 796 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 797 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 798 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 799 AR_CH0_DPLL2_KD, 0x40); 800 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 801 AR_CH0_DPLL2_KI, 0x4); 802 803 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 804 AR_CH0_BB_DPLL1_REFDIV, 0x5); 805 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 806 AR_CH0_BB_DPLL1_NINI, 0x58); 807 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 808 AR_CH0_BB_DPLL1_NFRAC, 0x0); 809 810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 811 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 813 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 815 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 816 817 /* program BB PLL phase_shift to 0x6 */ 818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 819 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 820 821 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 822 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 823 udelay(1000); 824 } else if (AR_SREV_9330(ah)) { 825 u32 ddr_dpll2, pll_control2, kd; 826 827 if (ah->is_clk_25mhz) { 828 ddr_dpll2 = 0x18e82f01; 829 pll_control2 = 0xe04a3d; 830 kd = 0x1d; 831 } else { 832 ddr_dpll2 = 0x19e82f01; 833 pll_control2 = 0x886666; 834 kd = 0x3d; 835 } 836 837 /* program DDR PLL ki and kd value */ 838 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 839 840 /* program DDR PLL phase_shift */ 841 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 842 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 843 844 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 845 udelay(1000); 846 847 /* program refdiv, nint, frac to RTC register */ 848 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 849 850 /* program BB PLL kd and ki value */ 851 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 852 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 853 854 /* program BB PLL phase_shift */ 855 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 856 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 857 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 858 u32 regval, pll2_divint, pll2_divfrac, refdiv; 859 860 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 861 udelay(1000); 862 863 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 864 udelay(100); 865 866 if (ah->is_clk_25mhz) { 867 pll2_divint = 0x54; 868 pll2_divfrac = 0x1eb85; 869 refdiv = 3; 870 } else { 871 if (AR_SREV_9340(ah)) { 872 pll2_divint = 88; 873 pll2_divfrac = 0; 874 refdiv = 5; 875 } else { 876 pll2_divint = 0x11; 877 pll2_divfrac = 0x26666; 878 refdiv = 1; 879 } 880 } 881 882 regval = REG_READ(ah, AR_PHY_PLL_MODE); 883 regval |= (0x1 << 16); 884 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 885 udelay(100); 886 887 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 888 (pll2_divint << 18) | pll2_divfrac); 889 udelay(100); 890 891 regval = REG_READ(ah, AR_PHY_PLL_MODE); 892 if (AR_SREV_9340(ah)) 893 regval = (regval & 0x80071fff) | (0x1 << 30) | 894 (0x1 << 13) | (0x4 << 26) | (0x18 << 19); 895 else 896 regval = (regval & 0x80071fff) | (0x3 << 30) | 897 (0x1 << 13) | (0x4 << 26) | (0x60 << 19); 898 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 899 REG_WRITE(ah, AR_PHY_PLL_MODE, 900 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 901 udelay(1000); 902 } 903 904 pll = ath9k_hw_compute_pll_control(ah, chan); 905 if (AR_SREV_9565(ah)) 906 pll |= 0x40000; 907 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 908 909 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 910 AR_SREV_9550(ah)) 911 udelay(1000); 912 913 /* Switch the core clock for ar9271 to 117Mhz */ 914 if (AR_SREV_9271(ah)) { 915 udelay(500); 916 REG_WRITE(ah, 0x50040, 0x304); 917 } 918 919 udelay(RTC_PLL_SETTLE_DELAY); 920 921 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 922 923 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 924 if (ah->is_clk_25mhz) { 925 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 926 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 927 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 928 } else { 929 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 930 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 931 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 932 } 933 udelay(100); 934 } 935} 936 937static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 938 enum nl80211_iftype opmode) 939{ 940 u32 sync_default = AR_INTR_SYNC_DEFAULT; 941 u32 imr_reg = AR_IMR_TXERR | 942 AR_IMR_TXURN | 943 AR_IMR_RXERR | 944 AR_IMR_RXORN | 945 AR_IMR_BCNMISC; 946 947 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) 948 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 949 950 if (AR_SREV_9300_20_OR_LATER(ah)) { 951 imr_reg |= AR_IMR_RXOK_HP; 952 if (ah->config.rx_intr_mitigation) 953 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 954 else 955 imr_reg |= AR_IMR_RXOK_LP; 956 957 } else { 958 if (ah->config.rx_intr_mitigation) 959 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 960 else 961 imr_reg |= AR_IMR_RXOK; 962 } 963 964 if (ah->config.tx_intr_mitigation) 965 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 966 else 967 imr_reg |= AR_IMR_TXOK; 968 969 ENABLE_REGWRITE_BUFFER(ah); 970 971 REG_WRITE(ah, AR_IMR, imr_reg); 972 ah->imrs2_reg |= AR_IMR_S2_GTT; 973 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 974 975 if (!AR_SREV_9100(ah)) { 976 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 977 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 978 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 979 } 980 981 REGWRITE_BUFFER_FLUSH(ah); 982 983 if (AR_SREV_9300_20_OR_LATER(ah)) { 984 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 985 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 986 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 987 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 988 } 989} 990 991static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 992{ 993 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 994 val = min(val, (u32) 0xFFFF); 995 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 996} 997 998static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 999{ 1000 u32 val = ath9k_hw_mac_to_clks(ah, us); 1001 val = min(val, (u32) 0xFFFF); 1002 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1003} 1004 1005static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1006{ 1007 u32 val = ath9k_hw_mac_to_clks(ah, us); 1008 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1009 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1010} 1011 1012static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1013{ 1014 u32 val = ath9k_hw_mac_to_clks(ah, us); 1015 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1016 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1017} 1018 1019static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1020{ 1021 if (tu > 0xFFFF) { 1022 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1023 tu); 1024 ah->globaltxtimeout = (u32) -1; 1025 return false; 1026 } else { 1027 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1028 ah->globaltxtimeout = tu; 1029 return true; 1030 } 1031} 1032 1033void ath9k_hw_init_global_settings(struct ath_hw *ah) 1034{ 1035 struct ath_common *common = ath9k_hw_common(ah); 1036 struct ieee80211_conf *conf = &common->hw->conf; 1037 const struct ath9k_channel *chan = ah->curchan; 1038 int acktimeout, ctstimeout, ack_offset = 0; 1039 int slottime; 1040 int sifstime; 1041 int rx_lat = 0, tx_lat = 0, eifs = 0; 1042 u32 reg; 1043 1044 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1045 ah->misc_mode); 1046 1047 if (!chan) 1048 return; 1049 1050 if (ah->misc_mode != 0) 1051 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1052 1053 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1054 rx_lat = 41; 1055 else 1056 rx_lat = 37; 1057 tx_lat = 54; 1058 1059 if (IS_CHAN_5GHZ(chan)) 1060 sifstime = 16; 1061 else 1062 sifstime = 10; 1063 1064 if (IS_CHAN_HALF_RATE(chan)) { 1065 eifs = 175; 1066 rx_lat *= 2; 1067 tx_lat *= 2; 1068 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1069 tx_lat += 11; 1070 1071 sifstime = 32; 1072 ack_offset = 16; 1073 slottime = 13; 1074 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1075 eifs = 340; 1076 rx_lat = (rx_lat * 4) - 1; 1077 tx_lat *= 4; 1078 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1079 tx_lat += 22; 1080 1081 sifstime = 64; 1082 ack_offset = 32; 1083 slottime = 21; 1084 } else { 1085 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1086 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1087 reg = AR_USEC_ASYNC_FIFO; 1088 } else { 1089 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1090 common->clockrate; 1091 reg = REG_READ(ah, AR_USEC); 1092 } 1093 rx_lat = MS(reg, AR_USEC_RX_LAT); 1094 tx_lat = MS(reg, AR_USEC_TX_LAT); 1095 1096 slottime = ah->slottime; 1097 } 1098 1099 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1100 slottime += 3 * ah->coverage_class; 1101 acktimeout = slottime + sifstime + ack_offset; 1102 ctstimeout = acktimeout; 1103 1104 /* 1105 * Workaround for early ACK timeouts, add an offset to match the 1106 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1107 * This was initially only meant to work around an issue with delayed 1108 * BA frames in some implementations, but it has been found to fix ACK 1109 * timeout issues in other cases as well. 1110 */ 1111 if (conf->chandef.chan && 1112 conf->chandef.chan->band == IEEE80211_BAND_2GHZ && 1113 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1114 acktimeout += 64 - sifstime - ah->slottime; 1115 ctstimeout += 48 - sifstime - ah->slottime; 1116 } 1117 1118 ath9k_hw_set_sifs_time(ah, sifstime); 1119 ath9k_hw_setslottime(ah, slottime); 1120 ath9k_hw_set_ack_timeout(ah, acktimeout); 1121 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1122 if (ah->globaltxtimeout != (u32) -1) 1123 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1124 1125 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1126 REG_RMW(ah, AR_USEC, 1127 (common->clockrate - 1) | 1128 SM(rx_lat, AR_USEC_RX_LAT) | 1129 SM(tx_lat, AR_USEC_TX_LAT), 1130 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1131 1132} 1133EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1134 1135void ath9k_hw_deinit(struct ath_hw *ah) 1136{ 1137 struct ath_common *common = ath9k_hw_common(ah); 1138 1139 if (common->state < ATH_HW_INITIALIZED) 1140 return; 1141 1142 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1143} 1144EXPORT_SYMBOL(ath9k_hw_deinit); 1145 1146/*******/ 1147/* INI */ 1148/*******/ 1149 1150u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1151{ 1152 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1153 1154 if (IS_CHAN_B(chan)) 1155 ctl |= CTL_11B; 1156 else if (IS_CHAN_G(chan)) 1157 ctl |= CTL_11G; 1158 else 1159 ctl |= CTL_11A; 1160 1161 return ctl; 1162} 1163 1164/****************************************/ 1165/* Reset and Channel Switching Routines */ 1166/****************************************/ 1167 1168static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1169{ 1170 struct ath_common *common = ath9k_hw_common(ah); 1171 int txbuf_size; 1172 1173 ENABLE_REGWRITE_BUFFER(ah); 1174 1175 /* 1176 * set AHB_MODE not to do cacheline prefetches 1177 */ 1178 if (!AR_SREV_9300_20_OR_LATER(ah)) 1179 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1180 1181 /* 1182 * let mac dma reads be in 128 byte chunks 1183 */ 1184 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1185 1186 REGWRITE_BUFFER_FLUSH(ah); 1187 1188 /* 1189 * Restore TX Trigger Level to its pre-reset value. 1190 * The initial value depends on whether aggregation is enabled, and is 1191 * adjusted whenever underruns are detected. 1192 */ 1193 if (!AR_SREV_9300_20_OR_LATER(ah)) 1194 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1195 1196 ENABLE_REGWRITE_BUFFER(ah); 1197 1198 /* 1199 * let mac dma writes be in 128 byte chunks 1200 */ 1201 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1202 1203 /* 1204 * Setup receive FIFO threshold to hold off TX activities 1205 */ 1206 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1207 1208 if (AR_SREV_9300_20_OR_LATER(ah)) { 1209 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1210 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1211 1212 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1213 ah->caps.rx_status_len); 1214 } 1215 1216 /* 1217 * reduce the number of usable entries in PCU TXBUF to avoid 1218 * wrap around issues. 1219 */ 1220 if (AR_SREV_9285(ah)) { 1221 /* For AR9285 the number of Fifos are reduced to half. 1222 * So set the usable tx buf size also to half to 1223 * avoid data/delimiter underruns 1224 */ 1225 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1226 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1227 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1228 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1229 } else { 1230 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1231 } 1232 1233 if (!AR_SREV_9271(ah)) 1234 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1235 1236 REGWRITE_BUFFER_FLUSH(ah); 1237 1238 if (AR_SREV_9300_20_OR_LATER(ah)) 1239 ath9k_hw_reset_txstatus_ring(ah); 1240} 1241 1242static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1243{ 1244 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1245 u32 set = AR_STA_ID1_KSRCH_MODE; 1246 1247 switch (opmode) { 1248 case NL80211_IFTYPE_ADHOC: 1249 set |= AR_STA_ID1_ADHOC; 1250 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1251 break; 1252 case NL80211_IFTYPE_MESH_POINT: 1253 case NL80211_IFTYPE_AP: 1254 set |= AR_STA_ID1_STA_AP; 1255 /* fall through */ 1256 case NL80211_IFTYPE_STATION: 1257 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1258 break; 1259 default: 1260 if (!ah->is_monitoring) 1261 set = 0; 1262 break; 1263 } 1264 REG_RMW(ah, AR_STA_ID1, set, mask); 1265} 1266 1267void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1268 u32 *coef_mantissa, u32 *coef_exponent) 1269{ 1270 u32 coef_exp, coef_man; 1271 1272 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1273 if ((coef_scaled >> coef_exp) & 0x1) 1274 break; 1275 1276 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1277 1278 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1279 1280 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1281 *coef_exponent = coef_exp - 16; 1282} 1283 1284static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1285{ 1286 u32 rst_flags; 1287 u32 tmpReg; 1288 1289 if (AR_SREV_9100(ah)) { 1290 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1291 AR_RTC_DERIVED_CLK_PERIOD, 1); 1292 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1293 } 1294 1295 ENABLE_REGWRITE_BUFFER(ah); 1296 1297 if (AR_SREV_9300_20_OR_LATER(ah)) { 1298 REG_WRITE(ah, AR_WA, ah->WARegVal); 1299 udelay(10); 1300 } 1301 1302 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1303 AR_RTC_FORCE_WAKE_ON_INT); 1304 1305 if (AR_SREV_9100(ah)) { 1306 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1307 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1308 } else { 1309 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1310 if (AR_SREV_9340(ah)) 1311 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1312 else 1313 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1314 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1315 1316 if (tmpReg) { 1317 u32 val; 1318 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1319 1320 val = AR_RC_HOSTIF; 1321 if (!AR_SREV_9300_20_OR_LATER(ah)) 1322 val |= AR_RC_AHB; 1323 REG_WRITE(ah, AR_RC, val); 1324 1325 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1326 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1327 1328 rst_flags = AR_RTC_RC_MAC_WARM; 1329 if (type == ATH9K_RESET_COLD) 1330 rst_flags |= AR_RTC_RC_MAC_COLD; 1331 } 1332 1333 if (AR_SREV_9330(ah)) { 1334 int npend = 0; 1335 int i; 1336 1337 /* AR9330 WAR: 1338 * call external reset function to reset WMAC if: 1339 * - doing a cold reset 1340 * - we have pending frames in the TX queues 1341 */ 1342 1343 for (i = 0; i < AR_NUM_QCU; i++) { 1344 npend = ath9k_hw_numtxpending(ah, i); 1345 if (npend) 1346 break; 1347 } 1348 1349 if (ah->external_reset && 1350 (npend || type == ATH9K_RESET_COLD)) { 1351 int reset_err = 0; 1352 1353 ath_dbg(ath9k_hw_common(ah), RESET, 1354 "reset MAC via external reset\n"); 1355 1356 reset_err = ah->external_reset(); 1357 if (reset_err) { 1358 ath_err(ath9k_hw_common(ah), 1359 "External reset failed, err=%d\n", 1360 reset_err); 1361 return false; 1362 } 1363 1364 REG_WRITE(ah, AR_RTC_RESET, 1); 1365 } 1366 } 1367 1368 if (ath9k_hw_mci_is_enabled(ah)) 1369 ar9003_mci_check_gpm_offset(ah); 1370 1371 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1372 1373 REGWRITE_BUFFER_FLUSH(ah); 1374 1375 udelay(50); 1376 1377 REG_WRITE(ah, AR_RTC_RC, 0); 1378 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1379 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1380 return false; 1381 } 1382 1383 if (!AR_SREV_9100(ah)) 1384 REG_WRITE(ah, AR_RC, 0); 1385 1386 if (AR_SREV_9100(ah)) 1387 udelay(50); 1388 1389 return true; 1390} 1391 1392static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1393{ 1394 ENABLE_REGWRITE_BUFFER(ah); 1395 1396 if (AR_SREV_9300_20_OR_LATER(ah)) { 1397 REG_WRITE(ah, AR_WA, ah->WARegVal); 1398 udelay(10); 1399 } 1400 1401 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1402 AR_RTC_FORCE_WAKE_ON_INT); 1403 1404 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1405 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1406 1407 REG_WRITE(ah, AR_RTC_RESET, 0); 1408 1409 REGWRITE_BUFFER_FLUSH(ah); 1410 1411 if (!AR_SREV_9300_20_OR_LATER(ah)) 1412 udelay(2); 1413 1414 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1415 REG_WRITE(ah, AR_RC, 0); 1416 1417 REG_WRITE(ah, AR_RTC_RESET, 1); 1418 1419 if (!ath9k_hw_wait(ah, 1420 AR_RTC_STATUS, 1421 AR_RTC_STATUS_M, 1422 AR_RTC_STATUS_ON, 1423 AH_WAIT_TIMEOUT)) { 1424 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1425 return false; 1426 } 1427 1428 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1429} 1430 1431static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1432{ 1433 bool ret = false; 1434 1435 if (AR_SREV_9300_20_OR_LATER(ah)) { 1436 REG_WRITE(ah, AR_WA, ah->WARegVal); 1437 udelay(10); 1438 } 1439 1440 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1441 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1442 1443 if (!ah->reset_power_on) 1444 type = ATH9K_RESET_POWER_ON; 1445 1446 switch (type) { 1447 case ATH9K_RESET_POWER_ON: 1448 ret = ath9k_hw_set_reset_power_on(ah); 1449 if (ret) 1450 ah->reset_power_on = true; 1451 break; 1452 case ATH9K_RESET_WARM: 1453 case ATH9K_RESET_COLD: 1454 ret = ath9k_hw_set_reset(ah, type); 1455 break; 1456 default: 1457 break; 1458 } 1459 1460 return ret; 1461} 1462 1463static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1464 struct ath9k_channel *chan) 1465{ 1466 int reset_type = ATH9K_RESET_WARM; 1467 1468 if (AR_SREV_9280(ah)) { 1469 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1470 reset_type = ATH9K_RESET_POWER_ON; 1471 else 1472 reset_type = ATH9K_RESET_COLD; 1473 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1474 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1475 reset_type = ATH9K_RESET_COLD; 1476 1477 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1478 return false; 1479 1480 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1481 return false; 1482 1483 ah->chip_fullsleep = false; 1484 1485 if (AR_SREV_9330(ah)) 1486 ar9003_hw_internal_regulator_apply(ah); 1487 ath9k_hw_init_pll(ah, chan); 1488 ath9k_hw_set_rfmode(ah, chan); 1489 1490 return true; 1491} 1492 1493static bool ath9k_hw_channel_change(struct ath_hw *ah, 1494 struct ath9k_channel *chan) 1495{ 1496 struct ath_common *common = ath9k_hw_common(ah); 1497 struct ath9k_hw_capabilities *pCap = &ah->caps; 1498 bool band_switch = false, mode_diff = false; 1499 u8 ini_reloaded = 0; 1500 u32 qnum; 1501 int r; 1502 1503 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1504 u32 cur = ah->curchan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ); 1505 u32 new = chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ); 1506 band_switch = (cur != new); 1507 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1508 } 1509 1510 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1511 if (ath9k_hw_numtxpending(ah, qnum)) { 1512 ath_dbg(common, QUEUE, 1513 "Transmit frames pending on queue %d\n", qnum); 1514 return false; 1515 } 1516 } 1517 1518 if (!ath9k_hw_rfbus_req(ah)) { 1519 ath_err(common, "Could not kill baseband RX\n"); 1520 return false; 1521 } 1522 1523 if (band_switch || mode_diff) { 1524 ath9k_hw_mark_phy_inactive(ah); 1525 udelay(5); 1526 1527 if (band_switch) 1528 ath9k_hw_init_pll(ah, chan); 1529 1530 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1531 ath_err(common, "Failed to do fast channel change\n"); 1532 return false; 1533 } 1534 } 1535 1536 ath9k_hw_set_channel_regs(ah, chan); 1537 1538 r = ath9k_hw_rf_set_freq(ah, chan); 1539 if (r) { 1540 ath_err(common, "Failed to set channel\n"); 1541 return false; 1542 } 1543 ath9k_hw_set_clockrate(ah); 1544 ath9k_hw_apply_txpower(ah, chan, false); 1545 1546 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1547 ath9k_hw_set_delta_slope(ah, chan); 1548 1549 ath9k_hw_spur_mitigate_freq(ah, chan); 1550 1551 if (band_switch || ini_reloaded) 1552 ah->eep_ops->set_board_values(ah, chan); 1553 1554 ath9k_hw_init_bb(ah, chan); 1555 ath9k_hw_rfbus_done(ah); 1556 1557 if (band_switch || ini_reloaded) { 1558 ah->ah_flags |= AH_FASTCC; 1559 ath9k_hw_init_cal(ah, chan); 1560 ah->ah_flags &= ~AH_FASTCC; 1561 } 1562 1563 return true; 1564} 1565 1566static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1567{ 1568 u32 gpio_mask = ah->gpio_mask; 1569 int i; 1570 1571 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1572 if (!(gpio_mask & 1)) 1573 continue; 1574 1575 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1576 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1577 } 1578} 1579 1580static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states, 1581 int *hang_state, int *hang_pos) 1582{ 1583 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */ 1584 u32 chain_state, dcs_pos, i; 1585 1586 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) { 1587 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f; 1588 for (i = 0; i < 3; i++) { 1589 if (chain_state == dcu_chain_state[i]) { 1590 *hang_state = chain_state; 1591 *hang_pos = dcs_pos; 1592 return true; 1593 } 1594 } 1595 } 1596 return false; 1597} 1598 1599#define DCU_COMPLETE_STATE 1 1600#define DCU_COMPLETE_STATE_MASK 0x3 1601#define NUM_STATUS_READS 50 1602static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah) 1603{ 1604 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4; 1605 u32 i, hang_pos, hang_state, num_state = 6; 1606 1607 comp_state = REG_READ(ah, AR_DMADBG_6); 1608 1609 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) { 1610 ath_dbg(ath9k_hw_common(ah), RESET, 1611 "MAC Hang signature not found at DCU complete\n"); 1612 return false; 1613 } 1614 1615 chain_state = REG_READ(ah, dcs_reg); 1616 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1617 goto hang_check_iter; 1618 1619 dcs_reg = AR_DMADBG_5; 1620 num_state = 4; 1621 chain_state = REG_READ(ah, dcs_reg); 1622 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1623 goto hang_check_iter; 1624 1625 ath_dbg(ath9k_hw_common(ah), RESET, 1626 "MAC Hang signature 1 not found\n"); 1627 return false; 1628 1629hang_check_iter: 1630 ath_dbg(ath9k_hw_common(ah), RESET, 1631 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n", 1632 chain_state, comp_state, hang_state, hang_pos); 1633 1634 for (i = 0; i < NUM_STATUS_READS; i++) { 1635 chain_state = REG_READ(ah, dcs_reg); 1636 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f; 1637 comp_state = REG_READ(ah, AR_DMADBG_6); 1638 1639 if (((comp_state & DCU_COMPLETE_STATE_MASK) != 1640 DCU_COMPLETE_STATE) || 1641 (chain_state != hang_state)) 1642 return false; 1643 } 1644 1645 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n"); 1646 1647 return true; 1648} 1649 1650bool ath9k_hw_check_alive(struct ath_hw *ah) 1651{ 1652 int count = 50; 1653 u32 reg; 1654 1655 if (AR_SREV_9300(ah)) 1656 return !ath9k_hw_detect_mac_hang(ah); 1657 1658 if (AR_SREV_9285_12_OR_LATER(ah)) 1659 return true; 1660 1661 do { 1662 reg = REG_READ(ah, AR_OBS_BUS_1); 1663 1664 if ((reg & 0x7E7FFFEF) == 0x00702400) 1665 continue; 1666 1667 switch (reg & 0x7E000B00) { 1668 case 0x1E000000: 1669 case 0x52000B00: 1670 case 0x18000B00: 1671 continue; 1672 default: 1673 return true; 1674 } 1675 } while (count-- > 0); 1676 1677 return false; 1678} 1679EXPORT_SYMBOL(ath9k_hw_check_alive); 1680 1681static void ath9k_hw_init_mfp(struct ath_hw *ah) 1682{ 1683 /* Setup MFP options for CCMP */ 1684 if (AR_SREV_9280_20_OR_LATER(ah)) { 1685 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1686 * frames when constructing CCMP AAD. */ 1687 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1688 0xc7ff); 1689 ah->sw_mgmt_crypto = false; 1690 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1691 /* Disable hardware crypto for management frames */ 1692 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1693 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1694 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1695 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1696 ah->sw_mgmt_crypto = true; 1697 } else { 1698 ah->sw_mgmt_crypto = true; 1699 } 1700} 1701 1702static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1703 u32 macStaId1, u32 saveDefAntenna) 1704{ 1705 struct ath_common *common = ath9k_hw_common(ah); 1706 1707 ENABLE_REGWRITE_BUFFER(ah); 1708 1709 REG_RMW(ah, AR_STA_ID1, macStaId1 1710 | AR_STA_ID1_RTS_USE_DEF 1711 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1712 | ah->sta_id1_defaults, 1713 ~AR_STA_ID1_SADH_MASK); 1714 ath_hw_setbssidmask(common); 1715 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1716 ath9k_hw_write_associd(ah); 1717 REG_WRITE(ah, AR_ISR, ~0); 1718 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1719 1720 REGWRITE_BUFFER_FLUSH(ah); 1721 1722 ath9k_hw_set_operating_mode(ah, ah->opmode); 1723} 1724 1725static void ath9k_hw_init_queues(struct ath_hw *ah) 1726{ 1727 int i; 1728 1729 ENABLE_REGWRITE_BUFFER(ah); 1730 1731 for (i = 0; i < AR_NUM_DCU; i++) 1732 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1733 1734 REGWRITE_BUFFER_FLUSH(ah); 1735 1736 ah->intr_txqs = 0; 1737 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1738 ath9k_hw_resettxqueue(ah, i); 1739} 1740 1741/* 1742 * For big endian systems turn on swapping for descriptors 1743 */ 1744static void ath9k_hw_init_desc(struct ath_hw *ah) 1745{ 1746 struct ath_common *common = ath9k_hw_common(ah); 1747 1748 if (AR_SREV_9100(ah)) { 1749 u32 mask; 1750 mask = REG_READ(ah, AR_CFG); 1751 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1752 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1753 mask); 1754 } else { 1755 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1756 REG_WRITE(ah, AR_CFG, mask); 1757 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1758 REG_READ(ah, AR_CFG)); 1759 } 1760 } else { 1761 if (common->bus_ops->ath_bus_type == ATH_USB) { 1762 /* Configure AR9271 target WLAN */ 1763 if (AR_SREV_9271(ah)) 1764 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1765 else 1766 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1767 } 1768#ifdef __BIG_ENDIAN 1769 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1770 AR_SREV_9550(ah)) 1771 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1772 else 1773 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1774#endif 1775 } 1776} 1777 1778/* 1779 * Fast channel change: 1780 * (Change synthesizer based on channel freq without resetting chip) 1781 */ 1782static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1783{ 1784 struct ath_common *common = ath9k_hw_common(ah); 1785 struct ath9k_hw_capabilities *pCap = &ah->caps; 1786 int ret; 1787 1788 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1789 goto fail; 1790 1791 if (ah->chip_fullsleep) 1792 goto fail; 1793 1794 if (!ah->curchan) 1795 goto fail; 1796 1797 if (chan->channel == ah->curchan->channel) 1798 goto fail; 1799 1800 if ((ah->curchan->channelFlags | chan->channelFlags) & 1801 (CHANNEL_HALF | CHANNEL_QUARTER)) 1802 goto fail; 1803 1804 /* 1805 * If cross-band fcc is not supoprted, bail out if 1806 * either channelFlags or chanmode differ. 1807 * 1808 * chanmode will be different if the HT operating mode 1809 * changes because of CSA. 1810 */ 1811 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH)) { 1812 if ((chan->channelFlags & CHANNEL_ALL) != 1813 (ah->curchan->channelFlags & CHANNEL_ALL)) 1814 goto fail; 1815 1816 if (chan->chanmode != ah->curchan->chanmode) 1817 goto fail; 1818 } 1819 1820 if (!ath9k_hw_check_alive(ah)) 1821 goto fail; 1822 1823 /* 1824 * For AR9462, make sure that calibration data for 1825 * re-using are present. 1826 */ 1827 if (AR_SREV_9462(ah) && (ah->caldata && 1828 (!ah->caldata->done_txiqcal_once || 1829 !ah->caldata->done_txclcal_once || 1830 !ah->caldata->rtt_done))) 1831 goto fail; 1832 1833 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1834 ah->curchan->channel, chan->channel); 1835 1836 ret = ath9k_hw_channel_change(ah, chan); 1837 if (!ret) 1838 goto fail; 1839 1840 if (ath9k_hw_mci_is_enabled(ah)) 1841 ar9003_mci_2g5g_switch(ah, false); 1842 1843 ath9k_hw_loadnf(ah, ah->curchan); 1844 ath9k_hw_start_nfcal(ah, true); 1845 1846 if (AR_SREV_9271(ah)) 1847 ar9002_hw_load_ani_reg(ah, chan); 1848 1849 return 0; 1850fail: 1851 return -EINVAL; 1852} 1853 1854int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1855 struct ath9k_hw_cal_data *caldata, bool fastcc) 1856{ 1857 struct ath_common *common = ath9k_hw_common(ah); 1858 u32 saveLedState; 1859 u32 saveDefAntenna; 1860 u32 macStaId1; 1861 u64 tsf = 0; 1862 int r; 1863 bool start_mci_reset = false; 1864 bool save_fullsleep = ah->chip_fullsleep; 1865 1866 if (ath9k_hw_mci_is_enabled(ah)) { 1867 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1868 if (start_mci_reset) 1869 return 0; 1870 } 1871 1872 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1873 return -EIO; 1874 1875 if (ah->curchan && !ah->chip_fullsleep) 1876 ath9k_hw_getnf(ah, ah->curchan); 1877 1878 ah->caldata = caldata; 1879 if (caldata && (chan->channel != caldata->channel || 1880 chan->channelFlags != caldata->channelFlags || 1881 chan->chanmode != caldata->chanmode)) { 1882 /* Operating channel changed, reset channel calibration data */ 1883 memset(caldata, 0, sizeof(*caldata)); 1884 ath9k_init_nfcal_hist_buffer(ah, chan); 1885 } else if (caldata) { 1886 caldata->paprd_packet_sent = false; 1887 } 1888 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1889 1890 if (fastcc) { 1891 r = ath9k_hw_do_fastcc(ah, chan); 1892 if (!r) 1893 return r; 1894 } 1895 1896 if (ath9k_hw_mci_is_enabled(ah)) 1897 ar9003_mci_stop_bt(ah, save_fullsleep); 1898 1899 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1900 if (saveDefAntenna == 0) 1901 saveDefAntenna = 1; 1902 1903 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1904 1905 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1906 if (AR_SREV_9100(ah) || 1907 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1908 tsf = ath9k_hw_gettsf64(ah); 1909 1910 saveLedState = REG_READ(ah, AR_CFG_LED) & 1911 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1912 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1913 1914 ath9k_hw_mark_phy_inactive(ah); 1915 1916 ah->paprd_table_write_done = false; 1917 1918 /* Only required on the first reset */ 1919 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1920 REG_WRITE(ah, 1921 AR9271_RESET_POWER_DOWN_CONTROL, 1922 AR9271_RADIO_RF_RST); 1923 udelay(50); 1924 } 1925 1926 if (!ath9k_hw_chip_reset(ah, chan)) { 1927 ath_err(common, "Chip reset failed\n"); 1928 return -EINVAL; 1929 } 1930 1931 /* Only required on the first reset */ 1932 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1933 ah->htc_reset_init = false; 1934 REG_WRITE(ah, 1935 AR9271_RESET_POWER_DOWN_CONTROL, 1936 AR9271_GATE_MAC_CTL); 1937 udelay(50); 1938 } 1939 1940 /* Restore TSF */ 1941 if (tsf) 1942 ath9k_hw_settsf64(ah, tsf); 1943 1944 if (AR_SREV_9280_20_OR_LATER(ah)) 1945 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1946 1947 if (!AR_SREV_9300_20_OR_LATER(ah)) 1948 ar9002_hw_enable_async_fifo(ah); 1949 1950 r = ath9k_hw_process_ini(ah, chan); 1951 if (r) 1952 return r; 1953 1954 if (ath9k_hw_mci_is_enabled(ah)) 1955 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1956 1957 /* 1958 * Some AR91xx SoC devices frequently fail to accept TSF writes 1959 * right after the chip reset. When that happens, write a new 1960 * value after the initvals have been applied, with an offset 1961 * based on measured time difference 1962 */ 1963 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1964 tsf += 1500; 1965 ath9k_hw_settsf64(ah, tsf); 1966 } 1967 1968 ath9k_hw_init_mfp(ah); 1969 1970 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1971 ath9k_hw_set_delta_slope(ah, chan); 1972 1973 ath9k_hw_spur_mitigate_freq(ah, chan); 1974 ah->eep_ops->set_board_values(ah, chan); 1975 1976 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1977 1978 r = ath9k_hw_rf_set_freq(ah, chan); 1979 if (r) 1980 return r; 1981 1982 ath9k_hw_set_clockrate(ah); 1983 1984 ath9k_hw_init_queues(ah); 1985 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1986 ath9k_hw_ani_cache_ini_regs(ah); 1987 ath9k_hw_init_qos(ah); 1988 1989 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1990 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1991 1992 ath9k_hw_init_global_settings(ah); 1993 1994 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1995 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1996 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1997 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1998 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1999 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 2000 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 2001 } 2002 2003 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2004 2005 ath9k_hw_set_dma(ah); 2006 2007 if (!ath9k_hw_mci_is_enabled(ah)) 2008 REG_WRITE(ah, AR_OBS, 8); 2009 2010 if (ah->config.rx_intr_mitigation) { 2011 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2012 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2013 } 2014 2015 if (ah->config.tx_intr_mitigation) { 2016 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 2017 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 2018 } 2019 2020 ath9k_hw_init_bb(ah, chan); 2021 2022 if (caldata) { 2023 caldata->done_txiqcal_once = false; 2024 caldata->done_txclcal_once = false; 2025 } 2026 if (!ath9k_hw_init_cal(ah, chan)) 2027 return -EIO; 2028 2029 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 2030 return -EIO; 2031 2032 ENABLE_REGWRITE_BUFFER(ah); 2033 2034 ath9k_hw_restore_chainmask(ah); 2035 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2036 2037 REGWRITE_BUFFER_FLUSH(ah); 2038 2039 ath9k_hw_init_desc(ah); 2040 2041 if (ath9k_hw_btcoex_is_enabled(ah)) 2042 ath9k_hw_btcoex_enable(ah); 2043 2044 if (ath9k_hw_mci_is_enabled(ah)) 2045 ar9003_mci_check_bt(ah); 2046 2047 ath9k_hw_loadnf(ah, chan); 2048 ath9k_hw_start_nfcal(ah, true); 2049 2050 if (AR_SREV_9300_20_OR_LATER(ah)) { 2051 ar9003_hw_bb_watchdog_config(ah); 2052 ar9003_hw_disable_phy_restart(ah); 2053 } 2054 2055 ath9k_hw_apply_gpio_override(ah); 2056 2057 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 2058 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2059 2060 return 0; 2061} 2062EXPORT_SYMBOL(ath9k_hw_reset); 2063 2064/******************************/ 2065/* Power Management (Chipset) */ 2066/******************************/ 2067 2068/* 2069 * Notify Power Mgt is disabled in self-generated frames. 2070 * If requested, force chip to sleep. 2071 */ 2072static void ath9k_set_power_sleep(struct ath_hw *ah) 2073{ 2074 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2075 2076 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2077 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2078 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2079 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2080 /* xxx Required for WLAN only case ? */ 2081 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2082 udelay(100); 2083 } 2084 2085 /* 2086 * Clear the RTC force wake bit to allow the 2087 * mac to go to sleep. 2088 */ 2089 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2090 2091 if (ath9k_hw_mci_is_enabled(ah)) 2092 udelay(100); 2093 2094 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2095 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2096 2097 /* Shutdown chip. Active low */ 2098 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2099 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2100 udelay(2); 2101 } 2102 2103 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2104 if (AR_SREV_9300_20_OR_LATER(ah)) 2105 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2106} 2107 2108/* 2109 * Notify Power Management is enabled in self-generating 2110 * frames. If request, set power mode of chip to 2111 * auto/normal. Duration in units of 128us (1/8 TU). 2112 */ 2113static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2114{ 2115 struct ath9k_hw_capabilities *pCap = &ah->caps; 2116 2117 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2118 2119 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2120 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2121 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2122 AR_RTC_FORCE_WAKE_ON_INT); 2123 } else { 2124 2125 /* When chip goes into network sleep, it could be waken 2126 * up by MCI_INT interrupt caused by BT's HW messages 2127 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2128 * rate (~100us). This will cause chip to leave and 2129 * re-enter network sleep mode frequently, which in 2130 * consequence will have WLAN MCI HW to generate lots of 2131 * SYS_WAKING and SYS_SLEEPING messages which will make 2132 * BT CPU to busy to process. 2133 */ 2134 if (ath9k_hw_mci_is_enabled(ah)) 2135 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2136 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2137 /* 2138 * Clear the RTC force wake bit to allow the 2139 * mac to go to sleep. 2140 */ 2141 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2142 2143 if (ath9k_hw_mci_is_enabled(ah)) 2144 udelay(30); 2145 } 2146 2147 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2148 if (AR_SREV_9300_20_OR_LATER(ah)) 2149 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2150} 2151 2152static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2153{ 2154 u32 val; 2155 int i; 2156 2157 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2158 if (AR_SREV_9300_20_OR_LATER(ah)) { 2159 REG_WRITE(ah, AR_WA, ah->WARegVal); 2160 udelay(10); 2161 } 2162 2163 if ((REG_READ(ah, AR_RTC_STATUS) & 2164 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2165 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2166 return false; 2167 } 2168 if (!AR_SREV_9300_20_OR_LATER(ah)) 2169 ath9k_hw_init_pll(ah, NULL); 2170 } 2171 if (AR_SREV_9100(ah)) 2172 REG_SET_BIT(ah, AR_RTC_RESET, 2173 AR_RTC_RESET_EN); 2174 2175 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2176 AR_RTC_FORCE_WAKE_EN); 2177 udelay(50); 2178 2179 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2180 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2181 if (val == AR_RTC_STATUS_ON) 2182 break; 2183 udelay(50); 2184 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2185 AR_RTC_FORCE_WAKE_EN); 2186 } 2187 if (i == 0) { 2188 ath_err(ath9k_hw_common(ah), 2189 "Failed to wakeup in %uus\n", 2190 POWER_UP_TIME / 20); 2191 return false; 2192 } 2193 2194 if (ath9k_hw_mci_is_enabled(ah)) 2195 ar9003_mci_set_power_awake(ah); 2196 2197 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2198 2199 return true; 2200} 2201 2202bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2203{ 2204 struct ath_common *common = ath9k_hw_common(ah); 2205 int status = true; 2206 static const char *modes[] = { 2207 "AWAKE", 2208 "FULL-SLEEP", 2209 "NETWORK SLEEP", 2210 "UNDEFINED" 2211 }; 2212 2213 if (ah->power_mode == mode) 2214 return status; 2215 2216 ath_dbg(common, RESET, "%s -> %s\n", 2217 modes[ah->power_mode], modes[mode]); 2218 2219 switch (mode) { 2220 case ATH9K_PM_AWAKE: 2221 status = ath9k_hw_set_power_awake(ah); 2222 break; 2223 case ATH9K_PM_FULL_SLEEP: 2224 if (ath9k_hw_mci_is_enabled(ah)) 2225 ar9003_mci_set_full_sleep(ah); 2226 2227 ath9k_set_power_sleep(ah); 2228 ah->chip_fullsleep = true; 2229 break; 2230 case ATH9K_PM_NETWORK_SLEEP: 2231 ath9k_set_power_network_sleep(ah); 2232 break; 2233 default: 2234 ath_err(common, "Unknown power mode %u\n", mode); 2235 return false; 2236 } 2237 ah->power_mode = mode; 2238 2239 /* 2240 * XXX: If this warning never comes up after a while then 2241 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2242 * ath9k_hw_setpower() return type void. 2243 */ 2244 2245 if (!(ah->ah_flags & AH_UNPLUGGED)) 2246 ATH_DBG_WARN_ON_ONCE(!status); 2247 2248 return status; 2249} 2250EXPORT_SYMBOL(ath9k_hw_setpower); 2251 2252/*******************/ 2253/* Beacon Handling */ 2254/*******************/ 2255 2256void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2257{ 2258 int flags = 0; 2259 2260 ENABLE_REGWRITE_BUFFER(ah); 2261 2262 switch (ah->opmode) { 2263 case NL80211_IFTYPE_ADHOC: 2264 REG_SET_BIT(ah, AR_TXCFG, 2265 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2266 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2267 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2268 flags |= AR_NDP_TIMER_EN; 2269 case NL80211_IFTYPE_MESH_POINT: 2270 case NL80211_IFTYPE_AP: 2271 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2272 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2273 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2274 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2275 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2276 flags |= 2277 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2278 break; 2279 default: 2280 ath_dbg(ath9k_hw_common(ah), BEACON, 2281 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2282 return; 2283 break; 2284 } 2285 2286 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2287 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2288 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2289 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2290 2291 REGWRITE_BUFFER_FLUSH(ah); 2292 2293 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2294} 2295EXPORT_SYMBOL(ath9k_hw_beaconinit); 2296 2297void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2298 const struct ath9k_beacon_state *bs) 2299{ 2300 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2301 struct ath9k_hw_capabilities *pCap = &ah->caps; 2302 struct ath_common *common = ath9k_hw_common(ah); 2303 2304 ENABLE_REGWRITE_BUFFER(ah); 2305 2306 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2307 2308 REG_WRITE(ah, AR_BEACON_PERIOD, 2309 TU_TO_USEC(bs->bs_intval)); 2310 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2311 TU_TO_USEC(bs->bs_intval)); 2312 2313 REGWRITE_BUFFER_FLUSH(ah); 2314 2315 REG_RMW_FIELD(ah, AR_RSSI_THR, 2316 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2317 2318 beaconintval = bs->bs_intval; 2319 2320 if (bs->bs_sleepduration > beaconintval) 2321 beaconintval = bs->bs_sleepduration; 2322 2323 dtimperiod = bs->bs_dtimperiod; 2324 if (bs->bs_sleepduration > dtimperiod) 2325 dtimperiod = bs->bs_sleepduration; 2326 2327 if (beaconintval == dtimperiod) 2328 nextTbtt = bs->bs_nextdtim; 2329 else 2330 nextTbtt = bs->bs_nexttbtt; 2331 2332 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2333 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2334 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2335 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2336 2337 ENABLE_REGWRITE_BUFFER(ah); 2338 2339 REG_WRITE(ah, AR_NEXT_DTIM, 2340 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2341 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2342 2343 REG_WRITE(ah, AR_SLEEP1, 2344 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2345 | AR_SLEEP1_ASSUME_DTIM); 2346 2347 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2348 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2349 else 2350 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2351 2352 REG_WRITE(ah, AR_SLEEP2, 2353 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2354 2355 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2356 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2357 2358 REGWRITE_BUFFER_FLUSH(ah); 2359 2360 REG_SET_BIT(ah, AR_TIMER_MODE, 2361 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2362 AR_DTIM_TIMER_EN); 2363 2364 /* TSF Out of Range Threshold */ 2365 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2366} 2367EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2368 2369/*******************/ 2370/* HW Capabilities */ 2371/*******************/ 2372 2373static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2374{ 2375 eeprom_chainmask &= chip_chainmask; 2376 if (eeprom_chainmask) 2377 return eeprom_chainmask; 2378 else 2379 return chip_chainmask; 2380} 2381 2382/** 2383 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2384 * @ah: the atheros hardware data structure 2385 * 2386 * We enable DFS support upstream on chipsets which have passed a series 2387 * of tests. The testing requirements are going to be documented. Desired 2388 * test requirements are documented at: 2389 * 2390 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2391 * 2392 * Once a new chipset gets properly tested an individual commit can be used 2393 * to document the testing for DFS for that chipset. 2394 */ 2395static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2396{ 2397 2398 switch (ah->hw_version.macVersion) { 2399 /* for temporary testing DFS with 9280 */ 2400 case AR_SREV_VERSION_9280: 2401 /* AR9580 will likely be our first target to get testing on */ 2402 case AR_SREV_VERSION_9580: 2403 return true; 2404 default: 2405 return false; 2406 } 2407} 2408 2409int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2410{ 2411 struct ath9k_hw_capabilities *pCap = &ah->caps; 2412 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2413 struct ath_common *common = ath9k_hw_common(ah); 2414 unsigned int chip_chainmask; 2415 2416 u16 eeval; 2417 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2418 2419 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2420 regulatory->current_rd = eeval; 2421 2422 if (ah->opmode != NL80211_IFTYPE_AP && 2423 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2424 if (regulatory->current_rd == 0x64 || 2425 regulatory->current_rd == 0x65) 2426 regulatory->current_rd += 5; 2427 else if (regulatory->current_rd == 0x41) 2428 regulatory->current_rd = 0x43; 2429 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2430 regulatory->current_rd); 2431 } 2432 2433 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2434 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2435 ath_err(common, 2436 "no band has been marked as supported in EEPROM\n"); 2437 return -EINVAL; 2438 } 2439 2440 if (eeval & AR5416_OPFLAGS_11A) 2441 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2442 2443 if (eeval & AR5416_OPFLAGS_11G) 2444 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2445 2446 if (AR_SREV_9485(ah) || 2447 AR_SREV_9285(ah) || 2448 AR_SREV_9330(ah) || 2449 AR_SREV_9565(ah)) 2450 chip_chainmask = 1; 2451 else if (AR_SREV_9462(ah)) 2452 chip_chainmask = 3; 2453 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2454 chip_chainmask = 7; 2455 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2456 chip_chainmask = 3; 2457 else 2458 chip_chainmask = 7; 2459 2460 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2461 /* 2462 * For AR9271 we will temporarilly uses the rx chainmax as read from 2463 * the EEPROM. 2464 */ 2465 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2466 !(eeval & AR5416_OPFLAGS_11A) && 2467 !(AR_SREV_9271(ah))) 2468 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2469 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2470 else if (AR_SREV_9100(ah)) 2471 pCap->rx_chainmask = 0x7; 2472 else 2473 /* Use rx_chainmask from EEPROM. */ 2474 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2475 2476 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2477 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2478 ah->txchainmask = pCap->tx_chainmask; 2479 ah->rxchainmask = pCap->rx_chainmask; 2480 2481 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2482 2483 /* enable key search for every frame in an aggregate */ 2484 if (AR_SREV_9300_20_OR_LATER(ah)) 2485 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2486 2487 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2488 2489 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2490 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2491 else 2492 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2493 2494 if (AR_SREV_9271(ah)) 2495 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2496 else if (AR_DEVID_7010(ah)) 2497 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2498 else if (AR_SREV_9300_20_OR_LATER(ah)) 2499 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2500 else if (AR_SREV_9287_11_OR_LATER(ah)) 2501 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2502 else if (AR_SREV_9285_12_OR_LATER(ah)) 2503 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2504 else if (AR_SREV_9280_20_OR_LATER(ah)) 2505 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2506 else 2507 pCap->num_gpio_pins = AR_NUM_GPIO; 2508 2509 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2510 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2511 else 2512 pCap->rts_aggr_limit = (8 * 1024); 2513 2514#ifdef CONFIG_ATH9K_RFKILL 2515 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2516 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2517 ah->rfkill_gpio = 2518 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2519 ah->rfkill_polarity = 2520 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2521 2522 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2523 } 2524#endif 2525 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2526 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2527 else 2528 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2529 2530 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2531 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2532 else 2533 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2534 2535 if (AR_SREV_9300_20_OR_LATER(ah)) { 2536 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2537 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2538 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2539 2540 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2541 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2542 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2543 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2544 pCap->txs_len = sizeof(struct ar9003_txs); 2545 } else { 2546 pCap->tx_desc_len = sizeof(struct ath_desc); 2547 if (AR_SREV_9280_20(ah)) 2548 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2549 } 2550 2551 if (AR_SREV_9300_20_OR_LATER(ah)) 2552 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2553 2554 if (AR_SREV_9300_20_OR_LATER(ah)) 2555 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2556 2557 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2558 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2559 2560 if (AR_SREV_9285(ah)) { 2561 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2562 ant_div_ctl1 = 2563 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2564 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2565 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2566 ath_info(common, "Enable LNA combining\n"); 2567 } 2568 } 2569 } 2570 2571 if (AR_SREV_9300_20_OR_LATER(ah)) { 2572 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2573 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2574 } 2575 2576 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2577 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2578 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2579 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2580 ath_info(common, "Enable LNA combining\n"); 2581 } 2582 } 2583 2584 if (ath9k_hw_dfs_tested(ah)) 2585 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2586 2587 tx_chainmask = pCap->tx_chainmask; 2588 rx_chainmask = pCap->rx_chainmask; 2589 while (tx_chainmask || rx_chainmask) { 2590 if (tx_chainmask & BIT(0)) 2591 pCap->max_txchains++; 2592 if (rx_chainmask & BIT(0)) 2593 pCap->max_rxchains++; 2594 2595 tx_chainmask >>= 1; 2596 rx_chainmask >>= 1; 2597 } 2598 2599 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2600 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2601 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2602 2603 if (AR_SREV_9462_20_OR_LATER(ah)) 2604 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2605 } 2606 2607 if (AR_SREV_9462(ah)) 2608 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE; 2609 2610 if (AR_SREV_9300_20_OR_LATER(ah) && 2611 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2612 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2613 2614 /* 2615 * Fast channel change across bands is available 2616 * only for AR9462 and AR9565. 2617 */ 2618 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2619 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH; 2620 2621 return 0; 2622} 2623 2624/****************************/ 2625/* GPIO / RFKILL / Antennae */ 2626/****************************/ 2627 2628static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2629 u32 gpio, u32 type) 2630{ 2631 int addr; 2632 u32 gpio_shift, tmp; 2633 2634 if (gpio > 11) 2635 addr = AR_GPIO_OUTPUT_MUX3; 2636 else if (gpio > 5) 2637 addr = AR_GPIO_OUTPUT_MUX2; 2638 else 2639 addr = AR_GPIO_OUTPUT_MUX1; 2640 2641 gpio_shift = (gpio % 6) * 5; 2642 2643 if (AR_SREV_9280_20_OR_LATER(ah) 2644 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2645 REG_RMW(ah, addr, (type << gpio_shift), 2646 (0x1f << gpio_shift)); 2647 } else { 2648 tmp = REG_READ(ah, addr); 2649 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2650 tmp &= ~(0x1f << gpio_shift); 2651 tmp |= (type << gpio_shift); 2652 REG_WRITE(ah, addr, tmp); 2653 } 2654} 2655 2656void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2657{ 2658 u32 gpio_shift; 2659 2660 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2661 2662 if (AR_DEVID_7010(ah)) { 2663 gpio_shift = gpio; 2664 REG_RMW(ah, AR7010_GPIO_OE, 2665 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2666 (AR7010_GPIO_OE_MASK << gpio_shift)); 2667 return; 2668 } 2669 2670 gpio_shift = gpio << 1; 2671 REG_RMW(ah, 2672 AR_GPIO_OE_OUT, 2673 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2674 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2675} 2676EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2677 2678u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2679{ 2680#define MS_REG_READ(x, y) \ 2681 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2682 2683 if (gpio >= ah->caps.num_gpio_pins) 2684 return 0xffffffff; 2685 2686 if (AR_DEVID_7010(ah)) { 2687 u32 val; 2688 val = REG_READ(ah, AR7010_GPIO_IN); 2689 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2690 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2691 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2692 AR_GPIO_BIT(gpio)) != 0; 2693 else if (AR_SREV_9271(ah)) 2694 return MS_REG_READ(AR9271, gpio) != 0; 2695 else if (AR_SREV_9287_11_OR_LATER(ah)) 2696 return MS_REG_READ(AR9287, gpio) != 0; 2697 else if (AR_SREV_9285_12_OR_LATER(ah)) 2698 return MS_REG_READ(AR9285, gpio) != 0; 2699 else if (AR_SREV_9280_20_OR_LATER(ah)) 2700 return MS_REG_READ(AR928X, gpio) != 0; 2701 else 2702 return MS_REG_READ(AR, gpio) != 0; 2703} 2704EXPORT_SYMBOL(ath9k_hw_gpio_get); 2705 2706void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2707 u32 ah_signal_type) 2708{ 2709 u32 gpio_shift; 2710 2711 if (AR_DEVID_7010(ah)) { 2712 gpio_shift = gpio; 2713 REG_RMW(ah, AR7010_GPIO_OE, 2714 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2715 (AR7010_GPIO_OE_MASK << gpio_shift)); 2716 return; 2717 } 2718 2719 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2720 gpio_shift = 2 * gpio; 2721 REG_RMW(ah, 2722 AR_GPIO_OE_OUT, 2723 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2724 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2725} 2726EXPORT_SYMBOL(ath9k_hw_cfg_output); 2727 2728void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2729{ 2730 if (AR_DEVID_7010(ah)) { 2731 val = val ? 0 : 1; 2732 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2733 AR_GPIO_BIT(gpio)); 2734 return; 2735 } 2736 2737 if (AR_SREV_9271(ah)) 2738 val = ~val; 2739 2740 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2741 AR_GPIO_BIT(gpio)); 2742} 2743EXPORT_SYMBOL(ath9k_hw_set_gpio); 2744 2745void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2746{ 2747 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2748} 2749EXPORT_SYMBOL(ath9k_hw_setantenna); 2750 2751/*********************/ 2752/* General Operation */ 2753/*********************/ 2754 2755u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2756{ 2757 u32 bits = REG_READ(ah, AR_RX_FILTER); 2758 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2759 2760 if (phybits & AR_PHY_ERR_RADAR) 2761 bits |= ATH9K_RX_FILTER_PHYRADAR; 2762 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2763 bits |= ATH9K_RX_FILTER_PHYERR; 2764 2765 return bits; 2766} 2767EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2768 2769void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2770{ 2771 u32 phybits; 2772 2773 ENABLE_REGWRITE_BUFFER(ah); 2774 2775 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2776 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2777 2778 REG_WRITE(ah, AR_RX_FILTER, bits); 2779 2780 phybits = 0; 2781 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2782 phybits |= AR_PHY_ERR_RADAR; 2783 if (bits & ATH9K_RX_FILTER_PHYERR) 2784 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2785 REG_WRITE(ah, AR_PHY_ERR, phybits); 2786 2787 if (phybits) 2788 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2789 else 2790 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2791 2792 REGWRITE_BUFFER_FLUSH(ah); 2793} 2794EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2795 2796bool ath9k_hw_phy_disable(struct ath_hw *ah) 2797{ 2798 if (ath9k_hw_mci_is_enabled(ah)) 2799 ar9003_mci_bt_gain_ctrl(ah); 2800 2801 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2802 return false; 2803 2804 ath9k_hw_init_pll(ah, NULL); 2805 ah->htc_reset_init = true; 2806 return true; 2807} 2808EXPORT_SYMBOL(ath9k_hw_phy_disable); 2809 2810bool ath9k_hw_disable(struct ath_hw *ah) 2811{ 2812 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2813 return false; 2814 2815 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2816 return false; 2817 2818 ath9k_hw_init_pll(ah, NULL); 2819 return true; 2820} 2821EXPORT_SYMBOL(ath9k_hw_disable); 2822 2823static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2824{ 2825 enum eeprom_param gain_param; 2826 2827 if (IS_CHAN_2GHZ(chan)) 2828 gain_param = EEP_ANTENNA_GAIN_2G; 2829 else 2830 gain_param = EEP_ANTENNA_GAIN_5G; 2831 2832 return ah->eep_ops->get_eeprom(ah, gain_param); 2833} 2834 2835void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2836 bool test) 2837{ 2838 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2839 struct ieee80211_channel *channel; 2840 int chan_pwr, new_pwr, max_gain; 2841 int ant_gain, ant_reduction = 0; 2842 2843 if (!chan) 2844 return; 2845 2846 channel = chan->chan; 2847 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2848 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2849 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2850 2851 ant_gain = get_antenna_gain(ah, chan); 2852 if (ant_gain > max_gain) 2853 ant_reduction = ant_gain - max_gain; 2854 2855 ah->eep_ops->set_txpower(ah, chan, 2856 ath9k_regd_get_ctl(reg, chan), 2857 ant_reduction, new_pwr, test); 2858} 2859 2860void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2861{ 2862 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2863 struct ath9k_channel *chan = ah->curchan; 2864 struct ieee80211_channel *channel = chan->chan; 2865 2866 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2867 if (test) 2868 channel->max_power = MAX_RATE_POWER / 2; 2869 2870 ath9k_hw_apply_txpower(ah, chan, test); 2871 2872 if (test) 2873 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2874} 2875EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2876 2877void ath9k_hw_setopmode(struct ath_hw *ah) 2878{ 2879 ath9k_hw_set_operating_mode(ah, ah->opmode); 2880} 2881EXPORT_SYMBOL(ath9k_hw_setopmode); 2882 2883void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2884{ 2885 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2886 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2887} 2888EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2889 2890void ath9k_hw_write_associd(struct ath_hw *ah) 2891{ 2892 struct ath_common *common = ath9k_hw_common(ah); 2893 2894 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2895 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2896 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2897} 2898EXPORT_SYMBOL(ath9k_hw_write_associd); 2899 2900#define ATH9K_MAX_TSF_READ 10 2901 2902u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2903{ 2904 u32 tsf_lower, tsf_upper1, tsf_upper2; 2905 int i; 2906 2907 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2908 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2909 tsf_lower = REG_READ(ah, AR_TSF_L32); 2910 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2911 if (tsf_upper2 == tsf_upper1) 2912 break; 2913 tsf_upper1 = tsf_upper2; 2914 } 2915 2916 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2917 2918 return (((u64)tsf_upper1 << 32) | tsf_lower); 2919} 2920EXPORT_SYMBOL(ath9k_hw_gettsf64); 2921 2922void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2923{ 2924 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2925 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2926} 2927EXPORT_SYMBOL(ath9k_hw_settsf64); 2928 2929void ath9k_hw_reset_tsf(struct ath_hw *ah) 2930{ 2931 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2932 AH_TSF_WRITE_TIMEOUT)) 2933 ath_dbg(ath9k_hw_common(ah), RESET, 2934 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2935 2936 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2937} 2938EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2939 2940void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2941{ 2942 if (set) 2943 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2944 else 2945 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2946} 2947EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2948 2949void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2950{ 2951 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2952 u32 macmode; 2953 2954 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2955 macmode = AR_2040_JOINED_RX_CLEAR; 2956 else 2957 macmode = 0; 2958 2959 REG_WRITE(ah, AR_2040_MODE, macmode); 2960} 2961 2962/* HW Generic timers configuration */ 2963 2964static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2965{ 2966 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2967 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2968 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2969 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2970 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2971 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2972 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2973 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2974 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2975 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2976 AR_NDP2_TIMER_MODE, 0x0002}, 2977 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2978 AR_NDP2_TIMER_MODE, 0x0004}, 2979 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2980 AR_NDP2_TIMER_MODE, 0x0008}, 2981 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2982 AR_NDP2_TIMER_MODE, 0x0010}, 2983 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2984 AR_NDP2_TIMER_MODE, 0x0020}, 2985 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2986 AR_NDP2_TIMER_MODE, 0x0040}, 2987 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2988 AR_NDP2_TIMER_MODE, 0x0080} 2989}; 2990 2991/* HW generic timer primitives */ 2992 2993/* compute and clear index of rightmost 1 */ 2994static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2995{ 2996 u32 b; 2997 2998 b = *mask; 2999 b &= (0-b); 3000 *mask &= ~b; 3001 b *= debruijn32; 3002 b >>= 27; 3003 3004 return timer_table->gen_timer_index[b]; 3005} 3006 3007u32 ath9k_hw_gettsf32(struct ath_hw *ah) 3008{ 3009 return REG_READ(ah, AR_TSF_L32); 3010} 3011EXPORT_SYMBOL(ath9k_hw_gettsf32); 3012 3013struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3014 void (*trigger)(void *), 3015 void (*overflow)(void *), 3016 void *arg, 3017 u8 timer_index) 3018{ 3019 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3020 struct ath_gen_timer *timer; 3021 3022 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3023 if (timer == NULL) 3024 return NULL; 3025 3026 /* allocate a hardware generic timer slot */ 3027 timer_table->timers[timer_index] = timer; 3028 timer->index = timer_index; 3029 timer->trigger = trigger; 3030 timer->overflow = overflow; 3031 timer->arg = arg; 3032 3033 return timer; 3034} 3035EXPORT_SYMBOL(ath_gen_timer_alloc); 3036 3037void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3038 struct ath_gen_timer *timer, 3039 u32 trig_timeout, 3040 u32 timer_period) 3041{ 3042 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3043 u32 tsf, timer_next; 3044 3045 BUG_ON(!timer_period); 3046 3047 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 3048 3049 tsf = ath9k_hw_gettsf32(ah); 3050 3051 timer_next = tsf + trig_timeout; 3052 3053 ath_dbg(ath9k_hw_common(ah), BTCOEX, 3054 "current tsf %x period %x timer_next %x\n", 3055 tsf, timer_period, timer_next); 3056 3057 /* 3058 * Program generic timer registers 3059 */ 3060 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3061 timer_next); 3062 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3063 timer_period); 3064 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3065 gen_tmr_configuration[timer->index].mode_mask); 3066 3067 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3068 /* 3069 * Starting from AR9462, each generic timer can select which tsf 3070 * to use. But we still follow the old rule, 0 - 7 use tsf and 3071 * 8 - 15 use tsf2. 3072 */ 3073 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3074 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3075 (1 << timer->index)); 3076 else 3077 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3078 (1 << timer->index)); 3079 } 3080 3081 /* Enable both trigger and thresh interrupt masks */ 3082 REG_SET_BIT(ah, AR_IMR_S5, 3083 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3084 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3085} 3086EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3087 3088void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3089{ 3090 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3091 3092 if ((timer->index < AR_FIRST_NDP_TIMER) || 3093 (timer->index >= ATH_MAX_GEN_TIMER)) { 3094 return; 3095 } 3096 3097 /* Clear generic timer enable bits. */ 3098 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3099 gen_tmr_configuration[timer->index].mode_mask); 3100 3101 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3102 /* 3103 * Need to switch back to TSF if it was using TSF2. 3104 */ 3105 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3106 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3107 (1 << timer->index)); 3108 } 3109 } 3110 3111 /* Disable both trigger and thresh interrupt masks */ 3112 REG_CLR_BIT(ah, AR_IMR_S5, 3113 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3114 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3115 3116 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3117} 3118EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3119 3120void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3121{ 3122 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3123 3124 /* free the hardware generic timer slot */ 3125 timer_table->timers[timer->index] = NULL; 3126 kfree(timer); 3127} 3128EXPORT_SYMBOL(ath_gen_timer_free); 3129 3130/* 3131 * Generic Timer Interrupts handling 3132 */ 3133void ath_gen_timer_isr(struct ath_hw *ah) 3134{ 3135 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3136 struct ath_gen_timer *timer; 3137 struct ath_common *common = ath9k_hw_common(ah); 3138 u32 trigger_mask, thresh_mask, index; 3139 3140 /* get hardware generic timer interrupt status */ 3141 trigger_mask = ah->intr_gen_timer_trigger; 3142 thresh_mask = ah->intr_gen_timer_thresh; 3143 trigger_mask &= timer_table->timer_mask.val; 3144 thresh_mask &= timer_table->timer_mask.val; 3145 3146 trigger_mask &= ~thresh_mask; 3147 3148 while (thresh_mask) { 3149 index = rightmost_index(timer_table, &thresh_mask); 3150 timer = timer_table->timers[index]; 3151 BUG_ON(!timer); 3152 ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n", 3153 index); 3154 timer->overflow(timer->arg); 3155 } 3156 3157 while (trigger_mask) { 3158 index = rightmost_index(timer_table, &trigger_mask); 3159 timer = timer_table->timers[index]; 3160 BUG_ON(!timer); 3161 ath_dbg(common, BTCOEX, 3162 "Gen timer[%d] trigger\n", index); 3163 timer->trigger(timer->arg); 3164 } 3165} 3166EXPORT_SYMBOL(ath_gen_timer_isr); 3167 3168/********/ 3169/* HTC */ 3170/********/ 3171 3172static struct { 3173 u32 version; 3174 const char * name; 3175} ath_mac_bb_names[] = { 3176 /* Devices with external radios */ 3177 { AR_SREV_VERSION_5416_PCI, "5416" }, 3178 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3179 { AR_SREV_VERSION_9100, "9100" }, 3180 { AR_SREV_VERSION_9160, "9160" }, 3181 /* Single-chip solutions */ 3182 { AR_SREV_VERSION_9280, "9280" }, 3183 { AR_SREV_VERSION_9285, "9285" }, 3184 { AR_SREV_VERSION_9287, "9287" }, 3185 { AR_SREV_VERSION_9271, "9271" }, 3186 { AR_SREV_VERSION_9300, "9300" }, 3187 { AR_SREV_VERSION_9330, "9330" }, 3188 { AR_SREV_VERSION_9340, "9340" }, 3189 { AR_SREV_VERSION_9485, "9485" }, 3190 { AR_SREV_VERSION_9462, "9462" }, 3191 { AR_SREV_VERSION_9550, "9550" }, 3192 { AR_SREV_VERSION_9565, "9565" }, 3193}; 3194 3195/* For devices with external radios */ 3196static struct { 3197 u16 version; 3198 const char * name; 3199} ath_rf_names[] = { 3200 { 0, "5133" }, 3201 { AR_RAD5133_SREV_MAJOR, "5133" }, 3202 { AR_RAD5122_SREV_MAJOR, "5122" }, 3203 { AR_RAD2133_SREV_MAJOR, "2133" }, 3204 { AR_RAD2122_SREV_MAJOR, "2122" } 3205}; 3206 3207/* 3208 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3209 */ 3210static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3211{ 3212 int i; 3213 3214 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3215 if (ath_mac_bb_names[i].version == mac_bb_version) { 3216 return ath_mac_bb_names[i].name; 3217 } 3218 } 3219 3220 return "????"; 3221} 3222 3223/* 3224 * Return the RF name. "????" is returned if the RF is unknown. 3225 * Used for devices with external radios. 3226 */ 3227static const char *ath9k_hw_rf_name(u16 rf_version) 3228{ 3229 int i; 3230 3231 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3232 if (ath_rf_names[i].version == rf_version) { 3233 return ath_rf_names[i].name; 3234 } 3235 } 3236 3237 return "????"; 3238} 3239 3240void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3241{ 3242 int used; 3243 3244 /* chipsets >= AR9280 are single-chip */ 3245 if (AR_SREV_9280_20_OR_LATER(ah)) { 3246 used = snprintf(hw_name, len, 3247 "Atheros AR%s Rev:%x", 3248 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3249 ah->hw_version.macRev); 3250 } 3251 else { 3252 used = snprintf(hw_name, len, 3253 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3254 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3255 ah->hw_version.macRev, 3256 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3257 AR_RADIO_SREV_MAJOR)), 3258 ah->hw_version.phyRev); 3259 } 3260 3261 hw_name[used] = '\0'; 3262} 3263EXPORT_SYMBOL(ath9k_hw_name); 3264