hw.c revision ffa49f8209ef77ebf2cce0bbc129ca40064b8fb6
1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <asm/unaligned.h> 19 20#include "hw.h" 21#include "rc.h" 22#include "initvals.h" 23 24#define ATH9K_CLOCK_RATE_CCK 22 25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 27 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan); 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 31 struct ar5416_eeprom_def *pEepData, 32 u32 reg, u32 value); 33 34MODULE_AUTHOR("Atheros Communications"); 35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 36MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 37MODULE_LICENSE("Dual BSD/GPL"); 38 39static int __init ath9k_init(void) 40{ 41 return 0; 42} 43module_init(ath9k_init); 44 45static void __exit ath9k_exit(void) 46{ 47 return; 48} 49module_exit(ath9k_exit); 50 51/********************/ 52/* Helper Functions */ 53/********************/ 54 55static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) 56{ 57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 58 59 if (!ah->curchan) /* should really check for CCK instead */ 60 return usecs *ATH9K_CLOCK_RATE_CCK; 61 if (conf->channel->band == IEEE80211_BAND_2GHZ) 62 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 63 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; 64} 65 66static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 67{ 68 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 69 70 if (conf_is_ht40(conf)) 71 return ath9k_hw_mac_clks(ah, usecs) * 2; 72 else 73 return ath9k_hw_mac_clks(ah, usecs); 74} 75 76bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 77{ 78 int i; 79 80 BUG_ON(timeout < AH_TIME_QUANTUM); 81 82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 83 if ((REG_READ(ah, reg) & mask) == val) 84 return true; 85 86 udelay(AH_TIME_QUANTUM); 87 } 88 89 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, 90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 91 timeout, reg, REG_READ(ah, reg), mask, val); 92 93 return false; 94} 95EXPORT_SYMBOL(ath9k_hw_wait); 96 97u32 ath9k_hw_reverse_bits(u32 val, u32 n) 98{ 99 u32 retval; 100 int i; 101 102 for (i = 0, retval = 0; i < n; i++) { 103 retval = (retval << 1) | (val & 1); 104 val >>= 1; 105 } 106 return retval; 107} 108 109bool ath9k_get_channel_edges(struct ath_hw *ah, 110 u16 flags, u16 *low, 111 u16 *high) 112{ 113 struct ath9k_hw_capabilities *pCap = &ah->caps; 114 115 if (flags & CHANNEL_5GHZ) { 116 *low = pCap->low_5ghz_chan; 117 *high = pCap->high_5ghz_chan; 118 return true; 119 } 120 if ((flags & CHANNEL_2GHZ)) { 121 *low = pCap->low_2ghz_chan; 122 *high = pCap->high_2ghz_chan; 123 return true; 124 } 125 return false; 126} 127 128u16 ath9k_hw_computetxtime(struct ath_hw *ah, 129 u8 phy, int kbps, 130 u32 frameLen, u16 rateix, 131 bool shortPreamble) 132{ 133 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 134 135 if (kbps == 0) 136 return 0; 137 138 switch (phy) { 139 case WLAN_RC_PHY_CCK: 140 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 141 if (shortPreamble) 142 phyTime >>= 1; 143 numBits = frameLen << 3; 144 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 145 break; 146 case WLAN_RC_PHY_OFDM: 147 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 148 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 149 numBits = OFDM_PLCP_BITS + (frameLen << 3); 150 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 151 txTime = OFDM_SIFS_TIME_QUARTER 152 + OFDM_PREAMBLE_TIME_QUARTER 153 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 154 } else if (ah->curchan && 155 IS_CHAN_HALF_RATE(ah->curchan)) { 156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 157 numBits = OFDM_PLCP_BITS + (frameLen << 3); 158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 159 txTime = OFDM_SIFS_TIME_HALF + 160 OFDM_PREAMBLE_TIME_HALF 161 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 162 } else { 163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 164 numBits = OFDM_PLCP_BITS + (frameLen << 3); 165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 166 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 167 + (numSymbols * OFDM_SYMBOL_TIME); 168 } 169 break; 170 default: 171 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 172 "Unknown phy %u (rate ix %u)\n", phy, rateix); 173 txTime = 0; 174 break; 175 } 176 177 return txTime; 178} 179EXPORT_SYMBOL(ath9k_hw_computetxtime); 180 181void ath9k_hw_get_channel_centers(struct ath_hw *ah, 182 struct ath9k_channel *chan, 183 struct chan_centers *centers) 184{ 185 int8_t extoff; 186 187 if (!IS_CHAN_HT40(chan)) { 188 centers->ctl_center = centers->ext_center = 189 centers->synth_center = chan->channel; 190 return; 191 } 192 193 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 194 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 195 centers->synth_center = 196 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 197 extoff = 1; 198 } else { 199 centers->synth_center = 200 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 201 extoff = -1; 202 } 203 204 centers->ctl_center = 205 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 206 /* 25 MHz spacing is supported by hw but not on upper layers */ 207 centers->ext_center = 208 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 209} 210 211/******************/ 212/* Chip Revisions */ 213/******************/ 214 215static void ath9k_hw_read_revisions(struct ath_hw *ah) 216{ 217 u32 val; 218 219 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 220 221 if (val == 0xFF) { 222 val = REG_READ(ah, AR_SREV); 223 ah->hw_version.macVersion = 224 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 225 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 226 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 227 } else { 228 if (!AR_SREV_9100(ah)) 229 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 230 231 ah->hw_version.macRev = val & AR_SREV_REVISION; 232 233 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 234 ah->is_pciexpress = true; 235 } 236} 237 238static int ath9k_hw_get_radiorev(struct ath_hw *ah) 239{ 240 u32 val; 241 int i; 242 243 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 244 245 for (i = 0; i < 8; i++) 246 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 247 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 248 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 249 250 return ath9k_hw_reverse_bits(val, 8); 251} 252 253/************************************/ 254/* HW Attach, Detach, Init Routines */ 255/************************************/ 256 257static void ath9k_hw_disablepcie(struct ath_hw *ah) 258{ 259 if (AR_SREV_9100(ah)) 260 return; 261 262 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 263 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 264 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 265 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 266 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 267 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 268 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 269 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 270 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 271 272 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 273} 274 275static bool ath9k_hw_chip_test(struct ath_hw *ah) 276{ 277 struct ath_common *common = ath9k_hw_common(ah); 278 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 279 u32 regHold[2]; 280 u32 patternData[4] = { 0x55555555, 281 0xaaaaaaaa, 282 0x66666666, 283 0x99999999 }; 284 int i, j; 285 286 for (i = 0; i < 2; i++) { 287 u32 addr = regAddr[i]; 288 u32 wrData, rdData; 289 290 regHold[i] = REG_READ(ah, addr); 291 for (j = 0; j < 0x100; j++) { 292 wrData = (j << 16) | j; 293 REG_WRITE(ah, addr, wrData); 294 rdData = REG_READ(ah, addr); 295 if (rdData != wrData) { 296 ath_print(common, ATH_DBG_FATAL, 297 "address test failed " 298 "addr: 0x%08x - wr:0x%08x != " 299 "rd:0x%08x\n", 300 addr, wrData, rdData); 301 return false; 302 } 303 } 304 for (j = 0; j < 4; j++) { 305 wrData = patternData[j]; 306 REG_WRITE(ah, addr, wrData); 307 rdData = REG_READ(ah, addr); 308 if (wrData != rdData) { 309 ath_print(common, ATH_DBG_FATAL, 310 "address test failed " 311 "addr: 0x%08x - wr:0x%08x != " 312 "rd:0x%08x\n", 313 addr, wrData, rdData); 314 return false; 315 } 316 } 317 REG_WRITE(ah, regAddr[i], regHold[i]); 318 } 319 udelay(100); 320 321 return true; 322} 323 324static void ath9k_hw_init_config(struct ath_hw *ah) 325{ 326 int i; 327 328 ah->config.dma_beacon_response_time = 2; 329 ah->config.sw_beacon_response_time = 10; 330 ah->config.additional_swba_backoff = 0; 331 ah->config.ack_6mb = 0x0; 332 ah->config.cwm_ignore_extcca = 0; 333 ah->config.pcie_powersave_enable = 0; 334 ah->config.pcie_clock_req = 0; 335 ah->config.pcie_waen = 0; 336 ah->config.analog_shiftreg = 1; 337 ah->config.ofdm_trig_low = 200; 338 ah->config.ofdm_trig_high = 500; 339 ah->config.cck_trig_high = 200; 340 ah->config.cck_trig_low = 100; 341 ah->config.enable_ani = 1; 342 343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 344 ah->config.spurchans[i][0] = AR_NO_SPUR; 345 ah->config.spurchans[i][1] = AR_NO_SPUR; 346 } 347 348 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 349 ah->config.ht_enable = 1; 350 else 351 ah->config.ht_enable = 0; 352 353 ah->config.rx_intr_mitigation = true; 354 355 /* 356 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 357 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 358 * This means we use it for all AR5416 devices, and the few 359 * minor PCI AR9280 devices out there. 360 * 361 * Serialization is required because these devices do not handle 362 * well the case of two concurrent reads/writes due to the latency 363 * involved. During one read/write another read/write can be issued 364 * on another CPU while the previous read/write may still be working 365 * on our hardware, if we hit this case the hardware poops in a loop. 366 * We prevent this by serializing reads and writes. 367 * 368 * This issue is not present on PCI-Express devices or pre-AR5416 369 * devices (legacy, 802.11abg). 370 */ 371 if (num_possible_cpus() > 1) 372 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 373} 374EXPORT_SYMBOL(ath9k_hw_init); 375 376static void ath9k_hw_init_defaults(struct ath_hw *ah) 377{ 378 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 379 380 regulatory->country_code = CTRY_DEFAULT; 381 regulatory->power_limit = MAX_RATE_POWER; 382 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 383 384 ah->hw_version.magic = AR5416_MAGIC; 385 ah->hw_version.subvendorid = 0; 386 387 ah->ah_flags = 0; 388 if (ah->hw_version.devid == AR5416_AR9100_DEVID) 389 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 390 if (!AR_SREV_9100(ah)) 391 ah->ah_flags = AH_USE_EEPROM; 392 393 ah->atim_window = 0; 394 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 395 ah->beacon_interval = 100; 396 ah->enable_32kHz_clock = DONT_USE_32KHZ; 397 ah->slottime = (u32) -1; 398 ah->globaltxtimeout = (u32) -1; 399 ah->power_mode = ATH9K_PM_UNDEFINED; 400} 401 402static int ath9k_hw_rf_claim(struct ath_hw *ah) 403{ 404 u32 val; 405 406 REG_WRITE(ah, AR_PHY(0), 0x00000007); 407 408 val = ath9k_hw_get_radiorev(ah); 409 switch (val & AR_RADIO_SREV_MAJOR) { 410 case 0: 411 val = AR_RAD5133_SREV_MAJOR; 412 break; 413 case AR_RAD5133_SREV_MAJOR: 414 case AR_RAD5122_SREV_MAJOR: 415 case AR_RAD2133_SREV_MAJOR: 416 case AR_RAD2122_SREV_MAJOR: 417 break; 418 default: 419 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 420 "Radio Chip Rev 0x%02X not supported\n", 421 val & AR_RADIO_SREV_MAJOR); 422 return -EOPNOTSUPP; 423 } 424 425 ah->hw_version.analog5GhzRev = val; 426 427 return 0; 428} 429 430static int ath9k_hw_init_macaddr(struct ath_hw *ah) 431{ 432 struct ath_common *common = ath9k_hw_common(ah); 433 u32 sum; 434 int i; 435 u16 eeval; 436 437 sum = 0; 438 for (i = 0; i < 3; i++) { 439 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); 440 sum += eeval; 441 common->macaddr[2 * i] = eeval >> 8; 442 common->macaddr[2 * i + 1] = eeval & 0xff; 443 } 444 if (sum == 0 || sum == 0xffff * 3) 445 return -EADDRNOTAVAIL; 446 447 return 0; 448} 449 450static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) 451{ 452 u32 rxgain_type; 453 454 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { 455 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); 456 457 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 458 INIT_INI_ARRAY(&ah->iniModesRxGain, 459 ar9280Modes_backoff_13db_rxgain_9280_2, 460 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); 461 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 462 INIT_INI_ARRAY(&ah->iniModesRxGain, 463 ar9280Modes_backoff_23db_rxgain_9280_2, 464 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); 465 else 466 INIT_INI_ARRAY(&ah->iniModesRxGain, 467 ar9280Modes_original_rxgain_9280_2, 468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 469 } else { 470 INIT_INI_ARRAY(&ah->iniModesRxGain, 471 ar9280Modes_original_rxgain_9280_2, 472 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 473 } 474} 475 476static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) 477{ 478 u32 txgain_type; 479 480 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { 481 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 482 483 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 484 INIT_INI_ARRAY(&ah->iniModesTxGain, 485 ar9280Modes_high_power_tx_gain_9280_2, 486 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); 487 else 488 INIT_INI_ARRAY(&ah->iniModesTxGain, 489 ar9280Modes_original_tx_gain_9280_2, 490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 491 } else { 492 INIT_INI_ARRAY(&ah->iniModesTxGain, 493 ar9280Modes_original_tx_gain_9280_2, 494 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 495 } 496} 497 498static int ath9k_hw_post_init(struct ath_hw *ah) 499{ 500 int ecode; 501 502 if (!AR_SREV_9271(ah)) { 503 if (!ath9k_hw_chip_test(ah)) 504 return -ENODEV; 505 } 506 507 ecode = ath9k_hw_rf_claim(ah); 508 if (ecode != 0) 509 return ecode; 510 511 ecode = ath9k_hw_eeprom_init(ah); 512 if (ecode != 0) 513 return ecode; 514 515 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, 516 "Eeprom VER: %d, REV: %d\n", 517 ah->eep_ops->get_eeprom_ver(ah), 518 ah->eep_ops->get_eeprom_rev(ah)); 519 520 if (!AR_SREV_9280_10_OR_LATER(ah)) { 521 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 522 if (ecode) { 523 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 524 "Failed allocating banks for " 525 "external radio\n"); 526 return ecode; 527 } 528 } 529 530 if (!AR_SREV_9100(ah)) { 531 ath9k_hw_ani_setup(ah); 532 ath9k_hw_ani_init(ah); 533 } 534 535 return 0; 536} 537 538static bool ath9k_hw_devid_supported(u16 devid) 539{ 540 switch (devid) { 541 case AR5416_DEVID_PCI: 542 case AR5416_DEVID_PCIE: 543 case AR5416_AR9100_DEVID: 544 case AR9160_DEVID_PCI: 545 case AR9280_DEVID_PCI: 546 case AR9280_DEVID_PCIE: 547 case AR9285_DEVID_PCIE: 548 case AR5416_DEVID_AR9287_PCI: 549 case AR5416_DEVID_AR9287_PCIE: 550 case AR2427_DEVID_PCIE: 551 return true; 552 default: 553 break; 554 } 555 return false; 556} 557 558static bool ath9k_hw_macversion_supported(u32 macversion) 559{ 560 switch (macversion) { 561 case AR_SREV_VERSION_5416_PCI: 562 case AR_SREV_VERSION_5416_PCIE: 563 case AR_SREV_VERSION_9160: 564 case AR_SREV_VERSION_9100: 565 case AR_SREV_VERSION_9280: 566 case AR_SREV_VERSION_9285: 567 case AR_SREV_VERSION_9287: 568 case AR_SREV_VERSION_9271: 569 return true; 570 default: 571 break; 572 } 573 return false; 574} 575 576static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 577{ 578 if (AR_SREV_9160_10_OR_LATER(ah)) { 579 if (AR_SREV_9280_10_OR_LATER(ah)) { 580 ah->iq_caldata.calData = &iq_cal_single_sample; 581 ah->adcgain_caldata.calData = 582 &adc_gain_cal_single_sample; 583 ah->adcdc_caldata.calData = 584 &adc_dc_cal_single_sample; 585 ah->adcdc_calinitdata.calData = 586 &adc_init_dc_cal; 587 } else { 588 ah->iq_caldata.calData = &iq_cal_multi_sample; 589 ah->adcgain_caldata.calData = 590 &adc_gain_cal_multi_sample; 591 ah->adcdc_caldata.calData = 592 &adc_dc_cal_multi_sample; 593 ah->adcdc_calinitdata.calData = 594 &adc_init_dc_cal; 595 } 596 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 597 } 598} 599 600static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 601{ 602 if (AR_SREV_9271(ah)) { 603 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, 604 ARRAY_SIZE(ar9271Modes_9271), 6); 605 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, 606 ARRAY_SIZE(ar9271Common_9271), 2); 607 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, 608 ar9271Common_normal_cck_fir_coeff_9271, 609 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2); 610 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271, 611 ar9271Common_japan_2484_cck_fir_coeff_9271, 612 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); 613 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, 614 ar9271Modes_9271_1_0_only, 615 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); 616 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, 617 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6); 618 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271, 619 ar9271Modes_high_power_tx_gain_9271, 620 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6); 621 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, 622 ar9271Modes_normal_power_tx_gain_9271, 623 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6); 624 return; 625 } 626 627 if (AR_SREV_9287_11_OR_LATER(ah)) { 628 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, 629 ARRAY_SIZE(ar9287Modes_9287_1_1), 6); 630 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, 631 ARRAY_SIZE(ar9287Common_9287_1_1), 2); 632 if (ah->config.pcie_clock_req) 633 INIT_INI_ARRAY(&ah->iniPcieSerdes, 634 ar9287PciePhy_clkreq_off_L1_9287_1_1, 635 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2); 636 else 637 INIT_INI_ARRAY(&ah->iniPcieSerdes, 638 ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 639 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), 640 2); 641 } else if (AR_SREV_9287_10_OR_LATER(ah)) { 642 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0, 643 ARRAY_SIZE(ar9287Modes_9287_1_0), 6); 644 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0, 645 ARRAY_SIZE(ar9287Common_9287_1_0), 2); 646 647 if (ah->config.pcie_clock_req) 648 INIT_INI_ARRAY(&ah->iniPcieSerdes, 649 ar9287PciePhy_clkreq_off_L1_9287_1_0, 650 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2); 651 else 652 INIT_INI_ARRAY(&ah->iniPcieSerdes, 653 ar9287PciePhy_clkreq_always_on_L1_9287_1_0, 654 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0), 655 2); 656 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 657 658 659 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, 660 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 661 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, 662 ARRAY_SIZE(ar9285Common_9285_1_2), 2); 663 664 if (ah->config.pcie_clock_req) { 665 INIT_INI_ARRAY(&ah->iniPcieSerdes, 666 ar9285PciePhy_clkreq_off_L1_9285_1_2, 667 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); 668 } else { 669 INIT_INI_ARRAY(&ah->iniPcieSerdes, 670 ar9285PciePhy_clkreq_always_on_L1_9285_1_2, 671 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 672 2); 673 } 674 } else if (AR_SREV_9285_10_OR_LATER(ah)) { 675 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, 676 ARRAY_SIZE(ar9285Modes_9285), 6); 677 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, 678 ARRAY_SIZE(ar9285Common_9285), 2); 679 680 if (ah->config.pcie_clock_req) { 681 INIT_INI_ARRAY(&ah->iniPcieSerdes, 682 ar9285PciePhy_clkreq_off_L1_9285, 683 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); 684 } else { 685 INIT_INI_ARRAY(&ah->iniPcieSerdes, 686 ar9285PciePhy_clkreq_always_on_L1_9285, 687 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); 688 } 689 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 690 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, 691 ARRAY_SIZE(ar9280Modes_9280_2), 6); 692 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, 693 ARRAY_SIZE(ar9280Common_9280_2), 2); 694 695 if (ah->config.pcie_clock_req) { 696 INIT_INI_ARRAY(&ah->iniPcieSerdes, 697 ar9280PciePhy_clkreq_off_L1_9280, 698 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); 699 } else { 700 INIT_INI_ARRAY(&ah->iniPcieSerdes, 701 ar9280PciePhy_clkreq_always_on_L1_9280, 702 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); 703 } 704 INIT_INI_ARRAY(&ah->iniModesAdditional, 705 ar9280Modes_fast_clock_9280_2, 706 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 707 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 708 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, 709 ARRAY_SIZE(ar9280Modes_9280), 6); 710 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, 711 ARRAY_SIZE(ar9280Common_9280), 2); 712 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 713 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, 714 ARRAY_SIZE(ar5416Modes_9160), 6); 715 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, 716 ARRAY_SIZE(ar5416Common_9160), 2); 717 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, 718 ARRAY_SIZE(ar5416Bank0_9160), 2); 719 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, 720 ARRAY_SIZE(ar5416BB_RfGain_9160), 3); 721 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, 722 ARRAY_SIZE(ar5416Bank1_9160), 2); 723 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, 724 ARRAY_SIZE(ar5416Bank2_9160), 2); 725 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, 726 ARRAY_SIZE(ar5416Bank3_9160), 3); 727 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, 728 ARRAY_SIZE(ar5416Bank6_9160), 3); 729 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, 730 ARRAY_SIZE(ar5416Bank6TPC_9160), 3); 731 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, 732 ARRAY_SIZE(ar5416Bank7_9160), 2); 733 if (AR_SREV_9160_11(ah)) { 734 INIT_INI_ARRAY(&ah->iniAddac, 735 ar5416Addac_91601_1, 736 ARRAY_SIZE(ar5416Addac_91601_1), 2); 737 } else { 738 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, 739 ARRAY_SIZE(ar5416Addac_9160), 2); 740 } 741 } else if (AR_SREV_9100_OR_LATER(ah)) { 742 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, 743 ARRAY_SIZE(ar5416Modes_9100), 6); 744 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, 745 ARRAY_SIZE(ar5416Common_9100), 2); 746 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, 747 ARRAY_SIZE(ar5416Bank0_9100), 2); 748 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, 749 ARRAY_SIZE(ar5416BB_RfGain_9100), 3); 750 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, 751 ARRAY_SIZE(ar5416Bank1_9100), 2); 752 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, 753 ARRAY_SIZE(ar5416Bank2_9100), 2); 754 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, 755 ARRAY_SIZE(ar5416Bank3_9100), 3); 756 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, 757 ARRAY_SIZE(ar5416Bank6_9100), 3); 758 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, 759 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 760 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, 761 ARRAY_SIZE(ar5416Bank7_9100), 2); 762 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, 763 ARRAY_SIZE(ar5416Addac_9100), 2); 764 } else { 765 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, 766 ARRAY_SIZE(ar5416Modes), 6); 767 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, 768 ARRAY_SIZE(ar5416Common), 2); 769 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, 770 ARRAY_SIZE(ar5416Bank0), 2); 771 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, 772 ARRAY_SIZE(ar5416BB_RfGain), 3); 773 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, 774 ARRAY_SIZE(ar5416Bank1), 2); 775 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, 776 ARRAY_SIZE(ar5416Bank2), 2); 777 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, 778 ARRAY_SIZE(ar5416Bank3), 3); 779 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, 780 ARRAY_SIZE(ar5416Bank6), 3); 781 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, 782 ARRAY_SIZE(ar5416Bank6TPC), 3); 783 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, 784 ARRAY_SIZE(ar5416Bank7), 2); 785 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, 786 ARRAY_SIZE(ar5416Addac), 2); 787 } 788} 789 790static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 791{ 792 if (AR_SREV_9287_11_OR_LATER(ah)) 793 INIT_INI_ARRAY(&ah->iniModesRxGain, 794 ar9287Modes_rx_gain_9287_1_1, 795 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); 796 else if (AR_SREV_9287_10(ah)) 797 INIT_INI_ARRAY(&ah->iniModesRxGain, 798 ar9287Modes_rx_gain_9287_1_0, 799 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6); 800 else if (AR_SREV_9280_20(ah)) 801 ath9k_hw_init_rxgain_ini(ah); 802 803 if (AR_SREV_9287_11_OR_LATER(ah)) { 804 INIT_INI_ARRAY(&ah->iniModesTxGain, 805 ar9287Modes_tx_gain_9287_1_1, 806 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); 807 } else if (AR_SREV_9287_10(ah)) { 808 INIT_INI_ARRAY(&ah->iniModesTxGain, 809 ar9287Modes_tx_gain_9287_1_0, 810 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6); 811 } else if (AR_SREV_9280_20(ah)) { 812 ath9k_hw_init_txgain_ini(ah); 813 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 814 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 815 816 /* txgain table */ 817 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { 818 INIT_INI_ARRAY(&ah->iniModesTxGain, 819 ar9285Modes_high_power_tx_gain_9285_1_2, 820 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6); 821 } else { 822 INIT_INI_ARRAY(&ah->iniModesTxGain, 823 ar9285Modes_original_tx_gain_9285_1_2, 824 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6); 825 } 826 827 } 828} 829 830static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah) 831{ 832 u32 i, j; 833 834 if (ah->hw_version.devid == AR9280_DEVID_PCI) { 835 836 /* EEPROM Fixup */ 837 for (i = 0; i < ah->iniModes.ia_rows; i++) { 838 u32 reg = INI_RA(&ah->iniModes, i, 0); 839 840 for (j = 1; j < ah->iniModes.ia_columns; j++) { 841 u32 val = INI_RA(&ah->iniModes, i, j); 842 843 INI_RA(&ah->iniModes, i, j) = 844 ath9k_hw_ini_fixup(ah, 845 &ah->eeprom.def, 846 reg, val); 847 } 848 } 849 } 850} 851 852int ath9k_hw_init(struct ath_hw *ah) 853{ 854 struct ath_common *common = ath9k_hw_common(ah); 855 int r = 0; 856 857 if (common->bus_ops->ath_bus_type != ATH_USB) { 858 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) { 859 ath_print(common, ATH_DBG_FATAL, 860 "Unsupported device ID: 0x%0x\n", 861 ah->hw_version.devid); 862 return -EOPNOTSUPP; 863 } 864 } 865 866 ath9k_hw_init_defaults(ah); 867 ath9k_hw_init_config(ah); 868 869 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 870 ath_print(common, ATH_DBG_FATAL, 871 "Couldn't reset chip\n"); 872 return -EIO; 873 } 874 875 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 876 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 877 return -EIO; 878 } 879 880 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 881 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 882 (AR_SREV_9280(ah) && !ah->is_pciexpress)) { 883 ah->config.serialize_regmode = 884 SER_REG_MODE_ON; 885 } else { 886 ah->config.serialize_regmode = 887 SER_REG_MODE_OFF; 888 } 889 } 890 891 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 892 ah->config.serialize_regmode); 893 894 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 895 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 896 else 897 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 898 899 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { 900 ath_print(common, ATH_DBG_FATAL, 901 "Mac Chip Rev 0x%02x.%x is not supported by " 902 "this driver\n", ah->hw_version.macVersion, 903 ah->hw_version.macRev); 904 return -EOPNOTSUPP; 905 } 906 907 if (AR_SREV_9100(ah)) { 908 ah->iq_caldata.calData = &iq_cal_multi_sample; 909 ah->supp_cals = IQ_MISMATCH_CAL; 910 ah->is_pciexpress = false; 911 } 912 913 if (AR_SREV_9271(ah)) 914 ah->is_pciexpress = false; 915 916 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 917 918 ath9k_hw_init_cal_settings(ah); 919 920 ah->ani_function = ATH9K_ANI_ALL; 921 if (AR_SREV_9280_10_OR_LATER(ah)) { 922 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 923 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel; 924 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate; 925 } else { 926 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel; 927 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate; 928 } 929 930 ath9k_hw_init_mode_regs(ah); 931 932 if (ah->is_pciexpress) 933 ath9k_hw_configpcipowersave(ah, 0, 0); 934 else 935 ath9k_hw_disablepcie(ah); 936 937 /* Support for Japan ch.14 (2484) spread */ 938 if (AR_SREV_9287_11_OR_LATER(ah)) { 939 INIT_INI_ARRAY(&ah->iniCckfirNormal, 940 ar9287Common_normal_cck_fir_coeff_92871_1, 941 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2); 942 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 943 ar9287Common_japan_2484_cck_fir_coeff_92871_1, 944 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2); 945 } 946 947 r = ath9k_hw_post_init(ah); 948 if (r) 949 return r; 950 951 ath9k_hw_init_mode_gain_regs(ah); 952 r = ath9k_hw_fill_cap_info(ah); 953 if (r) 954 return r; 955 956 ath9k_hw_init_eeprom_fix(ah); 957 958 r = ath9k_hw_init_macaddr(ah); 959 if (r) { 960 ath_print(common, ATH_DBG_FATAL, 961 "Failed to initialize MAC address\n"); 962 return r; 963 } 964 965 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 966 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 967 else 968 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 969 970 ath9k_init_nfcal_hist_buffer(ah); 971 972 common->state = ATH_HW_INITIALIZED; 973 974 return 0; 975} 976 977static void ath9k_hw_init_bb(struct ath_hw *ah, 978 struct ath9k_channel *chan) 979{ 980 u32 synthDelay; 981 982 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 983 if (IS_CHAN_B(chan)) 984 synthDelay = (4 * synthDelay) / 22; 985 else 986 synthDelay /= 10; 987 988 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 989 990 udelay(synthDelay + BASE_ACTIVATE_DELAY); 991} 992 993static void ath9k_hw_init_qos(struct ath_hw *ah) 994{ 995 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 996 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 997 998 REG_WRITE(ah, AR_QOS_NO_ACK, 999 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 1000 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 1001 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 1002 1003 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 1004 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 1005 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 1006 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 1007 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 1008} 1009 1010static void ath9k_hw_init_pll(struct ath_hw *ah, 1011 struct ath9k_channel *chan) 1012{ 1013 u32 pll; 1014 1015 if (AR_SREV_9100(ah)) { 1016 if (chan && IS_CHAN_5GHZ(chan)) 1017 pll = 0x1450; 1018 else 1019 pll = 0x1458; 1020 } else { 1021 if (AR_SREV_9280_10_OR_LATER(ah)) { 1022 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 1023 1024 if (chan && IS_CHAN_HALF_RATE(chan)) 1025 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 1026 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1027 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 1028 1029 if (chan && IS_CHAN_5GHZ(chan)) { 1030 pll |= SM(0x28, AR_RTC_9160_PLL_DIV); 1031 1032 1033 if (AR_SREV_9280_20(ah)) { 1034 if (((chan->channel % 20) == 0) 1035 || ((chan->channel % 10) == 0)) 1036 pll = 0x2850; 1037 else 1038 pll = 0x142c; 1039 } 1040 } else { 1041 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); 1042 } 1043 1044 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1045 1046 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 1047 1048 if (chan && IS_CHAN_HALF_RATE(chan)) 1049 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 1050 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1051 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 1052 1053 if (chan && IS_CHAN_5GHZ(chan)) 1054 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 1055 else 1056 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 1057 } else { 1058 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 1059 1060 if (chan && IS_CHAN_HALF_RATE(chan)) 1061 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1062 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1063 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1064 1065 if (chan && IS_CHAN_5GHZ(chan)) 1066 pll |= SM(0xa, AR_RTC_PLL_DIV); 1067 else 1068 pll |= SM(0xb, AR_RTC_PLL_DIV); 1069 } 1070 } 1071 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1072 1073 /* Switch the core clock for ar9271 to 117Mhz */ 1074 if (AR_SREV_9271(ah)) { 1075 udelay(500); 1076 REG_WRITE(ah, 0x50040, 0x304); 1077 } 1078 1079 udelay(RTC_PLL_SETTLE_DELAY); 1080 1081 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 1082} 1083 1084static void ath9k_hw_init_chain_masks(struct ath_hw *ah) 1085{ 1086 int rx_chainmask, tx_chainmask; 1087 1088 rx_chainmask = ah->rxchainmask; 1089 tx_chainmask = ah->txchainmask; 1090 1091 switch (rx_chainmask) { 1092 case 0x5: 1093 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 1094 AR_PHY_SWAP_ALT_CHAIN); 1095 case 0x3: 1096 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 1097 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 1098 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 1099 break; 1100 } 1101 case 0x1: 1102 case 0x2: 1103 case 0x7: 1104 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1105 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1106 break; 1107 default: 1108 break; 1109 } 1110 1111 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 1112 if (tx_chainmask == 0x5) { 1113 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 1114 AR_PHY_SWAP_ALT_CHAIN); 1115 } 1116 if (AR_SREV_9100(ah)) 1117 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 1118 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1119} 1120 1121static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 1122 enum nl80211_iftype opmode) 1123{ 1124 u32 imr_reg = AR_IMR_TXERR | 1125 AR_IMR_TXURN | 1126 AR_IMR_RXERR | 1127 AR_IMR_RXORN | 1128 AR_IMR_BCNMISC; 1129 1130 if (ah->config.rx_intr_mitigation) 1131 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 1132 else 1133 imr_reg |= AR_IMR_RXOK; 1134 1135 imr_reg |= AR_IMR_TXOK; 1136 1137 if (opmode == NL80211_IFTYPE_AP) 1138 imr_reg |= AR_IMR_MIB; 1139 1140 REG_WRITE(ah, AR_IMR, imr_reg); 1141 ah->imrs2_reg |= AR_IMR_S2_GTT; 1142 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 1143 1144 if (!AR_SREV_9100(ah)) { 1145 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 1146 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 1147 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 1148 } 1149} 1150 1151static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 1152{ 1153 u32 val = ath9k_hw_mac_to_clks(ah, us); 1154 val = min(val, (u32) 0xFFFF); 1155 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1156} 1157 1158static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1159{ 1160 u32 val = ath9k_hw_mac_to_clks(ah, us); 1161 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1162 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1163} 1164 1165static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1166{ 1167 u32 val = ath9k_hw_mac_to_clks(ah, us); 1168 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1169 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1170} 1171 1172static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1173{ 1174 if (tu > 0xFFFF) { 1175 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 1176 "bad global tx timeout %u\n", tu); 1177 ah->globaltxtimeout = (u32) -1; 1178 return false; 1179 } else { 1180 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1181 ah->globaltxtimeout = tu; 1182 return true; 1183 } 1184} 1185 1186void ath9k_hw_init_global_settings(struct ath_hw *ah) 1187{ 1188 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 1189 int acktimeout; 1190 int slottime; 1191 int sifstime; 1192 1193 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 1194 ah->misc_mode); 1195 1196 if (ah->misc_mode != 0) 1197 REG_WRITE(ah, AR_PCU_MISC, 1198 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 1199 1200 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 1201 sifstime = 16; 1202 else 1203 sifstime = 10; 1204 1205 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1206 slottime = ah->slottime + 3 * ah->coverage_class; 1207 acktimeout = slottime + sifstime; 1208 1209 /* 1210 * Workaround for early ACK timeouts, add an offset to match the 1211 * initval's 64us ack timeout value. 1212 * This was initially only meant to work around an issue with delayed 1213 * BA frames in some implementations, but it has been found to fix ACK 1214 * timeout issues in other cases as well. 1215 */ 1216 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 1217 acktimeout += 64 - sifstime - ah->slottime; 1218 1219 ath9k_hw_setslottime(ah, slottime); 1220 ath9k_hw_set_ack_timeout(ah, acktimeout); 1221 ath9k_hw_set_cts_timeout(ah, acktimeout); 1222 if (ah->globaltxtimeout != (u32) -1) 1223 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1224} 1225EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1226 1227void ath9k_hw_deinit(struct ath_hw *ah) 1228{ 1229 struct ath_common *common = ath9k_hw_common(ah); 1230 1231 if (common->state < ATH_HW_INITIALIZED) 1232 goto free_hw; 1233 1234 if (!AR_SREV_9100(ah)) 1235 ath9k_hw_ani_disable(ah); 1236 1237 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1238 1239free_hw: 1240 if (!AR_SREV_9280_10_OR_LATER(ah)) 1241 ath9k_hw_rf_free_ext_banks(ah); 1242} 1243EXPORT_SYMBOL(ath9k_hw_deinit); 1244 1245/*******/ 1246/* INI */ 1247/*******/ 1248 1249static void ath9k_hw_override_ini(struct ath_hw *ah, 1250 struct ath9k_channel *chan) 1251{ 1252 u32 val; 1253 1254 /* 1255 * Set the RX_ABORT and RX_DIS and clear if off only after 1256 * RXE is set for MAC. This prevents frames with corrupted 1257 * descriptor status. 1258 */ 1259 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 1260 1261 if (AR_SREV_9280_10_OR_LATER(ah)) { 1262 val = REG_READ(ah, AR_PCU_MISC_MODE2); 1263 1264 if (!AR_SREV_9271(ah)) 1265 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 1266 1267 if (AR_SREV_9287_10_OR_LATER(ah)) 1268 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 1269 1270 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 1271 } 1272 1273 if (!AR_SREV_5416_20_OR_LATER(ah) || 1274 AR_SREV_9280_10_OR_LATER(ah)) 1275 return; 1276 /* 1277 * Disable BB clock gating 1278 * Necessary to avoid issues on AR5416 2.0 1279 */ 1280 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 1281 1282 /* 1283 * Disable RIFS search on some chips to avoid baseband 1284 * hang issues. 1285 */ 1286 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 1287 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 1288 val &= ~AR_PHY_RIFS_INIT_DELAY; 1289 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 1290 } 1291} 1292 1293static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah, 1294 struct ar5416_eeprom_def *pEepData, 1295 u32 reg, u32 value) 1296{ 1297 struct base_eep_header *pBase = &(pEepData->baseEepHeader); 1298 struct ath_common *common = ath9k_hw_common(ah); 1299 1300 switch (ah->hw_version.devid) { 1301 case AR9280_DEVID_PCI: 1302 if (reg == 0x7894) { 1303 ath_print(common, ATH_DBG_EEPROM, 1304 "ini VAL: %x EEPROM: %x\n", value, 1305 (pBase->version & 0xff)); 1306 1307 if ((pBase->version & 0xff) > 0x0a) { 1308 ath_print(common, ATH_DBG_EEPROM, 1309 "PWDCLKIND: %d\n", 1310 pBase->pwdclkind); 1311 value &= ~AR_AN_TOP2_PWDCLKIND; 1312 value |= AR_AN_TOP2_PWDCLKIND & 1313 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); 1314 } else { 1315 ath_print(common, ATH_DBG_EEPROM, 1316 "PWDCLKIND Earlier Rev\n"); 1317 } 1318 1319 ath_print(common, ATH_DBG_EEPROM, 1320 "final ini VAL: %x\n", value); 1321 } 1322 break; 1323 } 1324 1325 return value; 1326} 1327 1328static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 1329 struct ar5416_eeprom_def *pEepData, 1330 u32 reg, u32 value) 1331{ 1332 if (ah->eep_map == EEP_MAP_4KBITS) 1333 return value; 1334 else 1335 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); 1336} 1337 1338static void ath9k_olc_init(struct ath_hw *ah) 1339{ 1340 u32 i; 1341 1342 if (OLC_FOR_AR9287_10_LATER) { 1343 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, 1344 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); 1345 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0, 1346 AR9287_AN_TXPC0_TXPCMODE, 1347 AR9287_AN_TXPC0_TXPCMODE_S, 1348 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); 1349 udelay(100); 1350 } else { 1351 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) 1352 ah->originalGain[i] = 1353 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), 1354 AR_PHY_TX_GAIN); 1355 ah->PDADCdelta = 0; 1356 } 1357} 1358 1359static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, 1360 struct ath9k_channel *chan) 1361{ 1362 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1363 1364 if (IS_CHAN_B(chan)) 1365 ctl |= CTL_11B; 1366 else if (IS_CHAN_G(chan)) 1367 ctl |= CTL_11G; 1368 else 1369 ctl |= CTL_11A; 1370 1371 return ctl; 1372} 1373 1374static int ath9k_hw_process_ini(struct ath_hw *ah, 1375 struct ath9k_channel *chan) 1376{ 1377 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1378 int i, regWrites = 0; 1379 struct ieee80211_channel *channel = chan->chan; 1380 u32 modesIndex, freqIndex; 1381 1382 switch (chan->chanmode) { 1383 case CHANNEL_A: 1384 case CHANNEL_A_HT20: 1385 modesIndex = 1; 1386 freqIndex = 1; 1387 break; 1388 case CHANNEL_A_HT40PLUS: 1389 case CHANNEL_A_HT40MINUS: 1390 modesIndex = 2; 1391 freqIndex = 1; 1392 break; 1393 case CHANNEL_G: 1394 case CHANNEL_G_HT20: 1395 case CHANNEL_B: 1396 modesIndex = 4; 1397 freqIndex = 2; 1398 break; 1399 case CHANNEL_G_HT40PLUS: 1400 case CHANNEL_G_HT40MINUS: 1401 modesIndex = 3; 1402 freqIndex = 2; 1403 break; 1404 1405 default: 1406 return -EINVAL; 1407 } 1408 1409 /* Set correct baseband to analog shift setting to access analog chips */ 1410 REG_WRITE(ah, AR_PHY(0), 0x00000007); 1411 1412 /* Write ADDAC shifts */ 1413 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 1414 ah->eep_ops->set_addac(ah, chan); 1415 1416 if (AR_SREV_5416_22_OR_LATER(ah)) { 1417 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 1418 } else { 1419 struct ar5416IniArray temp; 1420 u32 addacSize = 1421 sizeof(u32) * ah->iniAddac.ia_rows * 1422 ah->iniAddac.ia_columns; 1423 1424 /* For AR5416 2.0/2.1 */ 1425 memcpy(ah->addac5416_21, 1426 ah->iniAddac.ia_array, addacSize); 1427 1428 /* override CLKDRV value at [row, column] = [31, 1] */ 1429 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; 1430 1431 temp.ia_array = ah->addac5416_21; 1432 temp.ia_columns = ah->iniAddac.ia_columns; 1433 temp.ia_rows = ah->iniAddac.ia_rows; 1434 REG_WRITE_ARRAY(&temp, 1, regWrites); 1435 } 1436 1437 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 1438 1439 for (i = 0; i < ah->iniModes.ia_rows; i++) { 1440 u32 reg = INI_RA(&ah->iniModes, i, 0); 1441 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 1442 1443 REG_WRITE(ah, reg, val); 1444 1445 if (reg >= 0x7800 && reg < 0x78a0 1446 && ah->config.analog_shiftreg) { 1447 udelay(100); 1448 } 1449 1450 DO_DELAY(regWrites); 1451 } 1452 1453 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah)) 1454 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 1455 1456 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 1457 AR_SREV_9287_10_OR_LATER(ah)) 1458 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 1459 1460 if (AR_SREV_9271_10(ah)) 1461 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only, 1462 modesIndex, regWrites); 1463 1464 /* Write common array parameters */ 1465 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 1466 u32 reg = INI_RA(&ah->iniCommon, i, 0); 1467 u32 val = INI_RA(&ah->iniCommon, i, 1); 1468 1469 REG_WRITE(ah, reg, val); 1470 1471 if (reg >= 0x7800 && reg < 0x78a0 1472 && ah->config.analog_shiftreg) { 1473 udelay(100); 1474 } 1475 1476 DO_DELAY(regWrites); 1477 } 1478 1479 if (AR_SREV_9271(ah)) { 1480 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1) 1481 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271, 1482 modesIndex, regWrites); 1483 else 1484 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, 1485 modesIndex, regWrites); 1486 } 1487 1488 ath9k_hw_write_regs(ah, freqIndex, regWrites); 1489 1490 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1491 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, 1492 regWrites); 1493 } 1494 1495 ath9k_hw_override_ini(ah, chan); 1496 ath9k_hw_set_regs(ah, chan); 1497 ath9k_hw_init_chain_masks(ah); 1498 1499 if (OLC_FOR_AR9280_20_LATER) 1500 ath9k_olc_init(ah); 1501 1502 /* Set TX power */ 1503 ah->eep_ops->set_txpower(ah, chan, 1504 ath9k_regd_get_ctl(regulatory, chan), 1505 channel->max_antenna_gain * 2, 1506 channel->max_power * 2, 1507 min((u32) MAX_RATE_POWER, 1508 (u32) regulatory->power_limit)); 1509 1510 /* Write analog registers */ 1511 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1512 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1513 "ar5416SetRfRegs failed\n"); 1514 return -EIO; 1515 } 1516 1517 return 0; 1518} 1519 1520/****************************************/ 1521/* Reset and Channel Switching Routines */ 1522/****************************************/ 1523 1524static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 1525{ 1526 u32 rfMode = 0; 1527 1528 if (chan == NULL) 1529 return; 1530 1531 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 1532 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1533 1534 if (!AR_SREV_9280_10_OR_LATER(ah)) 1535 rfMode |= (IS_CHAN_5GHZ(chan)) ? 1536 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 1537 1538 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) 1539 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 1540 1541 REG_WRITE(ah, AR_PHY_MODE, rfMode); 1542} 1543 1544static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah) 1545{ 1546 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1547} 1548 1549static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1550{ 1551 u32 regval; 1552 1553 /* 1554 * set AHB_MODE not to do cacheline prefetches 1555 */ 1556 regval = REG_READ(ah, AR_AHB_MODE); 1557 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 1558 1559 /* 1560 * let mac dma reads be in 128 byte chunks 1561 */ 1562 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 1563 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 1564 1565 /* 1566 * Restore TX Trigger Level to its pre-reset value. 1567 * The initial value depends on whether aggregation is enabled, and is 1568 * adjusted whenever underruns are detected. 1569 */ 1570 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1571 1572 /* 1573 * let mac dma writes be in 128 byte chunks 1574 */ 1575 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 1576 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 1577 1578 /* 1579 * Setup receive FIFO threshold to hold off TX activities 1580 */ 1581 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1582 1583 /* 1584 * reduce the number of usable entries in PCU TXBUF to avoid 1585 * wrap around issues. 1586 */ 1587 if (AR_SREV_9285(ah)) { 1588 /* For AR9285 the number of Fifos are reduced to half. 1589 * So set the usable tx buf size also to half to 1590 * avoid data/delimiter underruns 1591 */ 1592 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1593 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1594 } else if (!AR_SREV_9271(ah)) { 1595 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1596 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1597 } 1598} 1599 1600static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1601{ 1602 u32 val; 1603 1604 val = REG_READ(ah, AR_STA_ID1); 1605 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 1606 switch (opmode) { 1607 case NL80211_IFTYPE_AP: 1608 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 1609 | AR_STA_ID1_KSRCH_MODE); 1610 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1611 break; 1612 case NL80211_IFTYPE_ADHOC: 1613 case NL80211_IFTYPE_MESH_POINT: 1614 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 1615 | AR_STA_ID1_KSRCH_MODE); 1616 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1617 break; 1618 case NL80211_IFTYPE_STATION: 1619 case NL80211_IFTYPE_MONITOR: 1620 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 1621 break; 1622 } 1623} 1624 1625static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, 1626 u32 coef_scaled, 1627 u32 *coef_mantissa, 1628 u32 *coef_exponent) 1629{ 1630 u32 coef_exp, coef_man; 1631 1632 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1633 if ((coef_scaled >> coef_exp) & 0x1) 1634 break; 1635 1636 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1637 1638 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1639 1640 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1641 *coef_exponent = coef_exp - 16; 1642} 1643 1644static void ath9k_hw_set_delta_slope(struct ath_hw *ah, 1645 struct ath9k_channel *chan) 1646{ 1647 u32 coef_scaled, ds_coef_exp, ds_coef_man; 1648 u32 clockMhzScaled = 0x64000000; 1649 struct chan_centers centers; 1650 1651 if (IS_CHAN_HALF_RATE(chan)) 1652 clockMhzScaled = clockMhzScaled >> 1; 1653 else if (IS_CHAN_QUARTER_RATE(chan)) 1654 clockMhzScaled = clockMhzScaled >> 2; 1655 1656 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 1657 coef_scaled = clockMhzScaled / centers.synth_center; 1658 1659 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1660 &ds_coef_exp); 1661 1662 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1663 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 1664 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1665 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 1666 1667 coef_scaled = (9 * coef_scaled) / 10; 1668 1669 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1670 &ds_coef_exp); 1671 1672 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 1673 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 1674 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 1675 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 1676} 1677 1678static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1679{ 1680 u32 rst_flags; 1681 u32 tmpReg; 1682 1683 if (AR_SREV_9100(ah)) { 1684 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 1685 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 1686 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 1687 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 1688 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1689 } 1690 1691 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1692 AR_RTC_FORCE_WAKE_ON_INT); 1693 1694 if (AR_SREV_9100(ah)) { 1695 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1696 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1697 } else { 1698 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1699 if (tmpReg & 1700 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1701 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1702 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1703 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1704 } else { 1705 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1706 } 1707 1708 rst_flags = AR_RTC_RC_MAC_WARM; 1709 if (type == ATH9K_RESET_COLD) 1710 rst_flags |= AR_RTC_RC_MAC_COLD; 1711 } 1712 1713 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1714 udelay(50); 1715 1716 REG_WRITE(ah, AR_RTC_RC, 0); 1717 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1718 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1719 "RTC stuck in MAC reset\n"); 1720 return false; 1721 } 1722 1723 if (!AR_SREV_9100(ah)) 1724 REG_WRITE(ah, AR_RC, 0); 1725 1726 if (AR_SREV_9100(ah)) 1727 udelay(50); 1728 1729 return true; 1730} 1731 1732static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1733{ 1734 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1735 AR_RTC_FORCE_WAKE_ON_INT); 1736 1737 if (!AR_SREV_9100(ah)) 1738 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1739 1740 REG_WRITE(ah, AR_RTC_RESET, 0); 1741 udelay(2); 1742 1743 if (!AR_SREV_9100(ah)) 1744 REG_WRITE(ah, AR_RC, 0); 1745 1746 REG_WRITE(ah, AR_RTC_RESET, 1); 1747 1748 if (!ath9k_hw_wait(ah, 1749 AR_RTC_STATUS, 1750 AR_RTC_STATUS_M, 1751 AR_RTC_STATUS_ON, 1752 AH_WAIT_TIMEOUT)) { 1753 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1754 "RTC not waking up\n"); 1755 return false; 1756 } 1757 1758 ath9k_hw_read_revisions(ah); 1759 1760 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1761} 1762 1763static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1764{ 1765 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1766 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1767 1768 switch (type) { 1769 case ATH9K_RESET_POWER_ON: 1770 return ath9k_hw_set_reset_power_on(ah); 1771 case ATH9K_RESET_WARM: 1772 case ATH9K_RESET_COLD: 1773 return ath9k_hw_set_reset(ah, type); 1774 default: 1775 return false; 1776 } 1777} 1778 1779static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan) 1780{ 1781 u32 phymode; 1782 u32 enableDacFifo = 0; 1783 1784 if (AR_SREV_9285_10_OR_LATER(ah)) 1785 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 1786 AR_PHY_FC_ENABLE_DAC_FIFO); 1787 1788 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 1789 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 1790 1791 if (IS_CHAN_HT40(chan)) { 1792 phymode |= AR_PHY_FC_DYN2040_EN; 1793 1794 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 1795 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1796 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1797 1798 } 1799 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1800 1801 ath9k_hw_set11nmac2040(ah); 1802 1803 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 1804 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 1805} 1806 1807static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1808 struct ath9k_channel *chan) 1809{ 1810 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1811 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1812 return false; 1813 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1814 return false; 1815 1816 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1817 return false; 1818 1819 ah->chip_fullsleep = false; 1820 ath9k_hw_init_pll(ah, chan); 1821 ath9k_hw_set_rfmode(ah, chan); 1822 1823 return true; 1824} 1825 1826static bool ath9k_hw_channel_change(struct ath_hw *ah, 1827 struct ath9k_channel *chan) 1828{ 1829 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1830 struct ath_common *common = ath9k_hw_common(ah); 1831 struct ieee80211_channel *channel = chan->chan; 1832 u32 synthDelay, qnum; 1833 int r; 1834 1835 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1836 if (ath9k_hw_numtxpending(ah, qnum)) { 1837 ath_print(common, ATH_DBG_QUEUE, 1838 "Transmit frames pending on " 1839 "queue %d\n", qnum); 1840 return false; 1841 } 1842 } 1843 1844 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1845 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1846 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { 1847 ath_print(common, ATH_DBG_FATAL, 1848 "Could not kill baseband RX\n"); 1849 return false; 1850 } 1851 1852 ath9k_hw_set_regs(ah, chan); 1853 1854 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1855 if (r) { 1856 ath_print(common, ATH_DBG_FATAL, 1857 "Failed to set channel\n"); 1858 return false; 1859 } 1860 1861 ah->eep_ops->set_txpower(ah, chan, 1862 ath9k_regd_get_ctl(regulatory, chan), 1863 channel->max_antenna_gain * 2, 1864 channel->max_power * 2, 1865 min((u32) MAX_RATE_POWER, 1866 (u32) regulatory->power_limit)); 1867 1868 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1869 if (IS_CHAN_B(chan)) 1870 synthDelay = (4 * synthDelay) / 22; 1871 else 1872 synthDelay /= 10; 1873 1874 udelay(synthDelay + BASE_ACTIVATE_DELAY); 1875 1876 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 1877 1878 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1879 ath9k_hw_set_delta_slope(ah, chan); 1880 1881 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1882 1883 if (!chan->oneTimeCalsDone) 1884 chan->oneTimeCalsDone = true; 1885 1886 return true; 1887} 1888 1889static void ath9k_enable_rfkill(struct ath_hw *ah) 1890{ 1891 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1892 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 1893 1894 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, 1895 AR_GPIO_INPUT_MUX2_RFSILENT); 1896 1897 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1898 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 1899} 1900 1901int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1902 bool bChannelChange) 1903{ 1904 struct ath_common *common = ath9k_hw_common(ah); 1905 u32 saveLedState; 1906 struct ath9k_channel *curchan = ah->curchan; 1907 u32 saveDefAntenna; 1908 u32 macStaId1; 1909 u64 tsf = 0; 1910 int i, rx_chainmask, r; 1911 1912 ah->txchainmask = common->tx_chainmask; 1913 ah->rxchainmask = common->rx_chainmask; 1914 1915 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1916 return -EIO; 1917 1918 if (curchan && !ah->chip_fullsleep) 1919 ath9k_hw_getnf(ah, curchan); 1920 1921 if (bChannelChange && 1922 (ah->chip_fullsleep != true) && 1923 (ah->curchan != NULL) && 1924 (chan->channel != ah->curchan->channel) && 1925 ((chan->channelFlags & CHANNEL_ALL) == 1926 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1927 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || 1928 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { 1929 1930 if (ath9k_hw_channel_change(ah, chan)) { 1931 ath9k_hw_loadnf(ah, ah->curchan); 1932 ath9k_hw_start_nfcal(ah); 1933 return 0; 1934 } 1935 } 1936 1937 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1938 if (saveDefAntenna == 0) 1939 saveDefAntenna = 1; 1940 1941 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1942 1943 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1944 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1945 tsf = ath9k_hw_gettsf64(ah); 1946 1947 saveLedState = REG_READ(ah, AR_CFG_LED) & 1948 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1949 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1950 1951 ath9k_hw_mark_phy_inactive(ah); 1952 1953 /* Only required on the first reset */ 1954 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1955 REG_WRITE(ah, 1956 AR9271_RESET_POWER_DOWN_CONTROL, 1957 AR9271_RADIO_RF_RST); 1958 udelay(50); 1959 } 1960 1961 if (!ath9k_hw_chip_reset(ah, chan)) { 1962 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); 1963 return -EINVAL; 1964 } 1965 1966 /* Only required on the first reset */ 1967 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1968 ah->htc_reset_init = false; 1969 REG_WRITE(ah, 1970 AR9271_RESET_POWER_DOWN_CONTROL, 1971 AR9271_GATE_MAC_CTL); 1972 udelay(50); 1973 } 1974 1975 /* Restore TSF */ 1976 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1977 ath9k_hw_settsf64(ah, tsf); 1978 1979 if (AR_SREV_9280_10_OR_LATER(ah)) 1980 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1981 1982 if (AR_SREV_9287_12_OR_LATER(ah)) { 1983 /* Enable ASYNC FIFO */ 1984 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 1985 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 1986 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 1987 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 1988 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 1989 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 1990 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 1991 } 1992 r = ath9k_hw_process_ini(ah, chan); 1993 if (r) 1994 return r; 1995 1996 /* Setup MFP options for CCMP */ 1997 if (AR_SREV_9280_20_OR_LATER(ah)) { 1998 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1999 * frames when constructing CCMP AAD. */ 2000 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 2001 0xc7ff); 2002 ah->sw_mgmt_crypto = false; 2003 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 2004 /* Disable hardware crypto for management frames */ 2005 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 2006 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2007 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 2008 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2009 ah->sw_mgmt_crypto = true; 2010 } else 2011 ah->sw_mgmt_crypto = true; 2012 2013 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2014 ath9k_hw_set_delta_slope(ah, chan); 2015 2016 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 2017 ah->eep_ops->set_board_values(ah, chan); 2018 2019 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 2020 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 2021 | macStaId1 2022 | AR_STA_ID1_RTS_USE_DEF 2023 | (ah->config. 2024 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 2025 | ah->sta_id1_defaults); 2026 ath9k_hw_set_operating_mode(ah, ah->opmode); 2027 2028 ath_hw_setbssidmask(common); 2029 2030 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 2031 2032 ath9k_hw_write_associd(ah); 2033 2034 REG_WRITE(ah, AR_ISR, ~0); 2035 2036 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2037 2038 r = ah->ath9k_hw_rf_set_freq(ah, chan); 2039 if (r) 2040 return r; 2041 2042 for (i = 0; i < AR_NUM_DCU; i++) 2043 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2044 2045 ah->intr_txqs = 0; 2046 for (i = 0; i < ah->caps.total_queues; i++) 2047 ath9k_hw_resettxqueue(ah, i); 2048 2049 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 2050 ath9k_hw_init_qos(ah); 2051 2052 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2053 ath9k_enable_rfkill(ah); 2054 2055 ath9k_hw_init_global_settings(ah); 2056 2057 if (AR_SREV_9287_12_OR_LATER(ah)) { 2058 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 2059 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 2060 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 2061 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 2062 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 2063 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 2064 2065 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 2066 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 2067 2068 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 2069 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 2070 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 2071 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 2072 } 2073 if (AR_SREV_9287_12_OR_LATER(ah)) { 2074 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 2075 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 2076 } 2077 2078 REG_WRITE(ah, AR_STA_ID1, 2079 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 2080 2081 ath9k_hw_set_dma(ah); 2082 2083 REG_WRITE(ah, AR_OBS, 8); 2084 2085 if (ah->config.rx_intr_mitigation) { 2086 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2087 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2088 } 2089 2090 ath9k_hw_init_bb(ah, chan); 2091 2092 if (!ath9k_hw_init_cal(ah, chan)) 2093 return -EIO; 2094 2095 rx_chainmask = ah->rxchainmask; 2096 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 2097 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 2098 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 2099 } 2100 2101 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2102 2103 /* 2104 * For big endian systems turn on swapping for descriptors 2105 */ 2106 if (AR_SREV_9100(ah)) { 2107 u32 mask; 2108 mask = REG_READ(ah, AR_CFG); 2109 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2110 ath_print(common, ATH_DBG_RESET, 2111 "CFG Byte Swap Set 0x%x\n", mask); 2112 } else { 2113 mask = 2114 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2115 REG_WRITE(ah, AR_CFG, mask); 2116 ath_print(common, ATH_DBG_RESET, 2117 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 2118 } 2119 } else { 2120 /* Configure AR9271 target WLAN */ 2121 if (AR_SREV_9271(ah)) 2122 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2123#ifdef __BIG_ENDIAN 2124 else 2125 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2126#endif 2127 } 2128 2129 if (ah->btcoex_hw.enabled) 2130 ath9k_hw_btcoex_enable(ah); 2131 2132 return 0; 2133} 2134EXPORT_SYMBOL(ath9k_hw_reset); 2135 2136/************************/ 2137/* Key Cache Management */ 2138/************************/ 2139 2140bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) 2141{ 2142 u32 keyType; 2143 2144 if (entry >= ah->caps.keycache_size) { 2145 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2146 "keychache entry %u out of range\n", entry); 2147 return false; 2148 } 2149 2150 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 2151 2152 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 2153 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 2154 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 2155 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 2156 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 2157 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 2158 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 2159 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 2160 2161 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 2162 u16 micentry = entry + 64; 2163 2164 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 2165 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 2166 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); 2167 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 2168 2169 } 2170 2171 return true; 2172} 2173EXPORT_SYMBOL(ath9k_hw_keyreset); 2174 2175bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) 2176{ 2177 u32 macHi, macLo; 2178 2179 if (entry >= ah->caps.keycache_size) { 2180 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2181 "keychache entry %u out of range\n", entry); 2182 return false; 2183 } 2184 2185 if (mac != NULL) { 2186 macHi = (mac[5] << 8) | mac[4]; 2187 macLo = (mac[3] << 24) | 2188 (mac[2] << 16) | 2189 (mac[1] << 8) | 2190 mac[0]; 2191 macLo >>= 1; 2192 macLo |= (macHi & 1) << 31; 2193 macHi >>= 1; 2194 } else { 2195 macLo = macHi = 0; 2196 } 2197 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 2198 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); 2199 2200 return true; 2201} 2202EXPORT_SYMBOL(ath9k_hw_keysetmac); 2203 2204bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, 2205 const struct ath9k_keyval *k, 2206 const u8 *mac) 2207{ 2208 const struct ath9k_hw_capabilities *pCap = &ah->caps; 2209 struct ath_common *common = ath9k_hw_common(ah); 2210 u32 key0, key1, key2, key3, key4; 2211 u32 keyType; 2212 2213 if (entry >= pCap->keycache_size) { 2214 ath_print(common, ATH_DBG_FATAL, 2215 "keycache entry %u out of range\n", entry); 2216 return false; 2217 } 2218 2219 switch (k->kv_type) { 2220 case ATH9K_CIPHER_AES_OCB: 2221 keyType = AR_KEYTABLE_TYPE_AES; 2222 break; 2223 case ATH9K_CIPHER_AES_CCM: 2224 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2225 ath_print(common, ATH_DBG_ANY, 2226 "AES-CCM not supported by mac rev 0x%x\n", 2227 ah->hw_version.macRev); 2228 return false; 2229 } 2230 keyType = AR_KEYTABLE_TYPE_CCM; 2231 break; 2232 case ATH9K_CIPHER_TKIP: 2233 keyType = AR_KEYTABLE_TYPE_TKIP; 2234 if (ATH9K_IS_MIC_ENABLED(ah) 2235 && entry + 64 >= pCap->keycache_size) { 2236 ath_print(common, ATH_DBG_ANY, 2237 "entry %u inappropriate for TKIP\n", entry); 2238 return false; 2239 } 2240 break; 2241 case ATH9K_CIPHER_WEP: 2242 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 2243 ath_print(common, ATH_DBG_ANY, 2244 "WEP key length %u too small\n", k->kv_len); 2245 return false; 2246 } 2247 if (k->kv_len <= WLAN_KEY_LEN_WEP40) 2248 keyType = AR_KEYTABLE_TYPE_40; 2249 else if (k->kv_len <= WLAN_KEY_LEN_WEP104) 2250 keyType = AR_KEYTABLE_TYPE_104; 2251 else 2252 keyType = AR_KEYTABLE_TYPE_128; 2253 break; 2254 case ATH9K_CIPHER_CLR: 2255 keyType = AR_KEYTABLE_TYPE_CLR; 2256 break; 2257 default: 2258 ath_print(common, ATH_DBG_FATAL, 2259 "cipher %u not supported\n", k->kv_type); 2260 return false; 2261 } 2262 2263 key0 = get_unaligned_le32(k->kv_val + 0); 2264 key1 = get_unaligned_le16(k->kv_val + 4); 2265 key2 = get_unaligned_le32(k->kv_val + 6); 2266 key3 = get_unaligned_le16(k->kv_val + 10); 2267 key4 = get_unaligned_le32(k->kv_val + 12); 2268 if (k->kv_len <= WLAN_KEY_LEN_WEP104) 2269 key4 &= 0xff; 2270 2271 /* 2272 * Note: Key cache registers access special memory area that requires 2273 * two 32-bit writes to actually update the values in the internal 2274 * memory. Consequently, the exact order and pairs used here must be 2275 * maintained. 2276 */ 2277 2278 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 2279 u16 micentry = entry + 64; 2280 2281 /* 2282 * Write inverted key[47:0] first to avoid Michael MIC errors 2283 * on frames that could be sent or received at the same time. 2284 * The correct key will be written in the end once everything 2285 * else is ready. 2286 */ 2287 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); 2288 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); 2289 2290 /* Write key[95:48] */ 2291 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 2292 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 2293 2294 /* Write key[127:96] and key type */ 2295 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 2296 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2297 2298 /* Write MAC address for the entry */ 2299 (void) ath9k_hw_keysetmac(ah, entry, mac); 2300 2301 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { 2302 /* 2303 * TKIP uses two key cache entries: 2304 * Michael MIC TX/RX keys in the same key cache entry 2305 * (idx = main index + 64): 2306 * key0 [31:0] = RX key [31:0] 2307 * key1 [15:0] = TX key [31:16] 2308 * key1 [31:16] = reserved 2309 * key2 [31:0] = RX key [63:32] 2310 * key3 [15:0] = TX key [15:0] 2311 * key3 [31:16] = reserved 2312 * key4 [31:0] = TX key [63:32] 2313 */ 2314 u32 mic0, mic1, mic2, mic3, mic4; 2315 2316 mic0 = get_unaligned_le32(k->kv_mic + 0); 2317 mic2 = get_unaligned_le32(k->kv_mic + 4); 2318 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; 2319 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; 2320 mic4 = get_unaligned_le32(k->kv_txmic + 4); 2321 2322 /* Write RX[31:0] and TX[31:16] */ 2323 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 2324 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); 2325 2326 /* Write RX[63:32] and TX[15:0] */ 2327 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 2328 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); 2329 2330 /* Write TX[63:32] and keyType(reserved) */ 2331 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); 2332 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 2333 AR_KEYTABLE_TYPE_CLR); 2334 2335 } else { 2336 /* 2337 * TKIP uses four key cache entries (two for group 2338 * keys): 2339 * Michael MIC TX/RX keys are in different key cache 2340 * entries (idx = main index + 64 for TX and 2341 * main index + 32 + 96 for RX): 2342 * key0 [31:0] = TX/RX MIC key [31:0] 2343 * key1 [31:0] = reserved 2344 * key2 [31:0] = TX/RX MIC key [63:32] 2345 * key3 [31:0] = reserved 2346 * key4 [31:0] = reserved 2347 * 2348 * Upper layer code will call this function separately 2349 * for TX and RX keys when these registers offsets are 2350 * used. 2351 */ 2352 u32 mic0, mic2; 2353 2354 mic0 = get_unaligned_le32(k->kv_mic + 0); 2355 mic2 = get_unaligned_le32(k->kv_mic + 4); 2356 2357 /* Write MIC key[31:0] */ 2358 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 2359 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 2360 2361 /* Write MIC key[63:32] */ 2362 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 2363 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 2364 2365 /* Write TX[63:32] and keyType(reserved) */ 2366 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); 2367 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 2368 AR_KEYTABLE_TYPE_CLR); 2369 } 2370 2371 /* MAC address registers are reserved for the MIC entry */ 2372 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); 2373 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); 2374 2375 /* 2376 * Write the correct (un-inverted) key[47:0] last to enable 2377 * TKIP now that all other registers are set with correct 2378 * values. 2379 */ 2380 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 2381 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 2382 } else { 2383 /* Write key[47:0] */ 2384 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 2385 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 2386 2387 /* Write key[95:48] */ 2388 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 2389 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 2390 2391 /* Write key[127:96] and key type */ 2392 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 2393 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2394 2395 /* Write MAC address for the entry */ 2396 (void) ath9k_hw_keysetmac(ah, entry, mac); 2397 } 2398 2399 return true; 2400} 2401EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); 2402 2403bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) 2404{ 2405 if (entry < ah->caps.keycache_size) { 2406 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 2407 if (val & AR_KEYTABLE_VALID) 2408 return true; 2409 } 2410 return false; 2411} 2412EXPORT_SYMBOL(ath9k_hw_keyisvalid); 2413 2414/******************************/ 2415/* Power Management (Chipset) */ 2416/******************************/ 2417 2418static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 2419{ 2420 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2421 if (setChip) { 2422 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2423 AR_RTC_FORCE_WAKE_EN); 2424 if (!AR_SREV_9100(ah)) 2425 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2426 2427 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 2428 REG_CLR_BIT(ah, (AR_RTC_RESET), 2429 AR_RTC_RESET_EN); 2430 } 2431} 2432 2433static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 2434{ 2435 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2436 if (setChip) { 2437 struct ath9k_hw_capabilities *pCap = &ah->caps; 2438 2439 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2440 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2441 AR_RTC_FORCE_WAKE_ON_INT); 2442 } else { 2443 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2444 AR_RTC_FORCE_WAKE_EN); 2445 } 2446 } 2447} 2448 2449static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 2450{ 2451 u32 val; 2452 int i; 2453 2454 if (setChip) { 2455 if ((REG_READ(ah, AR_RTC_STATUS) & 2456 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2457 if (ath9k_hw_set_reset_reg(ah, 2458 ATH9K_RESET_POWER_ON) != true) { 2459 return false; 2460 } 2461 ath9k_hw_init_pll(ah, NULL); 2462 } 2463 if (AR_SREV_9100(ah)) 2464 REG_SET_BIT(ah, AR_RTC_RESET, 2465 AR_RTC_RESET_EN); 2466 2467 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2468 AR_RTC_FORCE_WAKE_EN); 2469 udelay(50); 2470 2471 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2472 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2473 if (val == AR_RTC_STATUS_ON) 2474 break; 2475 udelay(50); 2476 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2477 AR_RTC_FORCE_WAKE_EN); 2478 } 2479 if (i == 0) { 2480 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2481 "Failed to wakeup in %uus\n", 2482 POWER_UP_TIME / 20); 2483 return false; 2484 } 2485 } 2486 2487 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2488 2489 return true; 2490} 2491 2492bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2493{ 2494 struct ath_common *common = ath9k_hw_common(ah); 2495 int status = true, setChip = true; 2496 static const char *modes[] = { 2497 "AWAKE", 2498 "FULL-SLEEP", 2499 "NETWORK SLEEP", 2500 "UNDEFINED" 2501 }; 2502 2503 if (ah->power_mode == mode) 2504 return status; 2505 2506 ath_print(common, ATH_DBG_RESET, "%s -> %s\n", 2507 modes[ah->power_mode], modes[mode]); 2508 2509 switch (mode) { 2510 case ATH9K_PM_AWAKE: 2511 status = ath9k_hw_set_power_awake(ah, setChip); 2512 break; 2513 case ATH9K_PM_FULL_SLEEP: 2514 ath9k_set_power_sleep(ah, setChip); 2515 ah->chip_fullsleep = true; 2516 break; 2517 case ATH9K_PM_NETWORK_SLEEP: 2518 ath9k_set_power_network_sleep(ah, setChip); 2519 break; 2520 default: 2521 ath_print(common, ATH_DBG_FATAL, 2522 "Unknown power mode %u\n", mode); 2523 return false; 2524 } 2525 ah->power_mode = mode; 2526 2527 return status; 2528} 2529EXPORT_SYMBOL(ath9k_hw_setpower); 2530 2531/* 2532 * Helper for ASPM support. 2533 * 2534 * Disable PLL when in L0s as well as receiver clock when in L1. 2535 * This power saving option must be enabled through the SerDes. 2536 * 2537 * Programming the SerDes must go through the same 288 bit serial shift 2538 * register as the other analog registers. Hence the 9 writes. 2539 */ 2540void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off) 2541{ 2542 u8 i; 2543 u32 val; 2544 2545 if (ah->is_pciexpress != true) 2546 return; 2547 2548 /* Do not touch SerDes registers */ 2549 if (ah->config.pcie_powersave_enable == 2) 2550 return; 2551 2552 /* Nothing to do on restore for 11N */ 2553 if (!restore) { 2554 if (AR_SREV_9280_20_OR_LATER(ah)) { 2555 /* 2556 * AR9280 2.0 or later chips use SerDes values from the 2557 * initvals.h initialized depending on chipset during 2558 * ath9k_hw_init() 2559 */ 2560 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { 2561 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), 2562 INI_RA(&ah->iniPcieSerdes, i, 1)); 2563 } 2564 } else if (AR_SREV_9280(ah) && 2565 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { 2566 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); 2567 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2568 2569 /* RX shut off when elecidle is asserted */ 2570 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); 2571 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); 2572 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); 2573 2574 /* Shut off CLKREQ active in L1 */ 2575 if (ah->config.pcie_clock_req) 2576 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); 2577 else 2578 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); 2579 2580 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 2581 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 2582 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); 2583 2584 /* Load the new settings */ 2585 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 2586 2587 } else { 2588 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 2589 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2590 2591 /* RX shut off when elecidle is asserted */ 2592 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 2593 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 2594 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 2595 2596 /* 2597 * Ignore ah->ah_config.pcie_clock_req setting for 2598 * pre-AR9280 11n 2599 */ 2600 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 2601 2602 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 2603 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 2604 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 2605 2606 /* Load the new settings */ 2607 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 2608 } 2609 2610 udelay(1000); 2611 2612 /* set bit 19 to allow forcing of pcie core into L1 state */ 2613 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 2614 2615 /* Several PCIe massages to ensure proper behaviour */ 2616 if (ah->config.pcie_waen) { 2617 val = ah->config.pcie_waen; 2618 if (!power_off) 2619 val &= (~AR_WA_D3_L1_DISABLE); 2620 } else { 2621 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || 2622 AR_SREV_9287(ah)) { 2623 val = AR9285_WA_DEFAULT; 2624 if (!power_off) 2625 val &= (~AR_WA_D3_L1_DISABLE); 2626 } else if (AR_SREV_9280(ah)) { 2627 /* 2628 * On AR9280 chips bit 22 of 0x4004 needs to be 2629 * set otherwise card may disappear. 2630 */ 2631 val = AR9280_WA_DEFAULT; 2632 if (!power_off) 2633 val &= (~AR_WA_D3_L1_DISABLE); 2634 } else 2635 val = AR_WA_DEFAULT; 2636 } 2637 2638 REG_WRITE(ah, AR_WA, val); 2639 } 2640 2641 if (power_off) { 2642 /* 2643 * Set PCIe workaround bits 2644 * bit 14 in WA register (disable L1) should only 2645 * be set when device enters D3 and be cleared 2646 * when device comes back to D0. 2647 */ 2648 if (ah->config.pcie_waen) { 2649 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) 2650 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); 2651 } else { 2652 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) || 2653 AR_SREV_9287(ah)) && 2654 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || 2655 (AR_SREV_9280(ah) && 2656 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { 2657 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); 2658 } 2659 } 2660 } 2661} 2662EXPORT_SYMBOL(ath9k_hw_configpcipowersave); 2663 2664/**********************/ 2665/* Interrupt Handling */ 2666/**********************/ 2667 2668bool ath9k_hw_intrpend(struct ath_hw *ah) 2669{ 2670 u32 host_isr; 2671 2672 if (AR_SREV_9100(ah)) 2673 return true; 2674 2675 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); 2676 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) 2677 return true; 2678 2679 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); 2680 if ((host_isr & AR_INTR_SYNC_DEFAULT) 2681 && (host_isr != AR_INTR_SPURIOUS)) 2682 return true; 2683 2684 return false; 2685} 2686EXPORT_SYMBOL(ath9k_hw_intrpend); 2687 2688bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) 2689{ 2690 u32 isr = 0; 2691 u32 mask2 = 0; 2692 struct ath9k_hw_capabilities *pCap = &ah->caps; 2693 u32 sync_cause = 0; 2694 bool fatal_int = false; 2695 struct ath_common *common = ath9k_hw_common(ah); 2696 2697 if (!AR_SREV_9100(ah)) { 2698 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2699 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 2700 == AR_RTC_STATUS_ON) { 2701 isr = REG_READ(ah, AR_ISR); 2702 } 2703 } 2704 2705 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & 2706 AR_INTR_SYNC_DEFAULT; 2707 2708 *masked = 0; 2709 2710 if (!isr && !sync_cause) 2711 return false; 2712 } else { 2713 *masked = 0; 2714 isr = REG_READ(ah, AR_ISR); 2715 } 2716 2717 if (isr) { 2718 if (isr & AR_ISR_BCNMISC) { 2719 u32 isr2; 2720 isr2 = REG_READ(ah, AR_ISR_S2); 2721 if (isr2 & AR_ISR_S2_TIM) 2722 mask2 |= ATH9K_INT_TIM; 2723 if (isr2 & AR_ISR_S2_DTIM) 2724 mask2 |= ATH9K_INT_DTIM; 2725 if (isr2 & AR_ISR_S2_DTIMSYNC) 2726 mask2 |= ATH9K_INT_DTIMSYNC; 2727 if (isr2 & (AR_ISR_S2_CABEND)) 2728 mask2 |= ATH9K_INT_CABEND; 2729 if (isr2 & AR_ISR_S2_GTT) 2730 mask2 |= ATH9K_INT_GTT; 2731 if (isr2 & AR_ISR_S2_CST) 2732 mask2 |= ATH9K_INT_CST; 2733 if (isr2 & AR_ISR_S2_TSFOOR) 2734 mask2 |= ATH9K_INT_TSFOOR; 2735 } 2736 2737 isr = REG_READ(ah, AR_ISR_RAC); 2738 if (isr == 0xffffffff) { 2739 *masked = 0; 2740 return false; 2741 } 2742 2743 *masked = isr & ATH9K_INT_COMMON; 2744 2745 if (ah->config.rx_intr_mitigation) { 2746 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2747 *masked |= ATH9K_INT_RX; 2748 } 2749 2750 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 2751 *masked |= ATH9K_INT_RX; 2752 if (isr & 2753 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | 2754 AR_ISR_TXEOL)) { 2755 u32 s0_s, s1_s; 2756 2757 *masked |= ATH9K_INT_TX; 2758 2759 s0_s = REG_READ(ah, AR_ISR_S0_S); 2760 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); 2761 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); 2762 2763 s1_s = REG_READ(ah, AR_ISR_S1_S); 2764 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); 2765 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); 2766 } 2767 2768 if (isr & AR_ISR_RXORN) { 2769 ath_print(common, ATH_DBG_INTERRUPT, 2770 "receive FIFO overrun interrupt\n"); 2771 } 2772 2773 if (!AR_SREV_9100(ah)) { 2774 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2775 u32 isr5 = REG_READ(ah, AR_ISR_S5_S); 2776 if (isr5 & AR_ISR_S5_TIM_TIMER) 2777 *masked |= ATH9K_INT_TIM_TIMER; 2778 } 2779 } 2780 2781 *masked |= mask2; 2782 } 2783 2784 if (AR_SREV_9100(ah)) 2785 return true; 2786 2787 if (isr & AR_ISR_GENTMR) { 2788 u32 s5_s; 2789 2790 s5_s = REG_READ(ah, AR_ISR_S5_S); 2791 if (isr & AR_ISR_GENTMR) { 2792 ah->intr_gen_timer_trigger = 2793 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); 2794 2795 ah->intr_gen_timer_thresh = 2796 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH); 2797 2798 if (ah->intr_gen_timer_trigger) 2799 *masked |= ATH9K_INT_GENTIMER; 2800 2801 } 2802 } 2803 2804 if (sync_cause) { 2805 fatal_int = 2806 (sync_cause & 2807 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) 2808 ? true : false; 2809 2810 if (fatal_int) { 2811 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 2812 ath_print(common, ATH_DBG_ANY, 2813 "received PCI FATAL interrupt\n"); 2814 } 2815 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 2816 ath_print(common, ATH_DBG_ANY, 2817 "received PCI PERR interrupt\n"); 2818 } 2819 *masked |= ATH9K_INT_FATAL; 2820 } 2821 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 2822 ath_print(common, ATH_DBG_INTERRUPT, 2823 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); 2824 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 2825 REG_WRITE(ah, AR_RC, 0); 2826 *masked |= ATH9K_INT_FATAL; 2827 } 2828 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 2829 ath_print(common, ATH_DBG_INTERRUPT, 2830 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 2831 } 2832 2833 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 2834 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 2835 } 2836 2837 return true; 2838} 2839EXPORT_SYMBOL(ath9k_hw_getisr); 2840 2841enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) 2842{ 2843 enum ath9k_int omask = ah->imask; 2844 u32 mask, mask2; 2845 struct ath9k_hw_capabilities *pCap = &ah->caps; 2846 struct ath_common *common = ath9k_hw_common(ah); 2847 2848 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 2849 2850 if (omask & ATH9K_INT_GLOBAL) { 2851 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n"); 2852 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 2853 (void) REG_READ(ah, AR_IER); 2854 if (!AR_SREV_9100(ah)) { 2855 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 2856 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); 2857 2858 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 2859 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); 2860 } 2861 } 2862 2863 mask = ints & ATH9K_INT_COMMON; 2864 mask2 = 0; 2865 2866 if (ints & ATH9K_INT_TX) { 2867 if (ah->txok_interrupt_mask) 2868 mask |= AR_IMR_TXOK; 2869 if (ah->txdesc_interrupt_mask) 2870 mask |= AR_IMR_TXDESC; 2871 if (ah->txerr_interrupt_mask) 2872 mask |= AR_IMR_TXERR; 2873 if (ah->txeol_interrupt_mask) 2874 mask |= AR_IMR_TXEOL; 2875 } 2876 if (ints & ATH9K_INT_RX) { 2877 mask |= AR_IMR_RXERR; 2878 if (ah->config.rx_intr_mitigation) 2879 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 2880 else 2881 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 2882 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 2883 mask |= AR_IMR_GENTMR; 2884 } 2885 2886 if (ints & (ATH9K_INT_BMISC)) { 2887 mask |= AR_IMR_BCNMISC; 2888 if (ints & ATH9K_INT_TIM) 2889 mask2 |= AR_IMR_S2_TIM; 2890 if (ints & ATH9K_INT_DTIM) 2891 mask2 |= AR_IMR_S2_DTIM; 2892 if (ints & ATH9K_INT_DTIMSYNC) 2893 mask2 |= AR_IMR_S2_DTIMSYNC; 2894 if (ints & ATH9K_INT_CABEND) 2895 mask2 |= AR_IMR_S2_CABEND; 2896 if (ints & ATH9K_INT_TSFOOR) 2897 mask2 |= AR_IMR_S2_TSFOOR; 2898 } 2899 2900 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { 2901 mask |= AR_IMR_BCNMISC; 2902 if (ints & ATH9K_INT_GTT) 2903 mask2 |= AR_IMR_S2_GTT; 2904 if (ints & ATH9K_INT_CST) 2905 mask2 |= AR_IMR_S2_CST; 2906 } 2907 2908 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); 2909 REG_WRITE(ah, AR_IMR, mask); 2910 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2911 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2912 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2913 ah->imrs2_reg |= mask2; 2914 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 2915 2916 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2917 if (ints & ATH9K_INT_TIM_TIMER) 2918 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2919 else 2920 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2921 } 2922 2923 if (ints & ATH9K_INT_GLOBAL) { 2924 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n"); 2925 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 2926 if (!AR_SREV_9100(ah)) { 2927 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 2928 AR_INTR_MAC_IRQ); 2929 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2930 2931 2932 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 2933 AR_INTR_SYNC_DEFAULT); 2934 REG_WRITE(ah, AR_INTR_SYNC_MASK, 2935 AR_INTR_SYNC_DEFAULT); 2936 } 2937 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 2938 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 2939 } 2940 2941 return omask; 2942} 2943EXPORT_SYMBOL(ath9k_hw_set_interrupts); 2944 2945/*******************/ 2946/* Beacon Handling */ 2947/*******************/ 2948 2949void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2950{ 2951 int flags = 0; 2952 2953 ah->beacon_interval = beacon_period; 2954 2955 switch (ah->opmode) { 2956 case NL80211_IFTYPE_STATION: 2957 case NL80211_IFTYPE_MONITOR: 2958 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 2959 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); 2960 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); 2961 flags |= AR_TBTT_TIMER_EN; 2962 break; 2963 case NL80211_IFTYPE_ADHOC: 2964 case NL80211_IFTYPE_MESH_POINT: 2965 REG_SET_BIT(ah, AR_TXCFG, 2966 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2967 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 2968 TU_TO_USEC(next_beacon + 2969 (ah->atim_window ? ah-> 2970 atim_window : 1))); 2971 flags |= AR_NDP_TIMER_EN; 2972 case NL80211_IFTYPE_AP: 2973 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 2974 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 2975 TU_TO_USEC(next_beacon - 2976 ah->config. 2977 dma_beacon_response_time)); 2978 REG_WRITE(ah, AR_NEXT_SWBA, 2979 TU_TO_USEC(next_beacon - 2980 ah->config. 2981 sw_beacon_response_time)); 2982 flags |= 2983 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2984 break; 2985 default: 2986 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, 2987 "%s: unsupported opmode: %d\n", 2988 __func__, ah->opmode); 2989 return; 2990 break; 2991 } 2992 2993 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 2994 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 2995 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 2996 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 2997 2998 beacon_period &= ~ATH9K_BEACON_ENA; 2999 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 3000 ath9k_hw_reset_tsf(ah); 3001 } 3002 3003 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3004} 3005EXPORT_SYMBOL(ath9k_hw_beaconinit); 3006 3007void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 3008 const struct ath9k_beacon_state *bs) 3009{ 3010 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3011 struct ath9k_hw_capabilities *pCap = &ah->caps; 3012 struct ath_common *common = ath9k_hw_common(ah); 3013 3014 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 3015 3016 REG_WRITE(ah, AR_BEACON_PERIOD, 3017 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 3018 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 3019 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 3020 3021 REG_RMW_FIELD(ah, AR_RSSI_THR, 3022 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 3023 3024 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 3025 3026 if (bs->bs_sleepduration > beaconintval) 3027 beaconintval = bs->bs_sleepduration; 3028 3029 dtimperiod = bs->bs_dtimperiod; 3030 if (bs->bs_sleepduration > dtimperiod) 3031 dtimperiod = bs->bs_sleepduration; 3032 3033 if (beaconintval == dtimperiod) 3034 nextTbtt = bs->bs_nextdtim; 3035 else 3036 nextTbtt = bs->bs_nexttbtt; 3037 3038 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 3039 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 3040 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 3041 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 3042 3043 REG_WRITE(ah, AR_NEXT_DTIM, 3044 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3045 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 3046 3047 REG_WRITE(ah, AR_SLEEP1, 3048 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 3049 | AR_SLEEP1_ASSUME_DTIM); 3050 3051 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 3052 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 3053 else 3054 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 3055 3056 REG_WRITE(ah, AR_SLEEP2, 3057 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 3058 3059 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 3060 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 3061 3062 REG_SET_BIT(ah, AR_TIMER_MODE, 3063 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 3064 AR_DTIM_TIMER_EN); 3065 3066 /* TSF Out of Range Threshold */ 3067 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 3068} 3069EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 3070 3071/*******************/ 3072/* HW Capabilities */ 3073/*******************/ 3074 3075int ath9k_hw_fill_cap_info(struct ath_hw *ah) 3076{ 3077 struct ath9k_hw_capabilities *pCap = &ah->caps; 3078 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 3079 struct ath_common *common = ath9k_hw_common(ah); 3080 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 3081 3082 u16 capField = 0, eeval; 3083 3084 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 3085 regulatory->current_rd = eeval; 3086 3087 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 3088 if (AR_SREV_9285_10_OR_LATER(ah)) 3089 eeval |= AR9285_RDEXT_DEFAULT; 3090 regulatory->current_rd_ext = eeval; 3091 3092 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 3093 3094 if (ah->opmode != NL80211_IFTYPE_AP && 3095 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 3096 if (regulatory->current_rd == 0x64 || 3097 regulatory->current_rd == 0x65) 3098 regulatory->current_rd += 5; 3099 else if (regulatory->current_rd == 0x41) 3100 regulatory->current_rd = 0x43; 3101 ath_print(common, ATH_DBG_REGULATORY, 3102 "regdomain mapped to 0x%x\n", regulatory->current_rd); 3103 } 3104 3105 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 3106 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 3107 ath_print(common, ATH_DBG_FATAL, 3108 "no band has been marked as supported in EEPROM.\n"); 3109 return -EINVAL; 3110 } 3111 3112 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); 3113 3114 if (eeval & AR5416_OPFLAGS_11A) { 3115 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 3116 if (ah->config.ht_enable) { 3117 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) 3118 set_bit(ATH9K_MODE_11NA_HT20, 3119 pCap->wireless_modes); 3120 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { 3121 set_bit(ATH9K_MODE_11NA_HT40PLUS, 3122 pCap->wireless_modes); 3123 set_bit(ATH9K_MODE_11NA_HT40MINUS, 3124 pCap->wireless_modes); 3125 } 3126 } 3127 } 3128 3129 if (eeval & AR5416_OPFLAGS_11G) { 3130 set_bit(ATH9K_MODE_11G, pCap->wireless_modes); 3131 if (ah->config.ht_enable) { 3132 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) 3133 set_bit(ATH9K_MODE_11NG_HT20, 3134 pCap->wireless_modes); 3135 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { 3136 set_bit(ATH9K_MODE_11NG_HT40PLUS, 3137 pCap->wireless_modes); 3138 set_bit(ATH9K_MODE_11NG_HT40MINUS, 3139 pCap->wireless_modes); 3140 } 3141 } 3142 } 3143 3144 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 3145 /* 3146 * For AR9271 we will temporarilly uses the rx chainmax as read from 3147 * the EEPROM. 3148 */ 3149 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 3150 !(eeval & AR5416_OPFLAGS_11A) && 3151 !(AR_SREV_9271(ah))) 3152 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 3153 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 3154 else 3155 /* Use rx_chainmask from EEPROM. */ 3156 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 3157 3158 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 3159 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 3160 3161 pCap->low_2ghz_chan = 2312; 3162 pCap->high_2ghz_chan = 2732; 3163 3164 pCap->low_5ghz_chan = 4920; 3165 pCap->high_5ghz_chan = 6100; 3166 3167 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; 3168 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; 3169 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; 3170 3171 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; 3172 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; 3173 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; 3174 3175 if (ah->config.ht_enable) 3176 pCap->hw_caps |= ATH9K_HW_CAP_HT; 3177 else 3178 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 3179 3180 pCap->hw_caps |= ATH9K_HW_CAP_GTT; 3181 pCap->hw_caps |= ATH9K_HW_CAP_VEOL; 3182 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; 3183 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; 3184 3185 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 3186 pCap->total_queues = 3187 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 3188 else 3189 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 3190 3191 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 3192 pCap->keycache_size = 3193 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 3194 else 3195 pCap->keycache_size = AR_KEYTABLE_SIZE; 3196 3197 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; 3198 3199 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 3200 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; 3201 else 3202 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 3203 3204 if (AR_SREV_9271(ah)) 3205 pCap->num_gpio_pins = AR9271_NUM_GPIO; 3206 else if (AR_SREV_9285_10_OR_LATER(ah)) 3207 pCap->num_gpio_pins = AR9285_NUM_GPIO; 3208 else if (AR_SREV_9280_10_OR_LATER(ah)) 3209 pCap->num_gpio_pins = AR928X_NUM_GPIO; 3210 else 3211 pCap->num_gpio_pins = AR_NUM_GPIO; 3212 3213 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 3214 pCap->hw_caps |= ATH9K_HW_CAP_CST; 3215 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 3216 } else { 3217 pCap->rts_aggr_limit = (8 * 1024); 3218 } 3219 3220 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 3221 3222#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3223 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 3224 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 3225 ah->rfkill_gpio = 3226 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 3227 ah->rfkill_polarity = 3228 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 3229 3230 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 3231 } 3232#endif 3233 3234 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 3235 3236 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 3237 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 3238 else 3239 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 3240 3241 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 3242 pCap->reg_cap = 3243 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3244 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 3245 AR_EEPROM_EEREGCAP_EN_KK_U2 | 3246 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 3247 } else { 3248 pCap->reg_cap = 3249 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3250 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 3251 } 3252 3253 /* Advertise midband for AR5416 with FCC midband set in eeprom */ 3254 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && 3255 AR_SREV_5416(ah)) 3256 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 3257 3258 pCap->num_antcfg_5ghz = 3259 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 3260 pCap->num_antcfg_2ghz = 3261 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 3262 3263 if (AR_SREV_9280_10_OR_LATER(ah) && 3264 ath9k_hw_btcoex_supported(ah)) { 3265 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 3266 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 3267 3268 if (AR_SREV_9285(ah)) { 3269 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 3270 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; 3271 } else { 3272 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 3273 } 3274 } else { 3275 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 3276 } 3277 3278 return 0; 3279} 3280 3281bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3282 u32 capability, u32 *result) 3283{ 3284 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 3285 switch (type) { 3286 case ATH9K_CAP_CIPHER: 3287 switch (capability) { 3288 case ATH9K_CIPHER_AES_CCM: 3289 case ATH9K_CIPHER_AES_OCB: 3290 case ATH9K_CIPHER_TKIP: 3291 case ATH9K_CIPHER_WEP: 3292 case ATH9K_CIPHER_MIC: 3293 case ATH9K_CIPHER_CLR: 3294 return true; 3295 default: 3296 return false; 3297 } 3298 case ATH9K_CAP_TKIP_MIC: 3299 switch (capability) { 3300 case 0: 3301 return true; 3302 case 1: 3303 return (ah->sta_id1_defaults & 3304 AR_STA_ID1_CRPT_MIC_ENABLE) ? true : 3305 false; 3306 } 3307 case ATH9K_CAP_TKIP_SPLIT: 3308 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 3309 false : true; 3310 case ATH9K_CAP_DIVERSITY: 3311 return (REG_READ(ah, AR_PHY_CCK_DETECT) & 3312 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 3313 true : false; 3314 case ATH9K_CAP_MCAST_KEYSRCH: 3315 switch (capability) { 3316 case 0: 3317 return true; 3318 case 1: 3319 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 3320 return false; 3321 } else { 3322 return (ah->sta_id1_defaults & 3323 AR_STA_ID1_MCAST_KSRCH) ? true : 3324 false; 3325 } 3326 } 3327 return false; 3328 case ATH9K_CAP_TXPOW: 3329 switch (capability) { 3330 case 0: 3331 return 0; 3332 case 1: 3333 *result = regulatory->power_limit; 3334 return 0; 3335 case 2: 3336 *result = regulatory->max_power_level; 3337 return 0; 3338 case 3: 3339 *result = regulatory->tp_scale; 3340 return 0; 3341 } 3342 return false; 3343 case ATH9K_CAP_DS: 3344 return (AR_SREV_9280_20_OR_LATER(ah) && 3345 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) 3346 ? false : true; 3347 default: 3348 return false; 3349 } 3350} 3351EXPORT_SYMBOL(ath9k_hw_getcapability); 3352 3353bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3354 u32 capability, u32 setting, int *status) 3355{ 3356 u32 v; 3357 3358 switch (type) { 3359 case ATH9K_CAP_TKIP_MIC: 3360 if (setting) 3361 ah->sta_id1_defaults |= 3362 AR_STA_ID1_CRPT_MIC_ENABLE; 3363 else 3364 ah->sta_id1_defaults &= 3365 ~AR_STA_ID1_CRPT_MIC_ENABLE; 3366 return true; 3367 case ATH9K_CAP_DIVERSITY: 3368 v = REG_READ(ah, AR_PHY_CCK_DETECT); 3369 if (setting) 3370 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 3371 else 3372 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 3373 REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 3374 return true; 3375 case ATH9K_CAP_MCAST_KEYSRCH: 3376 if (setting) 3377 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 3378 else 3379 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 3380 return true; 3381 default: 3382 return false; 3383 } 3384} 3385EXPORT_SYMBOL(ath9k_hw_setcapability); 3386 3387/****************************/ 3388/* GPIO / RFKILL / Antennae */ 3389/****************************/ 3390 3391static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 3392 u32 gpio, u32 type) 3393{ 3394 int addr; 3395 u32 gpio_shift, tmp; 3396 3397 if (gpio > 11) 3398 addr = AR_GPIO_OUTPUT_MUX3; 3399 else if (gpio > 5) 3400 addr = AR_GPIO_OUTPUT_MUX2; 3401 else 3402 addr = AR_GPIO_OUTPUT_MUX1; 3403 3404 gpio_shift = (gpio % 6) * 5; 3405 3406 if (AR_SREV_9280_20_OR_LATER(ah) 3407 || (addr != AR_GPIO_OUTPUT_MUX1)) { 3408 REG_RMW(ah, addr, (type << gpio_shift), 3409 (0x1f << gpio_shift)); 3410 } else { 3411 tmp = REG_READ(ah, addr); 3412 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 3413 tmp &= ~(0x1f << gpio_shift); 3414 tmp |= (type << gpio_shift); 3415 REG_WRITE(ah, addr, tmp); 3416 } 3417} 3418 3419void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 3420{ 3421 u32 gpio_shift; 3422 3423 BUG_ON(gpio >= ah->caps.num_gpio_pins); 3424 3425 gpio_shift = gpio << 1; 3426 3427 REG_RMW(ah, 3428 AR_GPIO_OE_OUT, 3429 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 3430 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3431} 3432EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 3433 3434u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 3435{ 3436#define MS_REG_READ(x, y) \ 3437 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 3438 3439 if (gpio >= ah->caps.num_gpio_pins) 3440 return 0xffffffff; 3441 3442 if (AR_SREV_9271(ah)) 3443 return MS_REG_READ(AR9271, gpio) != 0; 3444 else if (AR_SREV_9287_10_OR_LATER(ah)) 3445 return MS_REG_READ(AR9287, gpio) != 0; 3446 else if (AR_SREV_9285_10_OR_LATER(ah)) 3447 return MS_REG_READ(AR9285, gpio) != 0; 3448 else if (AR_SREV_9280_10_OR_LATER(ah)) 3449 return MS_REG_READ(AR928X, gpio) != 0; 3450 else 3451 return MS_REG_READ(AR, gpio) != 0; 3452} 3453EXPORT_SYMBOL(ath9k_hw_gpio_get); 3454 3455void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 3456 u32 ah_signal_type) 3457{ 3458 u32 gpio_shift; 3459 3460 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 3461 3462 gpio_shift = 2 * gpio; 3463 3464 REG_RMW(ah, 3465 AR_GPIO_OE_OUT, 3466 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 3467 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3468} 3469EXPORT_SYMBOL(ath9k_hw_cfg_output); 3470 3471void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 3472{ 3473 if (AR_SREV_9271(ah)) 3474 val = ~val; 3475 3476 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 3477 AR_GPIO_BIT(gpio)); 3478} 3479EXPORT_SYMBOL(ath9k_hw_set_gpio); 3480 3481u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 3482{ 3483 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 3484} 3485EXPORT_SYMBOL(ath9k_hw_getdefantenna); 3486 3487void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 3488{ 3489 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 3490} 3491EXPORT_SYMBOL(ath9k_hw_setantenna); 3492 3493/*********************/ 3494/* General Operation */ 3495/*********************/ 3496 3497u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 3498{ 3499 u32 bits = REG_READ(ah, AR_RX_FILTER); 3500 u32 phybits = REG_READ(ah, AR_PHY_ERR); 3501 3502 if (phybits & AR_PHY_ERR_RADAR) 3503 bits |= ATH9K_RX_FILTER_PHYRADAR; 3504 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 3505 bits |= ATH9K_RX_FILTER_PHYERR; 3506 3507 return bits; 3508} 3509EXPORT_SYMBOL(ath9k_hw_getrxfilter); 3510 3511void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 3512{ 3513 u32 phybits; 3514 3515 REG_WRITE(ah, AR_RX_FILTER, bits); 3516 3517 phybits = 0; 3518 if (bits & ATH9K_RX_FILTER_PHYRADAR) 3519 phybits |= AR_PHY_ERR_RADAR; 3520 if (bits & ATH9K_RX_FILTER_PHYERR) 3521 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 3522 REG_WRITE(ah, AR_PHY_ERR, phybits); 3523 3524 if (phybits) 3525 REG_WRITE(ah, AR_RXCFG, 3526 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 3527 else 3528 REG_WRITE(ah, AR_RXCFG, 3529 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 3530} 3531EXPORT_SYMBOL(ath9k_hw_setrxfilter); 3532 3533bool ath9k_hw_phy_disable(struct ath_hw *ah) 3534{ 3535 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 3536 return false; 3537 3538 ath9k_hw_init_pll(ah, NULL); 3539 return true; 3540} 3541EXPORT_SYMBOL(ath9k_hw_phy_disable); 3542 3543bool ath9k_hw_disable(struct ath_hw *ah) 3544{ 3545 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 3546 return false; 3547 3548 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 3549 return false; 3550 3551 ath9k_hw_init_pll(ah, NULL); 3552 return true; 3553} 3554EXPORT_SYMBOL(ath9k_hw_disable); 3555 3556void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 3557{ 3558 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 3559 struct ath9k_channel *chan = ah->curchan; 3560 struct ieee80211_channel *channel = chan->chan; 3561 3562 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 3563 3564 ah->eep_ops->set_txpower(ah, chan, 3565 ath9k_regd_get_ctl(regulatory, chan), 3566 channel->max_antenna_gain * 2, 3567 channel->max_power * 2, 3568 min((u32) MAX_RATE_POWER, 3569 (u32) regulatory->power_limit)); 3570} 3571EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 3572 3573void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) 3574{ 3575 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN); 3576} 3577EXPORT_SYMBOL(ath9k_hw_setmac); 3578 3579void ath9k_hw_setopmode(struct ath_hw *ah) 3580{ 3581 ath9k_hw_set_operating_mode(ah, ah->opmode); 3582} 3583EXPORT_SYMBOL(ath9k_hw_setopmode); 3584 3585void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 3586{ 3587 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 3588 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 3589} 3590EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 3591 3592void ath9k_hw_write_associd(struct ath_hw *ah) 3593{ 3594 struct ath_common *common = ath9k_hw_common(ah); 3595 3596 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 3597 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 3598 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 3599} 3600EXPORT_SYMBOL(ath9k_hw_write_associd); 3601 3602u64 ath9k_hw_gettsf64(struct ath_hw *ah) 3603{ 3604 u64 tsf; 3605 3606 tsf = REG_READ(ah, AR_TSF_U32); 3607 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); 3608 3609 return tsf; 3610} 3611EXPORT_SYMBOL(ath9k_hw_gettsf64); 3612 3613void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 3614{ 3615 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3616 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3617} 3618EXPORT_SYMBOL(ath9k_hw_settsf64); 3619 3620void ath9k_hw_reset_tsf(struct ath_hw *ah) 3621{ 3622 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 3623 AH_TSF_WRITE_TIMEOUT)) 3624 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 3625 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 3626 3627 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3628} 3629EXPORT_SYMBOL(ath9k_hw_reset_tsf); 3630 3631void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 3632{ 3633 if (setting) 3634 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 3635 else 3636 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 3637} 3638EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 3639 3640/* 3641 * Extend 15-bit time stamp from rx descriptor to 3642 * a full 64-bit TSF using the current h/w TSF. 3643*/ 3644u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp) 3645{ 3646 u64 tsf; 3647 3648 tsf = ath9k_hw_gettsf64(ah); 3649 if ((tsf & 0x7fff) < rstamp) 3650 tsf -= 0x8000; 3651 return (tsf & ~0x7fff) | rstamp; 3652} 3653EXPORT_SYMBOL(ath9k_hw_extend_tsf); 3654 3655void ath9k_hw_set11nmac2040(struct ath_hw *ah) 3656{ 3657 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 3658 u32 macmode; 3659 3660 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 3661 macmode = AR_2040_JOINED_RX_CLEAR; 3662 else 3663 macmode = 0; 3664 3665 REG_WRITE(ah, AR_2040_MODE, macmode); 3666} 3667 3668/* HW Generic timers configuration */ 3669 3670static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 3671{ 3672 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3673 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3674 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3675 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3676 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3677 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3678 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3679 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3680 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 3681 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 3682 AR_NDP2_TIMER_MODE, 0x0002}, 3683 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 3684 AR_NDP2_TIMER_MODE, 0x0004}, 3685 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 3686 AR_NDP2_TIMER_MODE, 0x0008}, 3687 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 3688 AR_NDP2_TIMER_MODE, 0x0010}, 3689 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 3690 AR_NDP2_TIMER_MODE, 0x0020}, 3691 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 3692 AR_NDP2_TIMER_MODE, 0x0040}, 3693 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 3694 AR_NDP2_TIMER_MODE, 0x0080} 3695}; 3696 3697/* HW generic timer primitives */ 3698 3699/* compute and clear index of rightmost 1 */ 3700static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 3701{ 3702 u32 b; 3703 3704 b = *mask; 3705 b &= (0-b); 3706 *mask &= ~b; 3707 b *= debruijn32; 3708 b >>= 27; 3709 3710 return timer_table->gen_timer_index[b]; 3711} 3712 3713u32 ath9k_hw_gettsf32(struct ath_hw *ah) 3714{ 3715 return REG_READ(ah, AR_TSF_L32); 3716} 3717EXPORT_SYMBOL(ath9k_hw_gettsf32); 3718 3719struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3720 void (*trigger)(void *), 3721 void (*overflow)(void *), 3722 void *arg, 3723 u8 timer_index) 3724{ 3725 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3726 struct ath_gen_timer *timer; 3727 3728 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3729 3730 if (timer == NULL) { 3731 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 3732 "Failed to allocate memory" 3733 "for hw timer[%d]\n", timer_index); 3734 return NULL; 3735 } 3736 3737 /* allocate a hardware generic timer slot */ 3738 timer_table->timers[timer_index] = timer; 3739 timer->index = timer_index; 3740 timer->trigger = trigger; 3741 timer->overflow = overflow; 3742 timer->arg = arg; 3743 3744 return timer; 3745} 3746EXPORT_SYMBOL(ath_gen_timer_alloc); 3747 3748void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3749 struct ath_gen_timer *timer, 3750 u32 timer_next, 3751 u32 timer_period) 3752{ 3753 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3754 u32 tsf; 3755 3756 BUG_ON(!timer_period); 3757 3758 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 3759 3760 tsf = ath9k_hw_gettsf32(ah); 3761 3762 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 3763 "curent tsf %x period %x" 3764 "timer_next %x\n", tsf, timer_period, timer_next); 3765 3766 /* 3767 * Pull timer_next forward if the current TSF already passed it 3768 * because of software latency 3769 */ 3770 if (timer_next < tsf) 3771 timer_next = tsf + timer_period; 3772 3773 /* 3774 * Program generic timer registers 3775 */ 3776 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3777 timer_next); 3778 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3779 timer_period); 3780 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3781 gen_tmr_configuration[timer->index].mode_mask); 3782 3783 /* Enable both trigger and thresh interrupt masks */ 3784 REG_SET_BIT(ah, AR_IMR_S5, 3785 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3786 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3787} 3788EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3789 3790void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3791{ 3792 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3793 3794 if ((timer->index < AR_FIRST_NDP_TIMER) || 3795 (timer->index >= ATH_MAX_GEN_TIMER)) { 3796 return; 3797 } 3798 3799 /* Clear generic timer enable bits. */ 3800 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3801 gen_tmr_configuration[timer->index].mode_mask); 3802 3803 /* Disable both trigger and thresh interrupt masks */ 3804 REG_CLR_BIT(ah, AR_IMR_S5, 3805 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3806 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3807 3808 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3809} 3810EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3811 3812void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3813{ 3814 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3815 3816 /* free the hardware generic timer slot */ 3817 timer_table->timers[timer->index] = NULL; 3818 kfree(timer); 3819} 3820EXPORT_SYMBOL(ath_gen_timer_free); 3821 3822/* 3823 * Generic Timer Interrupts handling 3824 */ 3825void ath_gen_timer_isr(struct ath_hw *ah) 3826{ 3827 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3828 struct ath_gen_timer *timer; 3829 struct ath_common *common = ath9k_hw_common(ah); 3830 u32 trigger_mask, thresh_mask, index; 3831 3832 /* get hardware generic timer interrupt status */ 3833 trigger_mask = ah->intr_gen_timer_trigger; 3834 thresh_mask = ah->intr_gen_timer_thresh; 3835 trigger_mask &= timer_table->timer_mask.val; 3836 thresh_mask &= timer_table->timer_mask.val; 3837 3838 trigger_mask &= ~thresh_mask; 3839 3840 while (thresh_mask) { 3841 index = rightmost_index(timer_table, &thresh_mask); 3842 timer = timer_table->timers[index]; 3843 BUG_ON(!timer); 3844 ath_print(common, ATH_DBG_HWTIMER, 3845 "TSF overflow for Gen timer %d\n", index); 3846 timer->overflow(timer->arg); 3847 } 3848 3849 while (trigger_mask) { 3850 index = rightmost_index(timer_table, &trigger_mask); 3851 timer = timer_table->timers[index]; 3852 BUG_ON(!timer); 3853 ath_print(common, ATH_DBG_HWTIMER, 3854 "Gen timer[%d] trigger\n", index); 3855 timer->trigger(timer->arg); 3856 } 3857} 3858EXPORT_SYMBOL(ath_gen_timer_isr); 3859 3860/********/ 3861/* HTC */ 3862/********/ 3863 3864void ath9k_hw_htc_resetinit(struct ath_hw *ah) 3865{ 3866 ah->htc_reset_init = true; 3867} 3868EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 3869 3870static struct { 3871 u32 version; 3872 const char * name; 3873} ath_mac_bb_names[] = { 3874 /* Devices with external radios */ 3875 { AR_SREV_VERSION_5416_PCI, "5416" }, 3876 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3877 { AR_SREV_VERSION_9100, "9100" }, 3878 { AR_SREV_VERSION_9160, "9160" }, 3879 /* Single-chip solutions */ 3880 { AR_SREV_VERSION_9280, "9280" }, 3881 { AR_SREV_VERSION_9285, "9285" }, 3882 { AR_SREV_VERSION_9287, "9287" }, 3883 { AR_SREV_VERSION_9271, "9271" }, 3884}; 3885 3886/* For devices with external radios */ 3887static struct { 3888 u16 version; 3889 const char * name; 3890} ath_rf_names[] = { 3891 { 0, "5133" }, 3892 { AR_RAD5133_SREV_MAJOR, "5133" }, 3893 { AR_RAD5122_SREV_MAJOR, "5122" }, 3894 { AR_RAD2133_SREV_MAJOR, "2133" }, 3895 { AR_RAD2122_SREV_MAJOR, "2122" } 3896}; 3897 3898/* 3899 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3900 */ 3901static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3902{ 3903 int i; 3904 3905 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3906 if (ath_mac_bb_names[i].version == mac_bb_version) { 3907 return ath_mac_bb_names[i].name; 3908 } 3909 } 3910 3911 return "????"; 3912} 3913 3914/* 3915 * Return the RF name. "????" is returned if the RF is unknown. 3916 * Used for devices with external radios. 3917 */ 3918static const char *ath9k_hw_rf_name(u16 rf_version) 3919{ 3920 int i; 3921 3922 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3923 if (ath_rf_names[i].version == rf_version) { 3924 return ath_rf_names[i].name; 3925 } 3926 } 3927 3928 return "????"; 3929} 3930 3931void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3932{ 3933 int used; 3934 3935 /* chipsets >= AR9280 are single-chip */ 3936 if (AR_SREV_9280_10_OR_LATER(ah)) { 3937 used = snprintf(hw_name, len, 3938 "Atheros AR%s Rev:%x", 3939 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3940 ah->hw_version.macRev); 3941 } 3942 else { 3943 used = snprintf(hw_name, len, 3944 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3945 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3946 ah->hw_version.macRev, 3947 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3948 AR_RADIO_SREV_MAJOR)), 3949 ah->hw_version.phyRev); 3950 } 3951 3952 hw_name[used] = '\0'; 3953} 3954EXPORT_SYMBOL(ath9k_hw_name); 3955