dhd_sdio.c revision 8a385ba542dd6d20e3067d486f5f75ff71baa4db
1/* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/types.h> 18#include <linux/kernel.h> 19#include <linux/kthread.h> 20#include <linux/printk.h> 21#include <linux/pci_ids.h> 22#include <linux/netdevice.h> 23#include <linux/interrupt.h> 24#include <linux/sched.h> 25#include <linux/mmc/sdio.h> 26#include <linux/mmc/sdio_ids.h> 27#include <linux/mmc/sdio_func.h> 28#include <linux/mmc/card.h> 29#include <linux/semaphore.h> 30#include <linux/firmware.h> 31#include <linux/module.h> 32#include <linux/bcma/bcma.h> 33#include <linux/debugfs.h> 34#include <linux/vmalloc.h> 35#include <linux/platform_data/brcmfmac-sdio.h> 36#include <linux/moduleparam.h> 37#include <asm/unaligned.h> 38#include <defs.h> 39#include <brcmu_wifi.h> 40#include <brcmu_utils.h> 41#include <brcm_hw_ids.h> 42#include <soc.h> 43#include "sdio_host.h" 44#include "chip.h" 45#include "nvram.h" 46 47#define DCMD_RESP_TIMEOUT 2000 /* In milli second */ 48 49#ifdef DEBUG 50 51#define BRCMF_TRAP_INFO_SIZE 80 52 53#define CBUF_LEN (128) 54 55/* Device console log buffer state */ 56#define CONSOLE_BUFFER_MAX 2024 57 58struct rte_log_le { 59 __le32 buf; /* Can't be pointer on (64-bit) hosts */ 60 __le32 buf_size; 61 __le32 idx; 62 char *_buf_compat; /* Redundant pointer for backward compat. */ 63}; 64 65struct rte_console { 66 /* Virtual UART 67 * When there is no UART (e.g. Quickturn), 68 * the host should write a complete 69 * input line directly into cbuf and then write 70 * the length into vcons_in. 71 * This may also be used when there is a real UART 72 * (at risk of conflicting with 73 * the real UART). vcons_out is currently unused. 74 */ 75 uint vcons_in; 76 uint vcons_out; 77 78 /* Output (logging) buffer 79 * Console output is written to a ring buffer log_buf at index log_idx. 80 * The host may read the output when it sees log_idx advance. 81 * Output will be lost if the output wraps around faster than the host 82 * polls. 83 */ 84 struct rte_log_le log_le; 85 86 /* Console input line buffer 87 * Characters are read one at a time into cbuf 88 * until <CR> is received, then 89 * the buffer is processed as a command line. 90 * Also used for virtual UART. 91 */ 92 uint cbuf_idx; 93 char cbuf[CBUF_LEN]; 94}; 95 96#endif /* DEBUG */ 97#include <chipcommon.h> 98 99#include "dhd_bus.h" 100#include "dhd_dbg.h" 101#include "tracepoint.h" 102 103#define TXQLEN 2048 /* bulk tx queue length */ 104#define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ 105#define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ 106#define PRIOMASK 7 107 108#define TXRETRIES 2 /* # of retries for tx frames */ 109 110#define BRCMF_RXBOUND 50 /* Default for max rx frames in 111 one scheduling */ 112 113#define BRCMF_TXBOUND 20 /* Default for max tx frames in 114 one scheduling */ 115 116#define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ 117 118#define MEMBLOCK 2048 /* Block size used for downloading 119 of dongle image */ 120#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold 121 biggest possible glom */ 122 123#define BRCMF_FIRSTREAD (1 << 6) 124 125 126/* SBSDIO_DEVICE_CTL */ 127 128/* 1: device will assert busy signal when receiving CMD53 */ 129#define SBSDIO_DEVCTL_SETBUSY 0x01 130/* 1: assertion of sdio interrupt is synchronous to the sdio clock */ 131#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 132/* 1: mask all interrupts to host except the chipActive (rev 8) */ 133#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 134/* 1: isolate internal sdio signals, put external pads in tri-state; requires 135 * sdio bus power cycle to clear (rev 9) */ 136#define SBSDIO_DEVCTL_PADS_ISO 0x08 137/* Force SD->SB reset mapping (rev 11) */ 138#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 139/* Determined by CoreControl bit */ 140#define SBSDIO_DEVCTL_RST_CORECTL 0x00 141/* Force backplane reset */ 142#define SBSDIO_DEVCTL_RST_BPRESET 0x10 143/* Force no backplane reset */ 144#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 145 146/* direct(mapped) cis space */ 147 148/* MAPPED common CIS address */ 149#define SBSDIO_CIS_BASE_COMMON 0x1000 150/* maximum bytes in one CIS */ 151#define SBSDIO_CIS_SIZE_LIMIT 0x200 152/* cis offset addr is < 17 bits */ 153#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF 154 155/* manfid tuple length, include tuple, link bytes */ 156#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 157 158#define CORE_BUS_REG(base, field) \ 159 (base + offsetof(struct sdpcmd_regs, field)) 160 161/* SDIO function 1 register CHIPCLKCSR */ 162/* Force ALP request to backplane */ 163#define SBSDIO_FORCE_ALP 0x01 164/* Force HT request to backplane */ 165#define SBSDIO_FORCE_HT 0x02 166/* Force ILP request to backplane */ 167#define SBSDIO_FORCE_ILP 0x04 168/* Make ALP ready (power up xtal) */ 169#define SBSDIO_ALP_AVAIL_REQ 0x08 170/* Make HT ready (power up PLL) */ 171#define SBSDIO_HT_AVAIL_REQ 0x10 172/* Squelch clock requests from HW */ 173#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 174/* Status: ALP is ready */ 175#define SBSDIO_ALP_AVAIL 0x40 176/* Status: HT is ready */ 177#define SBSDIO_HT_AVAIL 0x80 178#define SBSDIO_CSR_MASK 0x1F 179#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 180#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 181#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 182#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 183#define SBSDIO_CLKAV(regval, alponly) \ 184 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) 185 186/* intstatus */ 187#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 188#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 189#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 190#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 191#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 192#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 193#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 194#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 195#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 196#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 197#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 198#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 199#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 200#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 201#define I_PC (1 << 10) /* descriptor error */ 202#define I_PD (1 << 11) /* data error */ 203#define I_DE (1 << 12) /* Descriptor protocol Error */ 204#define I_RU (1 << 13) /* Receive descriptor Underflow */ 205#define I_RO (1 << 14) /* Receive fifo Overflow */ 206#define I_XU (1 << 15) /* Transmit fifo Underflow */ 207#define I_RI (1 << 16) /* Receive Interrupt */ 208#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 209#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 210#define I_XI (1 << 24) /* Transmit Interrupt */ 211#define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 212#define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 213#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 214#define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 215#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ 216#define I_SRESET (1 << 30) /* CCCR RES interrupt */ 217#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 218#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) 219#define I_DMA (I_RI | I_XI | I_ERRORS) 220 221/* corecontrol */ 222#define CC_CISRDY (1 << 0) /* CIS Ready */ 223#define CC_BPRESEN (1 << 1) /* CCCR RES signal */ 224#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 225#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ 226#define CC_XMTDATAAVAIL_MODE (1 << 4) 227#define CC_XMTDATAAVAIL_CTRL (1 << 5) 228 229/* SDA_FRAMECTRL */ 230#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 231#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 232#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ 233#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ 234 235/* 236 * Software allocation of To SB Mailbox resources 237 */ 238 239/* tosbmailbox bits corresponding to intstatus bits */ 240#define SMB_NAK (1 << 0) /* Frame NAK */ 241#define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ 242#define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ 243#define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ 244 245/* tosbmailboxdata */ 246#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ 247 248/* 249 * Software allocation of To Host Mailbox resources 250 */ 251 252/* intstatus bits */ 253#define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ 254#define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ 255#define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ 256#define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ 257 258/* tohostmailboxdata */ 259#define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ 260#define HMB_DATA_DEVREADY 2 /* talk to host after enable */ 261#define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ 262#define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ 263 264#define HMB_DATA_FCDATA_MASK 0xff000000 265#define HMB_DATA_FCDATA_SHIFT 24 266 267#define HMB_DATA_VERSION_MASK 0x00ff0000 268#define HMB_DATA_VERSION_SHIFT 16 269 270/* 271 * Software-defined protocol header 272 */ 273 274/* Current protocol version */ 275#define SDPCM_PROT_VERSION 4 276 277/* 278 * Shared structure between dongle and the host. 279 * The structure contains pointers to trap or assert information. 280 */ 281#define SDPCM_SHARED_VERSION 0x0003 282#define SDPCM_SHARED_VERSION_MASK 0x00FF 283#define SDPCM_SHARED_ASSERT_BUILT 0x0100 284#define SDPCM_SHARED_ASSERT 0x0200 285#define SDPCM_SHARED_TRAP 0x0400 286 287/* Space for header read, limit for data packets */ 288#define MAX_HDR_READ (1 << 6) 289#define MAX_RX_DATASZ 2048 290 291/* Bump up limit on waiting for HT to account for first startup; 292 * if the image is doing a CRC calculation before programming the PMU 293 * for HT availability, it could take a couple hundred ms more, so 294 * max out at a 1 second (1000000us). 295 */ 296#undef PMU_MAX_TRANSITION_DLY 297#define PMU_MAX_TRANSITION_DLY 1000000 298 299/* Value for ChipClockCSR during initial setup */ 300#define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ 301 SBSDIO_ALP_AVAIL_REQ) 302 303/* Flags for SDH calls */ 304#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) 305 306#define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change 307 * when idle 308 */ 309#define BRCMF_IDLE_INTERVAL 1 310 311#define KSO_WAIT_US 50 312#define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) 313 314/* 315 * Conversion of 802.1D priority to precedence level 316 */ 317static uint prio2prec(u32 prio) 318{ 319 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? 320 (prio^2) : prio; 321} 322 323#ifdef DEBUG 324/* Device console log buffer state */ 325struct brcmf_console { 326 uint count; /* Poll interval msec counter */ 327 uint log_addr; /* Log struct address (fixed) */ 328 struct rte_log_le log_le; /* Log struct (host copy) */ 329 uint bufsize; /* Size of log buffer */ 330 u8 *buf; /* Log buffer (host copy) */ 331 uint last; /* Last buffer read index */ 332}; 333 334struct brcmf_trap_info { 335 __le32 type; 336 __le32 epc; 337 __le32 cpsr; 338 __le32 spsr; 339 __le32 r0; /* a1 */ 340 __le32 r1; /* a2 */ 341 __le32 r2; /* a3 */ 342 __le32 r3; /* a4 */ 343 __le32 r4; /* v1 */ 344 __le32 r5; /* v2 */ 345 __le32 r6; /* v3 */ 346 __le32 r7; /* v4 */ 347 __le32 r8; /* v5 */ 348 __le32 r9; /* sb/v6 */ 349 __le32 r10; /* sl/v7 */ 350 __le32 r11; /* fp/v8 */ 351 __le32 r12; /* ip */ 352 __le32 r13; /* sp */ 353 __le32 r14; /* lr */ 354 __le32 pc; /* r15 */ 355}; 356#endif /* DEBUG */ 357 358struct sdpcm_shared { 359 u32 flags; 360 u32 trap_addr; 361 u32 assert_exp_addr; 362 u32 assert_file_addr; 363 u32 assert_line; 364 u32 console_addr; /* Address of struct rte_console */ 365 u32 msgtrace_addr; 366 u8 tag[32]; 367 u32 brpt_addr; 368}; 369 370struct sdpcm_shared_le { 371 __le32 flags; 372 __le32 trap_addr; 373 __le32 assert_exp_addr; 374 __le32 assert_file_addr; 375 __le32 assert_line; 376 __le32 console_addr; /* Address of struct rte_console */ 377 __le32 msgtrace_addr; 378 u8 tag[32]; 379 __le32 brpt_addr; 380}; 381 382/* dongle SDIO bus specific header info */ 383struct brcmf_sdio_hdrinfo { 384 u8 seq_num; 385 u8 channel; 386 u16 len; 387 u16 len_left; 388 u16 len_nxtfrm; 389 u8 dat_offset; 390 bool lastfrm; 391 u16 tail_pad; 392}; 393 394/* misc chip info needed by some of the routines */ 395/* Private data for SDIO bus interaction */ 396struct brcmf_sdio { 397 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ 398 struct brcmf_chip *ci; /* Chip info struct */ 399 400 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */ 401 402 u32 hostintmask; /* Copy of Host Interrupt Mask */ 403 atomic_t intstatus; /* Intstatus bits (events) pending */ 404 atomic_t fcstate; /* State of dongle flow-control */ 405 406 uint blocksize; /* Block size of SDIO transfers */ 407 uint roundup; /* Max roundup limit */ 408 409 struct pktq txq; /* Queue length used for flow-control */ 410 u8 flowcontrol; /* per prio flow control bitmask */ 411 u8 tx_seq; /* Transmit sequence number (next) */ 412 u8 tx_max; /* Maximum transmit sequence allowed */ 413 414 u8 *hdrbuf; /* buffer for handling rx frame */ 415 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ 416 u8 rx_seq; /* Receive sequence number (expected) */ 417 struct brcmf_sdio_hdrinfo cur_read; 418 /* info of current read frame */ 419 bool rxskip; /* Skip receive (awaiting NAK ACK) */ 420 bool rxpending; /* Data frame pending in dongle */ 421 422 uint rxbound; /* Rx frames to read before resched */ 423 uint txbound; /* Tx frames to send before resched */ 424 uint txminmax; 425 426 struct sk_buff *glomd; /* Packet containing glomming descriptor */ 427 struct sk_buff_head glom; /* Packet list for glommed superframe */ 428 uint glomerr; /* Glom packet read errors */ 429 430 u8 *rxbuf; /* Buffer for receiving control packets */ 431 uint rxblen; /* Allocated length of rxbuf */ 432 u8 *rxctl; /* Aligned pointer into rxbuf */ 433 u8 *rxctl_orig; /* pointer for freeing rxctl */ 434 uint rxlen; /* Length of valid data in buffer */ 435 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ 436 437 u8 sdpcm_ver; /* Bus protocol reported by dongle */ 438 439 bool intr; /* Use interrupts */ 440 bool poll; /* Use polling */ 441 atomic_t ipend; /* Device interrupt is pending */ 442 uint spurious; /* Count of spurious interrupts */ 443 uint pollrate; /* Ticks between device polls */ 444 uint polltick; /* Tick counter */ 445 446#ifdef DEBUG 447 uint console_interval; 448 struct brcmf_console console; /* Console output polling support */ 449 uint console_addr; /* Console address from shared struct */ 450#endif /* DEBUG */ 451 452 uint clkstate; /* State of sd and backplane clock(s) */ 453 bool activity; /* Activity flag for clock down */ 454 s32 idletime; /* Control for activity timeout */ 455 s32 idlecount; /* Activity timeout counter */ 456 s32 idleclock; /* How to set bus driver when idle */ 457 bool rxflow_mode; /* Rx flow control mode */ 458 bool rxflow; /* Is rx flow control on */ 459 bool alp_only; /* Don't use HT clock (ALP only) */ 460 461 u8 *ctrl_frame_buf; 462 u16 ctrl_frame_len; 463 bool ctrl_frame_stat; 464 465 spinlock_t txq_lock; /* protect bus->txq */ 466 struct semaphore tx_seq_lock; /* protect bus->tx_seq */ 467 wait_queue_head_t ctrl_wait; 468 wait_queue_head_t dcmd_resp_wait; 469 470 struct timer_list timer; 471 struct completion watchdog_wait; 472 struct task_struct *watchdog_tsk; 473 bool wd_timer_valid; 474 uint save_ms; 475 476 struct workqueue_struct *brcmf_wq; 477 struct work_struct datawork; 478 atomic_t dpc_tskcnt; 479 480 bool txoff; /* Transmit flow-controlled */ 481 struct brcmf_sdio_count sdcnt; 482 bool sr_enabled; /* SaveRestore enabled */ 483 bool sleeping; /* SDIO bus sleeping */ 484 485 u8 tx_hdrlen; /* sdio bus header length for tx packet */ 486 bool txglom; /* host tx glomming enable flag */ 487 u16 head_align; /* buffer pointer alignment */ 488 u16 sgentry_align; /* scatter-gather buffer alignment */ 489}; 490 491/* clkstate */ 492#define CLK_NONE 0 493#define CLK_SDONLY 1 494#define CLK_PENDING 2 495#define CLK_AVAIL 3 496 497#ifdef DEBUG 498static int qcount[NUMPRIO]; 499#endif /* DEBUG */ 500 501#define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ 502 503#define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) 504 505/* Retry count for register access failures */ 506static const uint retry_limit = 2; 507 508/* Limit on rounding up frames */ 509static const uint max_roundup = 512; 510 511#define ALIGNMENT 4 512 513enum brcmf_sdio_frmtype { 514 BRCMF_SDIO_FT_NORMAL, 515 BRCMF_SDIO_FT_SUPER, 516 BRCMF_SDIO_FT_SUB, 517}; 518 519#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) 520 521/* SDIO Pad drive strength to select value mappings */ 522struct sdiod_drive_str { 523 u8 strength; /* Pad Drive Strength in mA */ 524 u8 sel; /* Chip-specific select value */ 525}; 526 527/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ 528static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { 529 {32, 0x6}, 530 {26, 0x7}, 531 {22, 0x4}, 532 {16, 0x5}, 533 {12, 0x2}, 534 {8, 0x3}, 535 {4, 0x0}, 536 {0, 0x1} 537}; 538 539/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ 540static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { 541 {6, 0x7}, 542 {5, 0x6}, 543 {4, 0x5}, 544 {3, 0x4}, 545 {2, 0x2}, 546 {1, 0x1}, 547 {0, 0x0} 548}; 549 550/* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ 551static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { 552 {3, 0x3}, 553 {2, 0x2}, 554 {1, 0x1}, 555 {0, 0x0} }; 556 557/* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ 558static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { 559 {16, 0x7}, 560 {12, 0x5}, 561 {8, 0x3}, 562 {4, 0x1} 563}; 564 565#define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin" 566#define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt" 567#define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin" 568#define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt" 569#define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin" 570#define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt" 571#define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin" 572#define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt" 573#define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin" 574#define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt" 575#define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin" 576#define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt" 577#define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin" 578#define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt" 579#define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin" 580#define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt" 581#define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin" 582#define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt" 583#define BCM4354_FIRMWARE_NAME "brcm/brcmfmac4354-sdio.bin" 584#define BCM4354_NVRAM_NAME "brcm/brcmfmac4354-sdio.txt" 585 586MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME); 587MODULE_FIRMWARE(BCM43143_NVRAM_NAME); 588MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME); 589MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME); 590MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME); 591MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME); 592MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME); 593MODULE_FIRMWARE(BCM4329_NVRAM_NAME); 594MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME); 595MODULE_FIRMWARE(BCM4330_NVRAM_NAME); 596MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME); 597MODULE_FIRMWARE(BCM4334_NVRAM_NAME); 598MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME); 599MODULE_FIRMWARE(BCM4335_NVRAM_NAME); 600MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME); 601MODULE_FIRMWARE(BCM43362_NVRAM_NAME); 602MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME); 603MODULE_FIRMWARE(BCM4339_NVRAM_NAME); 604MODULE_FIRMWARE(BCM4354_FIRMWARE_NAME); 605MODULE_FIRMWARE(BCM4354_NVRAM_NAME); 606 607struct brcmf_firmware_names { 608 u32 chipid; 609 u32 revmsk; 610 const char *bin; 611 const char *nv; 612}; 613 614enum brcmf_firmware_type { 615 BRCMF_FIRMWARE_BIN, 616 BRCMF_FIRMWARE_NVRAM 617}; 618 619#define BRCMF_FIRMWARE_NVRAM(name) \ 620 name ## _FIRMWARE_NAME, name ## _NVRAM_NAME 621 622static const struct brcmf_firmware_names brcmf_fwname_data[] = { 623 { BCM43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) }, 624 { BCM43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) }, 625 { BCM43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) }, 626 { BCM4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) }, 627 { BCM4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) }, 628 { BCM4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) }, 629 { BCM4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) }, 630 { BCM43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) }, 631 { BCM4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) }, 632 { BCM4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) } 633}; 634 635 636static const struct firmware *brcmf_sdio_get_fw(struct brcmf_sdio *bus, 637 enum brcmf_firmware_type type) 638{ 639 const struct firmware *fw; 640 const char *name; 641 int err, i; 642 643 for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) { 644 if (brcmf_fwname_data[i].chipid == bus->ci->chip && 645 brcmf_fwname_data[i].revmsk & BIT(bus->ci->chiprev)) { 646 switch (type) { 647 case BRCMF_FIRMWARE_BIN: 648 name = brcmf_fwname_data[i].bin; 649 break; 650 case BRCMF_FIRMWARE_NVRAM: 651 name = brcmf_fwname_data[i].nv; 652 break; 653 default: 654 brcmf_err("invalid firmware type (%d)\n", type); 655 return NULL; 656 } 657 goto found; 658 } 659 } 660 brcmf_err("Unknown chipid %d [%d]\n", 661 bus->ci->chip, bus->ci->chiprev); 662 return NULL; 663 664found: 665 err = request_firmware(&fw, name, &bus->sdiodev->func[2]->dev); 666 if ((err) || (!fw)) { 667 brcmf_err("fail to request firmware %s (%d)\n", name, err); 668 return NULL; 669 } 670 671 return fw; 672} 673 674static void pkt_align(struct sk_buff *p, int len, int align) 675{ 676 uint datalign; 677 datalign = (unsigned long)(p->data); 678 datalign = roundup(datalign, (align)) - datalign; 679 if (datalign) 680 skb_pull(p, datalign); 681 __skb_trim(p, len); 682} 683 684/* To check if there's window offered */ 685static bool data_ok(struct brcmf_sdio *bus) 686{ 687 return (u8)(bus->tx_max - bus->tx_seq) != 0 && 688 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; 689} 690 691/* 692 * Reads a register in the SDIO hardware block. This block occupies a series of 693 * adresses on the 32 bit backplane bus. 694 */ 695static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset) 696{ 697 struct brcmf_core *core; 698 int ret; 699 700 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); 701 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret); 702 703 return ret; 704} 705 706static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) 707{ 708 struct brcmf_core *core; 709 int ret; 710 711 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); 712 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret); 713 714 return ret; 715} 716 717static int 718brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) 719{ 720 u8 wr_val = 0, rd_val, cmp_val, bmask; 721 int err = 0; 722 int try_cnt = 0; 723 724 brcmf_dbg(TRACE, "Enter: on=%d\n", on); 725 726 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 727 /* 1st KSO write goes to AOS wake up core if device is asleep */ 728 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 729 wr_val, &err); 730 731 if (on) { 732 /* device WAKEUP through KSO: 733 * write bit 0 & read back until 734 * both bits 0 (kso bit) & 1 (dev on status) are set 735 */ 736 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | 737 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; 738 bmask = cmp_val; 739 usleep_range(2000, 3000); 740 } else { 741 /* Put device to sleep, turn off KSO */ 742 cmp_val = 0; 743 /* only check for bit0, bit1(dev on status) may not 744 * get cleared right away 745 */ 746 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; 747 } 748 749 do { 750 /* reliable KSO bit set/clr: 751 * the sdiod sleep write access is synced to PMU 32khz clk 752 * just one write attempt may fail, 753 * read it back until it matches written value 754 */ 755 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 756 &err); 757 if (((rd_val & bmask) == cmp_val) && !err) 758 break; 759 760 udelay(KSO_WAIT_US); 761 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 762 wr_val, &err); 763 } while (try_cnt++ < MAX_KSO_ATTEMPTS); 764 765 if (try_cnt > 2) 766 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, 767 rd_val, err); 768 769 if (try_cnt > MAX_KSO_ATTEMPTS) 770 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); 771 772 return err; 773} 774 775#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) 776 777/* Turn backplane clock on or off */ 778static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) 779{ 780 int err; 781 u8 clkctl, clkreq, devctl; 782 unsigned long timeout; 783 784 brcmf_dbg(SDIO, "Enter\n"); 785 786 clkctl = 0; 787 788 if (bus->sr_enabled) { 789 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); 790 return 0; 791 } 792 793 if (on) { 794 /* Request HT Avail */ 795 clkreq = 796 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; 797 798 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 799 clkreq, &err); 800 if (err) { 801 brcmf_err("HT Avail request error: %d\n", err); 802 return -EBADE; 803 } 804 805 /* Check current status */ 806 clkctl = brcmf_sdiod_regrb(bus->sdiodev, 807 SBSDIO_FUNC1_CHIPCLKCSR, &err); 808 if (err) { 809 brcmf_err("HT Avail read error: %d\n", err); 810 return -EBADE; 811 } 812 813 /* Go to pending and await interrupt if appropriate */ 814 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { 815 /* Allow only clock-available interrupt */ 816 devctl = brcmf_sdiod_regrb(bus->sdiodev, 817 SBSDIO_DEVICE_CTL, &err); 818 if (err) { 819 brcmf_err("Devctl error setting CA: %d\n", 820 err); 821 return -EBADE; 822 } 823 824 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; 825 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, 826 devctl, &err); 827 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); 828 bus->clkstate = CLK_PENDING; 829 830 return 0; 831 } else if (bus->clkstate == CLK_PENDING) { 832 /* Cancel CA-only interrupt filter */ 833 devctl = brcmf_sdiod_regrb(bus->sdiodev, 834 SBSDIO_DEVICE_CTL, &err); 835 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 836 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, 837 devctl, &err); 838 } 839 840 /* Otherwise, wait here (polling) for HT Avail */ 841 timeout = jiffies + 842 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); 843 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 844 clkctl = brcmf_sdiod_regrb(bus->sdiodev, 845 SBSDIO_FUNC1_CHIPCLKCSR, 846 &err); 847 if (time_after(jiffies, timeout)) 848 break; 849 else 850 usleep_range(5000, 10000); 851 } 852 if (err) { 853 brcmf_err("HT Avail request error: %d\n", err); 854 return -EBADE; 855 } 856 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 857 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", 858 PMU_MAX_TRANSITION_DLY, clkctl); 859 return -EBADE; 860 } 861 862 /* Mark clock available */ 863 bus->clkstate = CLK_AVAIL; 864 brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); 865 866#if defined(DEBUG) 867 if (!bus->alp_only) { 868 if (SBSDIO_ALPONLY(clkctl)) 869 brcmf_err("HT Clock should be on\n"); 870 } 871#endif /* defined (DEBUG) */ 872 873 } else { 874 clkreq = 0; 875 876 if (bus->clkstate == CLK_PENDING) { 877 /* Cancel CA-only interrupt filter */ 878 devctl = brcmf_sdiod_regrb(bus->sdiodev, 879 SBSDIO_DEVICE_CTL, &err); 880 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 881 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, 882 devctl, &err); 883 } 884 885 bus->clkstate = CLK_SDONLY; 886 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 887 clkreq, &err); 888 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); 889 if (err) { 890 brcmf_err("Failed access turning clock off: %d\n", 891 err); 892 return -EBADE; 893 } 894 } 895 return 0; 896} 897 898/* Change idle/active SD state */ 899static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) 900{ 901 brcmf_dbg(SDIO, "Enter\n"); 902 903 if (on) 904 bus->clkstate = CLK_SDONLY; 905 else 906 bus->clkstate = CLK_NONE; 907 908 return 0; 909} 910 911/* Transition SD and backplane clock readiness */ 912static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) 913{ 914#ifdef DEBUG 915 uint oldstate = bus->clkstate; 916#endif /* DEBUG */ 917 918 brcmf_dbg(SDIO, "Enter\n"); 919 920 /* Early exit if we're already there */ 921 if (bus->clkstate == target) { 922 if (target == CLK_AVAIL) { 923 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); 924 bus->activity = true; 925 } 926 return 0; 927 } 928 929 switch (target) { 930 case CLK_AVAIL: 931 /* Make sure SD clock is available */ 932 if (bus->clkstate == CLK_NONE) 933 brcmf_sdio_sdclk(bus, true); 934 /* Now request HT Avail on the backplane */ 935 brcmf_sdio_htclk(bus, true, pendok); 936 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); 937 bus->activity = true; 938 break; 939 940 case CLK_SDONLY: 941 /* Remove HT request, or bring up SD clock */ 942 if (bus->clkstate == CLK_NONE) 943 brcmf_sdio_sdclk(bus, true); 944 else if (bus->clkstate == CLK_AVAIL) 945 brcmf_sdio_htclk(bus, false, false); 946 else 947 brcmf_err("request for %d -> %d\n", 948 bus->clkstate, target); 949 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); 950 break; 951 952 case CLK_NONE: 953 /* Make sure to remove HT request */ 954 if (bus->clkstate == CLK_AVAIL) 955 brcmf_sdio_htclk(bus, false, false); 956 /* Now remove the SD clock */ 957 brcmf_sdio_sdclk(bus, false); 958 brcmf_sdio_wd_timer(bus, 0); 959 break; 960 } 961#ifdef DEBUG 962 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); 963#endif /* DEBUG */ 964 965 return 0; 966} 967 968static int 969brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) 970{ 971 int err = 0; 972 u8 clkcsr; 973 974 brcmf_dbg(SDIO, "Enter: request %s currently %s\n", 975 (sleep ? "SLEEP" : "WAKE"), 976 (bus->sleeping ? "SLEEP" : "WAKE")); 977 978 /* If SR is enabled control bus state with KSO */ 979 if (bus->sr_enabled) { 980 /* Done if we're already in the requested state */ 981 if (sleep == bus->sleeping) 982 goto end; 983 984 /* Going to sleep */ 985 if (sleep) { 986 /* Don't sleep if something is pending */ 987 if (atomic_read(&bus->intstatus) || 988 atomic_read(&bus->ipend) > 0 || 989 (!atomic_read(&bus->fcstate) && 990 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && 991 data_ok(bus))) { 992 err = -EBUSY; 993 goto done; 994 } 995 996 clkcsr = brcmf_sdiod_regrb(bus->sdiodev, 997 SBSDIO_FUNC1_CHIPCLKCSR, 998 &err); 999 if ((clkcsr & SBSDIO_CSR_MASK) == 0) { 1000 brcmf_dbg(SDIO, "no clock, set ALP\n"); 1001 brcmf_sdiod_regwb(bus->sdiodev, 1002 SBSDIO_FUNC1_CHIPCLKCSR, 1003 SBSDIO_ALP_AVAIL_REQ, &err); 1004 } 1005 err = brcmf_sdio_kso_control(bus, false); 1006 /* disable watchdog */ 1007 if (!err) 1008 brcmf_sdio_wd_timer(bus, 0); 1009 } else { 1010 bus->idlecount = 0; 1011 err = brcmf_sdio_kso_control(bus, true); 1012 } 1013 if (!err) { 1014 /* Change state */ 1015 bus->sleeping = sleep; 1016 brcmf_dbg(SDIO, "new state %s\n", 1017 (sleep ? "SLEEP" : "WAKE")); 1018 } else { 1019 brcmf_err("error while changing bus sleep state %d\n", 1020 err); 1021 goto done; 1022 } 1023 } 1024 1025end: 1026 /* control clocks */ 1027 if (sleep) { 1028 if (!bus->sr_enabled) 1029 brcmf_sdio_clkctl(bus, CLK_NONE, pendok); 1030 } else { 1031 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); 1032 } 1033done: 1034 brcmf_dbg(SDIO, "Exit: err=%d\n", err); 1035 return err; 1036 1037} 1038 1039#ifdef DEBUG 1040static inline bool brcmf_sdio_valid_shared_address(u32 addr) 1041{ 1042 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); 1043} 1044 1045static int brcmf_sdio_readshared(struct brcmf_sdio *bus, 1046 struct sdpcm_shared *sh) 1047{ 1048 u32 addr; 1049 int rv; 1050 u32 shaddr = 0; 1051 struct sdpcm_shared_le sh_le; 1052 __le32 addr_le; 1053 1054 shaddr = bus->ci->rambase + bus->ramsize - 4; 1055 1056 /* 1057 * Read last word in socram to determine 1058 * address of sdpcm_shared structure 1059 */ 1060 sdio_claim_host(bus->sdiodev->func[1]); 1061 brcmf_sdio_bus_sleep(bus, false, false); 1062 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4); 1063 sdio_release_host(bus->sdiodev->func[1]); 1064 if (rv < 0) 1065 return rv; 1066 1067 addr = le32_to_cpu(addr_le); 1068 1069 brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr); 1070 1071 /* 1072 * Check if addr is valid. 1073 * NVRAM length at the end of memory should have been overwritten. 1074 */ 1075 if (!brcmf_sdio_valid_shared_address(addr)) { 1076 brcmf_err("invalid sdpcm_shared address 0x%08X\n", 1077 addr); 1078 return -EINVAL; 1079 } 1080 1081 /* Read hndrte_shared structure */ 1082 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, 1083 sizeof(struct sdpcm_shared_le)); 1084 if (rv < 0) 1085 return rv; 1086 1087 /* Endianness */ 1088 sh->flags = le32_to_cpu(sh_le.flags); 1089 sh->trap_addr = le32_to_cpu(sh_le.trap_addr); 1090 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); 1091 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); 1092 sh->assert_line = le32_to_cpu(sh_le.assert_line); 1093 sh->console_addr = le32_to_cpu(sh_le.console_addr); 1094 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); 1095 1096 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { 1097 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", 1098 SDPCM_SHARED_VERSION, 1099 sh->flags & SDPCM_SHARED_VERSION_MASK); 1100 return -EPROTO; 1101 } 1102 1103 return 0; 1104} 1105 1106static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1107{ 1108 struct sdpcm_shared sh; 1109 1110 if (brcmf_sdio_readshared(bus, &sh) == 0) 1111 bus->console_addr = sh.console_addr; 1112} 1113#else 1114static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1115{ 1116} 1117#endif /* DEBUG */ 1118 1119static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) 1120{ 1121 u32 intstatus = 0; 1122 u32 hmb_data; 1123 u8 fcbits; 1124 int ret; 1125 1126 brcmf_dbg(SDIO, "Enter\n"); 1127 1128 /* Read mailbox data and ack that we did so */ 1129 ret = r_sdreg32(bus, &hmb_data, 1130 offsetof(struct sdpcmd_regs, tohostmailboxdata)); 1131 1132 if (ret == 0) 1133 w_sdreg32(bus, SMB_INT_ACK, 1134 offsetof(struct sdpcmd_regs, tosbmailbox)); 1135 bus->sdcnt.f1regdata += 2; 1136 1137 /* Dongle recomposed rx frames, accept them again */ 1138 if (hmb_data & HMB_DATA_NAKHANDLED) { 1139 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", 1140 bus->rx_seq); 1141 if (!bus->rxskip) 1142 brcmf_err("unexpected NAKHANDLED!\n"); 1143 1144 bus->rxskip = false; 1145 intstatus |= I_HMB_FRAME_IND; 1146 } 1147 1148 /* 1149 * DEVREADY does not occur with gSPI. 1150 */ 1151 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { 1152 bus->sdpcm_ver = 1153 (hmb_data & HMB_DATA_VERSION_MASK) >> 1154 HMB_DATA_VERSION_SHIFT; 1155 if (bus->sdpcm_ver != SDPCM_PROT_VERSION) 1156 brcmf_err("Version mismatch, dongle reports %d, " 1157 "expecting %d\n", 1158 bus->sdpcm_ver, SDPCM_PROT_VERSION); 1159 else 1160 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", 1161 bus->sdpcm_ver); 1162 1163 /* 1164 * Retrieve console state address now that firmware should have 1165 * updated it. 1166 */ 1167 brcmf_sdio_get_console_addr(bus); 1168 } 1169 1170 /* 1171 * Flow Control has been moved into the RX headers and this out of band 1172 * method isn't used any more. 1173 * remaining backward compatible with older dongles. 1174 */ 1175 if (hmb_data & HMB_DATA_FC) { 1176 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> 1177 HMB_DATA_FCDATA_SHIFT; 1178 1179 if (fcbits & ~bus->flowcontrol) 1180 bus->sdcnt.fc_xoff++; 1181 1182 if (bus->flowcontrol & ~fcbits) 1183 bus->sdcnt.fc_xon++; 1184 1185 bus->sdcnt.fc_rcvd++; 1186 bus->flowcontrol = fcbits; 1187 } 1188 1189 /* Shouldn't be any others */ 1190 if (hmb_data & ~(HMB_DATA_DEVREADY | 1191 HMB_DATA_NAKHANDLED | 1192 HMB_DATA_FC | 1193 HMB_DATA_FWREADY | 1194 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) 1195 brcmf_err("Unknown mailbox data content: 0x%02x\n", 1196 hmb_data); 1197 1198 return intstatus; 1199} 1200 1201static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) 1202{ 1203 uint retries = 0; 1204 u16 lastrbc; 1205 u8 hi, lo; 1206 int err; 1207 1208 brcmf_err("%sterminate frame%s\n", 1209 abort ? "abort command, " : "", 1210 rtx ? ", send NAK" : ""); 1211 1212 if (abort) 1213 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2); 1214 1215 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, 1216 SFC_RF_TERM, &err); 1217 bus->sdcnt.f1regdata++; 1218 1219 /* Wait until the packet has been flushed (device/FIFO stable) */ 1220 for (lastrbc = retries = 0xffff; retries > 0; retries--) { 1221 hi = brcmf_sdiod_regrb(bus->sdiodev, 1222 SBSDIO_FUNC1_RFRAMEBCHI, &err); 1223 lo = brcmf_sdiod_regrb(bus->sdiodev, 1224 SBSDIO_FUNC1_RFRAMEBCLO, &err); 1225 bus->sdcnt.f1regdata += 2; 1226 1227 if ((hi == 0) && (lo == 0)) 1228 break; 1229 1230 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { 1231 brcmf_err("count growing: last 0x%04x now 0x%04x\n", 1232 lastrbc, (hi << 8) + lo); 1233 } 1234 lastrbc = (hi << 8) + lo; 1235 } 1236 1237 if (!retries) 1238 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); 1239 else 1240 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); 1241 1242 if (rtx) { 1243 bus->sdcnt.rxrtx++; 1244 err = w_sdreg32(bus, SMB_NAK, 1245 offsetof(struct sdpcmd_regs, tosbmailbox)); 1246 1247 bus->sdcnt.f1regdata++; 1248 if (err == 0) 1249 bus->rxskip = true; 1250 } 1251 1252 /* Clear partial in any case */ 1253 bus->cur_read.len = 0; 1254} 1255 1256static void brcmf_sdio_txfail(struct brcmf_sdio *bus) 1257{ 1258 struct brcmf_sdio_dev *sdiodev = bus->sdiodev; 1259 u8 i, hi, lo; 1260 1261 /* On failure, abort the command and terminate the frame */ 1262 brcmf_err("sdio error, abort command and terminate frame\n"); 1263 bus->sdcnt.tx_sderrs++; 1264 1265 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2); 1266 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); 1267 bus->sdcnt.f1regdata++; 1268 1269 for (i = 0; i < 3; i++) { 1270 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); 1271 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); 1272 bus->sdcnt.f1regdata += 2; 1273 if ((hi == 0) && (lo == 0)) 1274 break; 1275 } 1276} 1277 1278/* return total length of buffer chain */ 1279static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) 1280{ 1281 struct sk_buff *p; 1282 uint total; 1283 1284 total = 0; 1285 skb_queue_walk(&bus->glom, p) 1286 total += p->len; 1287 return total; 1288} 1289 1290static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) 1291{ 1292 struct sk_buff *cur, *next; 1293 1294 skb_queue_walk_safe(&bus->glom, cur, next) { 1295 skb_unlink(cur, &bus->glom); 1296 brcmu_pkt_buf_free_skb(cur); 1297 } 1298} 1299 1300/** 1301 * brcmfmac sdio bus specific header 1302 * This is the lowest layer header wrapped on the packets transmitted between 1303 * host and WiFi dongle which contains information needed for SDIO core and 1304 * firmware 1305 * 1306 * It consists of 3 parts: hardware header, hardware extension header and 1307 * software header 1308 * hardware header (frame tag) - 4 bytes 1309 * Byte 0~1: Frame length 1310 * Byte 2~3: Checksum, bit-wise inverse of frame length 1311 * hardware extension header - 8 bytes 1312 * Tx glom mode only, N/A for Rx or normal Tx 1313 * Byte 0~1: Packet length excluding hw frame tag 1314 * Byte 2: Reserved 1315 * Byte 3: Frame flags, bit 0: last frame indication 1316 * Byte 4~5: Reserved 1317 * Byte 6~7: Tail padding length 1318 * software header - 8 bytes 1319 * Byte 0: Rx/Tx sequence number 1320 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag 1321 * Byte 2: Length of next data frame, reserved for Tx 1322 * Byte 3: Data offset 1323 * Byte 4: Flow control bits, reserved for Tx 1324 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet 1325 * Byte 6~7: Reserved 1326 */ 1327#define SDPCM_HWHDR_LEN 4 1328#define SDPCM_HWEXT_LEN 8 1329#define SDPCM_SWHDR_LEN 8 1330#define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) 1331/* software header */ 1332#define SDPCM_SEQ_MASK 0x000000ff 1333#define SDPCM_SEQ_WRAP 256 1334#define SDPCM_CHANNEL_MASK 0x00000f00 1335#define SDPCM_CHANNEL_SHIFT 8 1336#define SDPCM_CONTROL_CHANNEL 0 /* Control */ 1337#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ 1338#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ 1339#define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ 1340#define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ 1341#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) 1342#define SDPCM_NEXTLEN_MASK 0x00ff0000 1343#define SDPCM_NEXTLEN_SHIFT 16 1344#define SDPCM_DOFFSET_MASK 0xff000000 1345#define SDPCM_DOFFSET_SHIFT 24 1346#define SDPCM_FCMASK_MASK 0x000000ff 1347#define SDPCM_WINDOW_MASK 0x0000ff00 1348#define SDPCM_WINDOW_SHIFT 8 1349 1350static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) 1351{ 1352 u32 hdrvalue; 1353 hdrvalue = *(u32 *)swheader; 1354 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); 1355} 1356 1357static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, 1358 struct brcmf_sdio_hdrinfo *rd, 1359 enum brcmf_sdio_frmtype type) 1360{ 1361 u16 len, checksum; 1362 u8 rx_seq, fc, tx_seq_max; 1363 u32 swheader; 1364 1365 trace_brcmf_sdpcm_hdr(SDPCM_RX, header); 1366 1367 /* hw header */ 1368 len = get_unaligned_le16(header); 1369 checksum = get_unaligned_le16(header + sizeof(u16)); 1370 /* All zero means no more to read */ 1371 if (!(len | checksum)) { 1372 bus->rxpending = false; 1373 return -ENODATA; 1374 } 1375 if ((u16)(~(len ^ checksum))) { 1376 brcmf_err("HW header checksum error\n"); 1377 bus->sdcnt.rx_badhdr++; 1378 brcmf_sdio_rxfail(bus, false, false); 1379 return -EIO; 1380 } 1381 if (len < SDPCM_HDRLEN) { 1382 brcmf_err("HW header length error\n"); 1383 return -EPROTO; 1384 } 1385 if (type == BRCMF_SDIO_FT_SUPER && 1386 (roundup(len, bus->blocksize) != rd->len)) { 1387 brcmf_err("HW superframe header length error\n"); 1388 return -EPROTO; 1389 } 1390 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { 1391 brcmf_err("HW subframe header length error\n"); 1392 return -EPROTO; 1393 } 1394 rd->len = len; 1395 1396 /* software header */ 1397 header += SDPCM_HWHDR_LEN; 1398 swheader = le32_to_cpu(*(__le32 *)header); 1399 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { 1400 brcmf_err("Glom descriptor found in superframe head\n"); 1401 rd->len = 0; 1402 return -EINVAL; 1403 } 1404 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); 1405 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; 1406 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && 1407 type != BRCMF_SDIO_FT_SUPER) { 1408 brcmf_err("HW header length too long\n"); 1409 bus->sdcnt.rx_toolong++; 1410 brcmf_sdio_rxfail(bus, false, false); 1411 rd->len = 0; 1412 return -EPROTO; 1413 } 1414 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { 1415 brcmf_err("Wrong channel for superframe\n"); 1416 rd->len = 0; 1417 return -EINVAL; 1418 } 1419 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && 1420 rd->channel != SDPCM_EVENT_CHANNEL) { 1421 brcmf_err("Wrong channel for subframe\n"); 1422 rd->len = 0; 1423 return -EINVAL; 1424 } 1425 rd->dat_offset = brcmf_sdio_getdatoffset(header); 1426 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { 1427 brcmf_err("seq %d: bad data offset\n", rx_seq); 1428 bus->sdcnt.rx_badhdr++; 1429 brcmf_sdio_rxfail(bus, false, false); 1430 rd->len = 0; 1431 return -ENXIO; 1432 } 1433 if (rd->seq_num != rx_seq) { 1434 brcmf_err("seq %d: sequence number error, expect %d\n", 1435 rx_seq, rd->seq_num); 1436 bus->sdcnt.rx_badseq++; 1437 rd->seq_num = rx_seq; 1438 } 1439 /* no need to check the reset for subframe */ 1440 if (type == BRCMF_SDIO_FT_SUB) 1441 return 0; 1442 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; 1443 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { 1444 /* only warm for NON glom packet */ 1445 if (rd->channel != SDPCM_GLOM_CHANNEL) 1446 brcmf_err("seq %d: next length error\n", rx_seq); 1447 rd->len_nxtfrm = 0; 1448 } 1449 swheader = le32_to_cpu(*(__le32 *)(header + 4)); 1450 fc = swheader & SDPCM_FCMASK_MASK; 1451 if (bus->flowcontrol != fc) { 1452 if (~bus->flowcontrol & fc) 1453 bus->sdcnt.fc_xoff++; 1454 if (bus->flowcontrol & ~fc) 1455 bus->sdcnt.fc_xon++; 1456 bus->sdcnt.fc_rcvd++; 1457 bus->flowcontrol = fc; 1458 } 1459 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; 1460 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { 1461 brcmf_err("seq %d: max tx seq number error\n", rx_seq); 1462 tx_seq_max = bus->tx_seq + 2; 1463 } 1464 bus->tx_max = tx_seq_max; 1465 1466 return 0; 1467} 1468 1469static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) 1470{ 1471 *(__le16 *)header = cpu_to_le16(frm_length); 1472 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); 1473} 1474 1475static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, 1476 struct brcmf_sdio_hdrinfo *hd_info) 1477{ 1478 u32 hdrval; 1479 u8 hdr_offset; 1480 1481 brcmf_sdio_update_hwhdr(header, hd_info->len); 1482 hdr_offset = SDPCM_HWHDR_LEN; 1483 1484 if (bus->txglom) { 1485 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); 1486 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1487 hdrval = (u16)hd_info->tail_pad << 16; 1488 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); 1489 hdr_offset += SDPCM_HWEXT_LEN; 1490 } 1491 1492 hdrval = hd_info->seq_num; 1493 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & 1494 SDPCM_CHANNEL_MASK; 1495 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & 1496 SDPCM_DOFFSET_MASK; 1497 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1498 *(((__le32 *)(header + hdr_offset)) + 1) = 0; 1499 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); 1500} 1501 1502static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) 1503{ 1504 u16 dlen, totlen; 1505 u8 *dptr, num = 0; 1506 u16 sublen; 1507 struct sk_buff *pfirst, *pnext; 1508 1509 int errcode; 1510 u8 doff, sfdoff; 1511 1512 struct brcmf_sdio_hdrinfo rd_new; 1513 1514 /* If packets, issue read(s) and send up packet chain */ 1515 /* Return sequence numbers consumed? */ 1516 1517 brcmf_dbg(SDIO, "start: glomd %p glom %p\n", 1518 bus->glomd, skb_peek(&bus->glom)); 1519 1520 /* If there's a descriptor, generate the packet chain */ 1521 if (bus->glomd) { 1522 pfirst = pnext = NULL; 1523 dlen = (u16) (bus->glomd->len); 1524 dptr = bus->glomd->data; 1525 if (!dlen || (dlen & 1)) { 1526 brcmf_err("bad glomd len(%d), ignore descriptor\n", 1527 dlen); 1528 dlen = 0; 1529 } 1530 1531 for (totlen = num = 0; dlen; num++) { 1532 /* Get (and move past) next length */ 1533 sublen = get_unaligned_le16(dptr); 1534 dlen -= sizeof(u16); 1535 dptr += sizeof(u16); 1536 if ((sublen < SDPCM_HDRLEN) || 1537 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { 1538 brcmf_err("descriptor len %d bad: %d\n", 1539 num, sublen); 1540 pnext = NULL; 1541 break; 1542 } 1543 if (sublen % bus->sgentry_align) { 1544 brcmf_err("sublen %d not multiple of %d\n", 1545 sublen, bus->sgentry_align); 1546 } 1547 totlen += sublen; 1548 1549 /* For last frame, adjust read len so total 1550 is a block multiple */ 1551 if (!dlen) { 1552 sublen += 1553 (roundup(totlen, bus->blocksize) - totlen); 1554 totlen = roundup(totlen, bus->blocksize); 1555 } 1556 1557 /* Allocate/chain packet for next subframe */ 1558 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); 1559 if (pnext == NULL) { 1560 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", 1561 num, sublen); 1562 break; 1563 } 1564 skb_queue_tail(&bus->glom, pnext); 1565 1566 /* Adhere to start alignment requirements */ 1567 pkt_align(pnext, sublen, bus->sgentry_align); 1568 } 1569 1570 /* If all allocations succeeded, save packet chain 1571 in bus structure */ 1572 if (pnext) { 1573 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", 1574 totlen, num); 1575 if (BRCMF_GLOM_ON() && bus->cur_read.len && 1576 totlen != bus->cur_read.len) { 1577 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", 1578 bus->cur_read.len, totlen, rxseq); 1579 } 1580 pfirst = pnext = NULL; 1581 } else { 1582 brcmf_sdio_free_glom(bus); 1583 num = 0; 1584 } 1585 1586 /* Done with descriptor packet */ 1587 brcmu_pkt_buf_free_skb(bus->glomd); 1588 bus->glomd = NULL; 1589 bus->cur_read.len = 0; 1590 } 1591 1592 /* Ok -- either we just generated a packet chain, 1593 or had one from before */ 1594 if (!skb_queue_empty(&bus->glom)) { 1595 if (BRCMF_GLOM_ON()) { 1596 brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); 1597 skb_queue_walk(&bus->glom, pnext) { 1598 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", 1599 pnext, (u8 *) (pnext->data), 1600 pnext->len, pnext->len); 1601 } 1602 } 1603 1604 pfirst = skb_peek(&bus->glom); 1605 dlen = (u16) brcmf_sdio_glom_len(bus); 1606 1607 /* Do an SDIO read for the superframe. Configurable iovar to 1608 * read directly into the chained packet, or allocate a large 1609 * packet and and copy into the chain. 1610 */ 1611 sdio_claim_host(bus->sdiodev->func[1]); 1612 errcode = brcmf_sdiod_recv_chain(bus->sdiodev, 1613 &bus->glom, dlen); 1614 sdio_release_host(bus->sdiodev->func[1]); 1615 bus->sdcnt.f2rxdata++; 1616 1617 /* On failure, kill the superframe, allow a couple retries */ 1618 if (errcode < 0) { 1619 brcmf_err("glom read of %d bytes failed: %d\n", 1620 dlen, errcode); 1621 1622 sdio_claim_host(bus->sdiodev->func[1]); 1623 if (bus->glomerr++ < 3) { 1624 brcmf_sdio_rxfail(bus, true, true); 1625 } else { 1626 bus->glomerr = 0; 1627 brcmf_sdio_rxfail(bus, true, false); 1628 bus->sdcnt.rxglomfail++; 1629 brcmf_sdio_free_glom(bus); 1630 } 1631 sdio_release_host(bus->sdiodev->func[1]); 1632 return 0; 1633 } 1634 1635 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1636 pfirst->data, min_t(int, pfirst->len, 48), 1637 "SUPERFRAME:\n"); 1638 1639 rd_new.seq_num = rxseq; 1640 rd_new.len = dlen; 1641 sdio_claim_host(bus->sdiodev->func[1]); 1642 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, 1643 BRCMF_SDIO_FT_SUPER); 1644 sdio_release_host(bus->sdiodev->func[1]); 1645 bus->cur_read.len = rd_new.len_nxtfrm << 4; 1646 1647 /* Remove superframe header, remember offset */ 1648 skb_pull(pfirst, rd_new.dat_offset); 1649 sfdoff = rd_new.dat_offset; 1650 num = 0; 1651 1652 /* Validate all the subframe headers */ 1653 skb_queue_walk(&bus->glom, pnext) { 1654 /* leave when invalid subframe is found */ 1655 if (errcode) 1656 break; 1657 1658 rd_new.len = pnext->len; 1659 rd_new.seq_num = rxseq++; 1660 sdio_claim_host(bus->sdiodev->func[1]); 1661 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, 1662 BRCMF_SDIO_FT_SUB); 1663 sdio_release_host(bus->sdiodev->func[1]); 1664 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1665 pnext->data, 32, "subframe:\n"); 1666 1667 num++; 1668 } 1669 1670 if (errcode) { 1671 /* Terminate frame on error, request 1672 a couple retries */ 1673 sdio_claim_host(bus->sdiodev->func[1]); 1674 if (bus->glomerr++ < 3) { 1675 /* Restore superframe header space */ 1676 skb_push(pfirst, sfdoff); 1677 brcmf_sdio_rxfail(bus, true, true); 1678 } else { 1679 bus->glomerr = 0; 1680 brcmf_sdio_rxfail(bus, true, false); 1681 bus->sdcnt.rxglomfail++; 1682 brcmf_sdio_free_glom(bus); 1683 } 1684 sdio_release_host(bus->sdiodev->func[1]); 1685 bus->cur_read.len = 0; 1686 return 0; 1687 } 1688 1689 /* Basic SD framing looks ok - process each packet (header) */ 1690 1691 skb_queue_walk_safe(&bus->glom, pfirst, pnext) { 1692 dptr = (u8 *) (pfirst->data); 1693 sublen = get_unaligned_le16(dptr); 1694 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); 1695 1696 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1697 dptr, pfirst->len, 1698 "Rx Subframe Data:\n"); 1699 1700 __skb_trim(pfirst, sublen); 1701 skb_pull(pfirst, doff); 1702 1703 if (pfirst->len == 0) { 1704 skb_unlink(pfirst, &bus->glom); 1705 brcmu_pkt_buf_free_skb(pfirst); 1706 continue; 1707 } 1708 1709 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1710 pfirst->data, 1711 min_t(int, pfirst->len, 32), 1712 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", 1713 bus->glom.qlen, pfirst, pfirst->data, 1714 pfirst->len, pfirst->next, 1715 pfirst->prev); 1716 skb_unlink(pfirst, &bus->glom); 1717 brcmf_rx_frame(bus->sdiodev->dev, pfirst); 1718 bus->sdcnt.rxglompkts++; 1719 } 1720 1721 bus->sdcnt.rxglomframes++; 1722 } 1723 return num; 1724} 1725 1726static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, 1727 bool *pending) 1728{ 1729 DECLARE_WAITQUEUE(wait, current); 1730 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT); 1731 1732 /* Wait until control frame is available */ 1733 add_wait_queue(&bus->dcmd_resp_wait, &wait); 1734 set_current_state(TASK_INTERRUPTIBLE); 1735 1736 while (!(*condition) && (!signal_pending(current) && timeout)) 1737 timeout = schedule_timeout(timeout); 1738 1739 if (signal_pending(current)) 1740 *pending = true; 1741 1742 set_current_state(TASK_RUNNING); 1743 remove_wait_queue(&bus->dcmd_resp_wait, &wait); 1744 1745 return timeout; 1746} 1747 1748static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) 1749{ 1750 if (waitqueue_active(&bus->dcmd_resp_wait)) 1751 wake_up_interruptible(&bus->dcmd_resp_wait); 1752 1753 return 0; 1754} 1755static void 1756brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) 1757{ 1758 uint rdlen, pad; 1759 u8 *buf = NULL, *rbuf; 1760 int sdret; 1761 1762 brcmf_dbg(TRACE, "Enter\n"); 1763 1764 if (bus->rxblen) 1765 buf = vzalloc(bus->rxblen); 1766 if (!buf) 1767 goto done; 1768 1769 rbuf = bus->rxbuf; 1770 pad = ((unsigned long)rbuf % bus->head_align); 1771 if (pad) 1772 rbuf += (bus->head_align - pad); 1773 1774 /* Copy the already-read portion over */ 1775 memcpy(buf, hdr, BRCMF_FIRSTREAD); 1776 if (len <= BRCMF_FIRSTREAD) 1777 goto gotpkt; 1778 1779 /* Raise rdlen to next SDIO block to avoid tail command */ 1780 rdlen = len - BRCMF_FIRSTREAD; 1781 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { 1782 pad = bus->blocksize - (rdlen % bus->blocksize); 1783 if ((pad <= bus->roundup) && (pad < bus->blocksize) && 1784 ((len + pad) < bus->sdiodev->bus_if->maxctl)) 1785 rdlen += pad; 1786 } else if (rdlen % bus->head_align) { 1787 rdlen += bus->head_align - (rdlen % bus->head_align); 1788 } 1789 1790 /* Drop if the read is too big or it exceeds our maximum */ 1791 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { 1792 brcmf_err("%d-byte control read exceeds %d-byte buffer\n", 1793 rdlen, bus->sdiodev->bus_if->maxctl); 1794 brcmf_sdio_rxfail(bus, false, false); 1795 goto done; 1796 } 1797 1798 if ((len - doff) > bus->sdiodev->bus_if->maxctl) { 1799 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", 1800 len, len - doff, bus->sdiodev->bus_if->maxctl); 1801 bus->sdcnt.rx_toolong++; 1802 brcmf_sdio_rxfail(bus, false, false); 1803 goto done; 1804 } 1805 1806 /* Read remain of frame body */ 1807 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); 1808 bus->sdcnt.f2rxdata++; 1809 1810 /* Control frame failures need retransmission */ 1811 if (sdret < 0) { 1812 brcmf_err("read %d control bytes failed: %d\n", 1813 rdlen, sdret); 1814 bus->sdcnt.rxc_errors++; 1815 brcmf_sdio_rxfail(bus, true, true); 1816 goto done; 1817 } else 1818 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); 1819 1820gotpkt: 1821 1822 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 1823 buf, len, "RxCtrl:\n"); 1824 1825 /* Point to valid data and indicate its length */ 1826 spin_lock_bh(&bus->rxctl_lock); 1827 if (bus->rxctl) { 1828 brcmf_err("last control frame is being processed.\n"); 1829 spin_unlock_bh(&bus->rxctl_lock); 1830 vfree(buf); 1831 goto done; 1832 } 1833 bus->rxctl = buf + doff; 1834 bus->rxctl_orig = buf; 1835 bus->rxlen = len - doff; 1836 spin_unlock_bh(&bus->rxctl_lock); 1837 1838done: 1839 /* Awake any waiters */ 1840 brcmf_sdio_dcmd_resp_wake(bus); 1841} 1842 1843/* Pad read to blocksize for efficiency */ 1844static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) 1845{ 1846 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { 1847 *pad = bus->blocksize - (*rdlen % bus->blocksize); 1848 if (*pad <= bus->roundup && *pad < bus->blocksize && 1849 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) 1850 *rdlen += *pad; 1851 } else if (*rdlen % bus->head_align) { 1852 *rdlen += bus->head_align - (*rdlen % bus->head_align); 1853 } 1854} 1855 1856static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) 1857{ 1858 struct sk_buff *pkt; /* Packet for event or data frames */ 1859 u16 pad; /* Number of pad bytes to read */ 1860 uint rxleft = 0; /* Remaining number of frames allowed */ 1861 int ret; /* Return code from calls */ 1862 uint rxcount = 0; /* Total frames read */ 1863 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; 1864 u8 head_read = 0; 1865 1866 brcmf_dbg(TRACE, "Enter\n"); 1867 1868 /* Not finished unless we encounter no more frames indication */ 1869 bus->rxpending = true; 1870 1871 for (rd->seq_num = bus->rx_seq, rxleft = maxframes; 1872 !bus->rxskip && rxleft && brcmf_bus_ready(bus->sdiodev->bus_if); 1873 rd->seq_num++, rxleft--) { 1874 1875 /* Handle glomming separately */ 1876 if (bus->glomd || !skb_queue_empty(&bus->glom)) { 1877 u8 cnt; 1878 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", 1879 bus->glomd, skb_peek(&bus->glom)); 1880 cnt = brcmf_sdio_rxglom(bus, rd->seq_num); 1881 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); 1882 rd->seq_num += cnt - 1; 1883 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; 1884 continue; 1885 } 1886 1887 rd->len_left = rd->len; 1888 /* read header first for unknow frame length */ 1889 sdio_claim_host(bus->sdiodev->func[1]); 1890 if (!rd->len) { 1891 ret = brcmf_sdiod_recv_buf(bus->sdiodev, 1892 bus->rxhdr, BRCMF_FIRSTREAD); 1893 bus->sdcnt.f2rxhdrs++; 1894 if (ret < 0) { 1895 brcmf_err("RXHEADER FAILED: %d\n", 1896 ret); 1897 bus->sdcnt.rx_hdrfail++; 1898 brcmf_sdio_rxfail(bus, true, true); 1899 sdio_release_host(bus->sdiodev->func[1]); 1900 continue; 1901 } 1902 1903 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), 1904 bus->rxhdr, SDPCM_HDRLEN, 1905 "RxHdr:\n"); 1906 1907 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, 1908 BRCMF_SDIO_FT_NORMAL)) { 1909 sdio_release_host(bus->sdiodev->func[1]); 1910 if (!bus->rxpending) 1911 break; 1912 else 1913 continue; 1914 } 1915 1916 if (rd->channel == SDPCM_CONTROL_CHANNEL) { 1917 brcmf_sdio_read_control(bus, bus->rxhdr, 1918 rd->len, 1919 rd->dat_offset); 1920 /* prepare the descriptor for the next read */ 1921 rd->len = rd->len_nxtfrm << 4; 1922 rd->len_nxtfrm = 0; 1923 /* treat all packet as event if we don't know */ 1924 rd->channel = SDPCM_EVENT_CHANNEL; 1925 sdio_release_host(bus->sdiodev->func[1]); 1926 continue; 1927 } 1928 rd->len_left = rd->len > BRCMF_FIRSTREAD ? 1929 rd->len - BRCMF_FIRSTREAD : 0; 1930 head_read = BRCMF_FIRSTREAD; 1931 } 1932 1933 brcmf_sdio_pad(bus, &pad, &rd->len_left); 1934 1935 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + 1936 bus->head_align); 1937 if (!pkt) { 1938 /* Give up on data, request rtx of events */ 1939 brcmf_err("brcmu_pkt_buf_get_skb failed\n"); 1940 brcmf_sdio_rxfail(bus, false, 1941 RETRYCHAN(rd->channel)); 1942 sdio_release_host(bus->sdiodev->func[1]); 1943 continue; 1944 } 1945 skb_pull(pkt, head_read); 1946 pkt_align(pkt, rd->len_left, bus->head_align); 1947 1948 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); 1949 bus->sdcnt.f2rxdata++; 1950 sdio_release_host(bus->sdiodev->func[1]); 1951 1952 if (ret < 0) { 1953 brcmf_err("read %d bytes from channel %d failed: %d\n", 1954 rd->len, rd->channel, ret); 1955 brcmu_pkt_buf_free_skb(pkt); 1956 sdio_claim_host(bus->sdiodev->func[1]); 1957 brcmf_sdio_rxfail(bus, true, 1958 RETRYCHAN(rd->channel)); 1959 sdio_release_host(bus->sdiodev->func[1]); 1960 continue; 1961 } 1962 1963 if (head_read) { 1964 skb_push(pkt, head_read); 1965 memcpy(pkt->data, bus->rxhdr, head_read); 1966 head_read = 0; 1967 } else { 1968 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); 1969 rd_new.seq_num = rd->seq_num; 1970 sdio_claim_host(bus->sdiodev->func[1]); 1971 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, 1972 BRCMF_SDIO_FT_NORMAL)) { 1973 rd->len = 0; 1974 brcmu_pkt_buf_free_skb(pkt); 1975 } 1976 bus->sdcnt.rx_readahead_cnt++; 1977 if (rd->len != roundup(rd_new.len, 16)) { 1978 brcmf_err("frame length mismatch:read %d, should be %d\n", 1979 rd->len, 1980 roundup(rd_new.len, 16) >> 4); 1981 rd->len = 0; 1982 brcmf_sdio_rxfail(bus, true, true); 1983 sdio_release_host(bus->sdiodev->func[1]); 1984 brcmu_pkt_buf_free_skb(pkt); 1985 continue; 1986 } 1987 sdio_release_host(bus->sdiodev->func[1]); 1988 rd->len_nxtfrm = rd_new.len_nxtfrm; 1989 rd->channel = rd_new.channel; 1990 rd->dat_offset = rd_new.dat_offset; 1991 1992 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && 1993 BRCMF_DATA_ON()) && 1994 BRCMF_HDRS_ON(), 1995 bus->rxhdr, SDPCM_HDRLEN, 1996 "RxHdr:\n"); 1997 1998 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { 1999 brcmf_err("readahead on control packet %d?\n", 2000 rd_new.seq_num); 2001 /* Force retry w/normal header read */ 2002 rd->len = 0; 2003 sdio_claim_host(bus->sdiodev->func[1]); 2004 brcmf_sdio_rxfail(bus, false, true); 2005 sdio_release_host(bus->sdiodev->func[1]); 2006 brcmu_pkt_buf_free_skb(pkt); 2007 continue; 2008 } 2009 } 2010 2011 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 2012 pkt->data, rd->len, "Rx Data:\n"); 2013 2014 /* Save superframe descriptor and allocate packet frame */ 2015 if (rd->channel == SDPCM_GLOM_CHANNEL) { 2016 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { 2017 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", 2018 rd->len); 2019 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 2020 pkt->data, rd->len, 2021 "Glom Data:\n"); 2022 __skb_trim(pkt, rd->len); 2023 skb_pull(pkt, SDPCM_HDRLEN); 2024 bus->glomd = pkt; 2025 } else { 2026 brcmf_err("%s: glom superframe w/o " 2027 "descriptor!\n", __func__); 2028 sdio_claim_host(bus->sdiodev->func[1]); 2029 brcmf_sdio_rxfail(bus, false, false); 2030 sdio_release_host(bus->sdiodev->func[1]); 2031 } 2032 /* prepare the descriptor for the next read */ 2033 rd->len = rd->len_nxtfrm << 4; 2034 rd->len_nxtfrm = 0; 2035 /* treat all packet as event if we don't know */ 2036 rd->channel = SDPCM_EVENT_CHANNEL; 2037 continue; 2038 } 2039 2040 /* Fill in packet len and prio, deliver upward */ 2041 __skb_trim(pkt, rd->len); 2042 skb_pull(pkt, rd->dat_offset); 2043 2044 /* prepare the descriptor for the next read */ 2045 rd->len = rd->len_nxtfrm << 4; 2046 rd->len_nxtfrm = 0; 2047 /* treat all packet as event if we don't know */ 2048 rd->channel = SDPCM_EVENT_CHANNEL; 2049 2050 if (pkt->len == 0) { 2051 brcmu_pkt_buf_free_skb(pkt); 2052 continue; 2053 } 2054 2055 brcmf_rx_frame(bus->sdiodev->dev, pkt); 2056 } 2057 2058 rxcount = maxframes - rxleft; 2059 /* Message if we hit the limit */ 2060 if (!rxleft) 2061 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); 2062 else 2063 brcmf_dbg(DATA, "processed %d frames\n", rxcount); 2064 /* Back off rxseq if awaiting rtx, update rx_seq */ 2065 if (bus->rxskip) 2066 rd->seq_num--; 2067 bus->rx_seq = rd->seq_num; 2068 2069 return rxcount; 2070} 2071 2072static void 2073brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) 2074{ 2075 if (waitqueue_active(&bus->ctrl_wait)) 2076 wake_up_interruptible(&bus->ctrl_wait); 2077 return; 2078} 2079 2080static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) 2081{ 2082 u16 head_pad; 2083 u8 *dat_buf; 2084 2085 dat_buf = (u8 *)(pkt->data); 2086 2087 /* Check head padding */ 2088 head_pad = ((unsigned long)dat_buf % bus->head_align); 2089 if (head_pad) { 2090 if (skb_headroom(pkt) < head_pad) { 2091 bus->sdiodev->bus_if->tx_realloc++; 2092 head_pad = 0; 2093 if (skb_cow(pkt, head_pad)) 2094 return -ENOMEM; 2095 } 2096 skb_push(pkt, head_pad); 2097 dat_buf = (u8 *)(pkt->data); 2098 memset(dat_buf, 0, head_pad + bus->tx_hdrlen); 2099 } 2100 return head_pad; 2101} 2102 2103/** 2104 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for 2105 * bus layer usage. 2106 */ 2107/* flag marking a dummy skb added for DMA alignment requirement */ 2108#define ALIGN_SKB_FLAG 0x8000 2109/* bit mask of data length chopped from the previous packet */ 2110#define ALIGN_SKB_CHOP_LEN_MASK 0x7fff 2111 2112static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, 2113 struct sk_buff_head *pktq, 2114 struct sk_buff *pkt, u16 total_len) 2115{ 2116 struct brcmf_sdio_dev *sdiodev; 2117 struct sk_buff *pkt_pad; 2118 u16 tail_pad, tail_chop, chain_pad; 2119 unsigned int blksize; 2120 bool lastfrm; 2121 int ntail, ret; 2122 2123 sdiodev = bus->sdiodev; 2124 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize; 2125 /* sg entry alignment should be a divisor of block size */ 2126 WARN_ON(blksize % bus->sgentry_align); 2127 2128 /* Check tail padding */ 2129 lastfrm = skb_queue_is_last(pktq, pkt); 2130 tail_pad = 0; 2131 tail_chop = pkt->len % bus->sgentry_align; 2132 if (tail_chop) 2133 tail_pad = bus->sgentry_align - tail_chop; 2134 chain_pad = (total_len + tail_pad) % blksize; 2135 if (lastfrm && chain_pad) 2136 tail_pad += blksize - chain_pad; 2137 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { 2138 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + 2139 bus->head_align); 2140 if (pkt_pad == NULL) 2141 return -ENOMEM; 2142 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); 2143 if (unlikely(ret < 0)) 2144 return ret; 2145 memcpy(pkt_pad->data, 2146 pkt->data + pkt->len - tail_chop, 2147 tail_chop); 2148 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; 2149 skb_trim(pkt, pkt->len - tail_chop); 2150 skb_trim(pkt_pad, tail_pad + tail_chop); 2151 __skb_queue_after(pktq, pkt, pkt_pad); 2152 } else { 2153 ntail = pkt->data_len + tail_pad - 2154 (pkt->end - pkt->tail); 2155 if (skb_cloned(pkt) || ntail > 0) 2156 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) 2157 return -ENOMEM; 2158 if (skb_linearize(pkt)) 2159 return -ENOMEM; 2160 __skb_put(pkt, tail_pad); 2161 } 2162 2163 return tail_pad; 2164} 2165 2166/** 2167 * brcmf_sdio_txpkt_prep - packet preparation for transmit 2168 * @bus: brcmf_sdio structure pointer 2169 * @pktq: packet list pointer 2170 * @chan: virtual channel to transmit the packet 2171 * 2172 * Processes to be applied to the packet 2173 * - Align data buffer pointer 2174 * - Align data buffer length 2175 * - Prepare header 2176 * Return: negative value if there is error 2177 */ 2178static int 2179brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2180 uint chan) 2181{ 2182 u16 head_pad, total_len; 2183 struct sk_buff *pkt_next; 2184 u8 txseq; 2185 int ret; 2186 struct brcmf_sdio_hdrinfo hd_info = {0}; 2187 2188 txseq = bus->tx_seq; 2189 total_len = 0; 2190 skb_queue_walk(pktq, pkt_next) { 2191 /* alignment packet inserted in previous 2192 * loop cycle can be skipped as it is 2193 * already properly aligned and does not 2194 * need an sdpcm header. 2195 */ 2196 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) 2197 continue; 2198 2199 /* align packet data pointer */ 2200 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); 2201 if (ret < 0) 2202 return ret; 2203 head_pad = (u16)ret; 2204 if (head_pad) 2205 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); 2206 2207 total_len += pkt_next->len; 2208 2209 hd_info.len = pkt_next->len; 2210 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); 2211 if (bus->txglom && pktq->qlen > 1) { 2212 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, 2213 pkt_next, total_len); 2214 if (ret < 0) 2215 return ret; 2216 hd_info.tail_pad = (u16)ret; 2217 total_len += (u16)ret; 2218 } 2219 2220 hd_info.channel = chan; 2221 hd_info.dat_offset = head_pad + bus->tx_hdrlen; 2222 hd_info.seq_num = txseq++; 2223 2224 /* Now fill the header */ 2225 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); 2226 2227 if (BRCMF_BYTES_ON() && 2228 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || 2229 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) 2230 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, 2231 "Tx Frame:\n"); 2232 else if (BRCMF_HDRS_ON()) 2233 brcmf_dbg_hex_dump(true, pkt_next->data, 2234 head_pad + bus->tx_hdrlen, 2235 "Tx Header:\n"); 2236 } 2237 /* Hardware length tag of the first packet should be total 2238 * length of the chain (including padding) 2239 */ 2240 if (bus->txglom) 2241 brcmf_sdio_update_hwhdr(pktq->next->data, total_len); 2242 return 0; 2243} 2244 2245/** 2246 * brcmf_sdio_txpkt_postp - packet post processing for transmit 2247 * @bus: brcmf_sdio structure pointer 2248 * @pktq: packet list pointer 2249 * 2250 * Processes to be applied to the packet 2251 * - Remove head padding 2252 * - Remove tail padding 2253 */ 2254static void 2255brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) 2256{ 2257 u8 *hdr; 2258 u32 dat_offset; 2259 u16 tail_pad; 2260 u16 dummy_flags, chop_len; 2261 struct sk_buff *pkt_next, *tmp, *pkt_prev; 2262 2263 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2264 dummy_flags = *(u16 *)(pkt_next->cb); 2265 if (dummy_flags & ALIGN_SKB_FLAG) { 2266 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; 2267 if (chop_len) { 2268 pkt_prev = pkt_next->prev; 2269 skb_put(pkt_prev, chop_len); 2270 } 2271 __skb_unlink(pkt_next, pktq); 2272 brcmu_pkt_buf_free_skb(pkt_next); 2273 } else { 2274 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; 2275 dat_offset = le32_to_cpu(*(__le32 *)hdr); 2276 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> 2277 SDPCM_DOFFSET_SHIFT; 2278 skb_pull(pkt_next, dat_offset); 2279 if (bus->txglom) { 2280 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); 2281 skb_trim(pkt_next, pkt_next->len - tail_pad); 2282 } 2283 } 2284 } 2285} 2286 2287/* Writes a HW/SW header into the packet and sends it. */ 2288/* Assumes: (a) header space already there, (b) caller holds lock */ 2289static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2290 uint chan) 2291{ 2292 int ret; 2293 struct sk_buff *pkt_next, *tmp; 2294 2295 brcmf_dbg(TRACE, "Enter\n"); 2296 2297 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); 2298 if (ret) 2299 goto done; 2300 2301 sdio_claim_host(bus->sdiodev->func[1]); 2302 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); 2303 bus->sdcnt.f2txdata++; 2304 2305 if (ret < 0) 2306 brcmf_sdio_txfail(bus); 2307 2308 sdio_release_host(bus->sdiodev->func[1]); 2309 2310done: 2311 brcmf_sdio_txpkt_postp(bus, pktq); 2312 if (ret == 0) 2313 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; 2314 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2315 __skb_unlink(pkt_next, pktq); 2316 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0); 2317 } 2318 return ret; 2319} 2320 2321static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) 2322{ 2323 struct sk_buff *pkt; 2324 struct sk_buff_head pktq; 2325 u32 intstatus = 0; 2326 int ret = 0, prec_out, i; 2327 uint cnt = 0; 2328 u8 tx_prec_map, pkt_num; 2329 2330 brcmf_dbg(TRACE, "Enter\n"); 2331 2332 tx_prec_map = ~bus->flowcontrol; 2333 2334 /* Send frames until the limit or some other event */ 2335 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { 2336 pkt_num = 1; 2337 if (down_interruptible(&bus->tx_seq_lock)) 2338 return cnt; 2339 if (bus->txglom) 2340 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, 2341 bus->sdiodev->txglomsz); 2342 pkt_num = min_t(u32, pkt_num, 2343 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); 2344 __skb_queue_head_init(&pktq); 2345 spin_lock_bh(&bus->txq_lock); 2346 for (i = 0; i < pkt_num; i++) { 2347 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, 2348 &prec_out); 2349 if (pkt == NULL) 2350 break; 2351 __skb_queue_tail(&pktq, pkt); 2352 } 2353 spin_unlock_bh(&bus->txq_lock); 2354 if (i == 0) { 2355 up(&bus->tx_seq_lock); 2356 break; 2357 } 2358 2359 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); 2360 up(&bus->tx_seq_lock); 2361 2362 cnt += i; 2363 2364 /* In poll mode, need to check for other events */ 2365 if (!bus->intr) { 2366 /* Check device status, signal pending interrupt */ 2367 sdio_claim_host(bus->sdiodev->func[1]); 2368 ret = r_sdreg32(bus, &intstatus, 2369 offsetof(struct sdpcmd_regs, 2370 intstatus)); 2371 sdio_release_host(bus->sdiodev->func[1]); 2372 bus->sdcnt.f2txdata++; 2373 if (ret != 0) 2374 break; 2375 if (intstatus & bus->hostintmask) 2376 atomic_set(&bus->ipend, 1); 2377 } 2378 } 2379 2380 /* Deflow-control stack if needed */ 2381 if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) && 2382 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { 2383 bus->txoff = false; 2384 brcmf_txflowblock(bus->sdiodev->dev, false); 2385 } 2386 2387 return cnt; 2388} 2389 2390static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) 2391{ 2392 u8 doff; 2393 u16 pad; 2394 uint retries = 0; 2395 struct brcmf_sdio_hdrinfo hd_info = {0}; 2396 int ret; 2397 2398 brcmf_dbg(TRACE, "Enter\n"); 2399 2400 /* Back the pointer to make room for bus header */ 2401 frame -= bus->tx_hdrlen; 2402 len += bus->tx_hdrlen; 2403 2404 /* Add alignment padding (optional for ctl frames) */ 2405 doff = ((unsigned long)frame % bus->head_align); 2406 if (doff) { 2407 frame -= doff; 2408 len += doff; 2409 memset(frame + bus->tx_hdrlen, 0, doff); 2410 } 2411 2412 /* Round send length to next SDIO block */ 2413 pad = 0; 2414 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { 2415 pad = bus->blocksize - (len % bus->blocksize); 2416 if ((pad > bus->roundup) || (pad >= bus->blocksize)) 2417 pad = 0; 2418 } else if (len % bus->head_align) { 2419 pad = bus->head_align - (len % bus->head_align); 2420 } 2421 len += pad; 2422 2423 hd_info.len = len - pad; 2424 hd_info.channel = SDPCM_CONTROL_CHANNEL; 2425 hd_info.dat_offset = doff + bus->tx_hdrlen; 2426 hd_info.seq_num = bus->tx_seq; 2427 hd_info.lastfrm = true; 2428 hd_info.tail_pad = pad; 2429 brcmf_sdio_hdpack(bus, frame, &hd_info); 2430 2431 if (bus->txglom) 2432 brcmf_sdio_update_hwhdr(frame, len); 2433 2434 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 2435 frame, len, "Tx Frame:\n"); 2436 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && 2437 BRCMF_HDRS_ON(), 2438 frame, min_t(u16, len, 16), "TxHdr:\n"); 2439 2440 do { 2441 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); 2442 2443 if (ret < 0) 2444 brcmf_sdio_txfail(bus); 2445 else 2446 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; 2447 } while (ret < 0 && retries++ < TXRETRIES); 2448 2449 return ret; 2450} 2451 2452static void brcmf_sdio_bus_stop(struct device *dev) 2453{ 2454 u32 local_hostintmask; 2455 u8 saveclk; 2456 int err; 2457 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2458 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2459 struct brcmf_sdio *bus = sdiodev->bus; 2460 2461 brcmf_dbg(TRACE, "Enter\n"); 2462 2463 if (bus->watchdog_tsk) { 2464 send_sig(SIGTERM, bus->watchdog_tsk, 1); 2465 kthread_stop(bus->watchdog_tsk); 2466 bus->watchdog_tsk = NULL; 2467 } 2468 2469 if (bus_if->state == BRCMF_BUS_DOWN) { 2470 sdio_claim_host(sdiodev->func[1]); 2471 2472 /* Enable clock for device interrupts */ 2473 brcmf_sdio_bus_sleep(bus, false, false); 2474 2475 /* Disable and clear interrupts at the chip level also */ 2476 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask)); 2477 local_hostintmask = bus->hostintmask; 2478 bus->hostintmask = 0; 2479 2480 /* Force backplane clocks to assure F2 interrupt propagates */ 2481 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2482 &err); 2483 if (!err) 2484 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2485 (saveclk | SBSDIO_FORCE_HT), &err); 2486 if (err) 2487 brcmf_err("Failed to force clock for F2: err %d\n", 2488 err); 2489 2490 /* Turn off the bus (F2), free any pending packets */ 2491 brcmf_dbg(INTR, "disable SDIO interrupts\n"); 2492 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); 2493 2494 /* Clear any pending interrupts now that F2 is disabled */ 2495 w_sdreg32(bus, local_hostintmask, 2496 offsetof(struct sdpcmd_regs, intstatus)); 2497 2498 sdio_release_host(sdiodev->func[1]); 2499 } 2500 /* Clear the data packet queues */ 2501 brcmu_pktq_flush(&bus->txq, true, NULL, NULL); 2502 2503 /* Clear any held glomming stuff */ 2504 if (bus->glomd) 2505 brcmu_pkt_buf_free_skb(bus->glomd); 2506 brcmf_sdio_free_glom(bus); 2507 2508 /* Clear rx control and wake any waiters */ 2509 spin_lock_bh(&bus->rxctl_lock); 2510 bus->rxlen = 0; 2511 spin_unlock_bh(&bus->rxctl_lock); 2512 brcmf_sdio_dcmd_resp_wake(bus); 2513 2514 /* Reset some F2 state stuff */ 2515 bus->rxskip = false; 2516 bus->tx_seq = bus->rx_seq = 0; 2517} 2518 2519static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) 2520{ 2521 unsigned long flags; 2522 2523 if (bus->sdiodev->oob_irq_requested) { 2524 spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags); 2525 if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) { 2526 enable_irq(bus->sdiodev->pdata->oob_irq_nr); 2527 bus->sdiodev->irq_en = true; 2528 } 2529 spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags); 2530 } 2531} 2532 2533static void atomic_orr(int val, atomic_t *v) 2534{ 2535 int old_val; 2536 2537 old_val = atomic_read(v); 2538 while (atomic_cmpxchg(v, old_val, val | old_val) != old_val) 2539 old_val = atomic_read(v); 2540} 2541 2542static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) 2543{ 2544 struct brcmf_core *buscore; 2545 u32 addr; 2546 unsigned long val; 2547 int ret; 2548 2549 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); 2550 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus); 2551 2552 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret); 2553 bus->sdcnt.f1regdata++; 2554 if (ret != 0) 2555 return ret; 2556 2557 val &= bus->hostintmask; 2558 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); 2559 2560 /* Clear interrupts */ 2561 if (val) { 2562 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret); 2563 bus->sdcnt.f1regdata++; 2564 atomic_orr(val, &bus->intstatus); 2565 } 2566 2567 return ret; 2568} 2569 2570static void brcmf_sdio_dpc(struct brcmf_sdio *bus) 2571{ 2572 u32 newstatus = 0; 2573 unsigned long intstatus; 2574 uint txlimit = bus->txbound; /* Tx frames to send before resched */ 2575 uint framecnt; /* Temporary counter of tx/rx frames */ 2576 int err = 0; 2577 2578 brcmf_dbg(TRACE, "Enter\n"); 2579 2580 sdio_claim_host(bus->sdiodev->func[1]); 2581 2582 /* If waiting for HTAVAIL, check status */ 2583 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { 2584 u8 clkctl, devctl = 0; 2585 2586#ifdef DEBUG 2587 /* Check for inconsistent device control */ 2588 devctl = brcmf_sdiod_regrb(bus->sdiodev, 2589 SBSDIO_DEVICE_CTL, &err); 2590#endif /* DEBUG */ 2591 2592 /* Read CSR, if clock on switch to AVAIL, else ignore */ 2593 clkctl = brcmf_sdiod_regrb(bus->sdiodev, 2594 SBSDIO_FUNC1_CHIPCLKCSR, &err); 2595 2596 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", 2597 devctl, clkctl); 2598 2599 if (SBSDIO_HTAV(clkctl)) { 2600 devctl = brcmf_sdiod_regrb(bus->sdiodev, 2601 SBSDIO_DEVICE_CTL, &err); 2602 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 2603 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL, 2604 devctl, &err); 2605 bus->clkstate = CLK_AVAIL; 2606 } 2607 } 2608 2609 /* Make sure backplane clock is on */ 2610 brcmf_sdio_bus_sleep(bus, false, true); 2611 2612 /* Pending interrupt indicates new device status */ 2613 if (atomic_read(&bus->ipend) > 0) { 2614 atomic_set(&bus->ipend, 0); 2615 err = brcmf_sdio_intr_rstatus(bus); 2616 } 2617 2618 /* Start with leftover status bits */ 2619 intstatus = atomic_xchg(&bus->intstatus, 0); 2620 2621 /* Handle flow-control change: read new state in case our ack 2622 * crossed another change interrupt. If change still set, assume 2623 * FC ON for safety, let next loop through do the debounce. 2624 */ 2625 if (intstatus & I_HMB_FC_CHANGE) { 2626 intstatus &= ~I_HMB_FC_CHANGE; 2627 err = w_sdreg32(bus, I_HMB_FC_CHANGE, 2628 offsetof(struct sdpcmd_regs, intstatus)); 2629 2630 err = r_sdreg32(bus, &newstatus, 2631 offsetof(struct sdpcmd_regs, intstatus)); 2632 bus->sdcnt.f1regdata += 2; 2633 atomic_set(&bus->fcstate, 2634 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); 2635 intstatus |= (newstatus & bus->hostintmask); 2636 } 2637 2638 /* Handle host mailbox indication */ 2639 if (intstatus & I_HMB_HOST_INT) { 2640 intstatus &= ~I_HMB_HOST_INT; 2641 intstatus |= brcmf_sdio_hostmail(bus); 2642 } 2643 2644 sdio_release_host(bus->sdiodev->func[1]); 2645 2646 /* Generally don't ask for these, can get CRC errors... */ 2647 if (intstatus & I_WR_OOSYNC) { 2648 brcmf_err("Dongle reports WR_OOSYNC\n"); 2649 intstatus &= ~I_WR_OOSYNC; 2650 } 2651 2652 if (intstatus & I_RD_OOSYNC) { 2653 brcmf_err("Dongle reports RD_OOSYNC\n"); 2654 intstatus &= ~I_RD_OOSYNC; 2655 } 2656 2657 if (intstatus & I_SBINT) { 2658 brcmf_err("Dongle reports SBINT\n"); 2659 intstatus &= ~I_SBINT; 2660 } 2661 2662 /* Would be active due to wake-wlan in gSPI */ 2663 if (intstatus & I_CHIPACTIVE) { 2664 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); 2665 intstatus &= ~I_CHIPACTIVE; 2666 } 2667 2668 /* Ignore frame indications if rxskip is set */ 2669 if (bus->rxskip) 2670 intstatus &= ~I_HMB_FRAME_IND; 2671 2672 /* On frame indication, read available frames */ 2673 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { 2674 brcmf_sdio_readframes(bus, bus->rxbound); 2675 if (!bus->rxpending) 2676 intstatus &= ~I_HMB_FRAME_IND; 2677 } 2678 2679 /* Keep still-pending events for next scheduling */ 2680 if (intstatus) 2681 atomic_orr(intstatus, &bus->intstatus); 2682 2683 brcmf_sdio_clrintr(bus); 2684 2685 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && 2686 (down_interruptible(&bus->tx_seq_lock) == 0)) { 2687 if (data_ok(bus)) { 2688 sdio_claim_host(bus->sdiodev->func[1]); 2689 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, 2690 bus->ctrl_frame_len); 2691 sdio_release_host(bus->sdiodev->func[1]); 2692 2693 bus->ctrl_frame_stat = false; 2694 brcmf_sdio_wait_event_wakeup(bus); 2695 } 2696 up(&bus->tx_seq_lock); 2697 } 2698 /* Send queued frames (limit 1 if rx may still be pending) */ 2699 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && 2700 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && 2701 data_ok(bus)) { 2702 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : 2703 txlimit; 2704 brcmf_sdio_sendfromq(bus, framecnt); 2705 } 2706 2707 if (!brcmf_bus_ready(bus->sdiodev->bus_if) || (err != 0)) { 2708 brcmf_err("failed backplane access over SDIO, halting operation\n"); 2709 atomic_set(&bus->intstatus, 0); 2710 } else if (atomic_read(&bus->intstatus) || 2711 atomic_read(&bus->ipend) > 0 || 2712 (!atomic_read(&bus->fcstate) && 2713 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && 2714 data_ok(bus))) { 2715 atomic_inc(&bus->dpc_tskcnt); 2716 } 2717} 2718 2719static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) 2720{ 2721 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2722 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2723 struct brcmf_sdio *bus = sdiodev->bus; 2724 2725 return &bus->txq; 2726} 2727 2728static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) 2729{ 2730 int ret = -EBADE; 2731 uint prec; 2732 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2733 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2734 struct brcmf_sdio *bus = sdiodev->bus; 2735 2736 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); 2737 2738 /* Add space for the header */ 2739 skb_push(pkt, bus->tx_hdrlen); 2740 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ 2741 2742 prec = prio2prec((pkt->priority & PRIOMASK)); 2743 2744 /* Check for existing queue, current flow-control, 2745 pending event, or pending clock */ 2746 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); 2747 bus->sdcnt.fcqueued++; 2748 2749 /* Priority based enq */ 2750 spin_lock_bh(&bus->txq_lock); 2751 /* reset bus_flags in packet cb */ 2752 *(u16 *)(pkt->cb) = 0; 2753 if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) { 2754 skb_pull(pkt, bus->tx_hdrlen); 2755 brcmf_err("out of bus->txq !!!\n"); 2756 ret = -ENOSR; 2757 } else { 2758 ret = 0; 2759 } 2760 2761 if (pktq_len(&bus->txq) >= TXHI) { 2762 bus->txoff = true; 2763 brcmf_txflowblock(bus->sdiodev->dev, true); 2764 } 2765 spin_unlock_bh(&bus->txq_lock); 2766 2767#ifdef DEBUG 2768 if (pktq_plen(&bus->txq, prec) > qcount[prec]) 2769 qcount[prec] = pktq_plen(&bus->txq, prec); 2770#endif 2771 2772 if (atomic_read(&bus->dpc_tskcnt) == 0) { 2773 atomic_inc(&bus->dpc_tskcnt); 2774 queue_work(bus->brcmf_wq, &bus->datawork); 2775 } 2776 2777 return ret; 2778} 2779 2780#ifdef DEBUG 2781#define CONSOLE_LINE_MAX 192 2782 2783static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) 2784{ 2785 struct brcmf_console *c = &bus->console; 2786 u8 line[CONSOLE_LINE_MAX], ch; 2787 u32 n, idx, addr; 2788 int rv; 2789 2790 /* Don't do anything until FWREADY updates console address */ 2791 if (bus->console_addr == 0) 2792 return 0; 2793 2794 /* Read console log struct */ 2795 addr = bus->console_addr + offsetof(struct rte_console, log_le); 2796 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, 2797 sizeof(c->log_le)); 2798 if (rv < 0) 2799 return rv; 2800 2801 /* Allocate console buffer (one time only) */ 2802 if (c->buf == NULL) { 2803 c->bufsize = le32_to_cpu(c->log_le.buf_size); 2804 c->buf = kmalloc(c->bufsize, GFP_ATOMIC); 2805 if (c->buf == NULL) 2806 return -ENOMEM; 2807 } 2808 2809 idx = le32_to_cpu(c->log_le.idx); 2810 2811 /* Protect against corrupt value */ 2812 if (idx > c->bufsize) 2813 return -EBADE; 2814 2815 /* Skip reading the console buffer if the index pointer 2816 has not moved */ 2817 if (idx == c->last) 2818 return 0; 2819 2820 /* Read the console buffer */ 2821 addr = le32_to_cpu(c->log_le.buf); 2822 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); 2823 if (rv < 0) 2824 return rv; 2825 2826 while (c->last != idx) { 2827 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { 2828 if (c->last == idx) { 2829 /* This would output a partial line. 2830 * Instead, back up 2831 * the buffer pointer and output this 2832 * line next time around. 2833 */ 2834 if (c->last >= n) 2835 c->last -= n; 2836 else 2837 c->last = c->bufsize - n; 2838 goto break2; 2839 } 2840 ch = c->buf[c->last]; 2841 c->last = (c->last + 1) % c->bufsize; 2842 if (ch == '\n') 2843 break; 2844 line[n] = ch; 2845 } 2846 2847 if (n > 0) { 2848 if (line[n - 1] == '\r') 2849 n--; 2850 line[n] = 0; 2851 pr_debug("CONSOLE: %s\n", line); 2852 } 2853 } 2854break2: 2855 2856 return 0; 2857} 2858#endif /* DEBUG */ 2859 2860static int 2861brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) 2862{ 2863 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2864 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2865 struct brcmf_sdio *bus = sdiodev->bus; 2866 int ret = -1; 2867 2868 brcmf_dbg(TRACE, "Enter\n"); 2869 2870 if (down_interruptible(&bus->tx_seq_lock)) 2871 return -EINTR; 2872 2873 if (!data_ok(bus)) { 2874 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n", 2875 bus->tx_max, bus->tx_seq); 2876 up(&bus->tx_seq_lock); 2877 /* Send from dpc */ 2878 bus->ctrl_frame_buf = msg; 2879 bus->ctrl_frame_len = msglen; 2880 bus->ctrl_frame_stat = true; 2881 2882 wait_event_interruptible_timeout(bus->ctrl_wait, 2883 !bus->ctrl_frame_stat, 2884 msecs_to_jiffies(2000)); 2885 2886 if (!bus->ctrl_frame_stat) { 2887 brcmf_dbg(SDIO, "ctrl_frame_stat == false\n"); 2888 ret = 0; 2889 } else { 2890 brcmf_dbg(SDIO, "ctrl_frame_stat == true\n"); 2891 bus->ctrl_frame_stat = false; 2892 if (down_interruptible(&bus->tx_seq_lock)) 2893 return -EINTR; 2894 ret = -1; 2895 } 2896 } 2897 if (ret == -1) { 2898 sdio_claim_host(bus->sdiodev->func[1]); 2899 brcmf_sdio_bus_sleep(bus, false, false); 2900 ret = brcmf_sdio_tx_ctrlframe(bus, msg, msglen); 2901 sdio_release_host(bus->sdiodev->func[1]); 2902 up(&bus->tx_seq_lock); 2903 } 2904 2905 if (ret) 2906 bus->sdcnt.tx_ctlerrs++; 2907 else 2908 bus->sdcnt.tx_ctlpkts++; 2909 2910 return ret ? -EIO : 0; 2911} 2912 2913#ifdef DEBUG 2914static int brcmf_sdio_dump_console(struct brcmf_sdio *bus, 2915 struct sdpcm_shared *sh, char __user *data, 2916 size_t count) 2917{ 2918 u32 addr, console_ptr, console_size, console_index; 2919 char *conbuf = NULL; 2920 __le32 sh_val; 2921 int rv; 2922 loff_t pos = 0; 2923 int nbytes = 0; 2924 2925 /* obtain console information from device memory */ 2926 addr = sh->console_addr + offsetof(struct rte_console, log_le); 2927 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2928 (u8 *)&sh_val, sizeof(u32)); 2929 if (rv < 0) 2930 return rv; 2931 console_ptr = le32_to_cpu(sh_val); 2932 2933 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); 2934 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2935 (u8 *)&sh_val, sizeof(u32)); 2936 if (rv < 0) 2937 return rv; 2938 console_size = le32_to_cpu(sh_val); 2939 2940 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); 2941 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2942 (u8 *)&sh_val, sizeof(u32)); 2943 if (rv < 0) 2944 return rv; 2945 console_index = le32_to_cpu(sh_val); 2946 2947 /* allocate buffer for console data */ 2948 if (console_size <= CONSOLE_BUFFER_MAX) 2949 conbuf = vzalloc(console_size+1); 2950 2951 if (!conbuf) 2952 return -ENOMEM; 2953 2954 /* obtain the console data from device */ 2955 conbuf[console_size] = '\0'; 2956 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, 2957 console_size); 2958 if (rv < 0) 2959 goto done; 2960 2961 rv = simple_read_from_buffer(data, count, &pos, 2962 conbuf + console_index, 2963 console_size - console_index); 2964 if (rv < 0) 2965 goto done; 2966 2967 nbytes = rv; 2968 if (console_index > 0) { 2969 pos = 0; 2970 rv = simple_read_from_buffer(data+nbytes, count, &pos, 2971 conbuf, console_index - 1); 2972 if (rv < 0) 2973 goto done; 2974 rv += nbytes; 2975 } 2976done: 2977 vfree(conbuf); 2978 return rv; 2979} 2980 2981static int brcmf_sdio_trap_info(struct brcmf_sdio *bus, struct sdpcm_shared *sh, 2982 char __user *data, size_t count) 2983{ 2984 int error, res; 2985 char buf[350]; 2986 struct brcmf_trap_info tr; 2987 loff_t pos = 0; 2988 2989 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { 2990 brcmf_dbg(INFO, "no trap in firmware\n"); 2991 return 0; 2992 } 2993 2994 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, 2995 sizeof(struct brcmf_trap_info)); 2996 if (error < 0) 2997 return error; 2998 2999 res = scnprintf(buf, sizeof(buf), 3000 "dongle trap info: type 0x%x @ epc 0x%08x\n" 3001 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 3002 " lr 0x%08x pc 0x%08x offset 0x%x\n" 3003 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 3004 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 3005 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 3006 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 3007 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 3008 le32_to_cpu(tr.pc), sh->trap_addr, 3009 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 3010 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 3011 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 3012 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 3013 3014 return simple_read_from_buffer(data, count, &pos, buf, res); 3015} 3016 3017static int brcmf_sdio_assert_info(struct brcmf_sdio *bus, 3018 struct sdpcm_shared *sh, char __user *data, 3019 size_t count) 3020{ 3021 int error = 0; 3022 char buf[200]; 3023 char file[80] = "?"; 3024 char expr[80] = "<???>"; 3025 int res; 3026 loff_t pos = 0; 3027 3028 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { 3029 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3030 return 0; 3031 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { 3032 brcmf_dbg(INFO, "no assert in dongle\n"); 3033 return 0; 3034 } 3035 3036 sdio_claim_host(bus->sdiodev->func[1]); 3037 if (sh->assert_file_addr != 0) { 3038 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3039 sh->assert_file_addr, (u8 *)file, 80); 3040 if (error < 0) 3041 return error; 3042 } 3043 if (sh->assert_exp_addr != 0) { 3044 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3045 sh->assert_exp_addr, (u8 *)expr, 80); 3046 if (error < 0) 3047 return error; 3048 } 3049 sdio_release_host(bus->sdiodev->func[1]); 3050 3051 res = scnprintf(buf, sizeof(buf), 3052 "dongle assert: %s:%d: assert(%s)\n", 3053 file, sh->assert_line, expr); 3054 return simple_read_from_buffer(data, count, &pos, buf, res); 3055} 3056 3057static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3058{ 3059 int error; 3060 struct sdpcm_shared sh; 3061 3062 error = brcmf_sdio_readshared(bus, &sh); 3063 3064 if (error < 0) 3065 return error; 3066 3067 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) 3068 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3069 else if (sh.flags & SDPCM_SHARED_ASSERT) 3070 brcmf_err("assertion in dongle\n"); 3071 3072 if (sh.flags & SDPCM_SHARED_TRAP) 3073 brcmf_err("firmware trap in dongle\n"); 3074 3075 return 0; 3076} 3077 3078static int brcmf_sdio_died_dump(struct brcmf_sdio *bus, char __user *data, 3079 size_t count, loff_t *ppos) 3080{ 3081 int error = 0; 3082 struct sdpcm_shared sh; 3083 int nbytes = 0; 3084 loff_t pos = *ppos; 3085 3086 if (pos != 0) 3087 return 0; 3088 3089 error = brcmf_sdio_readshared(bus, &sh); 3090 if (error < 0) 3091 goto done; 3092 3093 error = brcmf_sdio_assert_info(bus, &sh, data, count); 3094 if (error < 0) 3095 goto done; 3096 nbytes = error; 3097 3098 error = brcmf_sdio_trap_info(bus, &sh, data+nbytes, count); 3099 if (error < 0) 3100 goto done; 3101 nbytes += error; 3102 3103 error = brcmf_sdio_dump_console(bus, &sh, data+nbytes, count); 3104 if (error < 0) 3105 goto done; 3106 nbytes += error; 3107 3108 error = nbytes; 3109 *ppos += nbytes; 3110done: 3111 return error; 3112} 3113 3114static ssize_t brcmf_sdio_forensic_read(struct file *f, char __user *data, 3115 size_t count, loff_t *ppos) 3116{ 3117 struct brcmf_sdio *bus = f->private_data; 3118 int res; 3119 3120 res = brcmf_sdio_died_dump(bus, data, count, ppos); 3121 if (res > 0) 3122 *ppos += res; 3123 return (ssize_t)res; 3124} 3125 3126static const struct file_operations brcmf_sdio_forensic_ops = { 3127 .owner = THIS_MODULE, 3128 .open = simple_open, 3129 .read = brcmf_sdio_forensic_read 3130}; 3131 3132static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) 3133{ 3134 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; 3135 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 3136 3137 if (IS_ERR_OR_NULL(dentry)) 3138 return; 3139 3140 debugfs_create_file("forensics", S_IRUGO, dentry, bus, 3141 &brcmf_sdio_forensic_ops); 3142 brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt); 3143 debugfs_create_u32("console_interval", 0644, dentry, 3144 &bus->console_interval); 3145} 3146#else 3147static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3148{ 3149 return 0; 3150} 3151 3152static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) 3153{ 3154} 3155#endif /* DEBUG */ 3156 3157static int 3158brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) 3159{ 3160 int timeleft; 3161 uint rxlen = 0; 3162 bool pending; 3163 u8 *buf; 3164 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3165 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3166 struct brcmf_sdio *bus = sdiodev->bus; 3167 3168 brcmf_dbg(TRACE, "Enter\n"); 3169 3170 /* Wait until control frame is available */ 3171 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); 3172 3173 spin_lock_bh(&bus->rxctl_lock); 3174 rxlen = bus->rxlen; 3175 memcpy(msg, bus->rxctl, min(msglen, rxlen)); 3176 bus->rxctl = NULL; 3177 buf = bus->rxctl_orig; 3178 bus->rxctl_orig = NULL; 3179 bus->rxlen = 0; 3180 spin_unlock_bh(&bus->rxctl_lock); 3181 vfree(buf); 3182 3183 if (rxlen) { 3184 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", 3185 rxlen, msglen); 3186 } else if (timeleft == 0) { 3187 brcmf_err("resumed on timeout\n"); 3188 brcmf_sdio_checkdied(bus); 3189 } else if (pending) { 3190 brcmf_dbg(CTL, "cancelled\n"); 3191 return -ERESTARTSYS; 3192 } else { 3193 brcmf_dbg(CTL, "resumed for unknown reason?\n"); 3194 brcmf_sdio_checkdied(bus); 3195 } 3196 3197 if (rxlen) 3198 bus->sdcnt.rx_ctlpkts++; 3199 else 3200 bus->sdcnt.rx_ctlerrs++; 3201 3202 return rxlen ? (int)rxlen : -ETIMEDOUT; 3203} 3204 3205#ifdef DEBUG 3206static bool 3207brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3208 u8 *ram_data, uint ram_sz) 3209{ 3210 char *ram_cmp; 3211 int err; 3212 bool ret = true; 3213 int address; 3214 int offset; 3215 int len; 3216 3217 /* read back and verify */ 3218 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, 3219 ram_sz); 3220 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); 3221 /* do not proceed while no memory but */ 3222 if (!ram_cmp) 3223 return true; 3224 3225 address = ram_addr; 3226 offset = 0; 3227 while (offset < ram_sz) { 3228 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : 3229 ram_sz - offset; 3230 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); 3231 if (err) { 3232 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3233 err, len, address); 3234 ret = false; 3235 break; 3236 } else if (memcmp(ram_cmp, &ram_data[offset], len)) { 3237 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", 3238 offset, len); 3239 ret = false; 3240 break; 3241 } 3242 offset += len; 3243 address += len; 3244 } 3245 3246 kfree(ram_cmp); 3247 3248 return ret; 3249} 3250#else /* DEBUG */ 3251static bool 3252brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3253 u8 *ram_data, uint ram_sz) 3254{ 3255 return true; 3256} 3257#endif /* DEBUG */ 3258 3259static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, 3260 const struct firmware *fw) 3261{ 3262 int err; 3263 3264 brcmf_dbg(TRACE, "Enter\n"); 3265 3266 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, 3267 (u8 *)fw->data, fw->size); 3268 if (err) 3269 brcmf_err("error %d on writing %d membytes at 0x%08x\n", 3270 err, (int)fw->size, bus->ci->rambase); 3271 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, 3272 (u8 *)fw->data, fw->size)) 3273 err = -EIO; 3274 3275 return err; 3276} 3277 3278static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, 3279 const struct firmware *nv) 3280{ 3281 void *vars; 3282 u32 varsz; 3283 int address; 3284 int err; 3285 3286 brcmf_dbg(TRACE, "Enter\n"); 3287 3288 vars = brcmf_nvram_strip(nv, &varsz); 3289 3290 if (vars == NULL) 3291 return -EINVAL; 3292 3293 address = bus->ci->ramsize - varsz + bus->ci->rambase; 3294 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); 3295 if (err) 3296 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", 3297 err, varsz, address); 3298 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) 3299 err = -EIO; 3300 3301 brcmf_nvram_free(vars); 3302 3303 return err; 3304} 3305 3306static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus) 3307{ 3308 int bcmerror = -EFAULT; 3309 const struct firmware *fw; 3310 u32 rstvec; 3311 3312 sdio_claim_host(bus->sdiodev->func[1]); 3313 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 3314 3315 /* Keep arm in reset */ 3316 brcmf_chip_enter_download(bus->ci); 3317 3318 fw = brcmf_sdio_get_fw(bus, BRCMF_FIRMWARE_BIN); 3319 if (fw == NULL) { 3320 bcmerror = -ENOENT; 3321 goto err; 3322 } 3323 3324 rstvec = get_unaligned_le32(fw->data); 3325 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); 3326 3327 bcmerror = brcmf_sdio_download_code_file(bus, fw); 3328 release_firmware(fw); 3329 if (bcmerror) { 3330 brcmf_err("dongle image file download failed\n"); 3331 goto err; 3332 } 3333 3334 fw = brcmf_sdio_get_fw(bus, BRCMF_FIRMWARE_NVRAM); 3335 if (fw == NULL) { 3336 bcmerror = -ENOENT; 3337 goto err; 3338 } 3339 3340 bcmerror = brcmf_sdio_download_nvram(bus, fw); 3341 release_firmware(fw); 3342 if (bcmerror) { 3343 brcmf_err("dongle nvram file download failed\n"); 3344 goto err; 3345 } 3346 3347 /* Take arm out of reset */ 3348 if (!brcmf_chip_exit_download(bus->ci, rstvec)) { 3349 brcmf_err("error getting out of ARM core reset\n"); 3350 goto err; 3351 } 3352 3353 /* Allow HT Clock now that the ARM is running. */ 3354 brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_LOAD); 3355 bcmerror = 0; 3356 3357err: 3358 brcmf_sdio_clkctl(bus, CLK_SDONLY, false); 3359 sdio_release_host(bus->sdiodev->func[1]); 3360 return bcmerror; 3361} 3362 3363static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) 3364{ 3365 int err = 0; 3366 u8 val; 3367 3368 brcmf_dbg(TRACE, "Enter\n"); 3369 3370 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); 3371 if (err) { 3372 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); 3373 return; 3374 } 3375 3376 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; 3377 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); 3378 if (err) { 3379 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); 3380 return; 3381 } 3382 3383 /* Add CMD14 Support */ 3384 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, 3385 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | 3386 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT), 3387 &err); 3388 if (err) { 3389 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); 3390 return; 3391 } 3392 3393 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3394 SBSDIO_FORCE_HT, &err); 3395 if (err) { 3396 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); 3397 return; 3398 } 3399 3400 /* set flag */ 3401 bus->sr_enabled = true; 3402 brcmf_dbg(INFO, "SR enabled\n"); 3403} 3404 3405/* enable KSO bit */ 3406static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) 3407{ 3408 u8 val; 3409 int err = 0; 3410 3411 brcmf_dbg(TRACE, "Enter\n"); 3412 3413 /* KSO bit added in SDIO core rev 12 */ 3414 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) 3415 return 0; 3416 3417 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); 3418 if (err) { 3419 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); 3420 return err; 3421 } 3422 3423 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { 3424 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << 3425 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 3426 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 3427 val, &err); 3428 if (err) { 3429 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); 3430 return err; 3431 } 3432 } 3433 3434 return 0; 3435} 3436 3437 3438static int brcmf_sdio_bus_preinit(struct device *dev) 3439{ 3440 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3441 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3442 struct brcmf_sdio *bus = sdiodev->bus; 3443 uint pad_size; 3444 u32 value; 3445 int err; 3446 3447 /* the commands below use the terms tx and rx from 3448 * a device perspective, ie. bus:txglom affects the 3449 * bus transfers from device to host. 3450 */ 3451 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) { 3452 /* for sdio core rev < 12, disable txgloming */ 3453 value = 0; 3454 err = brcmf_iovar_data_set(dev, "bus:txglom", &value, 3455 sizeof(u32)); 3456 } else { 3457 /* otherwise, set txglomalign */ 3458 value = 4; 3459 if (sdiodev->pdata) 3460 value = sdiodev->pdata->sd_sgentry_align; 3461 /* SDIO ADMA requires at least 32 bit alignment */ 3462 value = max_t(u32, value, 4); 3463 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value, 3464 sizeof(u32)); 3465 } 3466 3467 if (err < 0) 3468 goto done; 3469 3470 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 3471 if (sdiodev->sg_support) { 3472 bus->txglom = false; 3473 value = 1; 3474 pad_size = bus->sdiodev->func[2]->cur_blksize << 1; 3475 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", 3476 &value, sizeof(u32)); 3477 if (err < 0) { 3478 /* bus:rxglom is allowed to fail */ 3479 err = 0; 3480 } else { 3481 bus->txglom = true; 3482 bus->tx_hdrlen += SDPCM_HWEXT_LEN; 3483 } 3484 } 3485 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); 3486 3487done: 3488 return err; 3489} 3490 3491static int brcmf_sdio_bus_init(struct device *dev) 3492{ 3493 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3494 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3495 struct brcmf_sdio *bus = sdiodev->bus; 3496 int err, ret = 0; 3497 u8 saveclk; 3498 3499 brcmf_dbg(TRACE, "Enter\n"); 3500 3501 /* try to download image and nvram to the dongle */ 3502 if (bus_if->state == BRCMF_BUS_DOWN) { 3503 bus->alp_only = true; 3504 err = brcmf_sdio_download_firmware(bus); 3505 if (err) 3506 return err; 3507 bus->alp_only = false; 3508 } 3509 3510 if (!bus->sdiodev->bus_if->drvr) 3511 return 0; 3512 3513 /* Start the watchdog timer */ 3514 bus->sdcnt.tickcnt = 0; 3515 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); 3516 3517 sdio_claim_host(bus->sdiodev->func[1]); 3518 3519 /* Make sure backplane clock is on, needed to generate F2 interrupt */ 3520 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 3521 if (bus->clkstate != CLK_AVAIL) 3522 goto exit; 3523 3524 /* Force clocks on backplane to be sure F2 interrupt propagates */ 3525 saveclk = brcmf_sdiod_regrb(bus->sdiodev, 3526 SBSDIO_FUNC1_CHIPCLKCSR, &err); 3527 if (!err) { 3528 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3529 (saveclk | SBSDIO_FORCE_HT), &err); 3530 } 3531 if (err) { 3532 brcmf_err("Failed to force clock for F2: err %d\n", err); 3533 goto exit; 3534 } 3535 3536 /* Enable function 2 (frame transfers) */ 3537 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, 3538 offsetof(struct sdpcmd_regs, tosbmailboxdata)); 3539 err = sdio_enable_func(bus->sdiodev->func[SDIO_FUNC_2]); 3540 3541 3542 brcmf_dbg(INFO, "enable F2: err=%d\n", err); 3543 3544 /* If F2 successfully enabled, set core and enable interrupts */ 3545 if (!err) { 3546 /* Set up the interrupt mask and enable interrupts */ 3547 bus->hostintmask = HOSTINTMASK; 3548 w_sdreg32(bus, bus->hostintmask, 3549 offsetof(struct sdpcmd_regs, hostintmask)); 3550 3551 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_WATERMARK, 8, &err); 3552 } else { 3553 /* Disable F2 again */ 3554 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]); 3555 ret = -ENODEV; 3556 } 3557 3558 if (brcmf_chip_sr_capable(bus->ci)) { 3559 brcmf_sdio_sr_init(bus); 3560 } else { 3561 /* Restore previous clock setting */ 3562 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3563 saveclk, &err); 3564 } 3565 3566 if (ret == 0) { 3567 ret = brcmf_sdiod_intr_register(bus->sdiodev); 3568 if (ret != 0) 3569 brcmf_err("intr register failed:%d\n", ret); 3570 } 3571 3572 /* If we didn't come up, turn off backplane clock */ 3573 if (ret != 0) 3574 brcmf_sdio_clkctl(bus, CLK_NONE, false); 3575 3576exit: 3577 sdio_release_host(bus->sdiodev->func[1]); 3578 3579 return ret; 3580} 3581 3582void brcmf_sdio_isr(struct brcmf_sdio *bus) 3583{ 3584 brcmf_dbg(TRACE, "Enter\n"); 3585 3586 if (!bus) { 3587 brcmf_err("bus is null pointer, exiting\n"); 3588 return; 3589 } 3590 3591 if (!brcmf_bus_ready(bus->sdiodev->bus_if)) { 3592 brcmf_err("bus is down. we have nothing to do\n"); 3593 return; 3594 } 3595 /* Count the interrupt call */ 3596 bus->sdcnt.intrcount++; 3597 if (in_interrupt()) 3598 atomic_set(&bus->ipend, 1); 3599 else 3600 if (brcmf_sdio_intr_rstatus(bus)) { 3601 brcmf_err("failed backplane access\n"); 3602 } 3603 3604 /* Disable additional interrupts (is this needed now)? */ 3605 if (!bus->intr) 3606 brcmf_err("isr w/o interrupt configured!\n"); 3607 3608 atomic_inc(&bus->dpc_tskcnt); 3609 queue_work(bus->brcmf_wq, &bus->datawork); 3610} 3611 3612static bool brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) 3613{ 3614#ifdef DEBUG 3615 struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev); 3616#endif /* DEBUG */ 3617 3618 brcmf_dbg(TIMER, "Enter\n"); 3619 3620 /* Poll period: check device if appropriate. */ 3621 if (!bus->sr_enabled && 3622 bus->poll && (++bus->polltick >= bus->pollrate)) { 3623 u32 intstatus = 0; 3624 3625 /* Reset poll tick */ 3626 bus->polltick = 0; 3627 3628 /* Check device if no interrupts */ 3629 if (!bus->intr || 3630 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { 3631 3632 if (atomic_read(&bus->dpc_tskcnt) == 0) { 3633 u8 devpend; 3634 3635 sdio_claim_host(bus->sdiodev->func[1]); 3636 devpend = brcmf_sdiod_regrb(bus->sdiodev, 3637 SDIO_CCCR_INTx, 3638 NULL); 3639 sdio_release_host(bus->sdiodev->func[1]); 3640 intstatus = 3641 devpend & (INTR_STATUS_FUNC1 | 3642 INTR_STATUS_FUNC2); 3643 } 3644 3645 /* If there is something, make like the ISR and 3646 schedule the DPC */ 3647 if (intstatus) { 3648 bus->sdcnt.pollcnt++; 3649 atomic_set(&bus->ipend, 1); 3650 3651 atomic_inc(&bus->dpc_tskcnt); 3652 queue_work(bus->brcmf_wq, &bus->datawork); 3653 } 3654 } 3655 3656 /* Update interrupt tracking */ 3657 bus->sdcnt.lastintrs = bus->sdcnt.intrcount; 3658 } 3659#ifdef DEBUG 3660 /* Poll for console output periodically */ 3661 if (bus_if && bus_if->state == BRCMF_BUS_DATA && 3662 bus->console_interval != 0) { 3663 bus->console.count += BRCMF_WD_POLL_MS; 3664 if (bus->console.count >= bus->console_interval) { 3665 bus->console.count -= bus->console_interval; 3666 sdio_claim_host(bus->sdiodev->func[1]); 3667 /* Make sure backplane clock is on */ 3668 brcmf_sdio_bus_sleep(bus, false, false); 3669 if (brcmf_sdio_readconsole(bus) < 0) 3670 /* stop on error */ 3671 bus->console_interval = 0; 3672 sdio_release_host(bus->sdiodev->func[1]); 3673 } 3674 } 3675#endif /* DEBUG */ 3676 3677 /* On idle timeout clear activity flag and/or turn off clock */ 3678 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) { 3679 if (++bus->idlecount >= bus->idletime) { 3680 bus->idlecount = 0; 3681 if (bus->activity) { 3682 bus->activity = false; 3683 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS); 3684 } else { 3685 brcmf_dbg(SDIO, "idle\n"); 3686 sdio_claim_host(bus->sdiodev->func[1]); 3687 brcmf_sdio_bus_sleep(bus, true, false); 3688 sdio_release_host(bus->sdiodev->func[1]); 3689 } 3690 } 3691 } 3692 3693 return (atomic_read(&bus->ipend) > 0); 3694} 3695 3696static void brcmf_sdio_dataworker(struct work_struct *work) 3697{ 3698 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, 3699 datawork); 3700 3701 while (atomic_read(&bus->dpc_tskcnt)) { 3702 atomic_set(&bus->dpc_tskcnt, 0); 3703 brcmf_sdio_dpc(bus); 3704 } 3705} 3706 3707static void 3708brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, 3709 struct brcmf_chip *ci, u32 drivestrength) 3710{ 3711 const struct sdiod_drive_str *str_tab = NULL; 3712 u32 str_mask; 3713 u32 str_shift; 3714 u32 base; 3715 u32 i; 3716 u32 drivestrength_sel = 0; 3717 u32 cc_data_temp; 3718 u32 addr; 3719 3720 if (!(ci->cc_caps & CC_CAP_PMU)) 3721 return; 3722 3723 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { 3724 case SDIOD_DRVSTR_KEY(BCM4330_CHIP_ID, 12): 3725 str_tab = sdiod_drvstr_tab1_1v8; 3726 str_mask = 0x00003800; 3727 str_shift = 11; 3728 break; 3729 case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17): 3730 str_tab = sdiod_drvstr_tab6_1v8; 3731 str_mask = 0x00001800; 3732 str_shift = 11; 3733 break; 3734 case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17): 3735 /* note: 43143 does not support tristate */ 3736 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; 3737 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { 3738 str_tab = sdiod_drvstr_tab2_3v3; 3739 str_mask = 0x00000007; 3740 str_shift = 0; 3741 } else 3742 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", 3743 ci->name, drivestrength); 3744 break; 3745 case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13): 3746 str_tab = sdiod_drive_strength_tab5_1v8; 3747 str_mask = 0x00003800; 3748 str_shift = 11; 3749 break; 3750 default: 3751 brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", 3752 ci->name, ci->chiprev, ci->pmurev); 3753 break; 3754 } 3755 3756 if (str_tab != NULL) { 3757 for (i = 0; str_tab[i].strength != 0; i++) { 3758 if (drivestrength >= str_tab[i].strength) { 3759 drivestrength_sel = str_tab[i].sel; 3760 break; 3761 } 3762 } 3763 base = brcmf_chip_get_chipcommon(ci)->base; 3764 addr = CORE_CC_REG(base, chipcontrol_addr); 3765 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL); 3766 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL); 3767 cc_data_temp &= ~str_mask; 3768 drivestrength_sel <<= str_shift; 3769 cc_data_temp |= drivestrength_sel; 3770 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL); 3771 3772 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", 3773 str_tab[i].strength, drivestrength, cc_data_temp); 3774 } 3775} 3776 3777static int brcmf_sdio_buscoreprep(void *ctx) 3778{ 3779 struct brcmf_sdio_dev *sdiodev = ctx; 3780 int err = 0; 3781 u8 clkval, clkset; 3782 3783 /* Try forcing SDIO core to do ALPAvail request only */ 3784 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; 3785 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3786 if (err) { 3787 brcmf_err("error writing for HT off\n"); 3788 return err; 3789 } 3790 3791 /* If register supported, wait for ALPAvail and then force ALP */ 3792 /* This may take up to 15 milliseconds */ 3793 clkval = brcmf_sdiod_regrb(sdiodev, 3794 SBSDIO_FUNC1_CHIPCLKCSR, NULL); 3795 3796 if ((clkval & ~SBSDIO_AVBITS) != clkset) { 3797 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", 3798 clkset, clkval); 3799 return -EACCES; 3800 } 3801 3802 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev, 3803 SBSDIO_FUNC1_CHIPCLKCSR, NULL)), 3804 !SBSDIO_ALPAV(clkval)), 3805 PMU_MAX_TRANSITION_DLY); 3806 if (!SBSDIO_ALPAV(clkval)) { 3807 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", 3808 clkval); 3809 return -EBUSY; 3810 } 3811 3812 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; 3813 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3814 udelay(65); 3815 3816 /* Also, disable the extra SDIO pull-ups */ 3817 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); 3818 3819 return 0; 3820} 3821 3822static void brcmf_sdio_buscore_exitdl(void *ctx, struct brcmf_chip *chip, 3823 u32 rstvec) 3824{ 3825 struct brcmf_sdio_dev *sdiodev = ctx; 3826 struct brcmf_core *core; 3827 u32 reg_addr; 3828 3829 /* clear all interrupts */ 3830 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV); 3831 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus); 3832 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL); 3833 3834 if (rstvec) 3835 /* Write reset vector to address 0 */ 3836 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, 3837 sizeof(rstvec)); 3838} 3839 3840static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) 3841{ 3842 struct brcmf_sdio_dev *sdiodev = ctx; 3843 u32 val, rev; 3844 3845 val = brcmf_sdiod_regrl(sdiodev, addr, NULL); 3846 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 && 3847 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) { 3848 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; 3849 if (rev >= 2) { 3850 val &= ~CID_ID_MASK; 3851 val |= BCM4339_CHIP_ID; 3852 } 3853 } 3854 return val; 3855} 3856 3857static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) 3858{ 3859 struct brcmf_sdio_dev *sdiodev = ctx; 3860 3861 brcmf_sdiod_regwl(sdiodev, addr, val, NULL); 3862} 3863 3864static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { 3865 .prepare = brcmf_sdio_buscoreprep, 3866 .exit_dl = brcmf_sdio_buscore_exitdl, 3867 .read32 = brcmf_sdio_buscore_read32, 3868 .write32 = brcmf_sdio_buscore_write32, 3869}; 3870 3871static bool 3872brcmf_sdio_probe_attach(struct brcmf_sdio *bus) 3873{ 3874 u8 clkctl = 0; 3875 int err = 0; 3876 int reg_addr; 3877 u32 reg_val; 3878 u32 drivestrength; 3879 3880 sdio_claim_host(bus->sdiodev->func[1]); 3881 3882 pr_debug("F1 signature read @0x18000000=0x%4x\n", 3883 brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL)); 3884 3885 /* 3886 * Force PLL off until brcmf_chip_attach() 3887 * programs PLL control regs 3888 */ 3889 3890 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3891 BRCMF_INIT_CLKCTL1, &err); 3892 if (!err) 3893 clkctl = brcmf_sdiod_regrb(bus->sdiodev, 3894 SBSDIO_FUNC1_CHIPCLKCSR, &err); 3895 3896 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { 3897 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", 3898 err, BRCMF_INIT_CLKCTL1, clkctl); 3899 goto fail; 3900 } 3901 3902 /* SDIO register access works so moving 3903 * state from UNKNOWN to DOWN. 3904 */ 3905 brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_DOWN); 3906 3907 bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops); 3908 if (IS_ERR(bus->ci)) { 3909 brcmf_err("brcmf_chip_attach failed!\n"); 3910 bus->ci = NULL; 3911 goto fail; 3912 } 3913 3914 if (brcmf_sdio_kso_init(bus)) { 3915 brcmf_err("error enabling KSO\n"); 3916 goto fail; 3917 } 3918 3919 if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength)) 3920 drivestrength = bus->sdiodev->pdata->drive_strength; 3921 else 3922 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; 3923 brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength); 3924 3925 /* Get info on the SOCRAM cores... */ 3926 bus->ramsize = bus->ci->ramsize; 3927 if (!(bus->ramsize)) { 3928 brcmf_err("failed to find SOCRAM memory!\n"); 3929 goto fail; 3930 } 3931 3932 /* Set card control so an SDIO card reset does a WLAN backplane reset */ 3933 reg_val = brcmf_sdiod_regrb(bus->sdiodev, 3934 SDIO_CCCR_BRCM_CARDCTRL, &err); 3935 if (err) 3936 goto fail; 3937 3938 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; 3939 3940 brcmf_sdiod_regwb(bus->sdiodev, 3941 SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); 3942 if (err) 3943 goto fail; 3944 3945 /* set PMUControl so a backplane reset does PMU state reload */ 3946 reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base, 3947 pmucontrol); 3948 reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err); 3949 if (err) 3950 goto fail; 3951 3952 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); 3953 3954 brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err); 3955 if (err) 3956 goto fail; 3957 3958 sdio_release_host(bus->sdiodev->func[1]); 3959 3960 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); 3961 3962 /* allocate header buffer */ 3963 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); 3964 if (!bus->hdrbuf) 3965 return false; 3966 /* Locate an appropriately-aligned portion of hdrbuf */ 3967 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], 3968 bus->head_align); 3969 3970 /* Set the poll and/or interrupt flags */ 3971 bus->intr = true; 3972 bus->poll = false; 3973 if (bus->poll) 3974 bus->pollrate = 1; 3975 3976 return true; 3977 3978fail: 3979 sdio_release_host(bus->sdiodev->func[1]); 3980 return false; 3981} 3982 3983static int 3984brcmf_sdio_watchdog_thread(void *data) 3985{ 3986 struct brcmf_sdio *bus = (struct brcmf_sdio *)data; 3987 3988 allow_signal(SIGTERM); 3989 /* Run until signal received */ 3990 while (1) { 3991 if (kthread_should_stop()) 3992 break; 3993 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) { 3994 brcmf_sdio_bus_watchdog(bus); 3995 /* Count the tick for reference */ 3996 bus->sdcnt.tickcnt++; 3997 } else 3998 break; 3999 } 4000 return 0; 4001} 4002 4003static void 4004brcmf_sdio_watchdog(unsigned long data) 4005{ 4006 struct brcmf_sdio *bus = (struct brcmf_sdio *)data; 4007 4008 if (bus->watchdog_tsk) { 4009 complete(&bus->watchdog_wait); 4010 /* Reschedule the watchdog */ 4011 if (bus->wd_timer_valid) 4012 mod_timer(&bus->timer, 4013 jiffies + BRCMF_WD_POLL_MS * HZ / 1000); 4014 } 4015} 4016 4017static struct brcmf_bus_ops brcmf_sdio_bus_ops = { 4018 .stop = brcmf_sdio_bus_stop, 4019 .preinit = brcmf_sdio_bus_preinit, 4020 .init = brcmf_sdio_bus_init, 4021 .txdata = brcmf_sdio_bus_txdata, 4022 .txctl = brcmf_sdio_bus_txctl, 4023 .rxctl = brcmf_sdio_bus_rxctl, 4024 .gettxq = brcmf_sdio_bus_gettxq, 4025}; 4026 4027struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) 4028{ 4029 int ret; 4030 struct brcmf_sdio *bus; 4031 4032 brcmf_dbg(TRACE, "Enter\n"); 4033 4034 /* Allocate private bus interface state */ 4035 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); 4036 if (!bus) 4037 goto fail; 4038 4039 bus->sdiodev = sdiodev; 4040 sdiodev->bus = bus; 4041 skb_queue_head_init(&bus->glom); 4042 bus->txbound = BRCMF_TXBOUND; 4043 bus->rxbound = BRCMF_RXBOUND; 4044 bus->txminmax = BRCMF_TXMINMAX; 4045 bus->tx_seq = SDPCM_SEQ_WRAP - 1; 4046 4047 /* platform specific configuration: 4048 * alignments must be at least 4 bytes for ADMA 4049 */ 4050 bus->head_align = ALIGNMENT; 4051 bus->sgentry_align = ALIGNMENT; 4052 if (sdiodev->pdata) { 4053 if (sdiodev->pdata->sd_head_align > ALIGNMENT) 4054 bus->head_align = sdiodev->pdata->sd_head_align; 4055 if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT) 4056 bus->sgentry_align = sdiodev->pdata->sd_sgentry_align; 4057 } 4058 4059 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); 4060 bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq"); 4061 if (bus->brcmf_wq == NULL) { 4062 brcmf_err("insufficient memory to create txworkqueue\n"); 4063 goto fail; 4064 } 4065 4066 /* attempt to attach to the dongle */ 4067 if (!(brcmf_sdio_probe_attach(bus))) { 4068 brcmf_err("brcmf_sdio_probe_attach failed\n"); 4069 goto fail; 4070 } 4071 4072 spin_lock_init(&bus->rxctl_lock); 4073 spin_lock_init(&bus->txq_lock); 4074 sema_init(&bus->tx_seq_lock, 1); 4075 init_waitqueue_head(&bus->ctrl_wait); 4076 init_waitqueue_head(&bus->dcmd_resp_wait); 4077 4078 /* Set up the watchdog timer */ 4079 init_timer(&bus->timer); 4080 bus->timer.data = (unsigned long)bus; 4081 bus->timer.function = brcmf_sdio_watchdog; 4082 4083 /* Initialize watchdog thread */ 4084 init_completion(&bus->watchdog_wait); 4085 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, 4086 bus, "brcmf_watchdog"); 4087 if (IS_ERR(bus->watchdog_tsk)) { 4088 pr_warn("brcmf_watchdog thread failed to start\n"); 4089 bus->watchdog_tsk = NULL; 4090 } 4091 /* Initialize DPC thread */ 4092 atomic_set(&bus->dpc_tskcnt, 0); 4093 4094 /* Assign bus interface call back */ 4095 bus->sdiodev->bus_if->dev = bus->sdiodev->dev; 4096 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops; 4097 bus->sdiodev->bus_if->chip = bus->ci->chip; 4098 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev; 4099 4100 /* default sdio bus header length for tx packet */ 4101 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 4102 4103 /* Attach to the common layer, reserve hdr space */ 4104 ret = brcmf_attach(bus->sdiodev->dev); 4105 if (ret != 0) { 4106 brcmf_err("brcmf_attach failed\n"); 4107 goto fail; 4108 } 4109 4110 /* Allocate buffers */ 4111 if (bus->sdiodev->bus_if->maxctl) { 4112 bus->rxblen = 4113 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN), 4114 ALIGNMENT) + bus->head_align; 4115 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); 4116 if (!(bus->rxbuf)) { 4117 brcmf_err("rxbuf allocation failed\n"); 4118 goto fail; 4119 } 4120 } 4121 4122 sdio_claim_host(bus->sdiodev->func[1]); 4123 4124 /* Disable F2 to clear any intermediate frame state on the dongle */ 4125 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]); 4126 4127 bus->rxflow = false; 4128 4129 /* Done with backplane-dependent accesses, can drop clock... */ 4130 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); 4131 4132 sdio_release_host(bus->sdiodev->func[1]); 4133 4134 /* ...and initialize clock/power states */ 4135 bus->clkstate = CLK_SDONLY; 4136 bus->idletime = BRCMF_IDLE_INTERVAL; 4137 bus->idleclock = BRCMF_IDLE_ACTIVE; 4138 4139 /* Query the F2 block size, set roundup accordingly */ 4140 bus->blocksize = bus->sdiodev->func[2]->cur_blksize; 4141 bus->roundup = min(max_roundup, bus->blocksize); 4142 4143 /* SR state */ 4144 bus->sleeping = false; 4145 bus->sr_enabled = false; 4146 4147 brcmf_sdio_debugfs_create(bus); 4148 brcmf_dbg(INFO, "completed!!\n"); 4149 4150 /* if firmware path present try to download and bring up bus */ 4151 ret = brcmf_bus_start(bus->sdiodev->dev); 4152 if (ret != 0) { 4153 brcmf_err("dongle is not responding\n"); 4154 goto fail; 4155 } 4156 4157 return bus; 4158 4159fail: 4160 brcmf_sdio_remove(bus); 4161 return NULL; 4162} 4163 4164/* Detach and free everything */ 4165void brcmf_sdio_remove(struct brcmf_sdio *bus) 4166{ 4167 brcmf_dbg(TRACE, "Enter\n"); 4168 4169 if (bus) { 4170 /* De-register interrupt handler */ 4171 brcmf_sdiod_intr_unregister(bus->sdiodev); 4172 4173 if (bus->sdiodev->bus_if->drvr) { 4174 brcmf_detach(bus->sdiodev->dev); 4175 } 4176 4177 cancel_work_sync(&bus->datawork); 4178 if (bus->brcmf_wq) 4179 destroy_workqueue(bus->brcmf_wq); 4180 4181 if (bus->ci) { 4182 if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) { 4183 sdio_claim_host(bus->sdiodev->func[1]); 4184 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4185 /* Leave the device in state where it is 4186 * 'quiet'. This is done by putting it in 4187 * download_state which essentially resets 4188 * all necessary cores. 4189 */ 4190 msleep(20); 4191 brcmf_chip_enter_download(bus->ci); 4192 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4193 sdio_release_host(bus->sdiodev->func[1]); 4194 } 4195 brcmf_chip_detach(bus->ci); 4196 } 4197 4198 kfree(bus->rxbuf); 4199 kfree(bus->hdrbuf); 4200 kfree(bus); 4201 } 4202 4203 brcmf_dbg(TRACE, "Disconnected\n"); 4204} 4205 4206void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick) 4207{ 4208 /* Totally stop the timer */ 4209 if (!wdtick && bus->wd_timer_valid) { 4210 del_timer_sync(&bus->timer); 4211 bus->wd_timer_valid = false; 4212 bus->save_ms = wdtick; 4213 return; 4214 } 4215 4216 /* don't start the wd until fw is loaded */ 4217 if (bus->sdiodev->bus_if->state != BRCMF_BUS_DATA) 4218 return; 4219 4220 if (wdtick) { 4221 if (bus->save_ms != BRCMF_WD_POLL_MS) { 4222 if (bus->wd_timer_valid) 4223 /* Stop timer and restart at new value */ 4224 del_timer_sync(&bus->timer); 4225 4226 /* Create timer again when watchdog period is 4227 dynamically changed or in the first instance 4228 */ 4229 bus->timer.expires = 4230 jiffies + BRCMF_WD_POLL_MS * HZ / 1000; 4231 add_timer(&bus->timer); 4232 4233 } else { 4234 /* Re arm the timer, at last watchdog period */ 4235 mod_timer(&bus->timer, 4236 jiffies + BRCMF_WD_POLL_MS * HZ / 1000); 4237 } 4238 4239 bus->wd_timer_valid = true; 4240 bus->save_ms = wdtick; 4241 } 4242} 4243