1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef	_BRCM_AIUTILS_H_
18#define	_BRCM_AIUTILS_H_
19
20#include <linux/bcma/bcma.h>
21
22#include "types.h"
23
24/*
25 * SOC Interconnect Address Map.
26 * All regions may not exist on all chips.
27 */
28/* each core gets 4Kbytes for registers */
29#define SI_CORE_SIZE		0x1000
30/*
31 * Max cores (this is arbitrary, for software
32 * convenience and could be changed if we
33 * make any larger chips
34 */
35#define	SI_MAXCORES		16
36
37/* Client Mode sb2pcitranslation2 size in bytes */
38#define SI_PCI_DMA_SZ		0x40000000
39
40/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
41#define SI_PCIE_DMA_H32		0x80000000
42
43/* chipcommon being the first core: */
44#define	SI_CC_IDX		0
45
46/* SOC Interconnect types (aka chip types) */
47#define	SOCI_AI			1
48
49/* A register that is common to all cores to
50 * communicate w/PMU regarding clock control.
51 */
52#define SI_CLK_CTL_ST		0x1e0	/* clock control and status */
53
54/* clk_ctl_st register */
55#define	CCS_FORCEALP		0x00000001	/* force ALP request */
56#define	CCS_FORCEHT		0x00000002	/* force HT request */
57#define	CCS_FORCEILP		0x00000004	/* force ILP request */
58#define	CCS_ALPAREQ		0x00000008	/* ALP Avail Request */
59#define	CCS_HTAREQ		0x00000010	/* HT Avail Request */
60#define	CCS_FORCEHWREQOFF	0x00000020	/* Force HW Clock Request Off */
61#define CCS_ERSRC_REQ_MASK	0x00000700	/* external resource requests */
62#define CCS_ERSRC_REQ_SHIFT	8
63#define	CCS_ALPAVAIL		0x00010000	/* ALP is available */
64#define	CCS_HTAVAIL		0x00020000	/* HT is available */
65#define CCS_BP_ON_APL		0x00040000	/* RO: running on ALP clock */
66#define CCS_BP_ON_HT		0x00080000	/* RO: running on HT clock */
67#define CCS_ERSRC_STS_MASK	0x07000000	/* external resource status */
68#define CCS_ERSRC_STS_SHIFT	24
69
70/* HT avail in chipc and pcmcia on 4328a0 */
71#define	CCS0_HTAVAIL		0x00010000
72/* ALP avail in chipc and pcmcia on 4328a0 */
73#define	CCS0_ALPAVAIL		0x00020000
74
75/* Not really related to SOC Interconnect, but a couple of software
76 * conventions for the use the flash space:
77 */
78
79/* Minumum amount of flash we support */
80#define FLASH_MIN		0x00020000	/* Minimum flash size */
81
82#define	CC_SROM_OTP		0x800	/* SROM/OTP address space */
83
84/* gpiotimerval */
85#define GPIO_ONTIME_SHIFT	16
86
87/* Fields in clkdiv */
88#define	CLKD_OTP		0x000f0000
89#define	CLKD_OTP_SHIFT		16
90
91/* dynamic clock control defines */
92#define	LPOMINFREQ		25000	/* low power oscillator min */
93#define	LPOMAXFREQ		43000	/* low power oscillator max */
94#define	XTALMINFREQ		19800000	/* 20 MHz - 1% */
95#define	XTALMAXFREQ		20200000	/* 20 MHz + 1% */
96#define	PCIMINFREQ		25000000	/* 25 MHz */
97#define	PCIMAXFREQ		34000000	/* 33 MHz + fudge */
98
99#define	ILP_DIV_5MHZ		0	/* ILP = 5 MHz */
100#define	ILP_DIV_1MHZ		4	/* ILP = 1 MHz */
101
102/* clkctl xtal what flags */
103#define	XTAL			0x1	/* primary crystal oscillator (2050) */
104#define	PLL			0x2	/* main chip pll */
105
106/* GPIO usage priorities */
107#define GPIO_DRV_PRIORITY	0	/* Driver */
108#define GPIO_APP_PRIORITY	1	/* Application */
109#define GPIO_HI_PRIORITY	2	/* Highest priority. Ignore GPIO
110					 * reservation
111					 */
112
113/* GPIO pull up/down */
114#define GPIO_PULLUP		0
115#define GPIO_PULLDN		1
116
117/* GPIO event regtype */
118#define GPIO_REGEVT		0	/* GPIO register event */
119#define GPIO_REGEVT_INTMSK	1	/* GPIO register event int mask */
120#define GPIO_REGEVT_INTPOL	2	/* GPIO register event int polarity */
121
122/* device path */
123#define SI_DEVPATH_BUFSZ	16	/* min buffer size in bytes */
124
125/* SI routine enumeration: to be used by update function with multiple hooks */
126#define	SI_DOATTACH	1
127#define SI_PCIDOWN	2
128#define SI_PCIUP	3
129
130/*
131 * Data structure to export all chip specific common variables
132 *   public (read-only) portion of aiutils handle returned by si_attach()
133 */
134struct si_pub {
135	int ccrev;		/* chip common core rev */
136	u32 cccaps;		/* chip common capabilities */
137	int pmurev;		/* pmu core rev */
138	u32 pmucaps;		/* pmu capabilities */
139	uint boardtype;		/* board type */
140	uint boardvendor;	/* board vendor */
141	uint chip;		/* chip number */
142	uint chiprev;		/* chip revision */
143	uint chippkg;		/* chip package option */
144};
145
146struct pci_dev;
147
148struct gpioh_item {
149	void *arg;
150	bool level;
151	void (*handler) (u32 stat, void *arg);
152	u32 event;
153	struct gpioh_item *next;
154};
155
156/* misc si info needed by some of the routines */
157struct si_info {
158	struct si_pub pub;	/* back plane public state (must be first) */
159	struct bcma_bus *icbus;	/* handle to soc interconnect bus */
160	struct pci_dev *pcibus;	/* handle to pci bus */
161
162	u32 chipst;		/* chip status */
163};
164
165/*
166 * Many of the routines below take an 'sih' handle as their first arg.
167 * Allocate this by calling si_attach().  Free it by calling si_detach().
168 * At any one time, the sih is logically focused on one particular si core
169 * (the "current core").
170 * Use si_setcore() or si_setcoreidx() to change the association to another core
171 */
172
173
174/* AMBA Interconnect exported externs */
175u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
176
177/* === exported functions === */
178struct si_pub *ai_attach(struct bcma_bus *pbus);
179void ai_detach(struct si_pub *sih);
180uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
181void ai_clkctl_init(struct si_pub *sih);
182u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
183bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
184bool ai_deviceremoved(struct si_pub *sih);
185
186/* Enable Ex-PA for 4313 */
187void ai_epa_4313war(struct si_pub *sih);
188
189static inline u32 ai_get_cccaps(struct si_pub *sih)
190{
191	return sih->cccaps;
192}
193
194static inline int ai_get_pmurev(struct si_pub *sih)
195{
196	return sih->pmurev;
197}
198
199static inline u32 ai_get_pmucaps(struct si_pub *sih)
200{
201	return sih->pmucaps;
202}
203
204static inline uint ai_get_boardtype(struct si_pub *sih)
205{
206	return sih->boardtype;
207}
208
209static inline uint ai_get_boardvendor(struct si_pub *sih)
210{
211	return sih->boardvendor;
212}
213
214static inline uint ai_get_chip_id(struct si_pub *sih)
215{
216	return sih->chip;
217}
218
219static inline uint ai_get_chiprev(struct si_pub *sih)
220{
221	return sih->chiprev;
222}
223
224static inline uint ai_get_chippkg(struct si_pub *sih)
225{
226	return sih->chippkg;
227}
228
229#endif				/* _BRCM_AIUTILS_H_ */
230